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CommitLineData
b2476490
MT
1/*
2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Standard functionality for the common clock API. See Documentation/clk.txt
10 */
11
3c373117 12#include <linux/clk.h>
b09d6d99 13#include <linux/clk-provider.h>
86be408b 14#include <linux/clk/clk-conf.h>
b2476490
MT
15#include <linux/module.h>
16#include <linux/mutex.h>
17#include <linux/spinlock.h>
18#include <linux/err.h>
19#include <linux/list.h>
20#include <linux/slab.h>
766e6a4e 21#include <linux/of.h>
46c8773a 22#include <linux/device.h>
f2f6c255 23#include <linux/init.h>
533ddeb1 24#include <linux/sched.h>
562ef0b0 25#include <linux/clkdev.h>
b2476490 26
d6782c26
SN
27#include "clk.h"
28
b2476490
MT
29static DEFINE_SPINLOCK(enable_lock);
30static DEFINE_MUTEX(prepare_lock);
31
533ddeb1
MT
32static struct task_struct *prepare_owner;
33static struct task_struct *enable_owner;
34
35static int prepare_refcnt;
36static int enable_refcnt;
37
b2476490
MT
38static HLIST_HEAD(clk_root_list);
39static HLIST_HEAD(clk_orphan_list);
40static LIST_HEAD(clk_notifier_list);
41
b09d6d99
MT
42/*** private data structures ***/
43
44struct clk_core {
45 const char *name;
46 const struct clk_ops *ops;
47 struct clk_hw *hw;
48 struct module *owner;
49 struct clk_core *parent;
50 const char **parent_names;
51 struct clk_core **parents;
52 u8 num_parents;
53 u8 new_parent_index;
54 unsigned long rate;
1c8e6004 55 unsigned long req_rate;
b09d6d99
MT
56 unsigned long new_rate;
57 struct clk_core *new_parent;
58 struct clk_core *new_child;
59 unsigned long flags;
e6500344 60 bool orphan;
b09d6d99
MT
61 unsigned int enable_count;
62 unsigned int prepare_count;
9783c0d9
SB
63 unsigned long min_rate;
64 unsigned long max_rate;
b09d6d99
MT
65 unsigned long accuracy;
66 int phase;
67 struct hlist_head children;
68 struct hlist_node child_node;
1c8e6004 69 struct hlist_head clks;
b09d6d99
MT
70 unsigned int notifier_count;
71#ifdef CONFIG_DEBUG_FS
72 struct dentry *dentry;
8c9a8a8f 73 struct hlist_node debug_node;
b09d6d99
MT
74#endif
75 struct kref ref;
76};
77
dfc202ea
SB
78#define CREATE_TRACE_POINTS
79#include <trace/events/clk.h>
80
b09d6d99
MT
81struct clk {
82 struct clk_core *core;
83 const char *dev_id;
84 const char *con_id;
1c8e6004
TV
85 unsigned long min_rate;
86 unsigned long max_rate;
50595f8b 87 struct hlist_node clks_node;
b09d6d99
MT
88};
89
eab89f69
MT
90/*** locking ***/
91static void clk_prepare_lock(void)
92{
533ddeb1
MT
93 if (!mutex_trylock(&prepare_lock)) {
94 if (prepare_owner == current) {
95 prepare_refcnt++;
96 return;
97 }
98 mutex_lock(&prepare_lock);
99 }
100 WARN_ON_ONCE(prepare_owner != NULL);
101 WARN_ON_ONCE(prepare_refcnt != 0);
102 prepare_owner = current;
103 prepare_refcnt = 1;
eab89f69
MT
104}
105
106static void clk_prepare_unlock(void)
107{
533ddeb1
MT
108 WARN_ON_ONCE(prepare_owner != current);
109 WARN_ON_ONCE(prepare_refcnt == 0);
110
111 if (--prepare_refcnt)
112 return;
113 prepare_owner = NULL;
eab89f69
MT
114 mutex_unlock(&prepare_lock);
115}
116
117static unsigned long clk_enable_lock(void)
a57aa185 118 __acquires(enable_lock)
eab89f69
MT
119{
120 unsigned long flags;
533ddeb1
MT
121
122 if (!spin_trylock_irqsave(&enable_lock, flags)) {
123 if (enable_owner == current) {
124 enable_refcnt++;
a57aa185 125 __acquire(enable_lock);
533ddeb1
MT
126 return flags;
127 }
128 spin_lock_irqsave(&enable_lock, flags);
129 }
130 WARN_ON_ONCE(enable_owner != NULL);
131 WARN_ON_ONCE(enable_refcnt != 0);
132 enable_owner = current;
133 enable_refcnt = 1;
eab89f69
MT
134 return flags;
135}
136
137static void clk_enable_unlock(unsigned long flags)
a57aa185 138 __releases(enable_lock)
eab89f69 139{
533ddeb1
MT
140 WARN_ON_ONCE(enable_owner != current);
141 WARN_ON_ONCE(enable_refcnt == 0);
142
a57aa185
SB
143 if (--enable_refcnt) {
144 __release(enable_lock);
533ddeb1 145 return;
a57aa185 146 }
533ddeb1 147 enable_owner = NULL;
eab89f69
MT
148 spin_unlock_irqrestore(&enable_lock, flags);
149}
150
4dff95dc
SB
151static bool clk_core_is_prepared(struct clk_core *core)
152{
153 /*
154 * .is_prepared is optional for clocks that can prepare
155 * fall back to software usage counter if it is missing
156 */
157 if (!core->ops->is_prepared)
158 return core->prepare_count;
b2476490 159
4dff95dc
SB
160 return core->ops->is_prepared(core->hw);
161}
b2476490 162
4dff95dc
SB
163static bool clk_core_is_enabled(struct clk_core *core)
164{
165 /*
166 * .is_enabled is only mandatory for clocks that gate
167 * fall back to software usage counter if .is_enabled is missing
168 */
169 if (!core->ops->is_enabled)
170 return core->enable_count;
6b44c854 171
4dff95dc
SB
172 return core->ops->is_enabled(core->hw);
173}
6b44c854 174
4dff95dc 175/*** helper functions ***/
1af599df 176
b76281cb 177const char *__clk_get_name(const struct clk *clk)
1af599df 178{
4dff95dc 179 return !clk ? NULL : clk->core->name;
1af599df 180}
4dff95dc 181EXPORT_SYMBOL_GPL(__clk_get_name);
1af599df 182
e7df6f6e 183const char *clk_hw_get_name(const struct clk_hw *hw)
1a9c069c
SB
184{
185 return hw->core->name;
186}
187EXPORT_SYMBOL_GPL(clk_hw_get_name);
188
4dff95dc
SB
189struct clk_hw *__clk_get_hw(struct clk *clk)
190{
191 return !clk ? NULL : clk->core->hw;
192}
193EXPORT_SYMBOL_GPL(__clk_get_hw);
1af599df 194
e7df6f6e 195unsigned int clk_hw_get_num_parents(const struct clk_hw *hw)
1a9c069c
SB
196{
197 return hw->core->num_parents;
198}
199EXPORT_SYMBOL_GPL(clk_hw_get_num_parents);
200
e7df6f6e 201struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw)
1a9c069c
SB
202{
203 return hw->core->parent ? hw->core->parent->hw : NULL;
204}
205EXPORT_SYMBOL_GPL(clk_hw_get_parent);
206
4dff95dc
SB
207static struct clk_core *__clk_lookup_subtree(const char *name,
208 struct clk_core *core)
bddca894 209{
035a61c3 210 struct clk_core *child;
4dff95dc 211 struct clk_core *ret;
bddca894 212
4dff95dc
SB
213 if (!strcmp(core->name, name))
214 return core;
bddca894 215
4dff95dc
SB
216 hlist_for_each_entry(child, &core->children, child_node) {
217 ret = __clk_lookup_subtree(name, child);
218 if (ret)
219 return ret;
bddca894
PG
220 }
221
4dff95dc 222 return NULL;
bddca894
PG
223}
224
4dff95dc 225static struct clk_core *clk_core_lookup(const char *name)
bddca894 226{
4dff95dc
SB
227 struct clk_core *root_clk;
228 struct clk_core *ret;
bddca894 229
4dff95dc
SB
230 if (!name)
231 return NULL;
bddca894 232
4dff95dc
SB
233 /* search the 'proper' clk tree first */
234 hlist_for_each_entry(root_clk, &clk_root_list, child_node) {
235 ret = __clk_lookup_subtree(name, root_clk);
236 if (ret)
237 return ret;
bddca894
PG
238 }
239
4dff95dc
SB
240 /* if not found, then search the orphan tree */
241 hlist_for_each_entry(root_clk, &clk_orphan_list, child_node) {
242 ret = __clk_lookup_subtree(name, root_clk);
243 if (ret)
244 return ret;
245 }
bddca894 246
4dff95dc 247 return NULL;
bddca894
PG
248}
249
4dff95dc
SB
250static struct clk_core *clk_core_get_parent_by_index(struct clk_core *core,
251 u8 index)
bddca894 252{
4dff95dc
SB
253 if (!core || index >= core->num_parents)
254 return NULL;
88cfbef2
MY
255
256 if (!core->parents[index])
257 core->parents[index] =
258 clk_core_lookup(core->parent_names[index]);
259
260 return core->parents[index];
bddca894
PG
261}
262
e7df6f6e
SB
263struct clk_hw *
264clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index)
1a9c069c
SB
265{
266 struct clk_core *parent;
267
268 parent = clk_core_get_parent_by_index(hw->core, index);
269
270 return !parent ? NULL : parent->hw;
271}
272EXPORT_SYMBOL_GPL(clk_hw_get_parent_by_index);
273
4dff95dc
SB
274unsigned int __clk_get_enable_count(struct clk *clk)
275{
276 return !clk ? 0 : clk->core->enable_count;
277}
b2476490 278
4dff95dc
SB
279static unsigned long clk_core_get_rate_nolock(struct clk_core *core)
280{
281 unsigned long ret;
b2476490 282
4dff95dc
SB
283 if (!core) {
284 ret = 0;
285 goto out;
286 }
b2476490 287
4dff95dc 288 ret = core->rate;
b2476490 289
47b0eeb3 290 if (!core->num_parents)
4dff95dc 291 goto out;
c646cbf1 292
4dff95dc
SB
293 if (!core->parent)
294 ret = 0;
b2476490 295
b2476490
MT
296out:
297 return ret;
298}
299
e7df6f6e 300unsigned long clk_hw_get_rate(const struct clk_hw *hw)
1a9c069c
SB
301{
302 return clk_core_get_rate_nolock(hw->core);
303}
304EXPORT_SYMBOL_GPL(clk_hw_get_rate);
305
4dff95dc
SB
306static unsigned long __clk_get_accuracy(struct clk_core *core)
307{
308 if (!core)
309 return 0;
b2476490 310
4dff95dc 311 return core->accuracy;
b2476490
MT
312}
313
4dff95dc 314unsigned long __clk_get_flags(struct clk *clk)
fcb0ee6a 315{
4dff95dc 316 return !clk ? 0 : clk->core->flags;
fcb0ee6a 317}
4dff95dc 318EXPORT_SYMBOL_GPL(__clk_get_flags);
fcb0ee6a 319
e7df6f6e 320unsigned long clk_hw_get_flags(const struct clk_hw *hw)
1a9c069c
SB
321{
322 return hw->core->flags;
323}
324EXPORT_SYMBOL_GPL(clk_hw_get_flags);
325
e7df6f6e 326bool clk_hw_is_prepared(const struct clk_hw *hw)
1a9c069c
SB
327{
328 return clk_core_is_prepared(hw->core);
329}
330
be68bf88
JE
331bool clk_hw_is_enabled(const struct clk_hw *hw)
332{
333 return clk_core_is_enabled(hw->core);
334}
335
4dff95dc 336bool __clk_is_enabled(struct clk *clk)
b2476490 337{
4dff95dc
SB
338 if (!clk)
339 return false;
b2476490 340
4dff95dc
SB
341 return clk_core_is_enabled(clk->core);
342}
343EXPORT_SYMBOL_GPL(__clk_is_enabled);
b2476490 344
4dff95dc
SB
345static bool mux_is_better_rate(unsigned long rate, unsigned long now,
346 unsigned long best, unsigned long flags)
347{
348 if (flags & CLK_MUX_ROUND_CLOSEST)
349 return abs(now - rate) < abs(best - rate);
1af599df 350
4dff95dc
SB
351 return now <= rate && now > best;
352}
bddca894 353
0817b62c
BB
354static int
355clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req,
4dff95dc
SB
356 unsigned long flags)
357{
358 struct clk_core *core = hw->core, *parent, *best_parent = NULL;
0817b62c
BB
359 int i, num_parents, ret;
360 unsigned long best = 0;
361 struct clk_rate_request parent_req = *req;
b2476490 362
4dff95dc
SB
363 /* if NO_REPARENT flag set, pass through to current parent */
364 if (core->flags & CLK_SET_RATE_NO_REPARENT) {
365 parent = core->parent;
0817b62c
BB
366 if (core->flags & CLK_SET_RATE_PARENT) {
367 ret = __clk_determine_rate(parent ? parent->hw : NULL,
368 &parent_req);
369 if (ret)
370 return ret;
371
372 best = parent_req.rate;
373 } else if (parent) {
4dff95dc 374 best = clk_core_get_rate_nolock(parent);
0817b62c 375 } else {
4dff95dc 376 best = clk_core_get_rate_nolock(core);
0817b62c
BB
377 }
378
4dff95dc
SB
379 goto out;
380 }
b2476490 381
4dff95dc
SB
382 /* find the parent that can provide the fastest rate <= rate */
383 num_parents = core->num_parents;
384 for (i = 0; i < num_parents; i++) {
385 parent = clk_core_get_parent_by_index(core, i);
386 if (!parent)
387 continue;
0817b62c
BB
388
389 if (core->flags & CLK_SET_RATE_PARENT) {
390 parent_req = *req;
391 ret = __clk_determine_rate(parent->hw, &parent_req);
392 if (ret)
393 continue;
394 } else {
395 parent_req.rate = clk_core_get_rate_nolock(parent);
396 }
397
398 if (mux_is_better_rate(req->rate, parent_req.rate,
399 best, flags)) {
4dff95dc 400 best_parent = parent;
0817b62c 401 best = parent_req.rate;
4dff95dc
SB
402 }
403 }
b2476490 404
57d866e6
BB
405 if (!best_parent)
406 return -EINVAL;
407
4dff95dc
SB
408out:
409 if (best_parent)
0817b62c
BB
410 req->best_parent_hw = best_parent->hw;
411 req->best_parent_rate = best;
412 req->rate = best;
b2476490 413
0817b62c 414 return 0;
b33d212f 415}
4dff95dc
SB
416
417struct clk *__clk_lookup(const char *name)
fcb0ee6a 418{
4dff95dc
SB
419 struct clk_core *core = clk_core_lookup(name);
420
421 return !core ? NULL : core->hw->clk;
fcb0ee6a 422}
b2476490 423
4dff95dc
SB
424static void clk_core_get_boundaries(struct clk_core *core,
425 unsigned long *min_rate,
426 unsigned long *max_rate)
1c155b3d 427{
4dff95dc 428 struct clk *clk_user;
1c155b3d 429
9783c0d9
SB
430 *min_rate = core->min_rate;
431 *max_rate = core->max_rate;
496eadf8 432
4dff95dc
SB
433 hlist_for_each_entry(clk_user, &core->clks, clks_node)
434 *min_rate = max(*min_rate, clk_user->min_rate);
1c155b3d 435
4dff95dc
SB
436 hlist_for_each_entry(clk_user, &core->clks, clks_node)
437 *max_rate = min(*max_rate, clk_user->max_rate);
438}
1c155b3d 439
9783c0d9
SB
440void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
441 unsigned long max_rate)
442{
443 hw->core->min_rate = min_rate;
444 hw->core->max_rate = max_rate;
445}
446EXPORT_SYMBOL_GPL(clk_hw_set_rate_range);
447
4dff95dc
SB
448/*
449 * Helper for finding best parent to provide a given frequency. This can be used
450 * directly as a determine_rate callback (e.g. for a mux), or from a more
451 * complex clock that may combine a mux with other operations.
452 */
0817b62c
BB
453int __clk_mux_determine_rate(struct clk_hw *hw,
454 struct clk_rate_request *req)
4dff95dc 455{
0817b62c 456 return clk_mux_determine_rate_flags(hw, req, 0);
1c155b3d 457}
4dff95dc 458EXPORT_SYMBOL_GPL(__clk_mux_determine_rate);
1c155b3d 459
0817b62c
BB
460int __clk_mux_determine_rate_closest(struct clk_hw *hw,
461 struct clk_rate_request *req)
b2476490 462{
0817b62c 463 return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST);
4dff95dc
SB
464}
465EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
b2476490 466
4dff95dc 467/*** clk api ***/
496eadf8 468
4dff95dc
SB
469static void clk_core_unprepare(struct clk_core *core)
470{
a6334725
SB
471 lockdep_assert_held(&prepare_lock);
472
4dff95dc
SB
473 if (!core)
474 return;
b2476490 475
4dff95dc
SB
476 if (WARN_ON(core->prepare_count == 0))
477 return;
b2476490 478
2e20fbf5
LJ
479 if (WARN_ON(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL))
480 return;
481
4dff95dc
SB
482 if (--core->prepare_count > 0)
483 return;
b2476490 484
4dff95dc 485 WARN_ON(core->enable_count > 0);
b2476490 486
4dff95dc 487 trace_clk_unprepare(core);
b2476490 488
4dff95dc
SB
489 if (core->ops->unprepare)
490 core->ops->unprepare(core->hw);
491
492 trace_clk_unprepare_complete(core);
493 clk_core_unprepare(core->parent);
b2476490
MT
494}
495
a6adc30b
DA
496static void clk_core_unprepare_lock(struct clk_core *core)
497{
498 clk_prepare_lock();
499 clk_core_unprepare(core);
500 clk_prepare_unlock();
501}
502
4dff95dc
SB
503/**
504 * clk_unprepare - undo preparation of a clock source
505 * @clk: the clk being unprepared
506 *
507 * clk_unprepare may sleep, which differentiates it from clk_disable. In a
508 * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
509 * if the operation may sleep. One example is a clk which is accessed over
510 * I2c. In the complex case a clk gate operation may require a fast and a slow
511 * part. It is this reason that clk_unprepare and clk_disable are not mutually
512 * exclusive. In fact clk_disable must be called before clk_unprepare.
513 */
514void clk_unprepare(struct clk *clk)
1e435256 515{
4dff95dc
SB
516 if (IS_ERR_OR_NULL(clk))
517 return;
518
a6adc30b 519 clk_core_unprepare_lock(clk->core);
1e435256 520}
4dff95dc 521EXPORT_SYMBOL_GPL(clk_unprepare);
1e435256 522
4dff95dc 523static int clk_core_prepare(struct clk_core *core)
b2476490 524{
4dff95dc 525 int ret = 0;
b2476490 526
a6334725
SB
527 lockdep_assert_held(&prepare_lock);
528
4dff95dc 529 if (!core)
1e435256 530 return 0;
1e435256 531
4dff95dc
SB
532 if (core->prepare_count == 0) {
533 ret = clk_core_prepare(core->parent);
534 if (ret)
535 return ret;
b2476490 536
4dff95dc 537 trace_clk_prepare(core);
b2476490 538
4dff95dc
SB
539 if (core->ops->prepare)
540 ret = core->ops->prepare(core->hw);
b2476490 541
4dff95dc 542 trace_clk_prepare_complete(core);
1c155b3d 543
4dff95dc
SB
544 if (ret) {
545 clk_core_unprepare(core->parent);
546 return ret;
547 }
548 }
1c155b3d 549
4dff95dc 550 core->prepare_count++;
b2476490
MT
551
552 return 0;
553}
b2476490 554
a6adc30b
DA
555static int clk_core_prepare_lock(struct clk_core *core)
556{
557 int ret;
558
559 clk_prepare_lock();
560 ret = clk_core_prepare(core);
561 clk_prepare_unlock();
562
563 return ret;
564}
565
4dff95dc
SB
566/**
567 * clk_prepare - prepare a clock source
568 * @clk: the clk being prepared
569 *
570 * clk_prepare may sleep, which differentiates it from clk_enable. In a simple
571 * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
572 * operation may sleep. One example is a clk which is accessed over I2c. In
573 * the complex case a clk ungate operation may require a fast and a slow part.
574 * It is this reason that clk_prepare and clk_enable are not mutually
575 * exclusive. In fact clk_prepare must be called before clk_enable.
576 * Returns 0 on success, -EERROR otherwise.
577 */
578int clk_prepare(struct clk *clk)
b2476490 579{
4dff95dc
SB
580 if (!clk)
581 return 0;
b2476490 582
a6adc30b 583 return clk_core_prepare_lock(clk->core);
b2476490 584}
4dff95dc 585EXPORT_SYMBOL_GPL(clk_prepare);
b2476490 586
4dff95dc 587static void clk_core_disable(struct clk_core *core)
b2476490 588{
a6334725
SB
589 lockdep_assert_held(&enable_lock);
590
4dff95dc
SB
591 if (!core)
592 return;
035a61c3 593
4dff95dc
SB
594 if (WARN_ON(core->enable_count == 0))
595 return;
b2476490 596
2e20fbf5
LJ
597 if (WARN_ON(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL))
598 return;
599
4dff95dc
SB
600 if (--core->enable_count > 0)
601 return;
035a61c3 602
2f87a6ea 603 trace_clk_disable_rcuidle(core);
035a61c3 604
4dff95dc
SB
605 if (core->ops->disable)
606 core->ops->disable(core->hw);
035a61c3 607
2f87a6ea 608 trace_clk_disable_complete_rcuidle(core);
035a61c3 609
4dff95dc 610 clk_core_disable(core->parent);
035a61c3 611}
7ef3dcc8 612
a6adc30b
DA
613static void clk_core_disable_lock(struct clk_core *core)
614{
615 unsigned long flags;
616
617 flags = clk_enable_lock();
618 clk_core_disable(core);
619 clk_enable_unlock(flags);
620}
621
4dff95dc
SB
622/**
623 * clk_disable - gate a clock
624 * @clk: the clk being gated
625 *
626 * clk_disable must not sleep, which differentiates it from clk_unprepare. In
627 * a simple case, clk_disable can be used instead of clk_unprepare to gate a
628 * clk if the operation is fast and will never sleep. One example is a
629 * SoC-internal clk which is controlled via simple register writes. In the
630 * complex case a clk gate operation may require a fast and a slow part. It is
631 * this reason that clk_unprepare and clk_disable are not mutually exclusive.
632 * In fact clk_disable must be called before clk_unprepare.
633 */
634void clk_disable(struct clk *clk)
b2476490 635{
4dff95dc
SB
636 if (IS_ERR_OR_NULL(clk))
637 return;
638
a6adc30b 639 clk_core_disable_lock(clk->core);
b2476490 640}
4dff95dc 641EXPORT_SYMBOL_GPL(clk_disable);
b2476490 642
4dff95dc 643static int clk_core_enable(struct clk_core *core)
b2476490 644{
4dff95dc 645 int ret = 0;
b2476490 646
a6334725
SB
647 lockdep_assert_held(&enable_lock);
648
4dff95dc
SB
649 if (!core)
650 return 0;
b2476490 651
4dff95dc
SB
652 if (WARN_ON(core->prepare_count == 0))
653 return -ESHUTDOWN;
b2476490 654
4dff95dc
SB
655 if (core->enable_count == 0) {
656 ret = clk_core_enable(core->parent);
b2476490 657
4dff95dc
SB
658 if (ret)
659 return ret;
b2476490 660
f17a0dd1 661 trace_clk_enable_rcuidle(core);
035a61c3 662
4dff95dc
SB
663 if (core->ops->enable)
664 ret = core->ops->enable(core->hw);
035a61c3 665
f17a0dd1 666 trace_clk_enable_complete_rcuidle(core);
4dff95dc
SB
667
668 if (ret) {
669 clk_core_disable(core->parent);
670 return ret;
671 }
672 }
673
674 core->enable_count++;
675 return 0;
035a61c3 676}
b2476490 677
a6adc30b
DA
678static int clk_core_enable_lock(struct clk_core *core)
679{
680 unsigned long flags;
681 int ret;
682
683 flags = clk_enable_lock();
684 ret = clk_core_enable(core);
685 clk_enable_unlock(flags);
686
687 return ret;
688}
689
4dff95dc
SB
690/**
691 * clk_enable - ungate a clock
692 * @clk: the clk being ungated
693 *
694 * clk_enable must not sleep, which differentiates it from clk_prepare. In a
695 * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
696 * if the operation will never sleep. One example is a SoC-internal clk which
697 * is controlled via simple register writes. In the complex case a clk ungate
698 * operation may require a fast and a slow part. It is this reason that
699 * clk_enable and clk_prepare are not mutually exclusive. In fact clk_prepare
700 * must be called before clk_enable. Returns 0 on success, -EERROR
701 * otherwise.
702 */
703int clk_enable(struct clk *clk)
5279fc40 704{
4dff95dc 705 if (!clk)
5279fc40
BB
706 return 0;
707
a6adc30b
DA
708 return clk_core_enable_lock(clk->core);
709}
710EXPORT_SYMBOL_GPL(clk_enable);
711
712static int clk_core_prepare_enable(struct clk_core *core)
713{
714 int ret;
715
716 ret = clk_core_prepare_lock(core);
717 if (ret)
718 return ret;
719
720 ret = clk_core_enable_lock(core);
721 if (ret)
722 clk_core_unprepare_lock(core);
5279fc40 723
4dff95dc 724 return ret;
b2476490 725}
a6adc30b
DA
726
727static void clk_core_disable_unprepare(struct clk_core *core)
728{
729 clk_core_disable_lock(core);
730 clk_core_unprepare_lock(core);
731}
b2476490 732
7ec986ef
DA
733static void clk_unprepare_unused_subtree(struct clk_core *core)
734{
735 struct clk_core *child;
736
737 lockdep_assert_held(&prepare_lock);
738
739 hlist_for_each_entry(child, &core->children, child_node)
740 clk_unprepare_unused_subtree(child);
741
742 if (core->prepare_count)
743 return;
744
745 if (core->flags & CLK_IGNORE_UNUSED)
746 return;
747
748 if (clk_core_is_prepared(core)) {
749 trace_clk_unprepare(core);
750 if (core->ops->unprepare_unused)
751 core->ops->unprepare_unused(core->hw);
752 else if (core->ops->unprepare)
753 core->ops->unprepare(core->hw);
754 trace_clk_unprepare_complete(core);
755 }
756}
757
758static void clk_disable_unused_subtree(struct clk_core *core)
759{
760 struct clk_core *child;
761 unsigned long flags;
762
763 lockdep_assert_held(&prepare_lock);
764
765 hlist_for_each_entry(child, &core->children, child_node)
766 clk_disable_unused_subtree(child);
767
a4b3518d
DA
768 if (core->flags & CLK_OPS_PARENT_ENABLE)
769 clk_core_prepare_enable(core->parent);
770
7ec986ef
DA
771 flags = clk_enable_lock();
772
773 if (core->enable_count)
774 goto unlock_out;
775
776 if (core->flags & CLK_IGNORE_UNUSED)
777 goto unlock_out;
778
779 /*
780 * some gate clocks have special needs during the disable-unused
781 * sequence. call .disable_unused if available, otherwise fall
782 * back to .disable
783 */
784 if (clk_core_is_enabled(core)) {
785 trace_clk_disable(core);
786 if (core->ops->disable_unused)
787 core->ops->disable_unused(core->hw);
788 else if (core->ops->disable)
789 core->ops->disable(core->hw);
790 trace_clk_disable_complete(core);
791 }
792
793unlock_out:
794 clk_enable_unlock(flags);
a4b3518d
DA
795 if (core->flags & CLK_OPS_PARENT_ENABLE)
796 clk_core_disable_unprepare(core->parent);
7ec986ef
DA
797}
798
799static bool clk_ignore_unused;
800static int __init clk_ignore_unused_setup(char *__unused)
801{
802 clk_ignore_unused = true;
803 return 1;
804}
805__setup("clk_ignore_unused", clk_ignore_unused_setup);
806
807static int clk_disable_unused(void)
808{
809 struct clk_core *core;
810
811 if (clk_ignore_unused) {
812 pr_warn("clk: Not disabling unused clocks\n");
813 return 0;
814 }
815
816 clk_prepare_lock();
817
818 hlist_for_each_entry(core, &clk_root_list, child_node)
819 clk_disable_unused_subtree(core);
820
821 hlist_for_each_entry(core, &clk_orphan_list, child_node)
822 clk_disable_unused_subtree(core);
823
824 hlist_for_each_entry(core, &clk_root_list, child_node)
825 clk_unprepare_unused_subtree(core);
826
827 hlist_for_each_entry(core, &clk_orphan_list, child_node)
828 clk_unprepare_unused_subtree(core);
829
830 clk_prepare_unlock();
831
832 return 0;
833}
834late_initcall_sync(clk_disable_unused);
835
0817b62c
BB
836static int clk_core_round_rate_nolock(struct clk_core *core,
837 struct clk_rate_request *req)
3d6ee287 838{
4dff95dc 839 struct clk_core *parent;
0817b62c 840 long rate;
4dff95dc
SB
841
842 lockdep_assert_held(&prepare_lock);
3d6ee287 843
d6968fca 844 if (!core)
4dff95dc 845 return 0;
3d6ee287 846
4dff95dc 847 parent = core->parent;
0817b62c
BB
848 if (parent) {
849 req->best_parent_hw = parent->hw;
850 req->best_parent_rate = parent->rate;
851 } else {
852 req->best_parent_hw = NULL;
853 req->best_parent_rate = 0;
854 }
3d6ee287 855
4dff95dc 856 if (core->ops->determine_rate) {
0817b62c
BB
857 return core->ops->determine_rate(core->hw, req);
858 } else if (core->ops->round_rate) {
859 rate = core->ops->round_rate(core->hw, req->rate,
860 &req->best_parent_rate);
861 if (rate < 0)
862 return rate;
863
864 req->rate = rate;
865 } else if (core->flags & CLK_SET_RATE_PARENT) {
866 return clk_core_round_rate_nolock(parent, req);
867 } else {
868 req->rate = core->rate;
869 }
870
871 return 0;
3d6ee287
UH
872}
873
4dff95dc
SB
874/**
875 * __clk_determine_rate - get the closest rate actually supported by a clock
876 * @hw: determine the rate of this clock
2d5b520c 877 * @req: target rate request
4dff95dc 878 *
6e5ab41b 879 * Useful for clk_ops such as .set_rate and .determine_rate.
4dff95dc 880 */
0817b62c 881int __clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
035a61c3 882{
0817b62c
BB
883 if (!hw) {
884 req->rate = 0;
4dff95dc 885 return 0;
0817b62c 886 }
035a61c3 887
0817b62c 888 return clk_core_round_rate_nolock(hw->core, req);
035a61c3 889}
4dff95dc 890EXPORT_SYMBOL_GPL(__clk_determine_rate);
035a61c3 891
1a9c069c
SB
892unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate)
893{
894 int ret;
895 struct clk_rate_request req;
896
897 clk_core_get_boundaries(hw->core, &req.min_rate, &req.max_rate);
898 req.rate = rate;
899
900 ret = clk_core_round_rate_nolock(hw->core, &req);
901 if (ret)
902 return 0;
903
904 return req.rate;
905}
906EXPORT_SYMBOL_GPL(clk_hw_round_rate);
907
4dff95dc
SB
908/**
909 * clk_round_rate - round the given rate for a clk
910 * @clk: the clk for which we are rounding a rate
911 * @rate: the rate which is to be rounded
912 *
913 * Takes in a rate as input and rounds it to a rate that the clk can actually
914 * use which is then returned. If clk doesn't support round_rate operation
915 * then the parent rate is returned.
916 */
917long clk_round_rate(struct clk *clk, unsigned long rate)
035a61c3 918{
fc4a05d4
SB
919 struct clk_rate_request req;
920 int ret;
4dff95dc 921
035a61c3 922 if (!clk)
4dff95dc 923 return 0;
035a61c3 924
4dff95dc 925 clk_prepare_lock();
fc4a05d4
SB
926
927 clk_core_get_boundaries(clk->core, &req.min_rate, &req.max_rate);
928 req.rate = rate;
929
930 ret = clk_core_round_rate_nolock(clk->core, &req);
4dff95dc
SB
931 clk_prepare_unlock();
932
fc4a05d4
SB
933 if (ret)
934 return ret;
935
936 return req.rate;
035a61c3 937}
4dff95dc 938EXPORT_SYMBOL_GPL(clk_round_rate);
b2476490 939
4dff95dc
SB
940/**
941 * __clk_notify - call clk notifier chain
942 * @core: clk that is changing rate
943 * @msg: clk notifier type (see include/linux/clk.h)
944 * @old_rate: old clk rate
945 * @new_rate: new clk rate
946 *
947 * Triggers a notifier call chain on the clk rate-change notification
948 * for 'clk'. Passes a pointer to the struct clk and the previous
949 * and current rates to the notifier callback. Intended to be called by
950 * internal clock code only. Returns NOTIFY_DONE from the last driver
951 * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
952 * a driver returns that.
953 */
954static int __clk_notify(struct clk_core *core, unsigned long msg,
955 unsigned long old_rate, unsigned long new_rate)
b2476490 956{
4dff95dc
SB
957 struct clk_notifier *cn;
958 struct clk_notifier_data cnd;
959 int ret = NOTIFY_DONE;
b2476490 960
4dff95dc
SB
961 cnd.old_rate = old_rate;
962 cnd.new_rate = new_rate;
b2476490 963
4dff95dc
SB
964 list_for_each_entry(cn, &clk_notifier_list, node) {
965 if (cn->clk->core == core) {
966 cnd.clk = cn->clk;
967 ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
968 &cnd);
17c34c56
PDS
969 if (ret & NOTIFY_STOP_MASK)
970 return ret;
4dff95dc 971 }
b2476490
MT
972 }
973
4dff95dc 974 return ret;
b2476490
MT
975}
976
4dff95dc
SB
977/**
978 * __clk_recalc_accuracies
979 * @core: first clk in the subtree
980 *
981 * Walks the subtree of clks starting with clk and recalculates accuracies as
982 * it goes. Note that if a clk does not implement the .recalc_accuracy
6e5ab41b 983 * callback then it is assumed that the clock will take on the accuracy of its
4dff95dc 984 * parent.
4dff95dc
SB
985 */
986static void __clk_recalc_accuracies(struct clk_core *core)
b2476490 987{
4dff95dc
SB
988 unsigned long parent_accuracy = 0;
989 struct clk_core *child;
b2476490 990
4dff95dc 991 lockdep_assert_held(&prepare_lock);
b2476490 992
4dff95dc
SB
993 if (core->parent)
994 parent_accuracy = core->parent->accuracy;
b2476490 995
4dff95dc
SB
996 if (core->ops->recalc_accuracy)
997 core->accuracy = core->ops->recalc_accuracy(core->hw,
998 parent_accuracy);
999 else
1000 core->accuracy = parent_accuracy;
b2476490 1001
4dff95dc
SB
1002 hlist_for_each_entry(child, &core->children, child_node)
1003 __clk_recalc_accuracies(child);
b2476490
MT
1004}
1005
4dff95dc 1006static long clk_core_get_accuracy(struct clk_core *core)
e366fdd7 1007{
4dff95dc 1008 unsigned long accuracy;
15a02c1f 1009
4dff95dc
SB
1010 clk_prepare_lock();
1011 if (core && (core->flags & CLK_GET_ACCURACY_NOCACHE))
1012 __clk_recalc_accuracies(core);
15a02c1f 1013
4dff95dc
SB
1014 accuracy = __clk_get_accuracy(core);
1015 clk_prepare_unlock();
e366fdd7 1016
4dff95dc 1017 return accuracy;
e366fdd7 1018}
15a02c1f 1019
4dff95dc
SB
1020/**
1021 * clk_get_accuracy - return the accuracy of clk
1022 * @clk: the clk whose accuracy is being returned
1023 *
1024 * Simply returns the cached accuracy of the clk, unless
1025 * CLK_GET_ACCURACY_NOCACHE flag is set, which means a recalc_rate will be
1026 * issued.
1027 * If clk is NULL then returns 0.
1028 */
1029long clk_get_accuracy(struct clk *clk)
035a61c3 1030{
4dff95dc
SB
1031 if (!clk)
1032 return 0;
035a61c3 1033
4dff95dc 1034 return clk_core_get_accuracy(clk->core);
035a61c3 1035}
4dff95dc 1036EXPORT_SYMBOL_GPL(clk_get_accuracy);
035a61c3 1037
4dff95dc
SB
1038static unsigned long clk_recalc(struct clk_core *core,
1039 unsigned long parent_rate)
1c8e6004 1040{
4dff95dc
SB
1041 if (core->ops->recalc_rate)
1042 return core->ops->recalc_rate(core->hw, parent_rate);
1043 return parent_rate;
1c8e6004
TV
1044}
1045
4dff95dc
SB
1046/**
1047 * __clk_recalc_rates
1048 * @core: first clk in the subtree
1049 * @msg: notification type (see include/linux/clk.h)
1050 *
1051 * Walks the subtree of clks starting with clk and recalculates rates as it
1052 * goes. Note that if a clk does not implement the .recalc_rate callback then
1053 * it is assumed that the clock will take on the rate of its parent.
1054 *
1055 * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
1056 * if necessary.
15a02c1f 1057 */
4dff95dc 1058static void __clk_recalc_rates(struct clk_core *core, unsigned long msg)
15a02c1f 1059{
4dff95dc
SB
1060 unsigned long old_rate;
1061 unsigned long parent_rate = 0;
1062 struct clk_core *child;
e366fdd7 1063
4dff95dc 1064 lockdep_assert_held(&prepare_lock);
15a02c1f 1065
4dff95dc 1066 old_rate = core->rate;
b2476490 1067
4dff95dc
SB
1068 if (core->parent)
1069 parent_rate = core->parent->rate;
b2476490 1070
4dff95dc 1071 core->rate = clk_recalc(core, parent_rate);
b2476490 1072
4dff95dc
SB
1073 /*
1074 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
1075 * & ABORT_RATE_CHANGE notifiers
1076 */
1077 if (core->notifier_count && msg)
1078 __clk_notify(core, msg, old_rate, core->rate);
b2476490 1079
4dff95dc
SB
1080 hlist_for_each_entry(child, &core->children, child_node)
1081 __clk_recalc_rates(child, msg);
1082}
b2476490 1083
4dff95dc
SB
1084static unsigned long clk_core_get_rate(struct clk_core *core)
1085{
1086 unsigned long rate;
dfc202ea 1087
4dff95dc 1088 clk_prepare_lock();
b2476490 1089
4dff95dc
SB
1090 if (core && (core->flags & CLK_GET_RATE_NOCACHE))
1091 __clk_recalc_rates(core, 0);
1092
1093 rate = clk_core_get_rate_nolock(core);
1094 clk_prepare_unlock();
1095
1096 return rate;
b2476490
MT
1097}
1098
1099/**
4dff95dc
SB
1100 * clk_get_rate - return the rate of clk
1101 * @clk: the clk whose rate is being returned
b2476490 1102 *
4dff95dc
SB
1103 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1104 * is set, which means a recalc_rate will be issued.
1105 * If clk is NULL then returns 0.
b2476490 1106 */
4dff95dc 1107unsigned long clk_get_rate(struct clk *clk)
b2476490 1108{
4dff95dc
SB
1109 if (!clk)
1110 return 0;
63589e92 1111
4dff95dc 1112 return clk_core_get_rate(clk->core);
b2476490 1113}
4dff95dc 1114EXPORT_SYMBOL_GPL(clk_get_rate);
b2476490 1115
4dff95dc
SB
1116static int clk_fetch_parent_index(struct clk_core *core,
1117 struct clk_core *parent)
b2476490 1118{
4dff95dc 1119 int i;
b2476490 1120
508f884a
MY
1121 if (!parent)
1122 return -EINVAL;
1123
470b5e2f
MY
1124 for (i = 0; i < core->num_parents; i++)
1125 if (clk_core_get_parent_by_index(core, i) == parent)
4dff95dc 1126 return i;
b2476490 1127
4dff95dc 1128 return -EINVAL;
b2476490
MT
1129}
1130
e6500344
HS
1131/*
1132 * Update the orphan status of @core and all its children.
1133 */
1134static void clk_core_update_orphan_status(struct clk_core *core, bool is_orphan)
1135{
1136 struct clk_core *child;
1137
1138 core->orphan = is_orphan;
1139
1140 hlist_for_each_entry(child, &core->children, child_node)
1141 clk_core_update_orphan_status(child, is_orphan);
1142}
1143
4dff95dc 1144static void clk_reparent(struct clk_core *core, struct clk_core *new_parent)
b2476490 1145{
e6500344
HS
1146 bool was_orphan = core->orphan;
1147
4dff95dc 1148 hlist_del(&core->child_node);
035a61c3 1149
4dff95dc 1150 if (new_parent) {
e6500344
HS
1151 bool becomes_orphan = new_parent->orphan;
1152
4dff95dc
SB
1153 /* avoid duplicate POST_RATE_CHANGE notifications */
1154 if (new_parent->new_child == core)
1155 new_parent->new_child = NULL;
b2476490 1156
4dff95dc 1157 hlist_add_head(&core->child_node, &new_parent->children);
e6500344
HS
1158
1159 if (was_orphan != becomes_orphan)
1160 clk_core_update_orphan_status(core, becomes_orphan);
4dff95dc
SB
1161 } else {
1162 hlist_add_head(&core->child_node, &clk_orphan_list);
e6500344
HS
1163 if (!was_orphan)
1164 clk_core_update_orphan_status(core, true);
4dff95dc 1165 }
dfc202ea 1166
4dff95dc 1167 core->parent = new_parent;
035a61c3
TV
1168}
1169
4dff95dc
SB
1170static struct clk_core *__clk_set_parent_before(struct clk_core *core,
1171 struct clk_core *parent)
b2476490
MT
1172{
1173 unsigned long flags;
4dff95dc 1174 struct clk_core *old_parent = core->parent;
b2476490 1175
4dff95dc 1176 /*
fc8726a2
DA
1177 * 1. enable parents for CLK_OPS_PARENT_ENABLE clock
1178 *
1179 * 2. Migrate prepare state between parents and prevent race with
4dff95dc
SB
1180 * clk_enable().
1181 *
1182 * If the clock is not prepared, then a race with
1183 * clk_enable/disable() is impossible since we already have the
1184 * prepare lock (future calls to clk_enable() need to be preceded by
1185 * a clk_prepare()).
1186 *
1187 * If the clock is prepared, migrate the prepared state to the new
1188 * parent and also protect against a race with clk_enable() by
1189 * forcing the clock and the new parent on. This ensures that all
1190 * future calls to clk_enable() are practically NOPs with respect to
1191 * hardware and software states.
1192 *
1193 * See also: Comment for clk_set_parent() below.
1194 */
fc8726a2
DA
1195
1196 /* enable old_parent & parent if CLK_OPS_PARENT_ENABLE is set */
1197 if (core->flags & CLK_OPS_PARENT_ENABLE) {
1198 clk_core_prepare_enable(old_parent);
1199 clk_core_prepare_enable(parent);
1200 }
1201
1202 /* migrate prepare count if > 0 */
4dff95dc 1203 if (core->prepare_count) {
fc8726a2
DA
1204 clk_core_prepare_enable(parent);
1205 clk_core_enable_lock(core);
4dff95dc 1206 }
63589e92 1207
4dff95dc 1208 /* update the clk tree topology */
eab89f69 1209 flags = clk_enable_lock();
4dff95dc 1210 clk_reparent(core, parent);
eab89f69 1211 clk_enable_unlock(flags);
4dff95dc
SB
1212
1213 return old_parent;
b2476490 1214}
b2476490 1215
4dff95dc
SB
1216static void __clk_set_parent_after(struct clk_core *core,
1217 struct clk_core *parent,
1218 struct clk_core *old_parent)
b2476490 1219{
4dff95dc
SB
1220 /*
1221 * Finish the migration of prepare state and undo the changes done
1222 * for preventing a race with clk_enable().
1223 */
1224 if (core->prepare_count) {
fc8726a2
DA
1225 clk_core_disable_lock(core);
1226 clk_core_disable_unprepare(old_parent);
1227 }
1228
1229 /* re-balance ref counting if CLK_OPS_PARENT_ENABLE is set */
1230 if (core->flags & CLK_OPS_PARENT_ENABLE) {
1231 clk_core_disable_unprepare(parent);
1232 clk_core_disable_unprepare(old_parent);
4dff95dc
SB
1233 }
1234}
b2476490 1235
4dff95dc
SB
1236static int __clk_set_parent(struct clk_core *core, struct clk_core *parent,
1237 u8 p_index)
1238{
1239 unsigned long flags;
1240 int ret = 0;
1241 struct clk_core *old_parent;
b2476490 1242
4dff95dc 1243 old_parent = __clk_set_parent_before(core, parent);
b2476490 1244
4dff95dc 1245 trace_clk_set_parent(core, parent);
b2476490 1246
4dff95dc
SB
1247 /* change clock input source */
1248 if (parent && core->ops->set_parent)
1249 ret = core->ops->set_parent(core->hw, p_index);
dfc202ea 1250
4dff95dc 1251 trace_clk_set_parent_complete(core, parent);
dfc202ea 1252
4dff95dc
SB
1253 if (ret) {
1254 flags = clk_enable_lock();
1255 clk_reparent(core, old_parent);
1256 clk_enable_unlock(flags);
c660b2eb 1257 __clk_set_parent_after(core, old_parent, parent);
dfc202ea 1258
4dff95dc 1259 return ret;
b2476490
MT
1260 }
1261
4dff95dc
SB
1262 __clk_set_parent_after(core, parent, old_parent);
1263
b2476490
MT
1264 return 0;
1265}
1266
1267/**
4dff95dc
SB
1268 * __clk_speculate_rates
1269 * @core: first clk in the subtree
1270 * @parent_rate: the "future" rate of clk's parent
b2476490 1271 *
4dff95dc
SB
1272 * Walks the subtree of clks starting with clk, speculating rates as it
1273 * goes and firing off PRE_RATE_CHANGE notifications as necessary.
1274 *
1275 * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
1276 * pre-rate change notifications and returns early if no clks in the
1277 * subtree have subscribed to the notifications. Note that if a clk does not
1278 * implement the .recalc_rate callback then it is assumed that the clock will
1279 * take on the rate of its parent.
b2476490 1280 */
4dff95dc
SB
1281static int __clk_speculate_rates(struct clk_core *core,
1282 unsigned long parent_rate)
b2476490 1283{
4dff95dc
SB
1284 struct clk_core *child;
1285 unsigned long new_rate;
1286 int ret = NOTIFY_DONE;
b2476490 1287
4dff95dc 1288 lockdep_assert_held(&prepare_lock);
864e160a 1289
4dff95dc
SB
1290 new_rate = clk_recalc(core, parent_rate);
1291
1292 /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */
1293 if (core->notifier_count)
1294 ret = __clk_notify(core, PRE_RATE_CHANGE, core->rate, new_rate);
1295
1296 if (ret & NOTIFY_STOP_MASK) {
1297 pr_debug("%s: clk notifier callback for clock %s aborted with error %d\n",
1298 __func__, core->name, ret);
1299 goto out;
1300 }
1301
1302 hlist_for_each_entry(child, &core->children, child_node) {
1303 ret = __clk_speculate_rates(child, new_rate);
1304 if (ret & NOTIFY_STOP_MASK)
1305 break;
1306 }
b2476490 1307
4dff95dc 1308out:
b2476490
MT
1309 return ret;
1310}
b2476490 1311
4dff95dc
SB
1312static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate,
1313 struct clk_core *new_parent, u8 p_index)
b2476490 1314{
4dff95dc 1315 struct clk_core *child;
b2476490 1316
4dff95dc
SB
1317 core->new_rate = new_rate;
1318 core->new_parent = new_parent;
1319 core->new_parent_index = p_index;
1320 /* include clk in new parent's PRE_RATE_CHANGE notifications */
1321 core->new_child = NULL;
1322 if (new_parent && new_parent != core->parent)
1323 new_parent->new_child = core;
496eadf8 1324
4dff95dc
SB
1325 hlist_for_each_entry(child, &core->children, child_node) {
1326 child->new_rate = clk_recalc(child, new_rate);
1327 clk_calc_subtree(child, child->new_rate, NULL, 0);
1328 }
1329}
b2476490 1330
4dff95dc
SB
1331/*
1332 * calculate the new rates returning the topmost clock that has to be
1333 * changed.
1334 */
1335static struct clk_core *clk_calc_new_rates(struct clk_core *core,
1336 unsigned long rate)
1337{
1338 struct clk_core *top = core;
1339 struct clk_core *old_parent, *parent;
4dff95dc
SB
1340 unsigned long best_parent_rate = 0;
1341 unsigned long new_rate;
1342 unsigned long min_rate;
1343 unsigned long max_rate;
1344 int p_index = 0;
1345 long ret;
1346
1347 /* sanity */
1348 if (IS_ERR_OR_NULL(core))
1349 return NULL;
1350
1351 /* save parent rate, if it exists */
1352 parent = old_parent = core->parent;
71472c0c 1353 if (parent)
4dff95dc 1354 best_parent_rate = parent->rate;
71472c0c 1355
4dff95dc
SB
1356 clk_core_get_boundaries(core, &min_rate, &max_rate);
1357
1358 /* find the closest rate and parent clk/rate */
d6968fca 1359 if (core->ops->determine_rate) {
0817b62c
BB
1360 struct clk_rate_request req;
1361
1362 req.rate = rate;
1363 req.min_rate = min_rate;
1364 req.max_rate = max_rate;
1365 if (parent) {
1366 req.best_parent_hw = parent->hw;
1367 req.best_parent_rate = parent->rate;
1368 } else {
1369 req.best_parent_hw = NULL;
1370 req.best_parent_rate = 0;
1371 }
1372
1373 ret = core->ops->determine_rate(core->hw, &req);
4dff95dc
SB
1374 if (ret < 0)
1375 return NULL;
1c8e6004 1376
0817b62c
BB
1377 best_parent_rate = req.best_parent_rate;
1378 new_rate = req.rate;
1379 parent = req.best_parent_hw ? req.best_parent_hw->core : NULL;
4dff95dc
SB
1380 } else if (core->ops->round_rate) {
1381 ret = core->ops->round_rate(core->hw, rate,
0817b62c 1382 &best_parent_rate);
4dff95dc
SB
1383 if (ret < 0)
1384 return NULL;
035a61c3 1385
4dff95dc
SB
1386 new_rate = ret;
1387 if (new_rate < min_rate || new_rate > max_rate)
1388 return NULL;
1389 } else if (!parent || !(core->flags & CLK_SET_RATE_PARENT)) {
1390 /* pass-through clock without adjustable parent */
1391 core->new_rate = core->rate;
1392 return NULL;
1393 } else {
1394 /* pass-through clock with adjustable parent */
1395 top = clk_calc_new_rates(parent, rate);
1396 new_rate = parent->new_rate;
1397 goto out;
1398 }
1c8e6004 1399
4dff95dc
SB
1400 /* some clocks must be gated to change parent */
1401 if (parent != old_parent &&
1402 (core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
1403 pr_debug("%s: %s not gated but wants to reparent\n",
1404 __func__, core->name);
1405 return NULL;
1406 }
b2476490 1407
4dff95dc
SB
1408 /* try finding the new parent index */
1409 if (parent && core->num_parents > 1) {
1410 p_index = clk_fetch_parent_index(core, parent);
1411 if (p_index < 0) {
1412 pr_debug("%s: clk %s can not be parent of clk %s\n",
1413 __func__, parent->name, core->name);
1414 return NULL;
1415 }
1416 }
b2476490 1417
4dff95dc
SB
1418 if ((core->flags & CLK_SET_RATE_PARENT) && parent &&
1419 best_parent_rate != parent->rate)
1420 top = clk_calc_new_rates(parent, best_parent_rate);
035a61c3 1421
4dff95dc
SB
1422out:
1423 clk_calc_subtree(core, new_rate, parent, p_index);
b2476490 1424
4dff95dc 1425 return top;
b2476490 1426}
b2476490 1427
4dff95dc
SB
1428/*
1429 * Notify about rate changes in a subtree. Always walk down the whole tree
1430 * so that in case of an error we can walk down the whole tree again and
1431 * abort the change.
b2476490 1432 */
4dff95dc
SB
1433static struct clk_core *clk_propagate_rate_change(struct clk_core *core,
1434 unsigned long event)
b2476490 1435{
4dff95dc 1436 struct clk_core *child, *tmp_clk, *fail_clk = NULL;
b2476490
MT
1437 int ret = NOTIFY_DONE;
1438
4dff95dc
SB
1439 if (core->rate == core->new_rate)
1440 return NULL;
b2476490 1441
4dff95dc
SB
1442 if (core->notifier_count) {
1443 ret = __clk_notify(core, event, core->rate, core->new_rate);
1444 if (ret & NOTIFY_STOP_MASK)
1445 fail_clk = core;
b2476490
MT
1446 }
1447
4dff95dc
SB
1448 hlist_for_each_entry(child, &core->children, child_node) {
1449 /* Skip children who will be reparented to another clock */
1450 if (child->new_parent && child->new_parent != core)
1451 continue;
1452 tmp_clk = clk_propagate_rate_change(child, event);
1453 if (tmp_clk)
1454 fail_clk = tmp_clk;
1455 }
5279fc40 1456
4dff95dc
SB
1457 /* handle the new child who might not be in core->children yet */
1458 if (core->new_child) {
1459 tmp_clk = clk_propagate_rate_change(core->new_child, event);
1460 if (tmp_clk)
1461 fail_clk = tmp_clk;
1462 }
5279fc40 1463
4dff95dc 1464 return fail_clk;
5279fc40
BB
1465}
1466
4dff95dc
SB
1467/*
1468 * walk down a subtree and set the new rates notifying the rate
1469 * change on the way
1470 */
1471static void clk_change_rate(struct clk_core *core)
035a61c3 1472{
4dff95dc
SB
1473 struct clk_core *child;
1474 struct hlist_node *tmp;
1475 unsigned long old_rate;
1476 unsigned long best_parent_rate = 0;
1477 bool skip_set_rate = false;
1478 struct clk_core *old_parent;
fc8726a2 1479 struct clk_core *parent = NULL;
035a61c3 1480
4dff95dc 1481 old_rate = core->rate;
035a61c3 1482
fc8726a2
DA
1483 if (core->new_parent) {
1484 parent = core->new_parent;
4dff95dc 1485 best_parent_rate = core->new_parent->rate;
fc8726a2
DA
1486 } else if (core->parent) {
1487 parent = core->parent;
4dff95dc 1488 best_parent_rate = core->parent->rate;
fc8726a2 1489 }
035a61c3 1490
2eb8c710
HS
1491 if (core->flags & CLK_SET_RATE_UNGATE) {
1492 unsigned long flags;
1493
1494 clk_core_prepare(core);
1495 flags = clk_enable_lock();
1496 clk_core_enable(core);
1497 clk_enable_unlock(flags);
1498 }
1499
4dff95dc
SB
1500 if (core->new_parent && core->new_parent != core->parent) {
1501 old_parent = __clk_set_parent_before(core, core->new_parent);
1502 trace_clk_set_parent(core, core->new_parent);
5279fc40 1503
4dff95dc
SB
1504 if (core->ops->set_rate_and_parent) {
1505 skip_set_rate = true;
1506 core->ops->set_rate_and_parent(core->hw, core->new_rate,
1507 best_parent_rate,
1508 core->new_parent_index);
1509 } else if (core->ops->set_parent) {
1510 core->ops->set_parent(core->hw, core->new_parent_index);
1511 }
5279fc40 1512
4dff95dc
SB
1513 trace_clk_set_parent_complete(core, core->new_parent);
1514 __clk_set_parent_after(core, core->new_parent, old_parent);
1515 }
8f2c2db1 1516
fc8726a2
DA
1517 if (core->flags & CLK_OPS_PARENT_ENABLE)
1518 clk_core_prepare_enable(parent);
1519
4dff95dc 1520 trace_clk_set_rate(core, core->new_rate);
b2476490 1521
4dff95dc
SB
1522 if (!skip_set_rate && core->ops->set_rate)
1523 core->ops->set_rate(core->hw, core->new_rate, best_parent_rate);
496eadf8 1524
4dff95dc 1525 trace_clk_set_rate_complete(core, core->new_rate);
b2476490 1526
4dff95dc 1527 core->rate = clk_recalc(core, best_parent_rate);
b2476490 1528
2eb8c710
HS
1529 if (core->flags & CLK_SET_RATE_UNGATE) {
1530 unsigned long flags;
1531
1532 flags = clk_enable_lock();
1533 clk_core_disable(core);
1534 clk_enable_unlock(flags);
1535 clk_core_unprepare(core);
1536 }
1537
fc8726a2
DA
1538 if (core->flags & CLK_OPS_PARENT_ENABLE)
1539 clk_core_disable_unprepare(parent);
1540
4dff95dc
SB
1541 if (core->notifier_count && old_rate != core->rate)
1542 __clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate);
b2476490 1543
85e88fab
MT
1544 if (core->flags & CLK_RECALC_NEW_RATES)
1545 (void)clk_calc_new_rates(core, core->new_rate);
d8d91987 1546
b2476490 1547 /*
4dff95dc
SB
1548 * Use safe iteration, as change_rate can actually swap parents
1549 * for certain clock types.
b2476490 1550 */
4dff95dc
SB
1551 hlist_for_each_entry_safe(child, tmp, &core->children, child_node) {
1552 /* Skip children who will be reparented to another clock */
1553 if (child->new_parent && child->new_parent != core)
1554 continue;
1555 clk_change_rate(child);
1556 }
b2476490 1557
4dff95dc
SB
1558 /* handle the new child who might not be in core->children yet */
1559 if (core->new_child)
1560 clk_change_rate(core->new_child);
b2476490
MT
1561}
1562
4dff95dc
SB
1563static int clk_core_set_rate_nolock(struct clk_core *core,
1564 unsigned long req_rate)
a093bde2 1565{
4dff95dc
SB
1566 struct clk_core *top, *fail_clk;
1567 unsigned long rate = req_rate;
a093bde2 1568
4dff95dc
SB
1569 if (!core)
1570 return 0;
a093bde2 1571
4dff95dc
SB
1572 /* bail early if nothing to do */
1573 if (rate == clk_core_get_rate_nolock(core))
1574 return 0;
a093bde2 1575
4dff95dc
SB
1576 if ((core->flags & CLK_SET_RATE_GATE) && core->prepare_count)
1577 return -EBUSY;
a093bde2 1578
4dff95dc
SB
1579 /* calculate new rates and get the topmost changed clock */
1580 top = clk_calc_new_rates(core, rate);
1581 if (!top)
1582 return -EINVAL;
1583
1584 /* notify that we are about to change rates */
1585 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
1586 if (fail_clk) {
1587 pr_debug("%s: failed to set %s rate\n", __func__,
1588 fail_clk->name);
1589 clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
1590 return -EBUSY;
1591 }
1592
1593 /* change the rates */
1594 clk_change_rate(top);
1595
1596 core->req_rate = req_rate;
1597
06b37e4a 1598 return 0;
a093bde2 1599}
035a61c3
TV
1600
1601/**
4dff95dc
SB
1602 * clk_set_rate - specify a new rate for clk
1603 * @clk: the clk whose rate is being changed
1604 * @rate: the new rate for clk
035a61c3 1605 *
4dff95dc
SB
1606 * In the simplest case clk_set_rate will only adjust the rate of clk.
1607 *
1608 * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to
1609 * propagate up to clk's parent; whether or not this happens depends on the
1610 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
1611 * after calling .round_rate then upstream parent propagation is ignored. If
1612 * *parent_rate comes back with a new rate for clk's parent then we propagate
1613 * up to clk's parent and set its rate. Upward propagation will continue
1614 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
1615 * .round_rate stops requesting changes to clk's parent_rate.
1616 *
1617 * Rate changes are accomplished via tree traversal that also recalculates the
1618 * rates for the clocks and fires off POST_RATE_CHANGE notifiers.
1619 *
1620 * Returns 0 on success, -EERROR otherwise.
035a61c3 1621 */
4dff95dc 1622int clk_set_rate(struct clk *clk, unsigned long rate)
035a61c3 1623{
4dff95dc
SB
1624 int ret;
1625
035a61c3
TV
1626 if (!clk)
1627 return 0;
1628
4dff95dc
SB
1629 /* prevent racing with updates to the clock topology */
1630 clk_prepare_lock();
da0f0b2c 1631
4dff95dc 1632 ret = clk_core_set_rate_nolock(clk->core, rate);
da0f0b2c 1633
4dff95dc 1634 clk_prepare_unlock();
4935b22c 1635
4dff95dc 1636 return ret;
4935b22c 1637}
4dff95dc 1638EXPORT_SYMBOL_GPL(clk_set_rate);
4935b22c 1639
4dff95dc
SB
1640/**
1641 * clk_set_rate_range - set a rate range for a clock source
1642 * @clk: clock source
1643 * @min: desired minimum clock rate in Hz, inclusive
1644 * @max: desired maximum clock rate in Hz, inclusive
1645 *
1646 * Returns success (0) or negative errno.
1647 */
1648int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
4935b22c 1649{
4dff95dc 1650 int ret = 0;
4935b22c 1651
4dff95dc
SB
1652 if (!clk)
1653 return 0;
903efc55 1654
4dff95dc
SB
1655 if (min > max) {
1656 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n",
1657 __func__, clk->core->name, clk->dev_id, clk->con_id,
1658 min, max);
1659 return -EINVAL;
903efc55 1660 }
4935b22c 1661
4dff95dc 1662 clk_prepare_lock();
4935b22c 1663
4dff95dc
SB
1664 if (min != clk->min_rate || max != clk->max_rate) {
1665 clk->min_rate = min;
1666 clk->max_rate = max;
1667 ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
4935b22c
JH
1668 }
1669
4dff95dc 1670 clk_prepare_unlock();
4935b22c 1671
4dff95dc 1672 return ret;
3fa2252b 1673}
4dff95dc 1674EXPORT_SYMBOL_GPL(clk_set_rate_range);
3fa2252b 1675
4dff95dc
SB
1676/**
1677 * clk_set_min_rate - set a minimum clock rate for a clock source
1678 * @clk: clock source
1679 * @rate: desired minimum clock rate in Hz, inclusive
1680 *
1681 * Returns success (0) or negative errno.
1682 */
1683int clk_set_min_rate(struct clk *clk, unsigned long rate)
3fa2252b 1684{
4dff95dc
SB
1685 if (!clk)
1686 return 0;
1687
1688 return clk_set_rate_range(clk, rate, clk->max_rate);
3fa2252b 1689}
4dff95dc 1690EXPORT_SYMBOL_GPL(clk_set_min_rate);
3fa2252b 1691
4dff95dc
SB
1692/**
1693 * clk_set_max_rate - set a maximum clock rate for a clock source
1694 * @clk: clock source
1695 * @rate: desired maximum clock rate in Hz, inclusive
1696 *
1697 * Returns success (0) or negative errno.
1698 */
1699int clk_set_max_rate(struct clk *clk, unsigned long rate)
3fa2252b 1700{
4dff95dc
SB
1701 if (!clk)
1702 return 0;
4935b22c 1703
4dff95dc 1704 return clk_set_rate_range(clk, clk->min_rate, rate);
4935b22c 1705}
4dff95dc 1706EXPORT_SYMBOL_GPL(clk_set_max_rate);
4935b22c 1707
b2476490 1708/**
4dff95dc
SB
1709 * clk_get_parent - return the parent of a clk
1710 * @clk: the clk whose parent gets returned
b2476490 1711 *
4dff95dc 1712 * Simply returns clk->parent. Returns NULL if clk is NULL.
b2476490 1713 */
4dff95dc 1714struct clk *clk_get_parent(struct clk *clk)
b2476490 1715{
4dff95dc 1716 struct clk *parent;
b2476490 1717
fc4a05d4
SB
1718 if (!clk)
1719 return NULL;
1720
4dff95dc 1721 clk_prepare_lock();
fc4a05d4
SB
1722 /* TODO: Create a per-user clk and change callers to call clk_put */
1723 parent = !clk->core->parent ? NULL : clk->core->parent->hw->clk;
4dff95dc 1724 clk_prepare_unlock();
496eadf8 1725
4dff95dc
SB
1726 return parent;
1727}
1728EXPORT_SYMBOL_GPL(clk_get_parent);
b2476490 1729
4dff95dc
SB
1730static struct clk_core *__clk_init_parent(struct clk_core *core)
1731{
5146e0b0 1732 u8 index = 0;
4dff95dc 1733
2430a94d 1734 if (core->num_parents > 1 && core->ops->get_parent)
5146e0b0 1735 index = core->ops->get_parent(core->hw);
b2476490 1736
5146e0b0 1737 return clk_core_get_parent_by_index(core, index);
b2476490
MT
1738}
1739
4dff95dc
SB
1740static void clk_core_reparent(struct clk_core *core,
1741 struct clk_core *new_parent)
b2476490 1742{
4dff95dc
SB
1743 clk_reparent(core, new_parent);
1744 __clk_recalc_accuracies(core);
1745 __clk_recalc_rates(core, POST_RATE_CHANGE);
b2476490
MT
1746}
1747
42c86547
TV
1748void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent)
1749{
1750 if (!hw)
1751 return;
1752
1753 clk_core_reparent(hw->core, !new_parent ? NULL : new_parent->core);
1754}
1755
4dff95dc
SB
1756/**
1757 * clk_has_parent - check if a clock is a possible parent for another
1758 * @clk: clock source
1759 * @parent: parent clock source
1760 *
1761 * This function can be used in drivers that need to check that a clock can be
1762 * the parent of another without actually changing the parent.
1763 *
1764 * Returns true if @parent is a possible parent for @clk, false otherwise.
b2476490 1765 */
4dff95dc 1766bool clk_has_parent(struct clk *clk, struct clk *parent)
b2476490 1767{
4dff95dc
SB
1768 struct clk_core *core, *parent_core;
1769 unsigned int i;
b2476490 1770
4dff95dc
SB
1771 /* NULL clocks should be nops, so return success if either is NULL. */
1772 if (!clk || !parent)
1773 return true;
7452b219 1774
4dff95dc
SB
1775 core = clk->core;
1776 parent_core = parent->core;
71472c0c 1777
4dff95dc
SB
1778 /* Optimize for the case where the parent is already the parent. */
1779 if (core->parent == parent_core)
1780 return true;
1c8e6004 1781
4dff95dc
SB
1782 for (i = 0; i < core->num_parents; i++)
1783 if (strcmp(core->parent_names[i], parent_core->name) == 0)
1784 return true;
03bc10ab 1785
4dff95dc
SB
1786 return false;
1787}
1788EXPORT_SYMBOL_GPL(clk_has_parent);
03bc10ab 1789
4dff95dc
SB
1790static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
1791{
1792 int ret = 0;
1793 int p_index = 0;
1794 unsigned long p_rate = 0;
1795
1796 if (!core)
1797 return 0;
1798
1799 /* prevent racing with updates to the clock topology */
1800 clk_prepare_lock();
1801
1802 if (core->parent == parent)
1803 goto out;
1804
1805 /* verify ops for for multi-parent clks */
1806 if ((core->num_parents > 1) && (!core->ops->set_parent)) {
1807 ret = -ENOSYS;
63f5c3b2 1808 goto out;
7452b219
MT
1809 }
1810
4dff95dc
SB
1811 /* check that we are allowed to re-parent if the clock is in use */
1812 if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
1813 ret = -EBUSY;
1814 goto out;
b2476490
MT
1815 }
1816
71472c0c 1817 /* try finding the new parent index */
4dff95dc 1818 if (parent) {
d6968fca 1819 p_index = clk_fetch_parent_index(core, parent);
f1c8b2ed 1820 if (p_index < 0) {
71472c0c 1821 pr_debug("%s: clk %s can not be parent of clk %s\n",
4dff95dc
SB
1822 __func__, parent->name, core->name);
1823 ret = p_index;
1824 goto out;
71472c0c 1825 }
e8f0e68e 1826 p_rate = parent->rate;
b2476490
MT
1827 }
1828
4dff95dc
SB
1829 /* propagate PRE_RATE_CHANGE notifications */
1830 ret = __clk_speculate_rates(core, p_rate);
b2476490 1831
4dff95dc
SB
1832 /* abort if a driver objects */
1833 if (ret & NOTIFY_STOP_MASK)
1834 goto out;
b2476490 1835
4dff95dc
SB
1836 /* do the re-parent */
1837 ret = __clk_set_parent(core, parent, p_index);
b2476490 1838
4dff95dc
SB
1839 /* propagate rate an accuracy recalculation accordingly */
1840 if (ret) {
1841 __clk_recalc_rates(core, ABORT_RATE_CHANGE);
1842 } else {
1843 __clk_recalc_rates(core, POST_RATE_CHANGE);
1844 __clk_recalc_accuracies(core);
b2476490
MT
1845 }
1846
4dff95dc
SB
1847out:
1848 clk_prepare_unlock();
71472c0c 1849
4dff95dc
SB
1850 return ret;
1851}
b2476490 1852
4dff95dc
SB
1853/**
1854 * clk_set_parent - switch the parent of a mux clk
1855 * @clk: the mux clk whose input we are switching
1856 * @parent: the new input to clk
1857 *
1858 * Re-parent clk to use parent as its new input source. If clk is in
1859 * prepared state, the clk will get enabled for the duration of this call. If
1860 * that's not acceptable for a specific clk (Eg: the consumer can't handle
1861 * that, the reparenting is glitchy in hardware, etc), use the
1862 * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
1863 *
1864 * After successfully changing clk's parent clk_set_parent will update the
1865 * clk topology, sysfs topology and propagate rate recalculation via
1866 * __clk_recalc_rates.
1867 *
1868 * Returns 0 on success, -EERROR otherwise.
1869 */
1870int clk_set_parent(struct clk *clk, struct clk *parent)
1871{
1872 if (!clk)
1873 return 0;
1874
1875 return clk_core_set_parent(clk->core, parent ? parent->core : NULL);
b2476490 1876}
4dff95dc 1877EXPORT_SYMBOL_GPL(clk_set_parent);
b2476490 1878
4dff95dc
SB
1879/**
1880 * clk_set_phase - adjust the phase shift of a clock signal
1881 * @clk: clock signal source
1882 * @degrees: number of degrees the signal is shifted
1883 *
1884 * Shifts the phase of a clock signal by the specified
1885 * degrees. Returns 0 on success, -EERROR otherwise.
1886 *
1887 * This function makes no distinction about the input or reference
1888 * signal that we adjust the clock signal phase against. For example
1889 * phase locked-loop clock signal generators we may shift phase with
1890 * respect to feedback clock signal input, but for other cases the
1891 * clock phase may be shifted with respect to some other, unspecified
1892 * signal.
1893 *
1894 * Additionally the concept of phase shift does not propagate through
1895 * the clock tree hierarchy, which sets it apart from clock rates and
1896 * clock accuracy. A parent clock phase attribute does not have an
1897 * impact on the phase attribute of a child clock.
b2476490 1898 */
4dff95dc 1899int clk_set_phase(struct clk *clk, int degrees)
b2476490 1900{
4dff95dc 1901 int ret = -EINVAL;
b2476490 1902
4dff95dc
SB
1903 if (!clk)
1904 return 0;
b2476490 1905
4dff95dc
SB
1906 /* sanity check degrees */
1907 degrees %= 360;
1908 if (degrees < 0)
1909 degrees += 360;
bf47b4fd 1910
4dff95dc 1911 clk_prepare_lock();
3fa2252b 1912
4dff95dc 1913 trace_clk_set_phase(clk->core, degrees);
3fa2252b 1914
4dff95dc
SB
1915 if (clk->core->ops->set_phase)
1916 ret = clk->core->ops->set_phase(clk->core->hw, degrees);
3fa2252b 1917
4dff95dc 1918 trace_clk_set_phase_complete(clk->core, degrees);
dfc202ea 1919
4dff95dc
SB
1920 if (!ret)
1921 clk->core->phase = degrees;
b2476490 1922
4dff95dc 1923 clk_prepare_unlock();
dfc202ea 1924
4dff95dc
SB
1925 return ret;
1926}
1927EXPORT_SYMBOL_GPL(clk_set_phase);
b2476490 1928
4dff95dc
SB
1929static int clk_core_get_phase(struct clk_core *core)
1930{
1931 int ret;
b2476490 1932
4dff95dc
SB
1933 clk_prepare_lock();
1934 ret = core->phase;
1935 clk_prepare_unlock();
71472c0c 1936
4dff95dc 1937 return ret;
b2476490
MT
1938}
1939
4dff95dc
SB
1940/**
1941 * clk_get_phase - return the phase shift of a clock signal
1942 * @clk: clock signal source
1943 *
1944 * Returns the phase shift of a clock node in degrees, otherwise returns
1945 * -EERROR.
1946 */
1947int clk_get_phase(struct clk *clk)
1c8e6004 1948{
4dff95dc 1949 if (!clk)
1c8e6004
TV
1950 return 0;
1951
4dff95dc
SB
1952 return clk_core_get_phase(clk->core);
1953}
1954EXPORT_SYMBOL_GPL(clk_get_phase);
1c8e6004 1955
4dff95dc
SB
1956/**
1957 * clk_is_match - check if two clk's point to the same hardware clock
1958 * @p: clk compared against q
1959 * @q: clk compared against p
1960 *
1961 * Returns true if the two struct clk pointers both point to the same hardware
1962 * clock node. Put differently, returns true if struct clk *p and struct clk *q
1963 * share the same struct clk_core object.
1964 *
1965 * Returns false otherwise. Note that two NULL clks are treated as matching.
1966 */
1967bool clk_is_match(const struct clk *p, const struct clk *q)
1968{
1969 /* trivial case: identical struct clk's or both NULL */
1970 if (p == q)
1971 return true;
1c8e6004 1972
3fe003f9 1973 /* true if clk->core pointers match. Avoid dereferencing garbage */
4dff95dc
SB
1974 if (!IS_ERR_OR_NULL(p) && !IS_ERR_OR_NULL(q))
1975 if (p->core == q->core)
1976 return true;
1c8e6004 1977
4dff95dc
SB
1978 return false;
1979}
1980EXPORT_SYMBOL_GPL(clk_is_match);
1c8e6004 1981
4dff95dc 1982/*** debugfs support ***/
1c8e6004 1983
4dff95dc
SB
1984#ifdef CONFIG_DEBUG_FS
1985#include <linux/debugfs.h>
1c8e6004 1986
4dff95dc
SB
1987static struct dentry *rootdir;
1988static int inited = 0;
1989static DEFINE_MUTEX(clk_debug_lock);
1990static HLIST_HEAD(clk_debug_list);
1c8e6004 1991
4dff95dc
SB
1992static struct hlist_head *all_lists[] = {
1993 &clk_root_list,
1994 &clk_orphan_list,
1995 NULL,
1996};
1997
1998static struct hlist_head *orphan_list[] = {
1999 &clk_orphan_list,
2000 NULL,
2001};
2002
2003static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
2004 int level)
b2476490 2005{
4dff95dc
SB
2006 if (!c)
2007 return;
b2476490 2008
4dff95dc
SB
2009 seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n",
2010 level * 3 + 1, "",
2011 30 - level * 3, c->name,
2012 c->enable_count, c->prepare_count, clk_core_get_rate(c),
2013 clk_core_get_accuracy(c), clk_core_get_phase(c));
2014}
89ac8d7a 2015
4dff95dc
SB
2016static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
2017 int level)
2018{
2019 struct clk_core *child;
b2476490 2020
4dff95dc
SB
2021 if (!c)
2022 return;
b2476490 2023
4dff95dc 2024 clk_summary_show_one(s, c, level);
0e1c0301 2025
4dff95dc
SB
2026 hlist_for_each_entry(child, &c->children, child_node)
2027 clk_summary_show_subtree(s, child, level + 1);
1c8e6004 2028}
b2476490 2029
4dff95dc 2030static int clk_summary_show(struct seq_file *s, void *data)
1c8e6004 2031{
4dff95dc
SB
2032 struct clk_core *c;
2033 struct hlist_head **lists = (struct hlist_head **)s->private;
1c8e6004 2034
4dff95dc
SB
2035 seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n");
2036 seq_puts(s, "----------------------------------------------------------------------------------------\n");
b2476490 2037
1c8e6004
TV
2038 clk_prepare_lock();
2039
4dff95dc
SB
2040 for (; *lists; lists++)
2041 hlist_for_each_entry(c, *lists, child_node)
2042 clk_summary_show_subtree(s, c, 0);
b2476490 2043
eab89f69 2044 clk_prepare_unlock();
b2476490 2045
4dff95dc 2046 return 0;
b2476490 2047}
1c8e6004 2048
1c8e6004 2049
4dff95dc 2050static int clk_summary_open(struct inode *inode, struct file *file)
1c8e6004 2051{
4dff95dc 2052 return single_open(file, clk_summary_show, inode->i_private);
1c8e6004 2053}
b2476490 2054
4dff95dc
SB
2055static const struct file_operations clk_summary_fops = {
2056 .open = clk_summary_open,
2057 .read = seq_read,
2058 .llseek = seq_lseek,
2059 .release = single_release,
2060};
b2476490 2061
4dff95dc
SB
2062static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
2063{
2064 if (!c)
2065 return;
b2476490 2066
7cb81136 2067 /* This should be JSON format, i.e. elements separated with a comma */
4dff95dc
SB
2068 seq_printf(s, "\"%s\": { ", c->name);
2069 seq_printf(s, "\"enable_count\": %d,", c->enable_count);
2070 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
7cb81136
SW
2071 seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
2072 seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
4dff95dc 2073 seq_printf(s, "\"phase\": %d", clk_core_get_phase(c));
b2476490 2074}
b2476490 2075
4dff95dc 2076static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
b2476490 2077{
4dff95dc 2078 struct clk_core *child;
b2476490 2079
4dff95dc
SB
2080 if (!c)
2081 return;
b2476490 2082
4dff95dc 2083 clk_dump_one(s, c, level);
b2476490 2084
4dff95dc 2085 hlist_for_each_entry(child, &c->children, child_node) {
4d327586 2086 seq_putc(s, ',');
4dff95dc 2087 clk_dump_subtree(s, child, level + 1);
b2476490
MT
2088 }
2089
4d327586 2090 seq_putc(s, '}');
b2476490
MT
2091}
2092
4dff95dc 2093static int clk_dump(struct seq_file *s, void *data)
4e88f3de 2094{
4dff95dc
SB
2095 struct clk_core *c;
2096 bool first_node = true;
2097 struct hlist_head **lists = (struct hlist_head **)s->private;
4e88f3de 2098
4d327586 2099 seq_putc(s, '{');
4dff95dc 2100 clk_prepare_lock();
035a61c3 2101
4dff95dc
SB
2102 for (; *lists; lists++) {
2103 hlist_for_each_entry(c, *lists, child_node) {
2104 if (!first_node)
4d327586 2105 seq_putc(s, ',');
4dff95dc
SB
2106 first_node = false;
2107 clk_dump_subtree(s, c, 0);
2108 }
2109 }
4e88f3de 2110
4dff95dc 2111 clk_prepare_unlock();
4e88f3de 2112
70e9f4dd 2113 seq_puts(s, "}\n");
4dff95dc 2114 return 0;
4e88f3de 2115}
4e88f3de 2116
4dff95dc
SB
2117
2118static int clk_dump_open(struct inode *inode, struct file *file)
b2476490 2119{
4dff95dc
SB
2120 return single_open(file, clk_dump, inode->i_private);
2121}
b2476490 2122
4dff95dc
SB
2123static const struct file_operations clk_dump_fops = {
2124 .open = clk_dump_open,
2125 .read = seq_read,
2126 .llseek = seq_lseek,
2127 .release = single_release,
2128};
89ac8d7a 2129
92031575
PDS
2130static int possible_parents_dump(struct seq_file *s, void *data)
2131{
2132 struct clk_core *core = s->private;
2133 int i;
2134
2135 for (i = 0; i < core->num_parents - 1; i++)
2136 seq_printf(s, "%s ", core->parent_names[i]);
2137
2138 seq_printf(s, "%s\n", core->parent_names[i]);
2139
2140 return 0;
2141}
2142
2143static int possible_parents_open(struct inode *inode, struct file *file)
2144{
2145 return single_open(file, possible_parents_dump, inode->i_private);
2146}
2147
2148static const struct file_operations possible_parents_fops = {
2149 .open = possible_parents_open,
2150 .read = seq_read,
2151 .llseek = seq_lseek,
2152 .release = single_release,
2153};
2154
4dff95dc
SB
2155static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
2156{
2157 struct dentry *d;
2158 int ret = -ENOMEM;
b2476490 2159
4dff95dc
SB
2160 if (!core || !pdentry) {
2161 ret = -EINVAL;
b2476490 2162 goto out;
4dff95dc 2163 }
b2476490 2164
4dff95dc
SB
2165 d = debugfs_create_dir(core->name, pdentry);
2166 if (!d)
b61c43c0 2167 goto out;
b61c43c0 2168
4dff95dc
SB
2169 core->dentry = d;
2170
2171 d = debugfs_create_u32("clk_rate", S_IRUGO, core->dentry,
2172 (u32 *)&core->rate);
2173 if (!d)
2174 goto err_out;
2175
2176 d = debugfs_create_u32("clk_accuracy", S_IRUGO, core->dentry,
2177 (u32 *)&core->accuracy);
2178 if (!d)
2179 goto err_out;
2180
2181 d = debugfs_create_u32("clk_phase", S_IRUGO, core->dentry,
2182 (u32 *)&core->phase);
2183 if (!d)
2184 goto err_out;
031dcc9b 2185
4dff95dc
SB
2186 d = debugfs_create_x32("clk_flags", S_IRUGO, core->dentry,
2187 (u32 *)&core->flags);
2188 if (!d)
2189 goto err_out;
031dcc9b 2190
4dff95dc
SB
2191 d = debugfs_create_u32("clk_prepare_count", S_IRUGO, core->dentry,
2192 (u32 *)&core->prepare_count);
2193 if (!d)
2194 goto err_out;
b2476490 2195
4dff95dc
SB
2196 d = debugfs_create_u32("clk_enable_count", S_IRUGO, core->dentry,
2197 (u32 *)&core->enable_count);
2198 if (!d)
2199 goto err_out;
b2476490 2200
4dff95dc
SB
2201 d = debugfs_create_u32("clk_notifier_count", S_IRUGO, core->dentry,
2202 (u32 *)&core->notifier_count);
2203 if (!d)
2204 goto err_out;
b2476490 2205
92031575
PDS
2206 if (core->num_parents > 1) {
2207 d = debugfs_create_file("clk_possible_parents", S_IRUGO,
2208 core->dentry, core, &possible_parents_fops);
2209 if (!d)
2210 goto err_out;
2211 }
2212
4dff95dc
SB
2213 if (core->ops->debug_init) {
2214 ret = core->ops->debug_init(core->hw, core->dentry);
2215 if (ret)
2216 goto err_out;
5279fc40 2217 }
b2476490 2218
4dff95dc
SB
2219 ret = 0;
2220 goto out;
b2476490 2221
4dff95dc
SB
2222err_out:
2223 debugfs_remove_recursive(core->dentry);
2224 core->dentry = NULL;
2225out:
b2476490
MT
2226 return ret;
2227}
035a61c3
TV
2228
2229/**
6e5ab41b
SB
2230 * clk_debug_register - add a clk node to the debugfs clk directory
2231 * @core: the clk being added to the debugfs clk directory
035a61c3 2232 *
6e5ab41b
SB
2233 * Dynamically adds a clk to the debugfs clk directory if debugfs has been
2234 * initialized. Otherwise it bails out early since the debugfs clk directory
4dff95dc 2235 * will be created lazily by clk_debug_init as part of a late_initcall.
035a61c3 2236 */
4dff95dc 2237static int clk_debug_register(struct clk_core *core)
035a61c3 2238{
4dff95dc 2239 int ret = 0;
035a61c3 2240
4dff95dc
SB
2241 mutex_lock(&clk_debug_lock);
2242 hlist_add_head(&core->debug_node, &clk_debug_list);
2243
2244 if (!inited)
2245 goto unlock;
2246
2247 ret = clk_debug_create_one(core, rootdir);
2248unlock:
2249 mutex_unlock(&clk_debug_lock);
2250
2251 return ret;
035a61c3 2252}
b2476490 2253
4dff95dc 2254 /**
6e5ab41b
SB
2255 * clk_debug_unregister - remove a clk node from the debugfs clk directory
2256 * @core: the clk being removed from the debugfs clk directory
e59c5371 2257 *
6e5ab41b
SB
2258 * Dynamically removes a clk and all its child nodes from the
2259 * debugfs clk directory if clk->dentry points to debugfs created by
706d5c73 2260 * clk_debug_register in __clk_core_init.
e59c5371 2261 */
4dff95dc 2262static void clk_debug_unregister(struct clk_core *core)
e59c5371 2263{
4dff95dc
SB
2264 mutex_lock(&clk_debug_lock);
2265 hlist_del_init(&core->debug_node);
2266 debugfs_remove_recursive(core->dentry);
2267 core->dentry = NULL;
2268 mutex_unlock(&clk_debug_lock);
2269}
e59c5371 2270
4dff95dc
SB
2271struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
2272 void *data, const struct file_operations *fops)
2273{
2274 struct dentry *d = NULL;
e59c5371 2275
4dff95dc
SB
2276 if (hw->core->dentry)
2277 d = debugfs_create_file(name, mode, hw->core->dentry, data,
2278 fops);
e59c5371 2279
4dff95dc
SB
2280 return d;
2281}
2282EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
e59c5371 2283
4dff95dc 2284/**
6e5ab41b 2285 * clk_debug_init - lazily populate the debugfs clk directory
4dff95dc 2286 *
6e5ab41b
SB
2287 * clks are often initialized very early during boot before memory can be
2288 * dynamically allocated and well before debugfs is setup. This function
2289 * populates the debugfs clk directory once at boot-time when we know that
2290 * debugfs is setup. It should only be called once at boot-time, all other clks
2291 * added dynamically will be done so with clk_debug_register.
4dff95dc
SB
2292 */
2293static int __init clk_debug_init(void)
2294{
2295 struct clk_core *core;
2296 struct dentry *d;
dfc202ea 2297
4dff95dc 2298 rootdir = debugfs_create_dir("clk", NULL);
e59c5371 2299
4dff95dc
SB
2300 if (!rootdir)
2301 return -ENOMEM;
dfc202ea 2302
4dff95dc
SB
2303 d = debugfs_create_file("clk_summary", S_IRUGO, rootdir, &all_lists,
2304 &clk_summary_fops);
2305 if (!d)
2306 return -ENOMEM;
e59c5371 2307
4dff95dc
SB
2308 d = debugfs_create_file("clk_dump", S_IRUGO, rootdir, &all_lists,
2309 &clk_dump_fops);
2310 if (!d)
2311 return -ENOMEM;
e59c5371 2312
4dff95dc
SB
2313 d = debugfs_create_file("clk_orphan_summary", S_IRUGO, rootdir,
2314 &orphan_list, &clk_summary_fops);
2315 if (!d)
2316 return -ENOMEM;
e59c5371 2317
4dff95dc
SB
2318 d = debugfs_create_file("clk_orphan_dump", S_IRUGO, rootdir,
2319 &orphan_list, &clk_dump_fops);
2320 if (!d)
2321 return -ENOMEM;
e59c5371 2322
4dff95dc
SB
2323 mutex_lock(&clk_debug_lock);
2324 hlist_for_each_entry(core, &clk_debug_list, debug_node)
2325 clk_debug_create_one(core, rootdir);
e59c5371 2326
4dff95dc
SB
2327 inited = 1;
2328 mutex_unlock(&clk_debug_lock);
e59c5371 2329
4dff95dc
SB
2330 return 0;
2331}
2332late_initcall(clk_debug_init);
2333#else
2334static inline int clk_debug_register(struct clk_core *core) { return 0; }
2335static inline void clk_debug_reparent(struct clk_core *core,
2336 struct clk_core *new_parent)
035a61c3 2337{
035a61c3 2338}
4dff95dc 2339static inline void clk_debug_unregister(struct clk_core *core)
3d3801ef 2340{
3d3801ef 2341}
4dff95dc 2342#endif
3d3801ef 2343
b2476490 2344/**
be45ebf2 2345 * __clk_core_init - initialize the data structures in a struct clk_core
d35c80c2 2346 * @core: clk_core being initialized
b2476490 2347 *
035a61c3 2348 * Initializes the lists in struct clk_core, queries the hardware for the
b2476490 2349 * parent and rate and sets them both.
b2476490 2350 */
be45ebf2 2351static int __clk_core_init(struct clk_core *core)
b2476490 2352{
d1302a36 2353 int i, ret = 0;
035a61c3 2354 struct clk_core *orphan;
b67bfe0d 2355 struct hlist_node *tmp2;
1c8e6004 2356 unsigned long rate;
b2476490 2357
d35c80c2 2358 if (!core)
d1302a36 2359 return -EINVAL;
b2476490 2360
eab89f69 2361 clk_prepare_lock();
b2476490
MT
2362
2363 /* check to see if a clock with this name is already registered */
d6968fca 2364 if (clk_core_lookup(core->name)) {
d1302a36 2365 pr_debug("%s: clk %s already initialized\n",
d6968fca 2366 __func__, core->name);
d1302a36 2367 ret = -EEXIST;
b2476490 2368 goto out;
d1302a36 2369 }
b2476490 2370
d4d7e3dd 2371 /* check that clk_ops are sane. See Documentation/clk.txt */
d6968fca
SB
2372 if (core->ops->set_rate &&
2373 !((core->ops->round_rate || core->ops->determine_rate) &&
2374 core->ops->recalc_rate)) {
c44fccb5
MY
2375 pr_err("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
2376 __func__, core->name);
d1302a36 2377 ret = -EINVAL;
d4d7e3dd
MT
2378 goto out;
2379 }
2380
d6968fca 2381 if (core->ops->set_parent && !core->ops->get_parent) {
c44fccb5
MY
2382 pr_err("%s: %s must implement .get_parent & .set_parent\n",
2383 __func__, core->name);
d1302a36 2384 ret = -EINVAL;
d4d7e3dd
MT
2385 goto out;
2386 }
2387
3c8e77dd
MY
2388 if (core->num_parents > 1 && !core->ops->get_parent) {
2389 pr_err("%s: %s must implement .get_parent as it has multi parents\n",
2390 __func__, core->name);
2391 ret = -EINVAL;
2392 goto out;
2393 }
2394
d6968fca
SB
2395 if (core->ops->set_rate_and_parent &&
2396 !(core->ops->set_parent && core->ops->set_rate)) {
c44fccb5 2397 pr_err("%s: %s must implement .set_parent & .set_rate\n",
d6968fca 2398 __func__, core->name);
3fa2252b
SB
2399 ret = -EINVAL;
2400 goto out;
2401 }
2402
b2476490 2403 /* throw a WARN if any entries in parent_names are NULL */
d6968fca
SB
2404 for (i = 0; i < core->num_parents; i++)
2405 WARN(!core->parent_names[i],
b2476490 2406 "%s: invalid NULL in %s's .parent_names\n",
d6968fca 2407 __func__, core->name);
b2476490 2408
d6968fca 2409 core->parent = __clk_init_parent(core);
b2476490
MT
2410
2411 /*
706d5c73
SB
2412 * Populate core->parent if parent has already been clk_core_init'd. If
2413 * parent has not yet been clk_core_init'd then place clk in the orphan
47b0eeb3 2414 * list. If clk doesn't have any parents then place it in the root
b2476490
MT
2415 * clk list.
2416 *
2417 * Every time a new clk is clk_init'd then we walk the list of orphan
2418 * clocks and re-parent any that are children of the clock currently
2419 * being clk_init'd.
2420 */
e6500344 2421 if (core->parent) {
d6968fca
SB
2422 hlist_add_head(&core->child_node,
2423 &core->parent->children);
e6500344 2424 core->orphan = core->parent->orphan;
47b0eeb3 2425 } else if (!core->num_parents) {
d6968fca 2426 hlist_add_head(&core->child_node, &clk_root_list);
e6500344
HS
2427 core->orphan = false;
2428 } else {
d6968fca 2429 hlist_add_head(&core->child_node, &clk_orphan_list);
e6500344
HS
2430 core->orphan = true;
2431 }
b2476490 2432
5279fc40
BB
2433 /*
2434 * Set clk's accuracy. The preferred method is to use
2435 * .recalc_accuracy. For simple clocks and lazy developers the default
2436 * fallback is to use the parent's accuracy. If a clock doesn't have a
2437 * parent (or is orphaned) then accuracy is set to zero (perfect
2438 * clock).
2439 */
d6968fca
SB
2440 if (core->ops->recalc_accuracy)
2441 core->accuracy = core->ops->recalc_accuracy(core->hw,
2442 __clk_get_accuracy(core->parent));
2443 else if (core->parent)
2444 core->accuracy = core->parent->accuracy;
5279fc40 2445 else
d6968fca 2446 core->accuracy = 0;
5279fc40 2447
9824cf73
MR
2448 /*
2449 * Set clk's phase.
2450 * Since a phase is by definition relative to its parent, just
2451 * query the current clock phase, or just assume it's in phase.
2452 */
d6968fca
SB
2453 if (core->ops->get_phase)
2454 core->phase = core->ops->get_phase(core->hw);
9824cf73 2455 else
d6968fca 2456 core->phase = 0;
9824cf73 2457
b2476490
MT
2458 /*
2459 * Set clk's rate. The preferred method is to use .recalc_rate. For
2460 * simple clocks and lazy developers the default fallback is to use the
2461 * parent's rate. If a clock doesn't have a parent (or is orphaned)
2462 * then rate is set to zero.
2463 */
d6968fca
SB
2464 if (core->ops->recalc_rate)
2465 rate = core->ops->recalc_rate(core->hw,
2466 clk_core_get_rate_nolock(core->parent));
2467 else if (core->parent)
2468 rate = core->parent->rate;
b2476490 2469 else
1c8e6004 2470 rate = 0;
d6968fca 2471 core->rate = core->req_rate = rate;
b2476490
MT
2472
2473 /*
0e8f6e49
MY
2474 * walk the list of orphan clocks and reparent any that newly finds a
2475 * parent.
b2476490 2476 */
b67bfe0d 2477 hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
0e8f6e49 2478 struct clk_core *parent = __clk_init_parent(orphan);
1f61e5f1 2479
904e6ead
MT
2480 /*
2481 * we could call __clk_set_parent, but that would result in a
2482 * redundant call to the .set_rate op, if it exists
2483 */
2484 if (parent) {
2485 __clk_set_parent_before(orphan, parent);
2486 __clk_set_parent_after(orphan, parent, NULL);
2487 __clk_recalc_accuracies(orphan);
2488 __clk_recalc_rates(orphan, 0);
2489 }
0e8f6e49 2490 }
b2476490
MT
2491
2492 /*
2493 * optional platform-specific magic
2494 *
2495 * The .init callback is not used by any of the basic clock types, but
2496 * exists for weird hardware that must perform initialization magic.
2497 * Please consider other ways of solving initialization problems before
24ee1a08 2498 * using this callback, as its use is discouraged.
b2476490 2499 */
d6968fca
SB
2500 if (core->ops->init)
2501 core->ops->init(core->hw);
b2476490 2502
32b9b109 2503 if (core->flags & CLK_IS_CRITICAL) {
ef56b79b
MR
2504 unsigned long flags;
2505
32b9b109 2506 clk_core_prepare(core);
ef56b79b
MR
2507
2508 flags = clk_enable_lock();
32b9b109 2509 clk_core_enable(core);
ef56b79b 2510 clk_enable_unlock(flags);
32b9b109
LJ
2511 }
2512
d6968fca 2513 kref_init(&core->ref);
b2476490 2514out:
eab89f69 2515 clk_prepare_unlock();
b2476490 2516
89f7e9de 2517 if (!ret)
d6968fca 2518 clk_debug_register(core);
89f7e9de 2519
d1302a36 2520 return ret;
b2476490
MT
2521}
2522
035a61c3
TV
2523struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
2524 const char *con_id)
0197b3ea 2525{
0197b3ea
SK
2526 struct clk *clk;
2527
035a61c3 2528 /* This is to allow this function to be chained to others */
c1de1357 2529 if (IS_ERR_OR_NULL(hw))
8a23133c 2530 return ERR_CAST(hw);
0197b3ea 2531
035a61c3
TV
2532 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
2533 if (!clk)
2534 return ERR_PTR(-ENOMEM);
2535
2536 clk->core = hw->core;
2537 clk->dev_id = dev_id;
253160a8 2538 clk->con_id = kstrdup_const(con_id, GFP_KERNEL);
1c8e6004
TV
2539 clk->max_rate = ULONG_MAX;
2540
2541 clk_prepare_lock();
50595f8b 2542 hlist_add_head(&clk->clks_node, &hw->core->clks);
1c8e6004 2543 clk_prepare_unlock();
0197b3ea
SK
2544
2545 return clk;
2546}
035a61c3 2547
73e0e496 2548void __clk_free_clk(struct clk *clk)
1c8e6004
TV
2549{
2550 clk_prepare_lock();
50595f8b 2551 hlist_del(&clk->clks_node);
1c8e6004
TV
2552 clk_prepare_unlock();
2553
253160a8 2554 kfree_const(clk->con_id);
1c8e6004
TV
2555 kfree(clk);
2556}
0197b3ea 2557
293ba3b4
SB
2558/**
2559 * clk_register - allocate a new clock, register it and return an opaque cookie
2560 * @dev: device that is registering this clock
2561 * @hw: link to hardware-specific clock data
2562 *
2563 * clk_register is the primary interface for populating the clock tree with new
2564 * clock nodes. It returns a pointer to the newly allocated struct clk which
a59a5163 2565 * cannot be dereferenced by driver code but may be used in conjunction with the
293ba3b4
SB
2566 * rest of the clock API. In the event of an error clk_register will return an
2567 * error code; drivers must test for an error code after calling clk_register.
2568 */
2569struct clk *clk_register(struct device *dev, struct clk_hw *hw)
b2476490 2570{
d1302a36 2571 int i, ret;
d6968fca 2572 struct clk_core *core;
293ba3b4 2573
d6968fca
SB
2574 core = kzalloc(sizeof(*core), GFP_KERNEL);
2575 if (!core) {
293ba3b4
SB
2576 ret = -ENOMEM;
2577 goto fail_out;
2578 }
b2476490 2579
d6968fca
SB
2580 core->name = kstrdup_const(hw->init->name, GFP_KERNEL);
2581 if (!core->name) {
0197b3ea
SK
2582 ret = -ENOMEM;
2583 goto fail_name;
2584 }
d6968fca 2585 core->ops = hw->init->ops;
ac2df527 2586 if (dev && dev->driver)
d6968fca
SB
2587 core->owner = dev->driver->owner;
2588 core->hw = hw;
2589 core->flags = hw->init->flags;
2590 core->num_parents = hw->init->num_parents;
9783c0d9
SB
2591 core->min_rate = 0;
2592 core->max_rate = ULONG_MAX;
d6968fca 2593 hw->core = core;
b2476490 2594
d1302a36 2595 /* allocate local copy in case parent_names is __initdata */
d6968fca 2596 core->parent_names = kcalloc(core->num_parents, sizeof(char *),
96a7ed90 2597 GFP_KERNEL);
d1302a36 2598
d6968fca 2599 if (!core->parent_names) {
d1302a36
MT
2600 ret = -ENOMEM;
2601 goto fail_parent_names;
2602 }
2603
2604
2605 /* copy each string name in case parent_names is __initdata */
d6968fca
SB
2606 for (i = 0; i < core->num_parents; i++) {
2607 core->parent_names[i] = kstrdup_const(hw->init->parent_names[i],
0197b3ea 2608 GFP_KERNEL);
d6968fca 2609 if (!core->parent_names[i]) {
d1302a36
MT
2610 ret = -ENOMEM;
2611 goto fail_parent_names_copy;
2612 }
2613 }
2614
176d1169
MY
2615 /* avoid unnecessary string look-ups of clk_core's possible parents. */
2616 core->parents = kcalloc(core->num_parents, sizeof(*core->parents),
2617 GFP_KERNEL);
2618 if (!core->parents) {
2619 ret = -ENOMEM;
2620 goto fail_parents;
2621 };
2622
d6968fca 2623 INIT_HLIST_HEAD(&core->clks);
1c8e6004 2624
035a61c3
TV
2625 hw->clk = __clk_create_clk(hw, NULL, NULL);
2626 if (IS_ERR(hw->clk)) {
035a61c3 2627 ret = PTR_ERR(hw->clk);
176d1169 2628 goto fail_parents;
035a61c3
TV
2629 }
2630
be45ebf2 2631 ret = __clk_core_init(core);
d1302a36 2632 if (!ret)
035a61c3 2633 return hw->clk;
b2476490 2634
1c8e6004 2635 __clk_free_clk(hw->clk);
035a61c3 2636 hw->clk = NULL;
b2476490 2637
176d1169
MY
2638fail_parents:
2639 kfree(core->parents);
d1302a36
MT
2640fail_parent_names_copy:
2641 while (--i >= 0)
d6968fca
SB
2642 kfree_const(core->parent_names[i]);
2643 kfree(core->parent_names);
d1302a36 2644fail_parent_names:
d6968fca 2645 kfree_const(core->name);
0197b3ea 2646fail_name:
d6968fca 2647 kfree(core);
d1302a36
MT
2648fail_out:
2649 return ERR_PTR(ret);
b2476490
MT
2650}
2651EXPORT_SYMBOL_GPL(clk_register);
2652
4143804c
SB
2653/**
2654 * clk_hw_register - register a clk_hw and return an error code
2655 * @dev: device that is registering this clock
2656 * @hw: link to hardware-specific clock data
2657 *
2658 * clk_hw_register is the primary interface for populating the clock tree with
2659 * new clock nodes. It returns an integer equal to zero indicating success or
2660 * less than zero indicating failure. Drivers must test for an error code after
2661 * calling clk_hw_register().
2662 */
2663int clk_hw_register(struct device *dev, struct clk_hw *hw)
2664{
2665 return PTR_ERR_OR_ZERO(clk_register(dev, hw));
2666}
2667EXPORT_SYMBOL_GPL(clk_hw_register);
2668
6e5ab41b 2669/* Free memory allocated for a clock. */
fcb0ee6a
SN
2670static void __clk_release(struct kref *ref)
2671{
d6968fca
SB
2672 struct clk_core *core = container_of(ref, struct clk_core, ref);
2673 int i = core->num_parents;
fcb0ee6a 2674
496eadf8
KK
2675 lockdep_assert_held(&prepare_lock);
2676
d6968fca 2677 kfree(core->parents);
fcb0ee6a 2678 while (--i >= 0)
d6968fca 2679 kfree_const(core->parent_names[i]);
fcb0ee6a 2680
d6968fca
SB
2681 kfree(core->parent_names);
2682 kfree_const(core->name);
2683 kfree(core);
fcb0ee6a
SN
2684}
2685
2686/*
2687 * Empty clk_ops for unregistered clocks. These are used temporarily
2688 * after clk_unregister() was called on a clock and until last clock
2689 * consumer calls clk_put() and the struct clk object is freed.
2690 */
2691static int clk_nodrv_prepare_enable(struct clk_hw *hw)
2692{
2693 return -ENXIO;
2694}
2695
2696static void clk_nodrv_disable_unprepare(struct clk_hw *hw)
2697{
2698 WARN_ON_ONCE(1);
2699}
2700
2701static int clk_nodrv_set_rate(struct clk_hw *hw, unsigned long rate,
2702 unsigned long parent_rate)
2703{
2704 return -ENXIO;
2705}
2706
2707static int clk_nodrv_set_parent(struct clk_hw *hw, u8 index)
2708{
2709 return -ENXIO;
2710}
2711
2712static const struct clk_ops clk_nodrv_ops = {
2713 .enable = clk_nodrv_prepare_enable,
2714 .disable = clk_nodrv_disable_unprepare,
2715 .prepare = clk_nodrv_prepare_enable,
2716 .unprepare = clk_nodrv_disable_unprepare,
2717 .set_rate = clk_nodrv_set_rate,
2718 .set_parent = clk_nodrv_set_parent,
2719};
2720
1df5c939
MB
2721/**
2722 * clk_unregister - unregister a currently registered clock
2723 * @clk: clock to unregister
1df5c939 2724 */
fcb0ee6a
SN
2725void clk_unregister(struct clk *clk)
2726{
2727 unsigned long flags;
2728
6314b679
SB
2729 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
2730 return;
2731
035a61c3 2732 clk_debug_unregister(clk->core);
fcb0ee6a
SN
2733
2734 clk_prepare_lock();
2735
035a61c3
TV
2736 if (clk->core->ops == &clk_nodrv_ops) {
2737 pr_err("%s: unregistered clock: %s\n", __func__,
2738 clk->core->name);
4106a3d9 2739 goto unlock;
fcb0ee6a
SN
2740 }
2741 /*
2742 * Assign empty clock ops for consumers that might still hold
2743 * a reference to this clock.
2744 */
2745 flags = clk_enable_lock();
035a61c3 2746 clk->core->ops = &clk_nodrv_ops;
fcb0ee6a
SN
2747 clk_enable_unlock(flags);
2748
035a61c3
TV
2749 if (!hlist_empty(&clk->core->children)) {
2750 struct clk_core *child;
874f224c 2751 struct hlist_node *t;
fcb0ee6a
SN
2752
2753 /* Reparent all children to the orphan list. */
035a61c3
TV
2754 hlist_for_each_entry_safe(child, t, &clk->core->children,
2755 child_node)
2756 clk_core_set_parent(child, NULL);
fcb0ee6a
SN
2757 }
2758
035a61c3 2759 hlist_del_init(&clk->core->child_node);
fcb0ee6a 2760
035a61c3 2761 if (clk->core->prepare_count)
fcb0ee6a 2762 pr_warn("%s: unregistering prepared clock: %s\n",
035a61c3
TV
2763 __func__, clk->core->name);
2764 kref_put(&clk->core->ref, __clk_release);
4106a3d9 2765unlock:
fcb0ee6a
SN
2766 clk_prepare_unlock();
2767}
1df5c939
MB
2768EXPORT_SYMBOL_GPL(clk_unregister);
2769
4143804c
SB
2770/**
2771 * clk_hw_unregister - unregister a currently registered clk_hw
2772 * @hw: hardware-specific clock data to unregister
2773 */
2774void clk_hw_unregister(struct clk_hw *hw)
2775{
2776 clk_unregister(hw->clk);
2777}
2778EXPORT_SYMBOL_GPL(clk_hw_unregister);
2779
46c8773a
SB
2780static void devm_clk_release(struct device *dev, void *res)
2781{
293ba3b4 2782 clk_unregister(*(struct clk **)res);
46c8773a
SB
2783}
2784
4143804c
SB
2785static void devm_clk_hw_release(struct device *dev, void *res)
2786{
2787 clk_hw_unregister(*(struct clk_hw **)res);
2788}
2789
46c8773a
SB
2790/**
2791 * devm_clk_register - resource managed clk_register()
2792 * @dev: device that is registering this clock
2793 * @hw: link to hardware-specific clock data
2794 *
2795 * Managed clk_register(). Clocks returned from this function are
2796 * automatically clk_unregister()ed on driver detach. See clk_register() for
2797 * more information.
2798 */
2799struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw)
2800{
2801 struct clk *clk;
293ba3b4 2802 struct clk **clkp;
46c8773a 2803
293ba3b4
SB
2804 clkp = devres_alloc(devm_clk_release, sizeof(*clkp), GFP_KERNEL);
2805 if (!clkp)
46c8773a
SB
2806 return ERR_PTR(-ENOMEM);
2807
293ba3b4
SB
2808 clk = clk_register(dev, hw);
2809 if (!IS_ERR(clk)) {
2810 *clkp = clk;
2811 devres_add(dev, clkp);
46c8773a 2812 } else {
293ba3b4 2813 devres_free(clkp);
46c8773a
SB
2814 }
2815
2816 return clk;
2817}
2818EXPORT_SYMBOL_GPL(devm_clk_register);
2819
4143804c
SB
2820/**
2821 * devm_clk_hw_register - resource managed clk_hw_register()
2822 * @dev: device that is registering this clock
2823 * @hw: link to hardware-specific clock data
2824 *
c47265ad 2825 * Managed clk_hw_register(). Clocks registered by this function are
4143804c
SB
2826 * automatically clk_hw_unregister()ed on driver detach. See clk_hw_register()
2827 * for more information.
2828 */
2829int devm_clk_hw_register(struct device *dev, struct clk_hw *hw)
2830{
2831 struct clk_hw **hwp;
2832 int ret;
2833
2834 hwp = devres_alloc(devm_clk_hw_release, sizeof(*hwp), GFP_KERNEL);
2835 if (!hwp)
2836 return -ENOMEM;
2837
2838 ret = clk_hw_register(dev, hw);
2839 if (!ret) {
2840 *hwp = hw;
2841 devres_add(dev, hwp);
2842 } else {
2843 devres_free(hwp);
2844 }
2845
2846 return ret;
2847}
2848EXPORT_SYMBOL_GPL(devm_clk_hw_register);
2849
46c8773a
SB
2850static int devm_clk_match(struct device *dev, void *res, void *data)
2851{
2852 struct clk *c = res;
2853 if (WARN_ON(!c))
2854 return 0;
2855 return c == data;
2856}
2857
4143804c
SB
2858static int devm_clk_hw_match(struct device *dev, void *res, void *data)
2859{
2860 struct clk_hw *hw = res;
2861
2862 if (WARN_ON(!hw))
2863 return 0;
2864 return hw == data;
2865}
2866
46c8773a
SB
2867/**
2868 * devm_clk_unregister - resource managed clk_unregister()
2869 * @clk: clock to unregister
2870 *
2871 * Deallocate a clock allocated with devm_clk_register(). Normally
2872 * this function will not need to be called and the resource management
2873 * code will ensure that the resource is freed.
2874 */
2875void devm_clk_unregister(struct device *dev, struct clk *clk)
2876{
2877 WARN_ON(devres_release(dev, devm_clk_release, devm_clk_match, clk));
2878}
2879EXPORT_SYMBOL_GPL(devm_clk_unregister);
2880
4143804c
SB
2881/**
2882 * devm_clk_hw_unregister - resource managed clk_hw_unregister()
2883 * @dev: device that is unregistering the hardware-specific clock data
2884 * @hw: link to hardware-specific clock data
2885 *
2886 * Unregister a clk_hw registered with devm_clk_hw_register(). Normally
2887 * this function will not need to be called and the resource management
2888 * code will ensure that the resource is freed.
2889 */
2890void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw)
2891{
2892 WARN_ON(devres_release(dev, devm_clk_hw_release, devm_clk_hw_match,
2893 hw));
2894}
2895EXPORT_SYMBOL_GPL(devm_clk_hw_unregister);
2896
ac2df527
SN
2897/*
2898 * clkdev helpers
2899 */
2900int __clk_get(struct clk *clk)
2901{
035a61c3
TV
2902 struct clk_core *core = !clk ? NULL : clk->core;
2903
2904 if (core) {
2905 if (!try_module_get(core->owner))
00efcb1c 2906 return 0;
ac2df527 2907
035a61c3 2908 kref_get(&core->ref);
00efcb1c 2909 }
ac2df527
SN
2910 return 1;
2911}
2912
2913void __clk_put(struct clk *clk)
2914{
10cdfe54
TV
2915 struct module *owner;
2916
00efcb1c 2917 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
ac2df527
SN
2918 return;
2919
fcb0ee6a 2920 clk_prepare_lock();
1c8e6004 2921
50595f8b 2922 hlist_del(&clk->clks_node);
ec02ace8
TV
2923 if (clk->min_rate > clk->core->req_rate ||
2924 clk->max_rate < clk->core->req_rate)
2925 clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
2926
1c8e6004
TV
2927 owner = clk->core->owner;
2928 kref_put(&clk->core->ref, __clk_release);
2929
fcb0ee6a
SN
2930 clk_prepare_unlock();
2931
10cdfe54 2932 module_put(owner);
035a61c3 2933
035a61c3 2934 kfree(clk);
ac2df527
SN
2935}
2936
b2476490
MT
2937/*** clk rate change notifiers ***/
2938
2939/**
2940 * clk_notifier_register - add a clk rate change notifier
2941 * @clk: struct clk * to watch
2942 * @nb: struct notifier_block * with callback info
2943 *
2944 * Request notification when clk's rate changes. This uses an SRCU
2945 * notifier because we want it to block and notifier unregistrations are
2946 * uncommon. The callbacks associated with the notifier must not
2947 * re-enter into the clk framework by calling any top-level clk APIs;
2948 * this will cause a nested prepare_lock mutex.
2949 *
198bb594
MY
2950 * In all notification cases (pre, post and abort rate change) the original
2951 * clock rate is passed to the callback via struct clk_notifier_data.old_rate
2952 * and the new frequency is passed via struct clk_notifier_data.new_rate.
b2476490 2953 *
b2476490
MT
2954 * clk_notifier_register() must be called from non-atomic context.
2955 * Returns -EINVAL if called with null arguments, -ENOMEM upon
2956 * allocation failure; otherwise, passes along the return value of
2957 * srcu_notifier_chain_register().
2958 */
2959int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
2960{
2961 struct clk_notifier *cn;
2962 int ret = -ENOMEM;
2963
2964 if (!clk || !nb)
2965 return -EINVAL;
2966
eab89f69 2967 clk_prepare_lock();
b2476490
MT
2968
2969 /* search the list of notifiers for this clk */
2970 list_for_each_entry(cn, &clk_notifier_list, node)
2971 if (cn->clk == clk)
2972 break;
2973
2974 /* if clk wasn't in the notifier list, allocate new clk_notifier */
2975 if (cn->clk != clk) {
1808a320 2976 cn = kzalloc(sizeof(*cn), GFP_KERNEL);
b2476490
MT
2977 if (!cn)
2978 goto out;
2979
2980 cn->clk = clk;
2981 srcu_init_notifier_head(&cn->notifier_head);
2982
2983 list_add(&cn->node, &clk_notifier_list);
2984 }
2985
2986 ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
2987
035a61c3 2988 clk->core->notifier_count++;
b2476490
MT
2989
2990out:
eab89f69 2991 clk_prepare_unlock();
b2476490
MT
2992
2993 return ret;
2994}
2995EXPORT_SYMBOL_GPL(clk_notifier_register);
2996
2997/**
2998 * clk_notifier_unregister - remove a clk rate change notifier
2999 * @clk: struct clk *
3000 * @nb: struct notifier_block * with callback info
3001 *
3002 * Request no further notification for changes to 'clk' and frees memory
3003 * allocated in clk_notifier_register.
3004 *
3005 * Returns -EINVAL if called with null arguments; otherwise, passes
3006 * along the return value of srcu_notifier_chain_unregister().
3007 */
3008int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
3009{
3010 struct clk_notifier *cn = NULL;
3011 int ret = -EINVAL;
3012
3013 if (!clk || !nb)
3014 return -EINVAL;
3015
eab89f69 3016 clk_prepare_lock();
b2476490
MT
3017
3018 list_for_each_entry(cn, &clk_notifier_list, node)
3019 if (cn->clk == clk)
3020 break;
3021
3022 if (cn->clk == clk) {
3023 ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
3024
035a61c3 3025 clk->core->notifier_count--;
b2476490
MT
3026
3027 /* XXX the notifier code should handle this better */
3028 if (!cn->notifier_head.head) {
3029 srcu_cleanup_notifier_head(&cn->notifier_head);
72b5322f 3030 list_del(&cn->node);
b2476490
MT
3031 kfree(cn);
3032 }
3033
3034 } else {
3035 ret = -ENOENT;
3036 }
3037
eab89f69 3038 clk_prepare_unlock();
b2476490
MT
3039
3040 return ret;
3041}
3042EXPORT_SYMBOL_GPL(clk_notifier_unregister);
766e6a4e
GL
3043
3044#ifdef CONFIG_OF
3045/**
3046 * struct of_clk_provider - Clock provider registration structure
3047 * @link: Entry in global list of clock providers
3048 * @node: Pointer to device tree node of clock provider
3049 * @get: Get clock callback. Returns NULL or a struct clk for the
3050 * given clock specifier
3051 * @data: context pointer to be passed into @get callback
3052 */
3053struct of_clk_provider {
3054 struct list_head link;
3055
3056 struct device_node *node;
3057 struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
0861e5b8 3058 struct clk_hw *(*get_hw)(struct of_phandle_args *clkspec, void *data);
766e6a4e
GL
3059 void *data;
3060};
3061
f2f6c255
PG
3062static const struct of_device_id __clk_of_table_sentinel
3063 __used __section(__clk_of_table_end);
3064
766e6a4e 3065static LIST_HEAD(of_clk_providers);
d6782c26
SN
3066static DEFINE_MUTEX(of_clk_mutex);
3067
766e6a4e
GL
3068struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
3069 void *data)
3070{
3071 return data;
3072}
3073EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
3074
0861e5b8
SB
3075struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
3076{
3077 return data;
3078}
3079EXPORT_SYMBOL_GPL(of_clk_hw_simple_get);
3080
494bfec9
SG
3081struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
3082{
3083 struct clk_onecell_data *clk_data = data;
3084 unsigned int idx = clkspec->args[0];
3085
3086 if (idx >= clk_data->clk_num) {
7e96353c 3087 pr_err("%s: invalid clock index %u\n", __func__, idx);
494bfec9
SG
3088 return ERR_PTR(-EINVAL);
3089 }
3090
3091 return clk_data->clks[idx];
3092}
3093EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
3094
0861e5b8
SB
3095struct clk_hw *
3096of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
3097{
3098 struct clk_hw_onecell_data *hw_data = data;
3099 unsigned int idx = clkspec->args[0];
3100
3101 if (idx >= hw_data->num) {
3102 pr_err("%s: invalid index %u\n", __func__, idx);
3103 return ERR_PTR(-EINVAL);
3104 }
3105
3106 return hw_data->hws[idx];
3107}
3108EXPORT_SYMBOL_GPL(of_clk_hw_onecell_get);
3109
766e6a4e
GL
3110/**
3111 * of_clk_add_provider() - Register a clock provider for a node
3112 * @np: Device node pointer associated with clock provider
3113 * @clk_src_get: callback for decoding clock
3114 * @data: context pointer for @clk_src_get callback.
3115 */
3116int of_clk_add_provider(struct device_node *np,
3117 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
3118 void *data),
3119 void *data)
3120{
3121 struct of_clk_provider *cp;
86be408b 3122 int ret;
766e6a4e 3123
1808a320 3124 cp = kzalloc(sizeof(*cp), GFP_KERNEL);
766e6a4e
GL
3125 if (!cp)
3126 return -ENOMEM;
3127
3128 cp->node = of_node_get(np);
3129 cp->data = data;
3130 cp->get = clk_src_get;
3131
d6782c26 3132 mutex_lock(&of_clk_mutex);
766e6a4e 3133 list_add(&cp->link, &of_clk_providers);
d6782c26 3134 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
3135 pr_debug("Added clock from %s\n", np->full_name);
3136
86be408b
SN
3137 ret = of_clk_set_defaults(np, true);
3138 if (ret < 0)
3139 of_clk_del_provider(np);
3140
3141 return ret;
766e6a4e
GL
3142}
3143EXPORT_SYMBOL_GPL(of_clk_add_provider);
3144
0861e5b8
SB
3145/**
3146 * of_clk_add_hw_provider() - Register a clock provider for a node
3147 * @np: Device node pointer associated with clock provider
3148 * @get: callback for decoding clk_hw
3149 * @data: context pointer for @get callback.
3150 */
3151int of_clk_add_hw_provider(struct device_node *np,
3152 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
3153 void *data),
3154 void *data)
3155{
3156 struct of_clk_provider *cp;
3157 int ret;
3158
3159 cp = kzalloc(sizeof(*cp), GFP_KERNEL);
3160 if (!cp)
3161 return -ENOMEM;
3162
3163 cp->node = of_node_get(np);
3164 cp->data = data;
3165 cp->get_hw = get;
3166
3167 mutex_lock(&of_clk_mutex);
3168 list_add(&cp->link, &of_clk_providers);
3169 mutex_unlock(&of_clk_mutex);
3170 pr_debug("Added clk_hw provider from %s\n", np->full_name);
3171
3172 ret = of_clk_set_defaults(np, true);
3173 if (ret < 0)
3174 of_clk_del_provider(np);
3175
3176 return ret;
3177}
3178EXPORT_SYMBOL_GPL(of_clk_add_hw_provider);
3179
766e6a4e
GL
3180/**
3181 * of_clk_del_provider() - Remove a previously registered clock provider
3182 * @np: Device node pointer associated with clock provider
3183 */
3184void of_clk_del_provider(struct device_node *np)
3185{
3186 struct of_clk_provider *cp;
3187
d6782c26 3188 mutex_lock(&of_clk_mutex);
766e6a4e
GL
3189 list_for_each_entry(cp, &of_clk_providers, link) {
3190 if (cp->node == np) {
3191 list_del(&cp->link);
3192 of_node_put(cp->node);
3193 kfree(cp);
3194 break;
3195 }
3196 }
d6782c26 3197 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
3198}
3199EXPORT_SYMBOL_GPL(of_clk_del_provider);
3200
0861e5b8
SB
3201static struct clk_hw *
3202__of_clk_get_hw_from_provider(struct of_clk_provider *provider,
3203 struct of_phandle_args *clkspec)
3204{
3205 struct clk *clk;
0861e5b8 3206
74002fcd
SB
3207 if (provider->get_hw)
3208 return provider->get_hw(clkspec, provider->data);
0861e5b8 3209
74002fcd
SB
3210 clk = provider->get(clkspec, provider->data);
3211 if (IS_ERR(clk))
3212 return ERR_CAST(clk);
3213 return __clk_get_hw(clk);
0861e5b8
SB
3214}
3215
73e0e496
SB
3216struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
3217 const char *dev_id, const char *con_id)
766e6a4e
GL
3218{
3219 struct of_clk_provider *provider;
a34cd466 3220 struct clk *clk = ERR_PTR(-EPROBE_DEFER);
f155d15b 3221 struct clk_hw *hw;
766e6a4e 3222
306c342f
SB
3223 if (!clkspec)
3224 return ERR_PTR(-EINVAL);
3225
766e6a4e 3226 /* Check if we have such a provider in our array */
306c342f 3227 mutex_lock(&of_clk_mutex);
766e6a4e 3228 list_for_each_entry(provider, &of_clk_providers, link) {
f155d15b 3229 if (provider->node == clkspec->np) {
0861e5b8 3230 hw = __of_clk_get_hw_from_provider(provider, clkspec);
0861e5b8 3231 clk = __clk_create_clk(hw, dev_id, con_id);
f155d15b 3232 }
73e0e496 3233
f155d15b
SB
3234 if (!IS_ERR(clk)) {
3235 if (!__clk_get(clk)) {
73e0e496
SB
3236 __clk_free_clk(clk);
3237 clk = ERR_PTR(-ENOENT);
3238 }
3239
766e6a4e 3240 break;
73e0e496 3241 }
766e6a4e 3242 }
306c342f 3243 mutex_unlock(&of_clk_mutex);
d6782c26
SN
3244
3245 return clk;
3246}
3247
306c342f
SB
3248/**
3249 * of_clk_get_from_provider() - Lookup a clock from a clock provider
3250 * @clkspec: pointer to a clock specifier data structure
3251 *
3252 * This function looks up a struct clk from the registered list of clock
3253 * providers, an input is a clock specifier data structure as returned
3254 * from the of_parse_phandle_with_args() function call.
3255 */
d6782c26
SN
3256struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
3257{
306c342f 3258 return __of_clk_get_from_provider(clkspec, NULL, __func__);
766e6a4e 3259}
fb4dd222 3260EXPORT_SYMBOL_GPL(of_clk_get_from_provider);
766e6a4e 3261
929e7f3b
SB
3262/**
3263 * of_clk_get_parent_count() - Count the number of clocks a device node has
3264 * @np: device node to count
3265 *
3266 * Returns: The number of clocks that are possible parents of this node
3267 */
3268unsigned int of_clk_get_parent_count(struct device_node *np)
f6102742 3269{
929e7f3b
SB
3270 int count;
3271
3272 count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
3273 if (count < 0)
3274 return 0;
3275
3276 return count;
f6102742
MT
3277}
3278EXPORT_SYMBOL_GPL(of_clk_get_parent_count);
3279
766e6a4e
GL
3280const char *of_clk_get_parent_name(struct device_node *np, int index)
3281{
3282 struct of_phandle_args clkspec;
7a0fc1a3 3283 struct property *prop;
766e6a4e 3284 const char *clk_name;
7a0fc1a3
BD
3285 const __be32 *vp;
3286 u32 pv;
766e6a4e 3287 int rc;
7a0fc1a3 3288 int count;
0a4807c2 3289 struct clk *clk;
766e6a4e 3290
766e6a4e
GL
3291 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
3292 &clkspec);
3293 if (rc)
3294 return NULL;
3295
7a0fc1a3
BD
3296 index = clkspec.args_count ? clkspec.args[0] : 0;
3297 count = 0;
3298
3299 /* if there is an indices property, use it to transfer the index
3300 * specified into an array offset for the clock-output-names property.
3301 */
3302 of_property_for_each_u32(clkspec.np, "clock-indices", prop, vp, pv) {
3303 if (index == pv) {
3304 index = count;
3305 break;
3306 }
3307 count++;
3308 }
8da411cc
MY
3309 /* We went off the end of 'clock-indices' without finding it */
3310 if (prop && !vp)
3311 return NULL;
7a0fc1a3 3312
766e6a4e 3313 if (of_property_read_string_index(clkspec.np, "clock-output-names",
7a0fc1a3 3314 index,
0a4807c2
SB
3315 &clk_name) < 0) {
3316 /*
3317 * Best effort to get the name if the clock has been
3318 * registered with the framework. If the clock isn't
3319 * registered, we return the node name as the name of
3320 * the clock as long as #clock-cells = 0.
3321 */
3322 clk = of_clk_get_from_provider(&clkspec);
3323 if (IS_ERR(clk)) {
3324 if (clkspec.args_count == 0)
3325 clk_name = clkspec.np->name;
3326 else
3327 clk_name = NULL;
3328 } else {
3329 clk_name = __clk_get_name(clk);
3330 clk_put(clk);
3331 }
3332 }
3333
766e6a4e
GL
3334
3335 of_node_put(clkspec.np);
3336 return clk_name;
3337}
3338EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
3339
2e61dfb3
DN
3340/**
3341 * of_clk_parent_fill() - Fill @parents with names of @np's parents and return
3342 * number of parents
3343 * @np: Device node pointer associated with clock provider
3344 * @parents: pointer to char array that hold the parents' names
3345 * @size: size of the @parents array
3346 *
3347 * Return: number of parents for the clock node.
3348 */
3349int of_clk_parent_fill(struct device_node *np, const char **parents,
3350 unsigned int size)
3351{
3352 unsigned int i = 0;
3353
3354 while (i < size && (parents[i] = of_clk_get_parent_name(np, i)) != NULL)
3355 i++;
3356
3357 return i;
3358}
3359EXPORT_SYMBOL_GPL(of_clk_parent_fill);
3360
1771b10d
GC
3361struct clock_provider {
3362 of_clk_init_cb_t clk_init_cb;
3363 struct device_node *np;
3364 struct list_head node;
3365};
3366
1771b10d
GC
3367/*
3368 * This function looks for a parent clock. If there is one, then it
3369 * checks that the provider for this parent clock was initialized, in
3370 * this case the parent clock will be ready.
3371 */
3372static int parent_ready(struct device_node *np)
3373{
3374 int i = 0;
3375
3376 while (true) {
3377 struct clk *clk = of_clk_get(np, i);
3378
3379 /* this parent is ready we can check the next one */
3380 if (!IS_ERR(clk)) {
3381 clk_put(clk);
3382 i++;
3383 continue;
3384 }
3385
3386 /* at least one parent is not ready, we exit now */
3387 if (PTR_ERR(clk) == -EPROBE_DEFER)
3388 return 0;
3389
3390 /*
3391 * Here we make assumption that the device tree is
3392 * written correctly. So an error means that there is
3393 * no more parent. As we didn't exit yet, then the
3394 * previous parent are ready. If there is no clock
3395 * parent, no need to wait for them, then we can
3396 * consider their absence as being ready
3397 */
3398 return 1;
3399 }
3400}
3401
d56f8994
LJ
3402/**
3403 * of_clk_detect_critical() - set CLK_IS_CRITICAL flag from Device Tree
3404 * @np: Device node pointer associated with clock provider
3405 * @index: clock index
3406 * @flags: pointer to clk_core->flags
3407 *
3408 * Detects if the clock-critical property exists and, if so, sets the
3409 * corresponding CLK_IS_CRITICAL flag.
3410 *
3411 * Do not use this function. It exists only for legacy Device Tree
3412 * bindings, such as the one-clock-per-node style that are outdated.
3413 * Those bindings typically put all clock data into .dts and the Linux
3414 * driver has no clock data, thus making it impossible to set this flag
3415 * correctly from the driver. Only those drivers may call
3416 * of_clk_detect_critical from their setup functions.
3417 *
3418 * Return: error code or zero on success
3419 */
3420int of_clk_detect_critical(struct device_node *np,
3421 int index, unsigned long *flags)
3422{
3423 struct property *prop;
3424 const __be32 *cur;
3425 uint32_t idx;
3426
3427 if (!np || !flags)
3428 return -EINVAL;
3429
3430 of_property_for_each_u32(np, "clock-critical", prop, cur, idx)
3431 if (index == idx)
3432 *flags |= CLK_IS_CRITICAL;
3433
3434 return 0;
3435}
3436
766e6a4e
GL
3437/**
3438 * of_clk_init() - Scan and init clock providers from the DT
3439 * @matches: array of compatible values and init functions for providers.
3440 *
1771b10d 3441 * This function scans the device tree for matching clock providers
e5ca8fb4 3442 * and calls their initialization functions. It also does it by trying
1771b10d 3443 * to follow the dependencies.
766e6a4e
GL
3444 */
3445void __init of_clk_init(const struct of_device_id *matches)
3446{
7f7ed584 3447 const struct of_device_id *match;
766e6a4e 3448 struct device_node *np;
1771b10d
GC
3449 struct clock_provider *clk_provider, *next;
3450 bool is_init_done;
3451 bool force = false;
2573a02a 3452 LIST_HEAD(clk_provider_list);
766e6a4e 3453
f2f6c255 3454 if (!matches)
819b4861 3455 matches = &__clk_of_table;
f2f6c255 3456
1771b10d 3457 /* First prepare the list of the clocks providers */
7f7ed584 3458 for_each_matching_node_and_match(np, matches, &match) {
2e3b19f1
SB
3459 struct clock_provider *parent;
3460
3e5dd6f6
GU
3461 if (!of_device_is_available(np))
3462 continue;
3463
2e3b19f1
SB
3464 parent = kzalloc(sizeof(*parent), GFP_KERNEL);
3465 if (!parent) {
3466 list_for_each_entry_safe(clk_provider, next,
3467 &clk_provider_list, node) {
3468 list_del(&clk_provider->node);
6bc9d9d6 3469 of_node_put(clk_provider->np);
2e3b19f1
SB
3470 kfree(clk_provider);
3471 }
6bc9d9d6 3472 of_node_put(np);
2e3b19f1
SB
3473 return;
3474 }
1771b10d
GC
3475
3476 parent->clk_init_cb = match->data;
6bc9d9d6 3477 parent->np = of_node_get(np);
3f6d439f 3478 list_add_tail(&parent->node, &clk_provider_list);
1771b10d
GC
3479 }
3480
3481 while (!list_empty(&clk_provider_list)) {
3482 is_init_done = false;
3483 list_for_each_entry_safe(clk_provider, next,
3484 &clk_provider_list, node) {
3485 if (force || parent_ready(clk_provider->np)) {
86be408b 3486
989eafd0
RRD
3487 /* Don't populate platform devices */
3488 of_node_set_flag(clk_provider->np,
3489 OF_POPULATED);
3490
1771b10d 3491 clk_provider->clk_init_cb(clk_provider->np);
86be408b
SN
3492 of_clk_set_defaults(clk_provider->np, true);
3493
1771b10d 3494 list_del(&clk_provider->node);
6bc9d9d6 3495 of_node_put(clk_provider->np);
1771b10d
GC
3496 kfree(clk_provider);
3497 is_init_done = true;
3498 }
3499 }
3500
3501 /*
e5ca8fb4 3502 * We didn't manage to initialize any of the
1771b10d
GC
3503 * remaining providers during the last loop, so now we
3504 * initialize all the remaining ones unconditionally
3505 * in case the clock parent was not mandatory
3506 */
3507 if (!is_init_done)
3508 force = true;
766e6a4e
GL
3509 }
3510}
3511#endif