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clk: Add functions to save/restore clock context en-masse
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CommitLineData
b2476490
MT
1/*
2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
5fb94e9c 9 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
b2476490
MT
10 */
11
3c373117 12#include <linux/clk.h>
b09d6d99 13#include <linux/clk-provider.h>
86be408b 14#include <linux/clk/clk-conf.h>
b2476490
MT
15#include <linux/module.h>
16#include <linux/mutex.h>
17#include <linux/spinlock.h>
18#include <linux/err.h>
19#include <linux/list.h>
20#include <linux/slab.h>
766e6a4e 21#include <linux/of.h>
46c8773a 22#include <linux/device.h>
f2f6c255 23#include <linux/init.h>
9a34b453 24#include <linux/pm_runtime.h>
533ddeb1 25#include <linux/sched.h>
562ef0b0 26#include <linux/clkdev.h>
b2476490 27
d6782c26
SN
28#include "clk.h"
29
b2476490
MT
30static DEFINE_SPINLOCK(enable_lock);
31static DEFINE_MUTEX(prepare_lock);
32
533ddeb1
MT
33static struct task_struct *prepare_owner;
34static struct task_struct *enable_owner;
35
36static int prepare_refcnt;
37static int enable_refcnt;
38
b2476490
MT
39static HLIST_HEAD(clk_root_list);
40static HLIST_HEAD(clk_orphan_list);
41static LIST_HEAD(clk_notifier_list);
42
b09d6d99
MT
43/*** private data structures ***/
44
45struct clk_core {
46 const char *name;
47 const struct clk_ops *ops;
48 struct clk_hw *hw;
49 struct module *owner;
9a34b453 50 struct device *dev;
b09d6d99
MT
51 struct clk_core *parent;
52 const char **parent_names;
53 struct clk_core **parents;
54 u8 num_parents;
55 u8 new_parent_index;
56 unsigned long rate;
1c8e6004 57 unsigned long req_rate;
b09d6d99
MT
58 unsigned long new_rate;
59 struct clk_core *new_parent;
60 struct clk_core *new_child;
61 unsigned long flags;
e6500344 62 bool orphan;
b09d6d99
MT
63 unsigned int enable_count;
64 unsigned int prepare_count;
e55a839a 65 unsigned int protect_count;
9783c0d9
SB
66 unsigned long min_rate;
67 unsigned long max_rate;
b09d6d99
MT
68 unsigned long accuracy;
69 int phase;
9fba738a 70 struct clk_duty duty;
b09d6d99
MT
71 struct hlist_head children;
72 struct hlist_node child_node;
1c8e6004 73 struct hlist_head clks;
b09d6d99
MT
74 unsigned int notifier_count;
75#ifdef CONFIG_DEBUG_FS
76 struct dentry *dentry;
8c9a8a8f 77 struct hlist_node debug_node;
b09d6d99
MT
78#endif
79 struct kref ref;
80};
81
dfc202ea
SB
82#define CREATE_TRACE_POINTS
83#include <trace/events/clk.h>
84
b09d6d99
MT
85struct clk {
86 struct clk_core *core;
87 const char *dev_id;
88 const char *con_id;
1c8e6004
TV
89 unsigned long min_rate;
90 unsigned long max_rate;
55e9b8b7 91 unsigned int exclusive_count;
50595f8b 92 struct hlist_node clks_node;
b09d6d99
MT
93};
94
9a34b453
MS
95/*** runtime pm ***/
96static int clk_pm_runtime_get(struct clk_core *core)
97{
98 int ret = 0;
99
100 if (!core->dev)
101 return 0;
102
103 ret = pm_runtime_get_sync(core->dev);
104 return ret < 0 ? ret : 0;
105}
106
107static void clk_pm_runtime_put(struct clk_core *core)
108{
109 if (!core->dev)
110 return;
111
112 pm_runtime_put_sync(core->dev);
113}
114
eab89f69
MT
115/*** locking ***/
116static void clk_prepare_lock(void)
117{
533ddeb1
MT
118 if (!mutex_trylock(&prepare_lock)) {
119 if (prepare_owner == current) {
120 prepare_refcnt++;
121 return;
122 }
123 mutex_lock(&prepare_lock);
124 }
125 WARN_ON_ONCE(prepare_owner != NULL);
126 WARN_ON_ONCE(prepare_refcnt != 0);
127 prepare_owner = current;
128 prepare_refcnt = 1;
eab89f69
MT
129}
130
131static void clk_prepare_unlock(void)
132{
533ddeb1
MT
133 WARN_ON_ONCE(prepare_owner != current);
134 WARN_ON_ONCE(prepare_refcnt == 0);
135
136 if (--prepare_refcnt)
137 return;
138 prepare_owner = NULL;
eab89f69
MT
139 mutex_unlock(&prepare_lock);
140}
141
142static unsigned long clk_enable_lock(void)
a57aa185 143 __acquires(enable_lock)
eab89f69
MT
144{
145 unsigned long flags;
533ddeb1 146
a12aa8a6
DL
147 /*
148 * On UP systems, spin_trylock_irqsave() always returns true, even if
149 * we already hold the lock. So, in that case, we rely only on
150 * reference counting.
151 */
152 if (!IS_ENABLED(CONFIG_SMP) ||
153 !spin_trylock_irqsave(&enable_lock, flags)) {
533ddeb1
MT
154 if (enable_owner == current) {
155 enable_refcnt++;
a57aa185 156 __acquire(enable_lock);
a12aa8a6
DL
157 if (!IS_ENABLED(CONFIG_SMP))
158 local_save_flags(flags);
533ddeb1
MT
159 return flags;
160 }
161 spin_lock_irqsave(&enable_lock, flags);
162 }
163 WARN_ON_ONCE(enable_owner != NULL);
164 WARN_ON_ONCE(enable_refcnt != 0);
165 enable_owner = current;
166 enable_refcnt = 1;
eab89f69
MT
167 return flags;
168}
169
170static void clk_enable_unlock(unsigned long flags)
a57aa185 171 __releases(enable_lock)
eab89f69 172{
533ddeb1
MT
173 WARN_ON_ONCE(enable_owner != current);
174 WARN_ON_ONCE(enable_refcnt == 0);
175
a57aa185
SB
176 if (--enable_refcnt) {
177 __release(enable_lock);
533ddeb1 178 return;
a57aa185 179 }
533ddeb1 180 enable_owner = NULL;
eab89f69
MT
181 spin_unlock_irqrestore(&enable_lock, flags);
182}
183
e55a839a
JB
184static bool clk_core_rate_is_protected(struct clk_core *core)
185{
186 return core->protect_count;
187}
188
4dff95dc
SB
189static bool clk_core_is_prepared(struct clk_core *core)
190{
9a34b453
MS
191 bool ret = false;
192
4dff95dc
SB
193 /*
194 * .is_prepared is optional for clocks that can prepare
195 * fall back to software usage counter if it is missing
196 */
197 if (!core->ops->is_prepared)
198 return core->prepare_count;
b2476490 199
9a34b453
MS
200 if (!clk_pm_runtime_get(core)) {
201 ret = core->ops->is_prepared(core->hw);
202 clk_pm_runtime_put(core);
203 }
204
205 return ret;
4dff95dc 206}
b2476490 207
4dff95dc
SB
208static bool clk_core_is_enabled(struct clk_core *core)
209{
9a34b453
MS
210 bool ret = false;
211
4dff95dc
SB
212 /*
213 * .is_enabled is only mandatory for clocks that gate
214 * fall back to software usage counter if .is_enabled is missing
215 */
216 if (!core->ops->is_enabled)
217 return core->enable_count;
6b44c854 218
9a34b453
MS
219 /*
220 * Check if clock controller's device is runtime active before
221 * calling .is_enabled callback. If not, assume that clock is
222 * disabled, because we might be called from atomic context, from
223 * which pm_runtime_get() is not allowed.
224 * This function is called mainly from clk_disable_unused_subtree,
225 * which ensures proper runtime pm activation of controller before
226 * taking enable spinlock, but the below check is needed if one tries
227 * to call it from other places.
228 */
229 if (core->dev) {
230 pm_runtime_get_noresume(core->dev);
231 if (!pm_runtime_active(core->dev)) {
232 ret = false;
233 goto done;
234 }
235 }
236
237 ret = core->ops->is_enabled(core->hw);
238done:
756efe13
DA
239 if (core->dev)
240 pm_runtime_put(core->dev);
9a34b453
MS
241
242 return ret;
4dff95dc 243}
6b44c854 244
4dff95dc 245/*** helper functions ***/
1af599df 246
b76281cb 247const char *__clk_get_name(const struct clk *clk)
1af599df 248{
4dff95dc 249 return !clk ? NULL : clk->core->name;
1af599df 250}
4dff95dc 251EXPORT_SYMBOL_GPL(__clk_get_name);
1af599df 252
e7df6f6e 253const char *clk_hw_get_name(const struct clk_hw *hw)
1a9c069c
SB
254{
255 return hw->core->name;
256}
257EXPORT_SYMBOL_GPL(clk_hw_get_name);
258
4dff95dc
SB
259struct clk_hw *__clk_get_hw(struct clk *clk)
260{
261 return !clk ? NULL : clk->core->hw;
262}
263EXPORT_SYMBOL_GPL(__clk_get_hw);
1af599df 264
e7df6f6e 265unsigned int clk_hw_get_num_parents(const struct clk_hw *hw)
1a9c069c
SB
266{
267 return hw->core->num_parents;
268}
269EXPORT_SYMBOL_GPL(clk_hw_get_num_parents);
270
e7df6f6e 271struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw)
1a9c069c
SB
272{
273 return hw->core->parent ? hw->core->parent->hw : NULL;
274}
275EXPORT_SYMBOL_GPL(clk_hw_get_parent);
276
4dff95dc
SB
277static struct clk_core *__clk_lookup_subtree(const char *name,
278 struct clk_core *core)
bddca894 279{
035a61c3 280 struct clk_core *child;
4dff95dc 281 struct clk_core *ret;
bddca894 282
4dff95dc
SB
283 if (!strcmp(core->name, name))
284 return core;
bddca894 285
4dff95dc
SB
286 hlist_for_each_entry(child, &core->children, child_node) {
287 ret = __clk_lookup_subtree(name, child);
288 if (ret)
289 return ret;
bddca894
PG
290 }
291
4dff95dc 292 return NULL;
bddca894
PG
293}
294
4dff95dc 295static struct clk_core *clk_core_lookup(const char *name)
bddca894 296{
4dff95dc
SB
297 struct clk_core *root_clk;
298 struct clk_core *ret;
bddca894 299
4dff95dc
SB
300 if (!name)
301 return NULL;
bddca894 302
4dff95dc
SB
303 /* search the 'proper' clk tree first */
304 hlist_for_each_entry(root_clk, &clk_root_list, child_node) {
305 ret = __clk_lookup_subtree(name, root_clk);
306 if (ret)
307 return ret;
bddca894
PG
308 }
309
4dff95dc
SB
310 /* if not found, then search the orphan tree */
311 hlist_for_each_entry(root_clk, &clk_orphan_list, child_node) {
312 ret = __clk_lookup_subtree(name, root_clk);
313 if (ret)
314 return ret;
315 }
bddca894 316
4dff95dc 317 return NULL;
bddca894
PG
318}
319
4dff95dc
SB
320static struct clk_core *clk_core_get_parent_by_index(struct clk_core *core,
321 u8 index)
bddca894 322{
4dff95dc
SB
323 if (!core || index >= core->num_parents)
324 return NULL;
88cfbef2
MY
325
326 if (!core->parents[index])
327 core->parents[index] =
328 clk_core_lookup(core->parent_names[index]);
329
330 return core->parents[index];
bddca894
PG
331}
332
e7df6f6e
SB
333struct clk_hw *
334clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index)
1a9c069c
SB
335{
336 struct clk_core *parent;
337
338 parent = clk_core_get_parent_by_index(hw->core, index);
339
340 return !parent ? NULL : parent->hw;
341}
342EXPORT_SYMBOL_GPL(clk_hw_get_parent_by_index);
343
4dff95dc
SB
344unsigned int __clk_get_enable_count(struct clk *clk)
345{
346 return !clk ? 0 : clk->core->enable_count;
347}
b2476490 348
4dff95dc
SB
349static unsigned long clk_core_get_rate_nolock(struct clk_core *core)
350{
351 unsigned long ret;
b2476490 352
4dff95dc
SB
353 if (!core) {
354 ret = 0;
355 goto out;
356 }
b2476490 357
4dff95dc 358 ret = core->rate;
b2476490 359
47b0eeb3 360 if (!core->num_parents)
4dff95dc 361 goto out;
c646cbf1 362
4dff95dc
SB
363 if (!core->parent)
364 ret = 0;
b2476490 365
b2476490
MT
366out:
367 return ret;
368}
369
e7df6f6e 370unsigned long clk_hw_get_rate(const struct clk_hw *hw)
1a9c069c
SB
371{
372 return clk_core_get_rate_nolock(hw->core);
373}
374EXPORT_SYMBOL_GPL(clk_hw_get_rate);
375
4dff95dc
SB
376static unsigned long __clk_get_accuracy(struct clk_core *core)
377{
378 if (!core)
379 return 0;
b2476490 380
4dff95dc 381 return core->accuracy;
b2476490
MT
382}
383
4dff95dc 384unsigned long __clk_get_flags(struct clk *clk)
fcb0ee6a 385{
4dff95dc 386 return !clk ? 0 : clk->core->flags;
fcb0ee6a 387}
4dff95dc 388EXPORT_SYMBOL_GPL(__clk_get_flags);
fcb0ee6a 389
e7df6f6e 390unsigned long clk_hw_get_flags(const struct clk_hw *hw)
1a9c069c
SB
391{
392 return hw->core->flags;
393}
394EXPORT_SYMBOL_GPL(clk_hw_get_flags);
395
e7df6f6e 396bool clk_hw_is_prepared(const struct clk_hw *hw)
1a9c069c
SB
397{
398 return clk_core_is_prepared(hw->core);
399}
400
e55a839a
JB
401bool clk_hw_rate_is_protected(const struct clk_hw *hw)
402{
403 return clk_core_rate_is_protected(hw->core);
404}
405
be68bf88
JE
406bool clk_hw_is_enabled(const struct clk_hw *hw)
407{
408 return clk_core_is_enabled(hw->core);
409}
410
4dff95dc 411bool __clk_is_enabled(struct clk *clk)
b2476490 412{
4dff95dc
SB
413 if (!clk)
414 return false;
b2476490 415
4dff95dc
SB
416 return clk_core_is_enabled(clk->core);
417}
418EXPORT_SYMBOL_GPL(__clk_is_enabled);
b2476490 419
4dff95dc
SB
420static bool mux_is_better_rate(unsigned long rate, unsigned long now,
421 unsigned long best, unsigned long flags)
422{
423 if (flags & CLK_MUX_ROUND_CLOSEST)
424 return abs(now - rate) < abs(best - rate);
1af599df 425
4dff95dc
SB
426 return now <= rate && now > best;
427}
bddca894 428
4ad69b80
JB
429int clk_mux_determine_rate_flags(struct clk_hw *hw,
430 struct clk_rate_request *req,
431 unsigned long flags)
4dff95dc
SB
432{
433 struct clk_core *core = hw->core, *parent, *best_parent = NULL;
0817b62c
BB
434 int i, num_parents, ret;
435 unsigned long best = 0;
436 struct clk_rate_request parent_req = *req;
b2476490 437
4dff95dc
SB
438 /* if NO_REPARENT flag set, pass through to current parent */
439 if (core->flags & CLK_SET_RATE_NO_REPARENT) {
440 parent = core->parent;
0817b62c
BB
441 if (core->flags & CLK_SET_RATE_PARENT) {
442 ret = __clk_determine_rate(parent ? parent->hw : NULL,
443 &parent_req);
444 if (ret)
445 return ret;
446
447 best = parent_req.rate;
448 } else if (parent) {
4dff95dc 449 best = clk_core_get_rate_nolock(parent);
0817b62c 450 } else {
4dff95dc 451 best = clk_core_get_rate_nolock(core);
0817b62c
BB
452 }
453
4dff95dc
SB
454 goto out;
455 }
b2476490 456
4dff95dc
SB
457 /* find the parent that can provide the fastest rate <= rate */
458 num_parents = core->num_parents;
459 for (i = 0; i < num_parents; i++) {
460 parent = clk_core_get_parent_by_index(core, i);
461 if (!parent)
462 continue;
0817b62c
BB
463
464 if (core->flags & CLK_SET_RATE_PARENT) {
465 parent_req = *req;
466 ret = __clk_determine_rate(parent->hw, &parent_req);
467 if (ret)
468 continue;
469 } else {
470 parent_req.rate = clk_core_get_rate_nolock(parent);
471 }
472
473 if (mux_is_better_rate(req->rate, parent_req.rate,
474 best, flags)) {
4dff95dc 475 best_parent = parent;
0817b62c 476 best = parent_req.rate;
4dff95dc
SB
477 }
478 }
b2476490 479
57d866e6
BB
480 if (!best_parent)
481 return -EINVAL;
482
4dff95dc
SB
483out:
484 if (best_parent)
0817b62c
BB
485 req->best_parent_hw = best_parent->hw;
486 req->best_parent_rate = best;
487 req->rate = best;
b2476490 488
0817b62c 489 return 0;
b33d212f 490}
4ad69b80 491EXPORT_SYMBOL_GPL(clk_mux_determine_rate_flags);
4dff95dc
SB
492
493struct clk *__clk_lookup(const char *name)
fcb0ee6a 494{
4dff95dc
SB
495 struct clk_core *core = clk_core_lookup(name);
496
497 return !core ? NULL : core->hw->clk;
fcb0ee6a 498}
b2476490 499
4dff95dc
SB
500static void clk_core_get_boundaries(struct clk_core *core,
501 unsigned long *min_rate,
502 unsigned long *max_rate)
1c155b3d 503{
4dff95dc 504 struct clk *clk_user;
1c155b3d 505
9783c0d9
SB
506 *min_rate = core->min_rate;
507 *max_rate = core->max_rate;
496eadf8 508
4dff95dc
SB
509 hlist_for_each_entry(clk_user, &core->clks, clks_node)
510 *min_rate = max(*min_rate, clk_user->min_rate);
1c155b3d 511
4dff95dc
SB
512 hlist_for_each_entry(clk_user, &core->clks, clks_node)
513 *max_rate = min(*max_rate, clk_user->max_rate);
514}
1c155b3d 515
9783c0d9
SB
516void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
517 unsigned long max_rate)
518{
519 hw->core->min_rate = min_rate;
520 hw->core->max_rate = max_rate;
521}
522EXPORT_SYMBOL_GPL(clk_hw_set_rate_range);
523
4dff95dc
SB
524/*
525 * Helper for finding best parent to provide a given frequency. This can be used
526 * directly as a determine_rate callback (e.g. for a mux), or from a more
527 * complex clock that may combine a mux with other operations.
528 */
0817b62c
BB
529int __clk_mux_determine_rate(struct clk_hw *hw,
530 struct clk_rate_request *req)
4dff95dc 531{
0817b62c 532 return clk_mux_determine_rate_flags(hw, req, 0);
1c155b3d 533}
4dff95dc 534EXPORT_SYMBOL_GPL(__clk_mux_determine_rate);
1c155b3d 535
0817b62c
BB
536int __clk_mux_determine_rate_closest(struct clk_hw *hw,
537 struct clk_rate_request *req)
b2476490 538{
0817b62c 539 return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST);
4dff95dc
SB
540}
541EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
b2476490 542
4dff95dc 543/*** clk api ***/
496eadf8 544
e55a839a
JB
545static void clk_core_rate_unprotect(struct clk_core *core)
546{
547 lockdep_assert_held(&prepare_lock);
548
549 if (!core)
550 return;
551
ab525dcc
FE
552 if (WARN(core->protect_count == 0,
553 "%s already unprotected\n", core->name))
e55a839a
JB
554 return;
555
556 if (--core->protect_count > 0)
557 return;
558
559 clk_core_rate_unprotect(core->parent);
560}
561
562static int clk_core_rate_nuke_protect(struct clk_core *core)
563{
564 int ret;
565
566 lockdep_assert_held(&prepare_lock);
567
568 if (!core)
569 return -EINVAL;
570
571 if (core->protect_count == 0)
572 return 0;
573
574 ret = core->protect_count;
575 core->protect_count = 1;
576 clk_core_rate_unprotect(core);
577
578 return ret;
579}
580
55e9b8b7
JB
581/**
582 * clk_rate_exclusive_put - release exclusivity over clock rate control
583 * @clk: the clk over which the exclusivity is released
584 *
585 * clk_rate_exclusive_put() completes a critical section during which a clock
586 * consumer cannot tolerate any other consumer making any operation on the
587 * clock which could result in a rate change or rate glitch. Exclusive clocks
588 * cannot have their rate changed, either directly or indirectly due to changes
589 * further up the parent chain of clocks. As a result, clocks up parent chain
590 * also get under exclusive control of the calling consumer.
591 *
592 * If exlusivity is claimed more than once on clock, even by the same consumer,
593 * the rate effectively gets locked as exclusivity can't be preempted.
594 *
595 * Calls to clk_rate_exclusive_put() must be balanced with calls to
596 * clk_rate_exclusive_get(). Calls to this function may sleep, and do not return
597 * error status.
598 */
599void clk_rate_exclusive_put(struct clk *clk)
600{
601 if (!clk)
602 return;
603
604 clk_prepare_lock();
605
606 /*
607 * if there is something wrong with this consumer protect count, stop
608 * here before messing with the provider
609 */
610 if (WARN_ON(clk->exclusive_count <= 0))
611 goto out;
612
613 clk_core_rate_unprotect(clk->core);
614 clk->exclusive_count--;
615out:
616 clk_prepare_unlock();
617}
618EXPORT_SYMBOL_GPL(clk_rate_exclusive_put);
619
e55a839a
JB
620static void clk_core_rate_protect(struct clk_core *core)
621{
622 lockdep_assert_held(&prepare_lock);
623
624 if (!core)
625 return;
626
627 if (core->protect_count == 0)
628 clk_core_rate_protect(core->parent);
629
630 core->protect_count++;
631}
632
633static void clk_core_rate_restore_protect(struct clk_core *core, int count)
634{
635 lockdep_assert_held(&prepare_lock);
636
637 if (!core)
638 return;
639
640 if (count == 0)
641 return;
642
643 clk_core_rate_protect(core);
644 core->protect_count = count;
645}
646
55e9b8b7
JB
647/**
648 * clk_rate_exclusive_get - get exclusivity over the clk rate control
649 * @clk: the clk over which the exclusity of rate control is requested
650 *
651 * clk_rate_exlusive_get() begins a critical section during which a clock
652 * consumer cannot tolerate any other consumer making any operation on the
653 * clock which could result in a rate change or rate glitch. Exclusive clocks
654 * cannot have their rate changed, either directly or indirectly due to changes
655 * further up the parent chain of clocks. As a result, clocks up parent chain
656 * also get under exclusive control of the calling consumer.
657 *
658 * If exlusivity is claimed more than once on clock, even by the same consumer,
659 * the rate effectively gets locked as exclusivity can't be preempted.
660 *
661 * Calls to clk_rate_exclusive_get() should be balanced with calls to
662 * clk_rate_exclusive_put(). Calls to this function may sleep.
663 * Returns 0 on success, -EERROR otherwise
664 */
665int clk_rate_exclusive_get(struct clk *clk)
666{
667 if (!clk)
668 return 0;
669
670 clk_prepare_lock();
671 clk_core_rate_protect(clk->core);
672 clk->exclusive_count++;
673 clk_prepare_unlock();
674
675 return 0;
676}
677EXPORT_SYMBOL_GPL(clk_rate_exclusive_get);
678
4dff95dc
SB
679static void clk_core_unprepare(struct clk_core *core)
680{
a6334725
SB
681 lockdep_assert_held(&prepare_lock);
682
4dff95dc
SB
683 if (!core)
684 return;
b2476490 685
ab525dcc
FE
686 if (WARN(core->prepare_count == 0,
687 "%s already unprepared\n", core->name))
4dff95dc 688 return;
b2476490 689
ab525dcc
FE
690 if (WARN(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL,
691 "Unpreparing critical %s\n", core->name))
2e20fbf5
LJ
692 return;
693
9461f7b3
JB
694 if (core->flags & CLK_SET_RATE_GATE)
695 clk_core_rate_unprotect(core);
696
4dff95dc
SB
697 if (--core->prepare_count > 0)
698 return;
b2476490 699
ab525dcc 700 WARN(core->enable_count > 0, "Unpreparing enabled %s\n", core->name);
b2476490 701
4dff95dc 702 trace_clk_unprepare(core);
b2476490 703
4dff95dc
SB
704 if (core->ops->unprepare)
705 core->ops->unprepare(core->hw);
706
9a34b453
MS
707 clk_pm_runtime_put(core);
708
4dff95dc
SB
709 trace_clk_unprepare_complete(core);
710 clk_core_unprepare(core->parent);
b2476490
MT
711}
712
a6adc30b
DA
713static void clk_core_unprepare_lock(struct clk_core *core)
714{
715 clk_prepare_lock();
716 clk_core_unprepare(core);
717 clk_prepare_unlock();
718}
719
4dff95dc
SB
720/**
721 * clk_unprepare - undo preparation of a clock source
722 * @clk: the clk being unprepared
723 *
724 * clk_unprepare may sleep, which differentiates it from clk_disable. In a
725 * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
726 * if the operation may sleep. One example is a clk which is accessed over
727 * I2c. In the complex case a clk gate operation may require a fast and a slow
728 * part. It is this reason that clk_unprepare and clk_disable are not mutually
729 * exclusive. In fact clk_disable must be called before clk_unprepare.
730 */
731void clk_unprepare(struct clk *clk)
1e435256 732{
4dff95dc
SB
733 if (IS_ERR_OR_NULL(clk))
734 return;
735
a6adc30b 736 clk_core_unprepare_lock(clk->core);
1e435256 737}
4dff95dc 738EXPORT_SYMBOL_GPL(clk_unprepare);
1e435256 739
4dff95dc 740static int clk_core_prepare(struct clk_core *core)
b2476490 741{
4dff95dc 742 int ret = 0;
b2476490 743
a6334725
SB
744 lockdep_assert_held(&prepare_lock);
745
4dff95dc 746 if (!core)
1e435256 747 return 0;
1e435256 748
4dff95dc 749 if (core->prepare_count == 0) {
9a34b453 750 ret = clk_pm_runtime_get(core);
4dff95dc
SB
751 if (ret)
752 return ret;
b2476490 753
9a34b453
MS
754 ret = clk_core_prepare(core->parent);
755 if (ret)
756 goto runtime_put;
757
4dff95dc 758 trace_clk_prepare(core);
b2476490 759
4dff95dc
SB
760 if (core->ops->prepare)
761 ret = core->ops->prepare(core->hw);
b2476490 762
4dff95dc 763 trace_clk_prepare_complete(core);
1c155b3d 764
9a34b453
MS
765 if (ret)
766 goto unprepare;
4dff95dc 767 }
1c155b3d 768
4dff95dc 769 core->prepare_count++;
b2476490 770
9461f7b3
JB
771 /*
772 * CLK_SET_RATE_GATE is a special case of clock protection
773 * Instead of a consumer claiming exclusive rate control, it is
774 * actually the provider which prevents any consumer from making any
775 * operation which could result in a rate change or rate glitch while
776 * the clock is prepared.
777 */
778 if (core->flags & CLK_SET_RATE_GATE)
779 clk_core_rate_protect(core);
780
b2476490 781 return 0;
9a34b453
MS
782unprepare:
783 clk_core_unprepare(core->parent);
784runtime_put:
785 clk_pm_runtime_put(core);
786 return ret;
b2476490 787}
b2476490 788
a6adc30b
DA
789static int clk_core_prepare_lock(struct clk_core *core)
790{
791 int ret;
792
793 clk_prepare_lock();
794 ret = clk_core_prepare(core);
795 clk_prepare_unlock();
796
797 return ret;
798}
799
4dff95dc
SB
800/**
801 * clk_prepare - prepare a clock source
802 * @clk: the clk being prepared
803 *
804 * clk_prepare may sleep, which differentiates it from clk_enable. In a simple
805 * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
806 * operation may sleep. One example is a clk which is accessed over I2c. In
807 * the complex case a clk ungate operation may require a fast and a slow part.
808 * It is this reason that clk_prepare and clk_enable are not mutually
809 * exclusive. In fact clk_prepare must be called before clk_enable.
810 * Returns 0 on success, -EERROR otherwise.
811 */
812int clk_prepare(struct clk *clk)
b2476490 813{
4dff95dc
SB
814 if (!clk)
815 return 0;
b2476490 816
a6adc30b 817 return clk_core_prepare_lock(clk->core);
b2476490 818}
4dff95dc 819EXPORT_SYMBOL_GPL(clk_prepare);
b2476490 820
4dff95dc 821static void clk_core_disable(struct clk_core *core)
b2476490 822{
a6334725
SB
823 lockdep_assert_held(&enable_lock);
824
4dff95dc
SB
825 if (!core)
826 return;
035a61c3 827
ab525dcc 828 if (WARN(core->enable_count == 0, "%s already disabled\n", core->name))
4dff95dc 829 return;
b2476490 830
ab525dcc
FE
831 if (WARN(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL,
832 "Disabling critical %s\n", core->name))
2e20fbf5
LJ
833 return;
834
4dff95dc
SB
835 if (--core->enable_count > 0)
836 return;
035a61c3 837
2f87a6ea 838 trace_clk_disable_rcuidle(core);
035a61c3 839
4dff95dc
SB
840 if (core->ops->disable)
841 core->ops->disable(core->hw);
035a61c3 842
2f87a6ea 843 trace_clk_disable_complete_rcuidle(core);
035a61c3 844
4dff95dc 845 clk_core_disable(core->parent);
035a61c3 846}
7ef3dcc8 847
a6adc30b
DA
848static void clk_core_disable_lock(struct clk_core *core)
849{
850 unsigned long flags;
851
852 flags = clk_enable_lock();
853 clk_core_disable(core);
854 clk_enable_unlock(flags);
855}
856
4dff95dc
SB
857/**
858 * clk_disable - gate a clock
859 * @clk: the clk being gated
860 *
861 * clk_disable must not sleep, which differentiates it from clk_unprepare. In
862 * a simple case, clk_disable can be used instead of clk_unprepare to gate a
863 * clk if the operation is fast and will never sleep. One example is a
864 * SoC-internal clk which is controlled via simple register writes. In the
865 * complex case a clk gate operation may require a fast and a slow part. It is
866 * this reason that clk_unprepare and clk_disable are not mutually exclusive.
867 * In fact clk_disable must be called before clk_unprepare.
868 */
869void clk_disable(struct clk *clk)
b2476490 870{
4dff95dc
SB
871 if (IS_ERR_OR_NULL(clk))
872 return;
873
a6adc30b 874 clk_core_disable_lock(clk->core);
b2476490 875}
4dff95dc 876EXPORT_SYMBOL_GPL(clk_disable);
b2476490 877
4dff95dc 878static int clk_core_enable(struct clk_core *core)
b2476490 879{
4dff95dc 880 int ret = 0;
b2476490 881
a6334725
SB
882 lockdep_assert_held(&enable_lock);
883
4dff95dc
SB
884 if (!core)
885 return 0;
b2476490 886
ab525dcc
FE
887 if (WARN(core->prepare_count == 0,
888 "Enabling unprepared %s\n", core->name))
4dff95dc 889 return -ESHUTDOWN;
b2476490 890
4dff95dc
SB
891 if (core->enable_count == 0) {
892 ret = clk_core_enable(core->parent);
b2476490 893
4dff95dc
SB
894 if (ret)
895 return ret;
b2476490 896
f17a0dd1 897 trace_clk_enable_rcuidle(core);
035a61c3 898
4dff95dc
SB
899 if (core->ops->enable)
900 ret = core->ops->enable(core->hw);
035a61c3 901
f17a0dd1 902 trace_clk_enable_complete_rcuidle(core);
4dff95dc
SB
903
904 if (ret) {
905 clk_core_disable(core->parent);
906 return ret;
907 }
908 }
909
910 core->enable_count++;
911 return 0;
035a61c3 912}
b2476490 913
a6adc30b
DA
914static int clk_core_enable_lock(struct clk_core *core)
915{
916 unsigned long flags;
917 int ret;
918
919 flags = clk_enable_lock();
920 ret = clk_core_enable(core);
921 clk_enable_unlock(flags);
922
923 return ret;
924}
925
8b95d1ce
RD
926static int _clk_save_context(struct clk_core *clk)
927{
928 struct clk_core *child;
929 int ret = 0;
930
931 hlist_for_each_entry(child, &clk->children, child_node) {
932 ret = _clk_save_context(child);
933 if (ret < 0)
934 return ret;
935 }
936
937 if (clk->ops && clk->ops->save_context)
938 ret = clk->ops->save_context(clk->hw);
939
940 return ret;
941}
942
943static void _clk_restore_context(struct clk_core *clk)
944{
945 struct clk_core *child;
946
947 if (clk->ops && clk->ops->restore_context)
948 clk->ops->restore_context(clk->hw);
949
950 hlist_for_each_entry(child, &clk->children, child_node)
951 _clk_restore_context(child);
952}
953
954/**
955 * clk_save_context - save clock context for poweroff
956 *
957 * Saves the context of the clock register for powerstates in which the
958 * contents of the registers will be lost. Occurs deep within the suspend
959 * code. Returns 0 on success.
960 */
961int clk_save_context(void)
962{
963 struct clk_core *clk;
964 int ret;
965
966 hlist_for_each_entry(clk, &clk_root_list, child_node) {
967 ret = _clk_save_context(clk);
968 if (ret < 0)
969 return ret;
970 }
971
972 hlist_for_each_entry(clk, &clk_orphan_list, child_node) {
973 ret = _clk_save_context(clk);
974 if (ret < 0)
975 return ret;
976 }
977
978 return 0;
979}
980EXPORT_SYMBOL_GPL(clk_save_context);
981
982/**
983 * clk_restore_context - restore clock context after poweroff
984 *
985 * Restore the saved clock context upon resume.
986 *
987 */
988void clk_restore_context(void)
989{
990 struct clk_core *clk;
991
992 hlist_for_each_entry(clk, &clk_root_list, child_node)
993 _clk_restore_context(clk);
994
995 hlist_for_each_entry(clk, &clk_orphan_list, child_node)
996 _clk_restore_context(clk);
997}
998EXPORT_SYMBOL_GPL(clk_restore_context);
999
4dff95dc
SB
1000/**
1001 * clk_enable - ungate a clock
1002 * @clk: the clk being ungated
1003 *
1004 * clk_enable must not sleep, which differentiates it from clk_prepare. In a
1005 * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
1006 * if the operation will never sleep. One example is a SoC-internal clk which
1007 * is controlled via simple register writes. In the complex case a clk ungate
1008 * operation may require a fast and a slow part. It is this reason that
1009 * clk_enable and clk_prepare are not mutually exclusive. In fact clk_prepare
1010 * must be called before clk_enable. Returns 0 on success, -EERROR
1011 * otherwise.
1012 */
1013int clk_enable(struct clk *clk)
5279fc40 1014{
4dff95dc 1015 if (!clk)
5279fc40
BB
1016 return 0;
1017
a6adc30b
DA
1018 return clk_core_enable_lock(clk->core);
1019}
1020EXPORT_SYMBOL_GPL(clk_enable);
1021
1022static int clk_core_prepare_enable(struct clk_core *core)
1023{
1024 int ret;
1025
1026 ret = clk_core_prepare_lock(core);
1027 if (ret)
1028 return ret;
1029
1030 ret = clk_core_enable_lock(core);
1031 if (ret)
1032 clk_core_unprepare_lock(core);
5279fc40 1033
4dff95dc 1034 return ret;
b2476490 1035}
a6adc30b
DA
1036
1037static void clk_core_disable_unprepare(struct clk_core *core)
1038{
1039 clk_core_disable_lock(core);
1040 clk_core_unprepare_lock(core);
1041}
b2476490 1042
7ec986ef
DA
1043static void clk_unprepare_unused_subtree(struct clk_core *core)
1044{
1045 struct clk_core *child;
1046
1047 lockdep_assert_held(&prepare_lock);
1048
1049 hlist_for_each_entry(child, &core->children, child_node)
1050 clk_unprepare_unused_subtree(child);
1051
1052 if (core->prepare_count)
1053 return;
1054
1055 if (core->flags & CLK_IGNORE_UNUSED)
1056 return;
1057
9a34b453
MS
1058 if (clk_pm_runtime_get(core))
1059 return;
1060
7ec986ef
DA
1061 if (clk_core_is_prepared(core)) {
1062 trace_clk_unprepare(core);
1063 if (core->ops->unprepare_unused)
1064 core->ops->unprepare_unused(core->hw);
1065 else if (core->ops->unprepare)
1066 core->ops->unprepare(core->hw);
1067 trace_clk_unprepare_complete(core);
1068 }
9a34b453
MS
1069
1070 clk_pm_runtime_put(core);
7ec986ef
DA
1071}
1072
1073static void clk_disable_unused_subtree(struct clk_core *core)
1074{
1075 struct clk_core *child;
1076 unsigned long flags;
1077
1078 lockdep_assert_held(&prepare_lock);
1079
1080 hlist_for_each_entry(child, &core->children, child_node)
1081 clk_disable_unused_subtree(child);
1082
a4b3518d
DA
1083 if (core->flags & CLK_OPS_PARENT_ENABLE)
1084 clk_core_prepare_enable(core->parent);
1085
9a34b453
MS
1086 if (clk_pm_runtime_get(core))
1087 goto unprepare_out;
1088
7ec986ef
DA
1089 flags = clk_enable_lock();
1090
1091 if (core->enable_count)
1092 goto unlock_out;
1093
1094 if (core->flags & CLK_IGNORE_UNUSED)
1095 goto unlock_out;
1096
1097 /*
1098 * some gate clocks have special needs during the disable-unused
1099 * sequence. call .disable_unused if available, otherwise fall
1100 * back to .disable
1101 */
1102 if (clk_core_is_enabled(core)) {
1103 trace_clk_disable(core);
1104 if (core->ops->disable_unused)
1105 core->ops->disable_unused(core->hw);
1106 else if (core->ops->disable)
1107 core->ops->disable(core->hw);
1108 trace_clk_disable_complete(core);
1109 }
1110
1111unlock_out:
1112 clk_enable_unlock(flags);
9a34b453
MS
1113 clk_pm_runtime_put(core);
1114unprepare_out:
a4b3518d
DA
1115 if (core->flags & CLK_OPS_PARENT_ENABLE)
1116 clk_core_disable_unprepare(core->parent);
7ec986ef
DA
1117}
1118
1119static bool clk_ignore_unused;
1120static int __init clk_ignore_unused_setup(char *__unused)
1121{
1122 clk_ignore_unused = true;
1123 return 1;
1124}
1125__setup("clk_ignore_unused", clk_ignore_unused_setup);
1126
1127static int clk_disable_unused(void)
1128{
1129 struct clk_core *core;
1130
1131 if (clk_ignore_unused) {
1132 pr_warn("clk: Not disabling unused clocks\n");
1133 return 0;
1134 }
1135
1136 clk_prepare_lock();
1137
1138 hlist_for_each_entry(core, &clk_root_list, child_node)
1139 clk_disable_unused_subtree(core);
1140
1141 hlist_for_each_entry(core, &clk_orphan_list, child_node)
1142 clk_disable_unused_subtree(core);
1143
1144 hlist_for_each_entry(core, &clk_root_list, child_node)
1145 clk_unprepare_unused_subtree(core);
1146
1147 hlist_for_each_entry(core, &clk_orphan_list, child_node)
1148 clk_unprepare_unused_subtree(core);
1149
1150 clk_prepare_unlock();
1151
1152 return 0;
1153}
1154late_initcall_sync(clk_disable_unused);
1155
0f6cc2b8
JB
1156static int clk_core_determine_round_nolock(struct clk_core *core,
1157 struct clk_rate_request *req)
3d6ee287 1158{
0817b62c 1159 long rate;
4dff95dc
SB
1160
1161 lockdep_assert_held(&prepare_lock);
3d6ee287 1162
d6968fca 1163 if (!core)
4dff95dc 1164 return 0;
3d6ee287 1165
55e9b8b7
JB
1166 /*
1167 * At this point, core protection will be disabled if
1168 * - if the provider is not protected at all
1169 * - if the calling consumer is the only one which has exclusivity
1170 * over the provider
1171 */
e55a839a
JB
1172 if (clk_core_rate_is_protected(core)) {
1173 req->rate = core->rate;
1174 } else if (core->ops->determine_rate) {
0817b62c
BB
1175 return core->ops->determine_rate(core->hw, req);
1176 } else if (core->ops->round_rate) {
1177 rate = core->ops->round_rate(core->hw, req->rate,
1178 &req->best_parent_rate);
1179 if (rate < 0)
1180 return rate;
1181
1182 req->rate = rate;
0817b62c 1183 } else {
0f6cc2b8 1184 return -EINVAL;
0817b62c
BB
1185 }
1186
1187 return 0;
3d6ee287
UH
1188}
1189
0f6cc2b8
JB
1190static void clk_core_init_rate_req(struct clk_core * const core,
1191 struct clk_rate_request *req)
1192{
1193 struct clk_core *parent;
1194
1195 if (WARN_ON(!core || !req))
1196 return;
1197
1198 parent = core->parent;
1199 if (parent) {
1200 req->best_parent_hw = parent->hw;
1201 req->best_parent_rate = parent->rate;
1202 } else {
1203 req->best_parent_hw = NULL;
1204 req->best_parent_rate = 0;
0817b62c 1205 }
0f6cc2b8 1206}
0817b62c 1207
0f6cc2b8
JB
1208static bool clk_core_can_round(struct clk_core * const core)
1209{
1210 if (core->ops->determine_rate || core->ops->round_rate)
1211 return true;
1212
1213 return false;
1214}
1215
1216static int clk_core_round_rate_nolock(struct clk_core *core,
1217 struct clk_rate_request *req)
1218{
1219 lockdep_assert_held(&prepare_lock);
1220
04bf9ab3
JB
1221 if (!core) {
1222 req->rate = 0;
0f6cc2b8 1223 return 0;
04bf9ab3 1224 }
0817b62c 1225
0f6cc2b8
JB
1226 clk_core_init_rate_req(core, req);
1227
1228 if (clk_core_can_round(core))
1229 return clk_core_determine_round_nolock(core, req);
1230 else if (core->flags & CLK_SET_RATE_PARENT)
1231 return clk_core_round_rate_nolock(core->parent, req);
1232
1233 req->rate = core->rate;
0817b62c 1234 return 0;
3d6ee287
UH
1235}
1236
4dff95dc
SB
1237/**
1238 * __clk_determine_rate - get the closest rate actually supported by a clock
1239 * @hw: determine the rate of this clock
2d5b520c 1240 * @req: target rate request
4dff95dc 1241 *
6e5ab41b 1242 * Useful for clk_ops such as .set_rate and .determine_rate.
4dff95dc 1243 */
0817b62c 1244int __clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
035a61c3 1245{
0817b62c
BB
1246 if (!hw) {
1247 req->rate = 0;
4dff95dc 1248 return 0;
0817b62c 1249 }
035a61c3 1250
0817b62c 1251 return clk_core_round_rate_nolock(hw->core, req);
035a61c3 1252}
4dff95dc 1253EXPORT_SYMBOL_GPL(__clk_determine_rate);
035a61c3 1254
1a9c069c
SB
1255unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate)
1256{
1257 int ret;
1258 struct clk_rate_request req;
1259
1260 clk_core_get_boundaries(hw->core, &req.min_rate, &req.max_rate);
1261 req.rate = rate;
1262
1263 ret = clk_core_round_rate_nolock(hw->core, &req);
1264 if (ret)
1265 return 0;
1266
1267 return req.rate;
1268}
1269EXPORT_SYMBOL_GPL(clk_hw_round_rate);
1270
4dff95dc
SB
1271/**
1272 * clk_round_rate - round the given rate for a clk
1273 * @clk: the clk for which we are rounding a rate
1274 * @rate: the rate which is to be rounded
1275 *
1276 * Takes in a rate as input and rounds it to a rate that the clk can actually
1277 * use which is then returned. If clk doesn't support round_rate operation
1278 * then the parent rate is returned.
1279 */
1280long clk_round_rate(struct clk *clk, unsigned long rate)
035a61c3 1281{
fc4a05d4
SB
1282 struct clk_rate_request req;
1283 int ret;
4dff95dc 1284
035a61c3 1285 if (!clk)
4dff95dc 1286 return 0;
035a61c3 1287
4dff95dc 1288 clk_prepare_lock();
fc4a05d4 1289
55e9b8b7
JB
1290 if (clk->exclusive_count)
1291 clk_core_rate_unprotect(clk->core);
1292
fc4a05d4
SB
1293 clk_core_get_boundaries(clk->core, &req.min_rate, &req.max_rate);
1294 req.rate = rate;
1295
1296 ret = clk_core_round_rate_nolock(clk->core, &req);
55e9b8b7
JB
1297
1298 if (clk->exclusive_count)
1299 clk_core_rate_protect(clk->core);
1300
4dff95dc
SB
1301 clk_prepare_unlock();
1302
fc4a05d4
SB
1303 if (ret)
1304 return ret;
1305
1306 return req.rate;
035a61c3 1307}
4dff95dc 1308EXPORT_SYMBOL_GPL(clk_round_rate);
b2476490 1309
4dff95dc
SB
1310/**
1311 * __clk_notify - call clk notifier chain
1312 * @core: clk that is changing rate
1313 * @msg: clk notifier type (see include/linux/clk.h)
1314 * @old_rate: old clk rate
1315 * @new_rate: new clk rate
1316 *
1317 * Triggers a notifier call chain on the clk rate-change notification
1318 * for 'clk'. Passes a pointer to the struct clk and the previous
1319 * and current rates to the notifier callback. Intended to be called by
1320 * internal clock code only. Returns NOTIFY_DONE from the last driver
1321 * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
1322 * a driver returns that.
1323 */
1324static int __clk_notify(struct clk_core *core, unsigned long msg,
1325 unsigned long old_rate, unsigned long new_rate)
b2476490 1326{
4dff95dc
SB
1327 struct clk_notifier *cn;
1328 struct clk_notifier_data cnd;
1329 int ret = NOTIFY_DONE;
b2476490 1330
4dff95dc
SB
1331 cnd.old_rate = old_rate;
1332 cnd.new_rate = new_rate;
b2476490 1333
4dff95dc
SB
1334 list_for_each_entry(cn, &clk_notifier_list, node) {
1335 if (cn->clk->core == core) {
1336 cnd.clk = cn->clk;
1337 ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
1338 &cnd);
17c34c56
PDS
1339 if (ret & NOTIFY_STOP_MASK)
1340 return ret;
4dff95dc 1341 }
b2476490
MT
1342 }
1343
4dff95dc 1344 return ret;
b2476490
MT
1345}
1346
4dff95dc
SB
1347/**
1348 * __clk_recalc_accuracies
1349 * @core: first clk in the subtree
1350 *
1351 * Walks the subtree of clks starting with clk and recalculates accuracies as
1352 * it goes. Note that if a clk does not implement the .recalc_accuracy
6e5ab41b 1353 * callback then it is assumed that the clock will take on the accuracy of its
4dff95dc 1354 * parent.
4dff95dc
SB
1355 */
1356static void __clk_recalc_accuracies(struct clk_core *core)
b2476490 1357{
4dff95dc
SB
1358 unsigned long parent_accuracy = 0;
1359 struct clk_core *child;
b2476490 1360
4dff95dc 1361 lockdep_assert_held(&prepare_lock);
b2476490 1362
4dff95dc
SB
1363 if (core->parent)
1364 parent_accuracy = core->parent->accuracy;
b2476490 1365
4dff95dc
SB
1366 if (core->ops->recalc_accuracy)
1367 core->accuracy = core->ops->recalc_accuracy(core->hw,
1368 parent_accuracy);
1369 else
1370 core->accuracy = parent_accuracy;
b2476490 1371
4dff95dc
SB
1372 hlist_for_each_entry(child, &core->children, child_node)
1373 __clk_recalc_accuracies(child);
b2476490
MT
1374}
1375
4dff95dc 1376static long clk_core_get_accuracy(struct clk_core *core)
e366fdd7 1377{
4dff95dc 1378 unsigned long accuracy;
15a02c1f 1379
4dff95dc
SB
1380 clk_prepare_lock();
1381 if (core && (core->flags & CLK_GET_ACCURACY_NOCACHE))
1382 __clk_recalc_accuracies(core);
15a02c1f 1383
4dff95dc
SB
1384 accuracy = __clk_get_accuracy(core);
1385 clk_prepare_unlock();
e366fdd7 1386
4dff95dc 1387 return accuracy;
e366fdd7 1388}
15a02c1f 1389
4dff95dc
SB
1390/**
1391 * clk_get_accuracy - return the accuracy of clk
1392 * @clk: the clk whose accuracy is being returned
1393 *
1394 * Simply returns the cached accuracy of the clk, unless
1395 * CLK_GET_ACCURACY_NOCACHE flag is set, which means a recalc_rate will be
1396 * issued.
1397 * If clk is NULL then returns 0.
1398 */
1399long clk_get_accuracy(struct clk *clk)
035a61c3 1400{
4dff95dc
SB
1401 if (!clk)
1402 return 0;
035a61c3 1403
4dff95dc 1404 return clk_core_get_accuracy(clk->core);
035a61c3 1405}
4dff95dc 1406EXPORT_SYMBOL_GPL(clk_get_accuracy);
035a61c3 1407
4dff95dc
SB
1408static unsigned long clk_recalc(struct clk_core *core,
1409 unsigned long parent_rate)
1c8e6004 1410{
9a34b453
MS
1411 unsigned long rate = parent_rate;
1412
1413 if (core->ops->recalc_rate && !clk_pm_runtime_get(core)) {
1414 rate = core->ops->recalc_rate(core->hw, parent_rate);
1415 clk_pm_runtime_put(core);
1416 }
1417 return rate;
1c8e6004
TV
1418}
1419
4dff95dc
SB
1420/**
1421 * __clk_recalc_rates
1422 * @core: first clk in the subtree
1423 * @msg: notification type (see include/linux/clk.h)
1424 *
1425 * Walks the subtree of clks starting with clk and recalculates rates as it
1426 * goes. Note that if a clk does not implement the .recalc_rate callback then
1427 * it is assumed that the clock will take on the rate of its parent.
1428 *
1429 * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
1430 * if necessary.
15a02c1f 1431 */
4dff95dc 1432static void __clk_recalc_rates(struct clk_core *core, unsigned long msg)
15a02c1f 1433{
4dff95dc
SB
1434 unsigned long old_rate;
1435 unsigned long parent_rate = 0;
1436 struct clk_core *child;
e366fdd7 1437
4dff95dc 1438 lockdep_assert_held(&prepare_lock);
15a02c1f 1439
4dff95dc 1440 old_rate = core->rate;
b2476490 1441
4dff95dc
SB
1442 if (core->parent)
1443 parent_rate = core->parent->rate;
b2476490 1444
4dff95dc 1445 core->rate = clk_recalc(core, parent_rate);
b2476490 1446
4dff95dc
SB
1447 /*
1448 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
1449 * & ABORT_RATE_CHANGE notifiers
1450 */
1451 if (core->notifier_count && msg)
1452 __clk_notify(core, msg, old_rate, core->rate);
b2476490 1453
4dff95dc
SB
1454 hlist_for_each_entry(child, &core->children, child_node)
1455 __clk_recalc_rates(child, msg);
1456}
b2476490 1457
4dff95dc
SB
1458static unsigned long clk_core_get_rate(struct clk_core *core)
1459{
1460 unsigned long rate;
dfc202ea 1461
4dff95dc 1462 clk_prepare_lock();
b2476490 1463
4dff95dc
SB
1464 if (core && (core->flags & CLK_GET_RATE_NOCACHE))
1465 __clk_recalc_rates(core, 0);
1466
1467 rate = clk_core_get_rate_nolock(core);
1468 clk_prepare_unlock();
1469
1470 return rate;
b2476490
MT
1471}
1472
1473/**
4dff95dc
SB
1474 * clk_get_rate - return the rate of clk
1475 * @clk: the clk whose rate is being returned
b2476490 1476 *
4dff95dc
SB
1477 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1478 * is set, which means a recalc_rate will be issued.
1479 * If clk is NULL then returns 0.
b2476490 1480 */
4dff95dc 1481unsigned long clk_get_rate(struct clk *clk)
b2476490 1482{
4dff95dc
SB
1483 if (!clk)
1484 return 0;
63589e92 1485
4dff95dc 1486 return clk_core_get_rate(clk->core);
b2476490 1487}
4dff95dc 1488EXPORT_SYMBOL_GPL(clk_get_rate);
b2476490 1489
4dff95dc
SB
1490static int clk_fetch_parent_index(struct clk_core *core,
1491 struct clk_core *parent)
b2476490 1492{
4dff95dc 1493 int i;
b2476490 1494
508f884a
MY
1495 if (!parent)
1496 return -EINVAL;
1497
470b5e2f
MY
1498 for (i = 0; i < core->num_parents; i++)
1499 if (clk_core_get_parent_by_index(core, i) == parent)
4dff95dc 1500 return i;
b2476490 1501
4dff95dc 1502 return -EINVAL;
b2476490
MT
1503}
1504
e6500344
HS
1505/*
1506 * Update the orphan status of @core and all its children.
1507 */
1508static void clk_core_update_orphan_status(struct clk_core *core, bool is_orphan)
1509{
1510 struct clk_core *child;
1511
1512 core->orphan = is_orphan;
1513
1514 hlist_for_each_entry(child, &core->children, child_node)
1515 clk_core_update_orphan_status(child, is_orphan);
1516}
1517
4dff95dc 1518static void clk_reparent(struct clk_core *core, struct clk_core *new_parent)
b2476490 1519{
e6500344
HS
1520 bool was_orphan = core->orphan;
1521
4dff95dc 1522 hlist_del(&core->child_node);
035a61c3 1523
4dff95dc 1524 if (new_parent) {
e6500344
HS
1525 bool becomes_orphan = new_parent->orphan;
1526
4dff95dc
SB
1527 /* avoid duplicate POST_RATE_CHANGE notifications */
1528 if (new_parent->new_child == core)
1529 new_parent->new_child = NULL;
b2476490 1530
4dff95dc 1531 hlist_add_head(&core->child_node, &new_parent->children);
e6500344
HS
1532
1533 if (was_orphan != becomes_orphan)
1534 clk_core_update_orphan_status(core, becomes_orphan);
4dff95dc
SB
1535 } else {
1536 hlist_add_head(&core->child_node, &clk_orphan_list);
e6500344
HS
1537 if (!was_orphan)
1538 clk_core_update_orphan_status(core, true);
4dff95dc 1539 }
dfc202ea 1540
4dff95dc 1541 core->parent = new_parent;
035a61c3
TV
1542}
1543
4dff95dc
SB
1544static struct clk_core *__clk_set_parent_before(struct clk_core *core,
1545 struct clk_core *parent)
b2476490
MT
1546{
1547 unsigned long flags;
4dff95dc 1548 struct clk_core *old_parent = core->parent;
b2476490 1549
4dff95dc 1550 /*
fc8726a2
DA
1551 * 1. enable parents for CLK_OPS_PARENT_ENABLE clock
1552 *
1553 * 2. Migrate prepare state between parents and prevent race with
4dff95dc
SB
1554 * clk_enable().
1555 *
1556 * If the clock is not prepared, then a race with
1557 * clk_enable/disable() is impossible since we already have the
1558 * prepare lock (future calls to clk_enable() need to be preceded by
1559 * a clk_prepare()).
1560 *
1561 * If the clock is prepared, migrate the prepared state to the new
1562 * parent and also protect against a race with clk_enable() by
1563 * forcing the clock and the new parent on. This ensures that all
1564 * future calls to clk_enable() are practically NOPs with respect to
1565 * hardware and software states.
1566 *
1567 * See also: Comment for clk_set_parent() below.
1568 */
fc8726a2
DA
1569
1570 /* enable old_parent & parent if CLK_OPS_PARENT_ENABLE is set */
1571 if (core->flags & CLK_OPS_PARENT_ENABLE) {
1572 clk_core_prepare_enable(old_parent);
1573 clk_core_prepare_enable(parent);
1574 }
1575
1576 /* migrate prepare count if > 0 */
4dff95dc 1577 if (core->prepare_count) {
fc8726a2
DA
1578 clk_core_prepare_enable(parent);
1579 clk_core_enable_lock(core);
4dff95dc 1580 }
63589e92 1581
4dff95dc 1582 /* update the clk tree topology */
eab89f69 1583 flags = clk_enable_lock();
4dff95dc 1584 clk_reparent(core, parent);
eab89f69 1585 clk_enable_unlock(flags);
4dff95dc
SB
1586
1587 return old_parent;
b2476490 1588}
b2476490 1589
4dff95dc
SB
1590static void __clk_set_parent_after(struct clk_core *core,
1591 struct clk_core *parent,
1592 struct clk_core *old_parent)
b2476490 1593{
4dff95dc
SB
1594 /*
1595 * Finish the migration of prepare state and undo the changes done
1596 * for preventing a race with clk_enable().
1597 */
1598 if (core->prepare_count) {
fc8726a2
DA
1599 clk_core_disable_lock(core);
1600 clk_core_disable_unprepare(old_parent);
1601 }
1602
1603 /* re-balance ref counting if CLK_OPS_PARENT_ENABLE is set */
1604 if (core->flags & CLK_OPS_PARENT_ENABLE) {
1605 clk_core_disable_unprepare(parent);
1606 clk_core_disable_unprepare(old_parent);
4dff95dc
SB
1607 }
1608}
b2476490 1609
4dff95dc
SB
1610static int __clk_set_parent(struct clk_core *core, struct clk_core *parent,
1611 u8 p_index)
1612{
1613 unsigned long flags;
1614 int ret = 0;
1615 struct clk_core *old_parent;
b2476490 1616
4dff95dc 1617 old_parent = __clk_set_parent_before(core, parent);
b2476490 1618
4dff95dc 1619 trace_clk_set_parent(core, parent);
b2476490 1620
4dff95dc
SB
1621 /* change clock input source */
1622 if (parent && core->ops->set_parent)
1623 ret = core->ops->set_parent(core->hw, p_index);
dfc202ea 1624
4dff95dc 1625 trace_clk_set_parent_complete(core, parent);
dfc202ea 1626
4dff95dc
SB
1627 if (ret) {
1628 flags = clk_enable_lock();
1629 clk_reparent(core, old_parent);
1630 clk_enable_unlock(flags);
c660b2eb 1631 __clk_set_parent_after(core, old_parent, parent);
dfc202ea 1632
4dff95dc 1633 return ret;
b2476490
MT
1634 }
1635
4dff95dc
SB
1636 __clk_set_parent_after(core, parent, old_parent);
1637
b2476490
MT
1638 return 0;
1639}
1640
1641/**
4dff95dc
SB
1642 * __clk_speculate_rates
1643 * @core: first clk in the subtree
1644 * @parent_rate: the "future" rate of clk's parent
b2476490 1645 *
4dff95dc
SB
1646 * Walks the subtree of clks starting with clk, speculating rates as it
1647 * goes and firing off PRE_RATE_CHANGE notifications as necessary.
1648 *
1649 * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
1650 * pre-rate change notifications and returns early if no clks in the
1651 * subtree have subscribed to the notifications. Note that if a clk does not
1652 * implement the .recalc_rate callback then it is assumed that the clock will
1653 * take on the rate of its parent.
b2476490 1654 */
4dff95dc
SB
1655static int __clk_speculate_rates(struct clk_core *core,
1656 unsigned long parent_rate)
b2476490 1657{
4dff95dc
SB
1658 struct clk_core *child;
1659 unsigned long new_rate;
1660 int ret = NOTIFY_DONE;
b2476490 1661
4dff95dc 1662 lockdep_assert_held(&prepare_lock);
864e160a 1663
4dff95dc
SB
1664 new_rate = clk_recalc(core, parent_rate);
1665
1666 /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */
1667 if (core->notifier_count)
1668 ret = __clk_notify(core, PRE_RATE_CHANGE, core->rate, new_rate);
1669
1670 if (ret & NOTIFY_STOP_MASK) {
1671 pr_debug("%s: clk notifier callback for clock %s aborted with error %d\n",
1672 __func__, core->name, ret);
1673 goto out;
1674 }
1675
1676 hlist_for_each_entry(child, &core->children, child_node) {
1677 ret = __clk_speculate_rates(child, new_rate);
1678 if (ret & NOTIFY_STOP_MASK)
1679 break;
1680 }
b2476490 1681
4dff95dc 1682out:
b2476490
MT
1683 return ret;
1684}
b2476490 1685
4dff95dc
SB
1686static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate,
1687 struct clk_core *new_parent, u8 p_index)
b2476490 1688{
4dff95dc 1689 struct clk_core *child;
b2476490 1690
4dff95dc
SB
1691 core->new_rate = new_rate;
1692 core->new_parent = new_parent;
1693 core->new_parent_index = p_index;
1694 /* include clk in new parent's PRE_RATE_CHANGE notifications */
1695 core->new_child = NULL;
1696 if (new_parent && new_parent != core->parent)
1697 new_parent->new_child = core;
496eadf8 1698
4dff95dc
SB
1699 hlist_for_each_entry(child, &core->children, child_node) {
1700 child->new_rate = clk_recalc(child, new_rate);
1701 clk_calc_subtree(child, child->new_rate, NULL, 0);
1702 }
1703}
b2476490 1704
4dff95dc
SB
1705/*
1706 * calculate the new rates returning the topmost clock that has to be
1707 * changed.
1708 */
1709static struct clk_core *clk_calc_new_rates(struct clk_core *core,
1710 unsigned long rate)
1711{
1712 struct clk_core *top = core;
1713 struct clk_core *old_parent, *parent;
4dff95dc
SB
1714 unsigned long best_parent_rate = 0;
1715 unsigned long new_rate;
1716 unsigned long min_rate;
1717 unsigned long max_rate;
1718 int p_index = 0;
1719 long ret;
1720
1721 /* sanity */
1722 if (IS_ERR_OR_NULL(core))
1723 return NULL;
1724
1725 /* save parent rate, if it exists */
1726 parent = old_parent = core->parent;
71472c0c 1727 if (parent)
4dff95dc 1728 best_parent_rate = parent->rate;
71472c0c 1729
4dff95dc
SB
1730 clk_core_get_boundaries(core, &min_rate, &max_rate);
1731
1732 /* find the closest rate and parent clk/rate */
0f6cc2b8 1733 if (clk_core_can_round(core)) {
0817b62c
BB
1734 struct clk_rate_request req;
1735
1736 req.rate = rate;
1737 req.min_rate = min_rate;
1738 req.max_rate = max_rate;
0817b62c 1739
0f6cc2b8
JB
1740 clk_core_init_rate_req(core, &req);
1741
1742 ret = clk_core_determine_round_nolock(core, &req);
4dff95dc
SB
1743 if (ret < 0)
1744 return NULL;
1c8e6004 1745
0817b62c
BB
1746 best_parent_rate = req.best_parent_rate;
1747 new_rate = req.rate;
1748 parent = req.best_parent_hw ? req.best_parent_hw->core : NULL;
035a61c3 1749
4dff95dc
SB
1750 if (new_rate < min_rate || new_rate > max_rate)
1751 return NULL;
1752 } else if (!parent || !(core->flags & CLK_SET_RATE_PARENT)) {
1753 /* pass-through clock without adjustable parent */
1754 core->new_rate = core->rate;
1755 return NULL;
1756 } else {
1757 /* pass-through clock with adjustable parent */
1758 top = clk_calc_new_rates(parent, rate);
1759 new_rate = parent->new_rate;
1760 goto out;
1761 }
1c8e6004 1762
4dff95dc
SB
1763 /* some clocks must be gated to change parent */
1764 if (parent != old_parent &&
1765 (core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
1766 pr_debug("%s: %s not gated but wants to reparent\n",
1767 __func__, core->name);
1768 return NULL;
1769 }
b2476490 1770
4dff95dc
SB
1771 /* try finding the new parent index */
1772 if (parent && core->num_parents > 1) {
1773 p_index = clk_fetch_parent_index(core, parent);
1774 if (p_index < 0) {
1775 pr_debug("%s: clk %s can not be parent of clk %s\n",
1776 __func__, parent->name, core->name);
1777 return NULL;
1778 }
1779 }
b2476490 1780
4dff95dc
SB
1781 if ((core->flags & CLK_SET_RATE_PARENT) && parent &&
1782 best_parent_rate != parent->rate)
1783 top = clk_calc_new_rates(parent, best_parent_rate);
035a61c3 1784
4dff95dc
SB
1785out:
1786 clk_calc_subtree(core, new_rate, parent, p_index);
b2476490 1787
4dff95dc 1788 return top;
b2476490 1789}
b2476490 1790
4dff95dc
SB
1791/*
1792 * Notify about rate changes in a subtree. Always walk down the whole tree
1793 * so that in case of an error we can walk down the whole tree again and
1794 * abort the change.
b2476490 1795 */
4dff95dc
SB
1796static struct clk_core *clk_propagate_rate_change(struct clk_core *core,
1797 unsigned long event)
b2476490 1798{
4dff95dc 1799 struct clk_core *child, *tmp_clk, *fail_clk = NULL;
b2476490
MT
1800 int ret = NOTIFY_DONE;
1801
4dff95dc
SB
1802 if (core->rate == core->new_rate)
1803 return NULL;
b2476490 1804
4dff95dc
SB
1805 if (core->notifier_count) {
1806 ret = __clk_notify(core, event, core->rate, core->new_rate);
1807 if (ret & NOTIFY_STOP_MASK)
1808 fail_clk = core;
b2476490
MT
1809 }
1810
4dff95dc
SB
1811 hlist_for_each_entry(child, &core->children, child_node) {
1812 /* Skip children who will be reparented to another clock */
1813 if (child->new_parent && child->new_parent != core)
1814 continue;
1815 tmp_clk = clk_propagate_rate_change(child, event);
1816 if (tmp_clk)
1817 fail_clk = tmp_clk;
1818 }
5279fc40 1819
4dff95dc
SB
1820 /* handle the new child who might not be in core->children yet */
1821 if (core->new_child) {
1822 tmp_clk = clk_propagate_rate_change(core->new_child, event);
1823 if (tmp_clk)
1824 fail_clk = tmp_clk;
1825 }
5279fc40 1826
4dff95dc 1827 return fail_clk;
5279fc40
BB
1828}
1829
4dff95dc
SB
1830/*
1831 * walk down a subtree and set the new rates notifying the rate
1832 * change on the way
1833 */
1834static void clk_change_rate(struct clk_core *core)
035a61c3 1835{
4dff95dc
SB
1836 struct clk_core *child;
1837 struct hlist_node *tmp;
1838 unsigned long old_rate;
1839 unsigned long best_parent_rate = 0;
1840 bool skip_set_rate = false;
1841 struct clk_core *old_parent;
fc8726a2 1842 struct clk_core *parent = NULL;
035a61c3 1843
4dff95dc 1844 old_rate = core->rate;
035a61c3 1845
fc8726a2
DA
1846 if (core->new_parent) {
1847 parent = core->new_parent;
4dff95dc 1848 best_parent_rate = core->new_parent->rate;
fc8726a2
DA
1849 } else if (core->parent) {
1850 parent = core->parent;
4dff95dc 1851 best_parent_rate = core->parent->rate;
fc8726a2 1852 }
035a61c3 1853
588fb54b
MS
1854 if (clk_pm_runtime_get(core))
1855 return;
1856
2eb8c710
HS
1857 if (core->flags & CLK_SET_RATE_UNGATE) {
1858 unsigned long flags;
1859
1860 clk_core_prepare(core);
1861 flags = clk_enable_lock();
1862 clk_core_enable(core);
1863 clk_enable_unlock(flags);
1864 }
1865
4dff95dc
SB
1866 if (core->new_parent && core->new_parent != core->parent) {
1867 old_parent = __clk_set_parent_before(core, core->new_parent);
1868 trace_clk_set_parent(core, core->new_parent);
5279fc40 1869
4dff95dc
SB
1870 if (core->ops->set_rate_and_parent) {
1871 skip_set_rate = true;
1872 core->ops->set_rate_and_parent(core->hw, core->new_rate,
1873 best_parent_rate,
1874 core->new_parent_index);
1875 } else if (core->ops->set_parent) {
1876 core->ops->set_parent(core->hw, core->new_parent_index);
1877 }
5279fc40 1878
4dff95dc
SB
1879 trace_clk_set_parent_complete(core, core->new_parent);
1880 __clk_set_parent_after(core, core->new_parent, old_parent);
1881 }
8f2c2db1 1882
fc8726a2
DA
1883 if (core->flags & CLK_OPS_PARENT_ENABLE)
1884 clk_core_prepare_enable(parent);
1885
4dff95dc 1886 trace_clk_set_rate(core, core->new_rate);
b2476490 1887
4dff95dc
SB
1888 if (!skip_set_rate && core->ops->set_rate)
1889 core->ops->set_rate(core->hw, core->new_rate, best_parent_rate);
496eadf8 1890
4dff95dc 1891 trace_clk_set_rate_complete(core, core->new_rate);
b2476490 1892
4dff95dc 1893 core->rate = clk_recalc(core, best_parent_rate);
b2476490 1894
2eb8c710
HS
1895 if (core->flags & CLK_SET_RATE_UNGATE) {
1896 unsigned long flags;
1897
1898 flags = clk_enable_lock();
1899 clk_core_disable(core);
1900 clk_enable_unlock(flags);
1901 clk_core_unprepare(core);
1902 }
1903
fc8726a2
DA
1904 if (core->flags & CLK_OPS_PARENT_ENABLE)
1905 clk_core_disable_unprepare(parent);
1906
4dff95dc
SB
1907 if (core->notifier_count && old_rate != core->rate)
1908 __clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate);
b2476490 1909
85e88fab
MT
1910 if (core->flags & CLK_RECALC_NEW_RATES)
1911 (void)clk_calc_new_rates(core, core->new_rate);
d8d91987 1912
b2476490 1913 /*
4dff95dc
SB
1914 * Use safe iteration, as change_rate can actually swap parents
1915 * for certain clock types.
b2476490 1916 */
4dff95dc
SB
1917 hlist_for_each_entry_safe(child, tmp, &core->children, child_node) {
1918 /* Skip children who will be reparented to another clock */
1919 if (child->new_parent && child->new_parent != core)
1920 continue;
1921 clk_change_rate(child);
1922 }
b2476490 1923
4dff95dc
SB
1924 /* handle the new child who might not be in core->children yet */
1925 if (core->new_child)
1926 clk_change_rate(core->new_child);
588fb54b
MS
1927
1928 clk_pm_runtime_put(core);
b2476490
MT
1929}
1930
ca5e089a
JB
1931static unsigned long clk_core_req_round_rate_nolock(struct clk_core *core,
1932 unsigned long req_rate)
1933{
e55a839a 1934 int ret, cnt;
ca5e089a
JB
1935 struct clk_rate_request req;
1936
1937 lockdep_assert_held(&prepare_lock);
1938
1939 if (!core)
1940 return 0;
1941
e55a839a
JB
1942 /* simulate what the rate would be if it could be freely set */
1943 cnt = clk_core_rate_nuke_protect(core);
1944 if (cnt < 0)
1945 return cnt;
1946
ca5e089a
JB
1947 clk_core_get_boundaries(core, &req.min_rate, &req.max_rate);
1948 req.rate = req_rate;
1949
1950 ret = clk_core_round_rate_nolock(core, &req);
1951
e55a839a
JB
1952 /* restore the protection */
1953 clk_core_rate_restore_protect(core, cnt);
1954
ca5e089a 1955 return ret ? 0 : req.rate;
b2476490
MT
1956}
1957
4dff95dc
SB
1958static int clk_core_set_rate_nolock(struct clk_core *core,
1959 unsigned long req_rate)
a093bde2 1960{
4dff95dc 1961 struct clk_core *top, *fail_clk;
ca5e089a 1962 unsigned long rate;
9a34b453 1963 int ret = 0;
a093bde2 1964
4dff95dc
SB
1965 if (!core)
1966 return 0;
a093bde2 1967
ca5e089a
JB
1968 rate = clk_core_req_round_rate_nolock(core, req_rate);
1969
4dff95dc
SB
1970 /* bail early if nothing to do */
1971 if (rate == clk_core_get_rate_nolock(core))
1972 return 0;
a093bde2 1973
e55a839a
JB
1974 /* fail on a direct rate set of a protected provider */
1975 if (clk_core_rate_is_protected(core))
1976 return -EBUSY;
1977
4dff95dc 1978 /* calculate new rates and get the topmost changed clock */
ca5e089a 1979 top = clk_calc_new_rates(core, req_rate);
4dff95dc
SB
1980 if (!top)
1981 return -EINVAL;
1982
9a34b453
MS
1983 ret = clk_pm_runtime_get(core);
1984 if (ret)
1985 return ret;
1986
4dff95dc
SB
1987 /* notify that we are about to change rates */
1988 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
1989 if (fail_clk) {
1990 pr_debug("%s: failed to set %s rate\n", __func__,
1991 fail_clk->name);
1992 clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
9a34b453
MS
1993 ret = -EBUSY;
1994 goto err;
4dff95dc
SB
1995 }
1996
1997 /* change the rates */
1998 clk_change_rate(top);
1999
2000 core->req_rate = req_rate;
9a34b453
MS
2001err:
2002 clk_pm_runtime_put(core);
4dff95dc 2003
9a34b453 2004 return ret;
a093bde2 2005}
035a61c3
TV
2006
2007/**
4dff95dc
SB
2008 * clk_set_rate - specify a new rate for clk
2009 * @clk: the clk whose rate is being changed
2010 * @rate: the new rate for clk
035a61c3 2011 *
4dff95dc
SB
2012 * In the simplest case clk_set_rate will only adjust the rate of clk.
2013 *
2014 * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to
2015 * propagate up to clk's parent; whether or not this happens depends on the
2016 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
2017 * after calling .round_rate then upstream parent propagation is ignored. If
2018 * *parent_rate comes back with a new rate for clk's parent then we propagate
2019 * up to clk's parent and set its rate. Upward propagation will continue
2020 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
2021 * .round_rate stops requesting changes to clk's parent_rate.
2022 *
2023 * Rate changes are accomplished via tree traversal that also recalculates the
2024 * rates for the clocks and fires off POST_RATE_CHANGE notifiers.
2025 *
2026 * Returns 0 on success, -EERROR otherwise.
035a61c3 2027 */
4dff95dc 2028int clk_set_rate(struct clk *clk, unsigned long rate)
035a61c3 2029{
4dff95dc
SB
2030 int ret;
2031
035a61c3
TV
2032 if (!clk)
2033 return 0;
2034
4dff95dc
SB
2035 /* prevent racing with updates to the clock topology */
2036 clk_prepare_lock();
da0f0b2c 2037
55e9b8b7
JB
2038 if (clk->exclusive_count)
2039 clk_core_rate_unprotect(clk->core);
2040
4dff95dc 2041 ret = clk_core_set_rate_nolock(clk->core, rate);
da0f0b2c 2042
55e9b8b7
JB
2043 if (clk->exclusive_count)
2044 clk_core_rate_protect(clk->core);
2045
4dff95dc 2046 clk_prepare_unlock();
4935b22c 2047
4dff95dc 2048 return ret;
4935b22c 2049}
4dff95dc 2050EXPORT_SYMBOL_GPL(clk_set_rate);
4935b22c 2051
55e9b8b7
JB
2052/**
2053 * clk_set_rate_exclusive - specify a new rate get exclusive control
2054 * @clk: the clk whose rate is being changed
2055 * @rate: the new rate for clk
2056 *
2057 * This is a combination of clk_set_rate() and clk_rate_exclusive_get()
2058 * within a critical section
2059 *
2060 * This can be used initially to ensure that at least 1 consumer is
2061 * statisfied when several consumers are competing for exclusivity over the
2062 * same clock provider.
2063 *
2064 * The exclusivity is not applied if setting the rate failed.
2065 *
2066 * Calls to clk_rate_exclusive_get() should be balanced with calls to
2067 * clk_rate_exclusive_put().
2068 *
2069 * Returns 0 on success, -EERROR otherwise.
2070 */
2071int clk_set_rate_exclusive(struct clk *clk, unsigned long rate)
2072{
2073 int ret;
2074
2075 if (!clk)
2076 return 0;
2077
2078 /* prevent racing with updates to the clock topology */
2079 clk_prepare_lock();
2080
2081 /*
2082 * The temporary protection removal is not here, on purpose
2083 * This function is meant to be used instead of clk_rate_protect,
2084 * so before the consumer code path protect the clock provider
2085 */
2086
2087 ret = clk_core_set_rate_nolock(clk->core, rate);
2088 if (!ret) {
2089 clk_core_rate_protect(clk->core);
2090 clk->exclusive_count++;
2091 }
2092
2093 clk_prepare_unlock();
2094
2095 return ret;
2096}
2097EXPORT_SYMBOL_GPL(clk_set_rate_exclusive);
2098
4dff95dc
SB
2099/**
2100 * clk_set_rate_range - set a rate range for a clock source
2101 * @clk: clock source
2102 * @min: desired minimum clock rate in Hz, inclusive
2103 * @max: desired maximum clock rate in Hz, inclusive
2104 *
2105 * Returns success (0) or negative errno.
2106 */
2107int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
4935b22c 2108{
4dff95dc 2109 int ret = 0;
6562fbcf 2110 unsigned long old_min, old_max, rate;
4935b22c 2111
4dff95dc
SB
2112 if (!clk)
2113 return 0;
903efc55 2114
4dff95dc
SB
2115 if (min > max) {
2116 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n",
2117 __func__, clk->core->name, clk->dev_id, clk->con_id,
2118 min, max);
2119 return -EINVAL;
903efc55 2120 }
4935b22c 2121
4dff95dc 2122 clk_prepare_lock();
4935b22c 2123
55e9b8b7
JB
2124 if (clk->exclusive_count)
2125 clk_core_rate_unprotect(clk->core);
2126
6562fbcf
JB
2127 /* Save the current values in case we need to rollback the change */
2128 old_min = clk->min_rate;
2129 old_max = clk->max_rate;
2130 clk->min_rate = min;
2131 clk->max_rate = max;
2132
2133 rate = clk_core_get_rate_nolock(clk->core);
2134 if (rate < min || rate > max) {
2135 /*
2136 * FIXME:
2137 * We are in bit of trouble here, current rate is outside the
2138 * the requested range. We are going try to request appropriate
2139 * range boundary but there is a catch. It may fail for the
2140 * usual reason (clock broken, clock protected, etc) but also
2141 * because:
2142 * - round_rate() was not favorable and fell on the wrong
2143 * side of the boundary
2144 * - the determine_rate() callback does not really check for
2145 * this corner case when determining the rate
2146 */
2147
2148 if (rate < min)
2149 rate = min;
2150 else
2151 rate = max;
2152
2153 ret = clk_core_set_rate_nolock(clk->core, rate);
2154 if (ret) {
2155 /* rollback the changes */
2156 clk->min_rate = old_min;
2157 clk->max_rate = old_max;
2158 }
4935b22c
JH
2159 }
2160
55e9b8b7
JB
2161 if (clk->exclusive_count)
2162 clk_core_rate_protect(clk->core);
2163
4dff95dc 2164 clk_prepare_unlock();
4935b22c 2165
4dff95dc 2166 return ret;
3fa2252b 2167}
4dff95dc 2168EXPORT_SYMBOL_GPL(clk_set_rate_range);
3fa2252b 2169
4dff95dc
SB
2170/**
2171 * clk_set_min_rate - set a minimum clock rate for a clock source
2172 * @clk: clock source
2173 * @rate: desired minimum clock rate in Hz, inclusive
2174 *
2175 * Returns success (0) or negative errno.
2176 */
2177int clk_set_min_rate(struct clk *clk, unsigned long rate)
3fa2252b 2178{
4dff95dc
SB
2179 if (!clk)
2180 return 0;
2181
2182 return clk_set_rate_range(clk, rate, clk->max_rate);
3fa2252b 2183}
4dff95dc 2184EXPORT_SYMBOL_GPL(clk_set_min_rate);
3fa2252b 2185
4dff95dc
SB
2186/**
2187 * clk_set_max_rate - set a maximum clock rate for a clock source
2188 * @clk: clock source
2189 * @rate: desired maximum clock rate in Hz, inclusive
2190 *
2191 * Returns success (0) or negative errno.
2192 */
2193int clk_set_max_rate(struct clk *clk, unsigned long rate)
3fa2252b 2194{
4dff95dc
SB
2195 if (!clk)
2196 return 0;
4935b22c 2197
4dff95dc 2198 return clk_set_rate_range(clk, clk->min_rate, rate);
4935b22c 2199}
4dff95dc 2200EXPORT_SYMBOL_GPL(clk_set_max_rate);
4935b22c 2201
b2476490 2202/**
4dff95dc
SB
2203 * clk_get_parent - return the parent of a clk
2204 * @clk: the clk whose parent gets returned
b2476490 2205 *
4dff95dc 2206 * Simply returns clk->parent. Returns NULL if clk is NULL.
b2476490 2207 */
4dff95dc 2208struct clk *clk_get_parent(struct clk *clk)
b2476490 2209{
4dff95dc 2210 struct clk *parent;
b2476490 2211
fc4a05d4
SB
2212 if (!clk)
2213 return NULL;
2214
4dff95dc 2215 clk_prepare_lock();
fc4a05d4
SB
2216 /* TODO: Create a per-user clk and change callers to call clk_put */
2217 parent = !clk->core->parent ? NULL : clk->core->parent->hw->clk;
4dff95dc 2218 clk_prepare_unlock();
496eadf8 2219
4dff95dc
SB
2220 return parent;
2221}
2222EXPORT_SYMBOL_GPL(clk_get_parent);
b2476490 2223
4dff95dc
SB
2224static struct clk_core *__clk_init_parent(struct clk_core *core)
2225{
5146e0b0 2226 u8 index = 0;
4dff95dc 2227
2430a94d 2228 if (core->num_parents > 1 && core->ops->get_parent)
5146e0b0 2229 index = core->ops->get_parent(core->hw);
b2476490 2230
5146e0b0 2231 return clk_core_get_parent_by_index(core, index);
b2476490
MT
2232}
2233
4dff95dc
SB
2234static void clk_core_reparent(struct clk_core *core,
2235 struct clk_core *new_parent)
b2476490 2236{
4dff95dc
SB
2237 clk_reparent(core, new_parent);
2238 __clk_recalc_accuracies(core);
2239 __clk_recalc_rates(core, POST_RATE_CHANGE);
b2476490
MT
2240}
2241
42c86547
TV
2242void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent)
2243{
2244 if (!hw)
2245 return;
2246
2247 clk_core_reparent(hw->core, !new_parent ? NULL : new_parent->core);
2248}
2249
4dff95dc
SB
2250/**
2251 * clk_has_parent - check if a clock is a possible parent for another
2252 * @clk: clock source
2253 * @parent: parent clock source
2254 *
2255 * This function can be used in drivers that need to check that a clock can be
2256 * the parent of another without actually changing the parent.
2257 *
2258 * Returns true if @parent is a possible parent for @clk, false otherwise.
b2476490 2259 */
4dff95dc 2260bool clk_has_parent(struct clk *clk, struct clk *parent)
b2476490 2261{
4dff95dc 2262 struct clk_core *core, *parent_core;
b2476490 2263
4dff95dc
SB
2264 /* NULL clocks should be nops, so return success if either is NULL. */
2265 if (!clk || !parent)
2266 return true;
7452b219 2267
4dff95dc
SB
2268 core = clk->core;
2269 parent_core = parent->core;
71472c0c 2270
4dff95dc
SB
2271 /* Optimize for the case where the parent is already the parent. */
2272 if (core->parent == parent_core)
2273 return true;
1c8e6004 2274
d6347445
YX
2275 return match_string(core->parent_names, core->num_parents,
2276 parent_core->name) >= 0;
4dff95dc
SB
2277}
2278EXPORT_SYMBOL_GPL(clk_has_parent);
03bc10ab 2279
91baa9ff
JB
2280static int clk_core_set_parent_nolock(struct clk_core *core,
2281 struct clk_core *parent)
4dff95dc
SB
2282{
2283 int ret = 0;
2284 int p_index = 0;
2285 unsigned long p_rate = 0;
2286
91baa9ff
JB
2287 lockdep_assert_held(&prepare_lock);
2288
4dff95dc
SB
2289 if (!core)
2290 return 0;
2291
4dff95dc 2292 if (core->parent == parent)
91baa9ff 2293 return 0;
4dff95dc
SB
2294
2295 /* verify ops for for multi-parent clks */
91baa9ff
JB
2296 if (core->num_parents > 1 && !core->ops->set_parent)
2297 return -EPERM;
7452b219 2298
4dff95dc 2299 /* check that we are allowed to re-parent if the clock is in use */
91baa9ff
JB
2300 if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count)
2301 return -EBUSY;
b2476490 2302
e55a839a
JB
2303 if (clk_core_rate_is_protected(core))
2304 return -EBUSY;
b2476490 2305
71472c0c 2306 /* try finding the new parent index */
4dff95dc 2307 if (parent) {
d6968fca 2308 p_index = clk_fetch_parent_index(core, parent);
f1c8b2ed 2309 if (p_index < 0) {
71472c0c 2310 pr_debug("%s: clk %s can not be parent of clk %s\n",
4dff95dc 2311 __func__, parent->name, core->name);
91baa9ff 2312 return p_index;
71472c0c 2313 }
e8f0e68e 2314 p_rate = parent->rate;
b2476490
MT
2315 }
2316
9a34b453
MS
2317 ret = clk_pm_runtime_get(core);
2318 if (ret)
91baa9ff 2319 return ret;
9a34b453 2320
4dff95dc
SB
2321 /* propagate PRE_RATE_CHANGE notifications */
2322 ret = __clk_speculate_rates(core, p_rate);
b2476490 2323
4dff95dc
SB
2324 /* abort if a driver objects */
2325 if (ret & NOTIFY_STOP_MASK)
9a34b453 2326 goto runtime_put;
b2476490 2327
4dff95dc
SB
2328 /* do the re-parent */
2329 ret = __clk_set_parent(core, parent, p_index);
b2476490 2330
4dff95dc
SB
2331 /* propagate rate an accuracy recalculation accordingly */
2332 if (ret) {
2333 __clk_recalc_rates(core, ABORT_RATE_CHANGE);
2334 } else {
2335 __clk_recalc_rates(core, POST_RATE_CHANGE);
2336 __clk_recalc_accuracies(core);
b2476490
MT
2337 }
2338
9a34b453
MS
2339runtime_put:
2340 clk_pm_runtime_put(core);
71472c0c 2341
4dff95dc
SB
2342 return ret;
2343}
b2476490 2344
4dff95dc
SB
2345/**
2346 * clk_set_parent - switch the parent of a mux clk
2347 * @clk: the mux clk whose input we are switching
2348 * @parent: the new input to clk
2349 *
2350 * Re-parent clk to use parent as its new input source. If clk is in
2351 * prepared state, the clk will get enabled for the duration of this call. If
2352 * that's not acceptable for a specific clk (Eg: the consumer can't handle
2353 * that, the reparenting is glitchy in hardware, etc), use the
2354 * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
2355 *
2356 * After successfully changing clk's parent clk_set_parent will update the
2357 * clk topology, sysfs topology and propagate rate recalculation via
2358 * __clk_recalc_rates.
2359 *
2360 * Returns 0 on success, -EERROR otherwise.
2361 */
2362int clk_set_parent(struct clk *clk, struct clk *parent)
2363{
91baa9ff
JB
2364 int ret;
2365
4dff95dc
SB
2366 if (!clk)
2367 return 0;
2368
91baa9ff 2369 clk_prepare_lock();
55e9b8b7
JB
2370
2371 if (clk->exclusive_count)
2372 clk_core_rate_unprotect(clk->core);
2373
91baa9ff
JB
2374 ret = clk_core_set_parent_nolock(clk->core,
2375 parent ? parent->core : NULL);
55e9b8b7
JB
2376
2377 if (clk->exclusive_count)
2378 clk_core_rate_protect(clk->core);
2379
91baa9ff
JB
2380 clk_prepare_unlock();
2381
2382 return ret;
b2476490 2383}
4dff95dc 2384EXPORT_SYMBOL_GPL(clk_set_parent);
b2476490 2385
9e4d04ad
JB
2386static int clk_core_set_phase_nolock(struct clk_core *core, int degrees)
2387{
2388 int ret = -EINVAL;
2389
2390 lockdep_assert_held(&prepare_lock);
2391
2392 if (!core)
2393 return 0;
2394
e55a839a
JB
2395 if (clk_core_rate_is_protected(core))
2396 return -EBUSY;
2397
9e4d04ad
JB
2398 trace_clk_set_phase(core, degrees);
2399
7f95beea 2400 if (core->ops->set_phase) {
9e4d04ad 2401 ret = core->ops->set_phase(core->hw, degrees);
7f95beea
SL
2402 if (!ret)
2403 core->phase = degrees;
2404 }
9e4d04ad
JB
2405
2406 trace_clk_set_phase_complete(core, degrees);
2407
2408 return ret;
2409}
2410
4dff95dc
SB
2411/**
2412 * clk_set_phase - adjust the phase shift of a clock signal
2413 * @clk: clock signal source
2414 * @degrees: number of degrees the signal is shifted
2415 *
2416 * Shifts the phase of a clock signal by the specified
2417 * degrees. Returns 0 on success, -EERROR otherwise.
2418 *
2419 * This function makes no distinction about the input or reference
2420 * signal that we adjust the clock signal phase against. For example
2421 * phase locked-loop clock signal generators we may shift phase with
2422 * respect to feedback clock signal input, but for other cases the
2423 * clock phase may be shifted with respect to some other, unspecified
2424 * signal.
2425 *
2426 * Additionally the concept of phase shift does not propagate through
2427 * the clock tree hierarchy, which sets it apart from clock rates and
2428 * clock accuracy. A parent clock phase attribute does not have an
2429 * impact on the phase attribute of a child clock.
b2476490 2430 */
4dff95dc 2431int clk_set_phase(struct clk *clk, int degrees)
b2476490 2432{
9e4d04ad 2433 int ret;
b2476490 2434
4dff95dc
SB
2435 if (!clk)
2436 return 0;
b2476490 2437
4dff95dc
SB
2438 /* sanity check degrees */
2439 degrees %= 360;
2440 if (degrees < 0)
2441 degrees += 360;
bf47b4fd 2442
4dff95dc 2443 clk_prepare_lock();
3fa2252b 2444
55e9b8b7
JB
2445 if (clk->exclusive_count)
2446 clk_core_rate_unprotect(clk->core);
3fa2252b 2447
9e4d04ad 2448 ret = clk_core_set_phase_nolock(clk->core, degrees);
3fa2252b 2449
55e9b8b7
JB
2450 if (clk->exclusive_count)
2451 clk_core_rate_protect(clk->core);
b2476490 2452
4dff95dc 2453 clk_prepare_unlock();
dfc202ea 2454
4dff95dc
SB
2455 return ret;
2456}
2457EXPORT_SYMBOL_GPL(clk_set_phase);
b2476490 2458
4dff95dc
SB
2459static int clk_core_get_phase(struct clk_core *core)
2460{
2461 int ret;
b2476490 2462
4dff95dc 2463 clk_prepare_lock();
1f9c63e8
SL
2464 /* Always try to update cached phase if possible */
2465 if (core->ops->get_phase)
2466 core->phase = core->ops->get_phase(core->hw);
4dff95dc
SB
2467 ret = core->phase;
2468 clk_prepare_unlock();
71472c0c 2469
4dff95dc 2470 return ret;
b2476490
MT
2471}
2472
4dff95dc
SB
2473/**
2474 * clk_get_phase - return the phase shift of a clock signal
2475 * @clk: clock signal source
2476 *
2477 * Returns the phase shift of a clock node in degrees, otherwise returns
2478 * -EERROR.
2479 */
2480int clk_get_phase(struct clk *clk)
1c8e6004 2481{
4dff95dc 2482 if (!clk)
1c8e6004
TV
2483 return 0;
2484
4dff95dc
SB
2485 return clk_core_get_phase(clk->core);
2486}
2487EXPORT_SYMBOL_GPL(clk_get_phase);
1c8e6004 2488
9fba738a
JB
2489static void clk_core_reset_duty_cycle_nolock(struct clk_core *core)
2490{
2491 /* Assume a default value of 50% */
2492 core->duty.num = 1;
2493 core->duty.den = 2;
2494}
2495
2496static int clk_core_update_duty_cycle_parent_nolock(struct clk_core *core);
2497
2498static int clk_core_update_duty_cycle_nolock(struct clk_core *core)
2499{
2500 struct clk_duty *duty = &core->duty;
2501 int ret = 0;
2502
2503 if (!core->ops->get_duty_cycle)
2504 return clk_core_update_duty_cycle_parent_nolock(core);
2505
2506 ret = core->ops->get_duty_cycle(core->hw, duty);
2507 if (ret)
2508 goto reset;
2509
2510 /* Don't trust the clock provider too much */
2511 if (duty->den == 0 || duty->num > duty->den) {
2512 ret = -EINVAL;
2513 goto reset;
2514 }
2515
2516 return 0;
2517
2518reset:
2519 clk_core_reset_duty_cycle_nolock(core);
2520 return ret;
2521}
2522
2523static int clk_core_update_duty_cycle_parent_nolock(struct clk_core *core)
2524{
2525 int ret = 0;
2526
2527 if (core->parent &&
2528 core->flags & CLK_DUTY_CYCLE_PARENT) {
2529 ret = clk_core_update_duty_cycle_nolock(core->parent);
2530 memcpy(&core->duty, &core->parent->duty, sizeof(core->duty));
2531 } else {
2532 clk_core_reset_duty_cycle_nolock(core);
2533 }
2534
2535 return ret;
2536}
2537
2538static int clk_core_set_duty_cycle_parent_nolock(struct clk_core *core,
2539 struct clk_duty *duty);
2540
2541static int clk_core_set_duty_cycle_nolock(struct clk_core *core,
2542 struct clk_duty *duty)
2543{
2544 int ret;
2545
2546 lockdep_assert_held(&prepare_lock);
2547
2548 if (clk_core_rate_is_protected(core))
2549 return -EBUSY;
2550
2551 trace_clk_set_duty_cycle(core, duty);
2552
2553 if (!core->ops->set_duty_cycle)
2554 return clk_core_set_duty_cycle_parent_nolock(core, duty);
2555
2556 ret = core->ops->set_duty_cycle(core->hw, duty);
2557 if (!ret)
2558 memcpy(&core->duty, duty, sizeof(*duty));
2559
2560 trace_clk_set_duty_cycle_complete(core, duty);
2561
2562 return ret;
2563}
2564
2565static int clk_core_set_duty_cycle_parent_nolock(struct clk_core *core,
2566 struct clk_duty *duty)
2567{
2568 int ret = 0;
2569
2570 if (core->parent &&
2571 core->flags & (CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT)) {
2572 ret = clk_core_set_duty_cycle_nolock(core->parent, duty);
2573 memcpy(&core->duty, &core->parent->duty, sizeof(core->duty));
2574 }
2575
2576 return ret;
2577}
2578
2579/**
2580 * clk_set_duty_cycle - adjust the duty cycle ratio of a clock signal
2581 * @clk: clock signal source
2582 * @num: numerator of the duty cycle ratio to be applied
2583 * @den: denominator of the duty cycle ratio to be applied
2584 *
2585 * Apply the duty cycle ratio if the ratio is valid and the clock can
2586 * perform this operation
2587 *
2588 * Returns (0) on success, a negative errno otherwise.
2589 */
2590int clk_set_duty_cycle(struct clk *clk, unsigned int num, unsigned int den)
2591{
2592 int ret;
2593 struct clk_duty duty;
2594
2595 if (!clk)
2596 return 0;
2597
2598 /* sanity check the ratio */
2599 if (den == 0 || num > den)
2600 return -EINVAL;
2601
2602 duty.num = num;
2603 duty.den = den;
2604
2605 clk_prepare_lock();
2606
2607 if (clk->exclusive_count)
2608 clk_core_rate_unprotect(clk->core);
2609
2610 ret = clk_core_set_duty_cycle_nolock(clk->core, &duty);
2611
2612 if (clk->exclusive_count)
2613 clk_core_rate_protect(clk->core);
2614
2615 clk_prepare_unlock();
2616
2617 return ret;
2618}
2619EXPORT_SYMBOL_GPL(clk_set_duty_cycle);
2620
2621static int clk_core_get_scaled_duty_cycle(struct clk_core *core,
2622 unsigned int scale)
2623{
2624 struct clk_duty *duty = &core->duty;
2625 int ret;
2626
2627 clk_prepare_lock();
2628
2629 ret = clk_core_update_duty_cycle_nolock(core);
2630 if (!ret)
2631 ret = mult_frac(scale, duty->num, duty->den);
2632
2633 clk_prepare_unlock();
2634
2635 return ret;
2636}
2637
2638/**
2639 * clk_get_scaled_duty_cycle - return the duty cycle ratio of a clock signal
2640 * @clk: clock signal source
2641 * @scale: scaling factor to be applied to represent the ratio as an integer
2642 *
2643 * Returns the duty cycle ratio of a clock node multiplied by the provided
2644 * scaling factor, or negative errno on error.
2645 */
2646int clk_get_scaled_duty_cycle(struct clk *clk, unsigned int scale)
2647{
2648 if (!clk)
2649 return 0;
2650
2651 return clk_core_get_scaled_duty_cycle(clk->core, scale);
2652}
2653EXPORT_SYMBOL_GPL(clk_get_scaled_duty_cycle);
2654
4dff95dc
SB
2655/**
2656 * clk_is_match - check if two clk's point to the same hardware clock
2657 * @p: clk compared against q
2658 * @q: clk compared against p
2659 *
2660 * Returns true if the two struct clk pointers both point to the same hardware
2661 * clock node. Put differently, returns true if struct clk *p and struct clk *q
2662 * share the same struct clk_core object.
2663 *
2664 * Returns false otherwise. Note that two NULL clks are treated as matching.
2665 */
2666bool clk_is_match(const struct clk *p, const struct clk *q)
2667{
2668 /* trivial case: identical struct clk's or both NULL */
2669 if (p == q)
2670 return true;
1c8e6004 2671
3fe003f9 2672 /* true if clk->core pointers match. Avoid dereferencing garbage */
4dff95dc
SB
2673 if (!IS_ERR_OR_NULL(p) && !IS_ERR_OR_NULL(q))
2674 if (p->core == q->core)
2675 return true;
1c8e6004 2676
4dff95dc
SB
2677 return false;
2678}
2679EXPORT_SYMBOL_GPL(clk_is_match);
1c8e6004 2680
4dff95dc 2681/*** debugfs support ***/
1c8e6004 2682
4dff95dc
SB
2683#ifdef CONFIG_DEBUG_FS
2684#include <linux/debugfs.h>
1c8e6004 2685
4dff95dc
SB
2686static struct dentry *rootdir;
2687static int inited = 0;
2688static DEFINE_MUTEX(clk_debug_lock);
2689static HLIST_HEAD(clk_debug_list);
1c8e6004 2690
4dff95dc
SB
2691static struct hlist_head *all_lists[] = {
2692 &clk_root_list,
2693 &clk_orphan_list,
2694 NULL,
2695};
2696
2697static struct hlist_head *orphan_list[] = {
2698 &clk_orphan_list,
2699 NULL,
2700};
2701
2702static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
2703 int level)
b2476490 2704{
4dff95dc
SB
2705 if (!c)
2706 return;
b2476490 2707
9fba738a 2708 seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %5d %6d\n",
4dff95dc
SB
2709 level * 3 + 1, "",
2710 30 - level * 3, c->name,
e55a839a
JB
2711 c->enable_count, c->prepare_count, c->protect_count,
2712 clk_core_get_rate(c), clk_core_get_accuracy(c),
9fba738a
JB
2713 clk_core_get_phase(c),
2714 clk_core_get_scaled_duty_cycle(c, 100000));
4dff95dc 2715}
89ac8d7a 2716
4dff95dc
SB
2717static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
2718 int level)
2719{
2720 struct clk_core *child;
b2476490 2721
4dff95dc
SB
2722 if (!c)
2723 return;
b2476490 2724
4dff95dc 2725 clk_summary_show_one(s, c, level);
0e1c0301 2726
4dff95dc
SB
2727 hlist_for_each_entry(child, &c->children, child_node)
2728 clk_summary_show_subtree(s, child, level + 1);
1c8e6004 2729}
b2476490 2730
4dff95dc 2731static int clk_summary_show(struct seq_file *s, void *data)
1c8e6004 2732{
4dff95dc
SB
2733 struct clk_core *c;
2734 struct hlist_head **lists = (struct hlist_head **)s->private;
1c8e6004 2735
9fba738a
JB
2736 seq_puts(s, " enable prepare protect duty\n");
2737 seq_puts(s, " clock count count count rate accuracy phase cycle\n");
2738 seq_puts(s, "---------------------------------------------------------------------------------------------\n");
b2476490 2739
1c8e6004
TV
2740 clk_prepare_lock();
2741
4dff95dc
SB
2742 for (; *lists; lists++)
2743 hlist_for_each_entry(c, *lists, child_node)
2744 clk_summary_show_subtree(s, c, 0);
b2476490 2745
eab89f69 2746 clk_prepare_unlock();
b2476490 2747
4dff95dc 2748 return 0;
b2476490 2749}
fec0ef3f 2750DEFINE_SHOW_ATTRIBUTE(clk_summary);
b2476490 2751
4dff95dc
SB
2752static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
2753{
2754 if (!c)
2755 return;
b2476490 2756
7cb81136 2757 /* This should be JSON format, i.e. elements separated with a comma */
4dff95dc
SB
2758 seq_printf(s, "\"%s\": { ", c->name);
2759 seq_printf(s, "\"enable_count\": %d,", c->enable_count);
2760 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
e55a839a 2761 seq_printf(s, "\"protect_count\": %d,", c->protect_count);
7cb81136
SW
2762 seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
2763 seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
4dff95dc 2764 seq_printf(s, "\"phase\": %d", clk_core_get_phase(c));
9fba738a
JB
2765 seq_printf(s, "\"duty_cycle\": %u",
2766 clk_core_get_scaled_duty_cycle(c, 100000));
b2476490 2767}
b2476490 2768
4dff95dc 2769static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
b2476490 2770{
4dff95dc 2771 struct clk_core *child;
b2476490 2772
4dff95dc
SB
2773 if (!c)
2774 return;
b2476490 2775
4dff95dc 2776 clk_dump_one(s, c, level);
b2476490 2777
4dff95dc 2778 hlist_for_each_entry(child, &c->children, child_node) {
4d327586 2779 seq_putc(s, ',');
4dff95dc 2780 clk_dump_subtree(s, child, level + 1);
b2476490
MT
2781 }
2782
4d327586 2783 seq_putc(s, '}');
b2476490
MT
2784}
2785
fec0ef3f 2786static int clk_dump_show(struct seq_file *s, void *data)
4e88f3de 2787{
4dff95dc
SB
2788 struct clk_core *c;
2789 bool first_node = true;
2790 struct hlist_head **lists = (struct hlist_head **)s->private;
4e88f3de 2791
4d327586 2792 seq_putc(s, '{');
4dff95dc 2793 clk_prepare_lock();
035a61c3 2794
4dff95dc
SB
2795 for (; *lists; lists++) {
2796 hlist_for_each_entry(c, *lists, child_node) {
2797 if (!first_node)
4d327586 2798 seq_putc(s, ',');
4dff95dc
SB
2799 first_node = false;
2800 clk_dump_subtree(s, c, 0);
2801 }
2802 }
4e88f3de 2803
4dff95dc 2804 clk_prepare_unlock();
4e88f3de 2805
70e9f4dd 2806 seq_puts(s, "}\n");
4dff95dc 2807 return 0;
4e88f3de 2808}
fec0ef3f 2809DEFINE_SHOW_ATTRIBUTE(clk_dump);
89ac8d7a 2810
a6059ab9
GU
2811static const struct {
2812 unsigned long flag;
2813 const char *name;
2814} clk_flags[] = {
40dd71c7 2815#define ENTRY(f) { f, #f }
a6059ab9
GU
2816 ENTRY(CLK_SET_RATE_GATE),
2817 ENTRY(CLK_SET_PARENT_GATE),
2818 ENTRY(CLK_SET_RATE_PARENT),
2819 ENTRY(CLK_IGNORE_UNUSED),
2820 ENTRY(CLK_IS_BASIC),
2821 ENTRY(CLK_GET_RATE_NOCACHE),
2822 ENTRY(CLK_SET_RATE_NO_REPARENT),
2823 ENTRY(CLK_GET_ACCURACY_NOCACHE),
2824 ENTRY(CLK_RECALC_NEW_RATES),
2825 ENTRY(CLK_SET_RATE_UNGATE),
2826 ENTRY(CLK_IS_CRITICAL),
2827 ENTRY(CLK_OPS_PARENT_ENABLE),
9fba738a 2828 ENTRY(CLK_DUTY_CYCLE_PARENT),
a6059ab9
GU
2829#undef ENTRY
2830};
2831
fec0ef3f 2832static int clk_flags_show(struct seq_file *s, void *data)
a6059ab9
GU
2833{
2834 struct clk_core *core = s->private;
2835 unsigned long flags = core->flags;
2836 unsigned int i;
2837
2838 for (i = 0; flags && i < ARRAY_SIZE(clk_flags); i++) {
2839 if (flags & clk_flags[i].flag) {
2840 seq_printf(s, "%s\n", clk_flags[i].name);
2841 flags &= ~clk_flags[i].flag;
2842 }
2843 }
2844 if (flags) {
2845 /* Unknown flags */
2846 seq_printf(s, "0x%lx\n", flags);
2847 }
2848
2849 return 0;
2850}
fec0ef3f 2851DEFINE_SHOW_ATTRIBUTE(clk_flags);
a6059ab9 2852
fec0ef3f 2853static int possible_parents_show(struct seq_file *s, void *data)
92031575
PDS
2854{
2855 struct clk_core *core = s->private;
2856 int i;
2857
2858 for (i = 0; i < core->num_parents - 1; i++)
2859 seq_printf(s, "%s ", core->parent_names[i]);
2860
2861 seq_printf(s, "%s\n", core->parent_names[i]);
2862
2863 return 0;
2864}
fec0ef3f 2865DEFINE_SHOW_ATTRIBUTE(possible_parents);
92031575 2866
9fba738a
JB
2867static int clk_duty_cycle_show(struct seq_file *s, void *data)
2868{
2869 struct clk_core *core = s->private;
2870 struct clk_duty *duty = &core->duty;
2871
2872 seq_printf(s, "%u/%u\n", duty->num, duty->den);
2873
2874 return 0;
2875}
2876DEFINE_SHOW_ATTRIBUTE(clk_duty_cycle);
2877
8a26bbbb 2878static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
4dff95dc 2879{
8a26bbbb 2880 struct dentry *root;
b61c43c0 2881
8a26bbbb
GKH
2882 if (!core || !pdentry)
2883 return;
b2476490 2884
8a26bbbb
GKH
2885 root = debugfs_create_dir(core->name, pdentry);
2886 core->dentry = root;
92031575 2887
8a26bbbb
GKH
2888 debugfs_create_ulong("clk_rate", 0444, root, &core->rate);
2889 debugfs_create_ulong("clk_accuracy", 0444, root, &core->accuracy);
2890 debugfs_create_u32("clk_phase", 0444, root, &core->phase);
2891 debugfs_create_file("clk_flags", 0444, root, core, &clk_flags_fops);
2892 debugfs_create_u32("clk_prepare_count", 0444, root, &core->prepare_count);
2893 debugfs_create_u32("clk_enable_count", 0444, root, &core->enable_count);
2894 debugfs_create_u32("clk_protect_count", 0444, root, &core->protect_count);
2895 debugfs_create_u32("clk_notifier_count", 0444, root, &core->notifier_count);
9fba738a
JB
2896 debugfs_create_file("clk_duty_cycle", 0444, root, core,
2897 &clk_duty_cycle_fops);
b2476490 2898
8a26bbbb
GKH
2899 if (core->num_parents > 1)
2900 debugfs_create_file("clk_possible_parents", 0444, root, core,
2901 &possible_parents_fops);
b2476490 2902
8a26bbbb
GKH
2903 if (core->ops->debug_init)
2904 core->ops->debug_init(core->hw, core->dentry);
b2476490 2905}
035a61c3
TV
2906
2907/**
6e5ab41b
SB
2908 * clk_debug_register - add a clk node to the debugfs clk directory
2909 * @core: the clk being added to the debugfs clk directory
035a61c3 2910 *
6e5ab41b
SB
2911 * Dynamically adds a clk to the debugfs clk directory if debugfs has been
2912 * initialized. Otherwise it bails out early since the debugfs clk directory
4dff95dc 2913 * will be created lazily by clk_debug_init as part of a late_initcall.
035a61c3 2914 */
8a26bbbb 2915static void clk_debug_register(struct clk_core *core)
035a61c3 2916{
4dff95dc
SB
2917 mutex_lock(&clk_debug_lock);
2918 hlist_add_head(&core->debug_node, &clk_debug_list);
db3188fa 2919 if (inited)
8a26bbbb 2920 clk_debug_create_one(core, rootdir);
4dff95dc 2921 mutex_unlock(&clk_debug_lock);
035a61c3 2922}
b2476490 2923
4dff95dc 2924 /**
6e5ab41b
SB
2925 * clk_debug_unregister - remove a clk node from the debugfs clk directory
2926 * @core: the clk being removed from the debugfs clk directory
e59c5371 2927 *
6e5ab41b
SB
2928 * Dynamically removes a clk and all its child nodes from the
2929 * debugfs clk directory if clk->dentry points to debugfs created by
706d5c73 2930 * clk_debug_register in __clk_core_init.
e59c5371 2931 */
4dff95dc 2932static void clk_debug_unregister(struct clk_core *core)
e59c5371 2933{
4dff95dc
SB
2934 mutex_lock(&clk_debug_lock);
2935 hlist_del_init(&core->debug_node);
2936 debugfs_remove_recursive(core->dentry);
2937 core->dentry = NULL;
2938 mutex_unlock(&clk_debug_lock);
2939}
e59c5371 2940
4dff95dc 2941/**
6e5ab41b 2942 * clk_debug_init - lazily populate the debugfs clk directory
4dff95dc 2943 *
6e5ab41b
SB
2944 * clks are often initialized very early during boot before memory can be
2945 * dynamically allocated and well before debugfs is setup. This function
2946 * populates the debugfs clk directory once at boot-time when we know that
2947 * debugfs is setup. It should only be called once at boot-time, all other clks
2948 * added dynamically will be done so with clk_debug_register.
4dff95dc
SB
2949 */
2950static int __init clk_debug_init(void)
2951{
2952 struct clk_core *core;
dfc202ea 2953
4dff95dc 2954 rootdir = debugfs_create_dir("clk", NULL);
e59c5371 2955
8a26bbbb
GKH
2956 debugfs_create_file("clk_summary", 0444, rootdir, &all_lists,
2957 &clk_summary_fops);
2958 debugfs_create_file("clk_dump", 0444, rootdir, &all_lists,
2959 &clk_dump_fops);
2960 debugfs_create_file("clk_orphan_summary", 0444, rootdir, &orphan_list,
2961 &clk_summary_fops);
2962 debugfs_create_file("clk_orphan_dump", 0444, rootdir, &orphan_list,
2963 &clk_dump_fops);
e59c5371 2964
4dff95dc
SB
2965 mutex_lock(&clk_debug_lock);
2966 hlist_for_each_entry(core, &clk_debug_list, debug_node)
2967 clk_debug_create_one(core, rootdir);
e59c5371 2968
4dff95dc
SB
2969 inited = 1;
2970 mutex_unlock(&clk_debug_lock);
e59c5371 2971
4dff95dc
SB
2972 return 0;
2973}
2974late_initcall(clk_debug_init);
2975#else
8a26bbbb 2976static inline void clk_debug_register(struct clk_core *core) { }
4dff95dc
SB
2977static inline void clk_debug_reparent(struct clk_core *core,
2978 struct clk_core *new_parent)
035a61c3 2979{
035a61c3 2980}
4dff95dc 2981static inline void clk_debug_unregister(struct clk_core *core)
3d3801ef 2982{
3d3801ef 2983}
4dff95dc 2984#endif
3d3801ef 2985
b2476490 2986/**
be45ebf2 2987 * __clk_core_init - initialize the data structures in a struct clk_core
d35c80c2 2988 * @core: clk_core being initialized
b2476490 2989 *
035a61c3 2990 * Initializes the lists in struct clk_core, queries the hardware for the
b2476490 2991 * parent and rate and sets them both.
b2476490 2992 */
be45ebf2 2993static int __clk_core_init(struct clk_core *core)
b2476490 2994{
9a34b453 2995 int i, ret;
035a61c3 2996 struct clk_core *orphan;
b67bfe0d 2997 struct hlist_node *tmp2;
1c8e6004 2998 unsigned long rate;
b2476490 2999
d35c80c2 3000 if (!core)
d1302a36 3001 return -EINVAL;
b2476490 3002
eab89f69 3003 clk_prepare_lock();
b2476490 3004
9a34b453
MS
3005 ret = clk_pm_runtime_get(core);
3006 if (ret)
3007 goto unlock;
3008
b2476490 3009 /* check to see if a clock with this name is already registered */
d6968fca 3010 if (clk_core_lookup(core->name)) {
d1302a36 3011 pr_debug("%s: clk %s already initialized\n",
d6968fca 3012 __func__, core->name);
d1302a36 3013 ret = -EEXIST;
b2476490 3014 goto out;
d1302a36 3015 }
b2476490 3016
5fb94e9c 3017 /* check that clk_ops are sane. See Documentation/driver-api/clk.rst */
d6968fca
SB
3018 if (core->ops->set_rate &&
3019 !((core->ops->round_rate || core->ops->determine_rate) &&
3020 core->ops->recalc_rate)) {
c44fccb5
MY
3021 pr_err("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
3022 __func__, core->name);
d1302a36 3023 ret = -EINVAL;
d4d7e3dd
MT
3024 goto out;
3025 }
3026
d6968fca 3027 if (core->ops->set_parent && !core->ops->get_parent) {
c44fccb5
MY
3028 pr_err("%s: %s must implement .get_parent & .set_parent\n",
3029 __func__, core->name);
d1302a36 3030 ret = -EINVAL;
d4d7e3dd
MT
3031 goto out;
3032 }
3033
3c8e77dd
MY
3034 if (core->num_parents > 1 && !core->ops->get_parent) {
3035 pr_err("%s: %s must implement .get_parent as it has multi parents\n",
3036 __func__, core->name);
3037 ret = -EINVAL;
3038 goto out;
3039 }
3040
d6968fca
SB
3041 if (core->ops->set_rate_and_parent &&
3042 !(core->ops->set_parent && core->ops->set_rate)) {
c44fccb5 3043 pr_err("%s: %s must implement .set_parent & .set_rate\n",
d6968fca 3044 __func__, core->name);
3fa2252b
SB
3045 ret = -EINVAL;
3046 goto out;
3047 }
3048
b2476490 3049 /* throw a WARN if any entries in parent_names are NULL */
d6968fca
SB
3050 for (i = 0; i < core->num_parents; i++)
3051 WARN(!core->parent_names[i],
b2476490 3052 "%s: invalid NULL in %s's .parent_names\n",
d6968fca 3053 __func__, core->name);
b2476490 3054
d6968fca 3055 core->parent = __clk_init_parent(core);
b2476490
MT
3056
3057 /*
706d5c73
SB
3058 * Populate core->parent if parent has already been clk_core_init'd. If
3059 * parent has not yet been clk_core_init'd then place clk in the orphan
47b0eeb3 3060 * list. If clk doesn't have any parents then place it in the root
b2476490
MT
3061 * clk list.
3062 *
3063 * Every time a new clk is clk_init'd then we walk the list of orphan
3064 * clocks and re-parent any that are children of the clock currently
3065 * being clk_init'd.
3066 */
e6500344 3067 if (core->parent) {
d6968fca
SB
3068 hlist_add_head(&core->child_node,
3069 &core->parent->children);
e6500344 3070 core->orphan = core->parent->orphan;
47b0eeb3 3071 } else if (!core->num_parents) {
d6968fca 3072 hlist_add_head(&core->child_node, &clk_root_list);
e6500344
HS
3073 core->orphan = false;
3074 } else {
d6968fca 3075 hlist_add_head(&core->child_node, &clk_orphan_list);
e6500344
HS
3076 core->orphan = true;
3077 }
b2476490 3078
541debae
JB
3079 /*
3080 * optional platform-specific magic
3081 *
3082 * The .init callback is not used by any of the basic clock types, but
3083 * exists for weird hardware that must perform initialization magic.
3084 * Please consider other ways of solving initialization problems before
3085 * using this callback, as its use is discouraged.
3086 */
3087 if (core->ops->init)
3088 core->ops->init(core->hw);
3089
5279fc40
BB
3090 /*
3091 * Set clk's accuracy. The preferred method is to use
3092 * .recalc_accuracy. For simple clocks and lazy developers the default
3093 * fallback is to use the parent's accuracy. If a clock doesn't have a
3094 * parent (or is orphaned) then accuracy is set to zero (perfect
3095 * clock).
3096 */
d6968fca
SB
3097 if (core->ops->recalc_accuracy)
3098 core->accuracy = core->ops->recalc_accuracy(core->hw,
3099 __clk_get_accuracy(core->parent));
3100 else if (core->parent)
3101 core->accuracy = core->parent->accuracy;
5279fc40 3102 else
d6968fca 3103 core->accuracy = 0;
5279fc40 3104
9824cf73
MR
3105 /*
3106 * Set clk's phase.
3107 * Since a phase is by definition relative to its parent, just
3108 * query the current clock phase, or just assume it's in phase.
3109 */
d6968fca
SB
3110 if (core->ops->get_phase)
3111 core->phase = core->ops->get_phase(core->hw);
9824cf73 3112 else
d6968fca 3113 core->phase = 0;
9824cf73 3114
9fba738a
JB
3115 /*
3116 * Set clk's duty cycle.
3117 */
3118 clk_core_update_duty_cycle_nolock(core);
3119
b2476490
MT
3120 /*
3121 * Set clk's rate. The preferred method is to use .recalc_rate. For
3122 * simple clocks and lazy developers the default fallback is to use the
3123 * parent's rate. If a clock doesn't have a parent (or is orphaned)
3124 * then rate is set to zero.
3125 */
d6968fca
SB
3126 if (core->ops->recalc_rate)
3127 rate = core->ops->recalc_rate(core->hw,
3128 clk_core_get_rate_nolock(core->parent));
3129 else if (core->parent)
3130 rate = core->parent->rate;
b2476490 3131 else
1c8e6004 3132 rate = 0;
d6968fca 3133 core->rate = core->req_rate = rate;
b2476490 3134
99652a46
JB
3135 /*
3136 * Enable CLK_IS_CRITICAL clocks so newly added critical clocks
3137 * don't get accidentally disabled when walking the orphan tree and
3138 * reparenting clocks
3139 */
3140 if (core->flags & CLK_IS_CRITICAL) {
3141 unsigned long flags;
3142
3143 clk_core_prepare(core);
3144
3145 flags = clk_enable_lock();
3146 clk_core_enable(core);
3147 clk_enable_unlock(flags);
3148 }
3149
b2476490 3150 /*
0e8f6e49
MY
3151 * walk the list of orphan clocks and reparent any that newly finds a
3152 * parent.
b2476490 3153 */
b67bfe0d 3154 hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
0e8f6e49 3155 struct clk_core *parent = __clk_init_parent(orphan);
1f61e5f1 3156
904e6ead 3157 /*
99652a46
JB
3158 * We need to use __clk_set_parent_before() and _after() to
3159 * to properly migrate any prepare/enable count of the orphan
3160 * clock. This is important for CLK_IS_CRITICAL clocks, which
3161 * are enabled during init but might not have a parent yet.
904e6ead
MT
3162 */
3163 if (parent) {
f8f8f1d0 3164 /* update the clk tree topology */
99652a46
JB
3165 __clk_set_parent_before(orphan, parent);
3166 __clk_set_parent_after(orphan, parent, NULL);
904e6ead
MT
3167 __clk_recalc_accuracies(orphan);
3168 __clk_recalc_rates(orphan, 0);
3169 }
0e8f6e49 3170 }
b2476490 3171
d6968fca 3172 kref_init(&core->ref);
b2476490 3173out:
9a34b453
MS
3174 clk_pm_runtime_put(core);
3175unlock:
eab89f69 3176 clk_prepare_unlock();
b2476490 3177
89f7e9de 3178 if (!ret)
d6968fca 3179 clk_debug_register(core);
89f7e9de 3180
d1302a36 3181 return ret;
b2476490
MT
3182}
3183
035a61c3
TV
3184struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
3185 const char *con_id)
0197b3ea 3186{
0197b3ea
SK
3187 struct clk *clk;
3188
035a61c3 3189 /* This is to allow this function to be chained to others */
c1de1357 3190 if (IS_ERR_OR_NULL(hw))
8a23133c 3191 return ERR_CAST(hw);
0197b3ea 3192
035a61c3
TV
3193 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
3194 if (!clk)
3195 return ERR_PTR(-ENOMEM);
3196
3197 clk->core = hw->core;
3198 clk->dev_id = dev_id;
253160a8 3199 clk->con_id = kstrdup_const(con_id, GFP_KERNEL);
1c8e6004
TV
3200 clk->max_rate = ULONG_MAX;
3201
3202 clk_prepare_lock();
50595f8b 3203 hlist_add_head(&clk->clks_node, &hw->core->clks);
1c8e6004 3204 clk_prepare_unlock();
0197b3ea
SK
3205
3206 return clk;
3207}
035a61c3 3208
365f7a89 3209/* keep in sync with __clk_put */
73e0e496 3210void __clk_free_clk(struct clk *clk)
1c8e6004
TV
3211{
3212 clk_prepare_lock();
50595f8b 3213 hlist_del(&clk->clks_node);
1c8e6004
TV
3214 clk_prepare_unlock();
3215
253160a8 3216 kfree_const(clk->con_id);
1c8e6004
TV
3217 kfree(clk);
3218}
0197b3ea 3219
293ba3b4
SB
3220/**
3221 * clk_register - allocate a new clock, register it and return an opaque cookie
3222 * @dev: device that is registering this clock
3223 * @hw: link to hardware-specific clock data
3224 *
3225 * clk_register is the primary interface for populating the clock tree with new
3226 * clock nodes. It returns a pointer to the newly allocated struct clk which
a59a5163 3227 * cannot be dereferenced by driver code but may be used in conjunction with the
293ba3b4
SB
3228 * rest of the clock API. In the event of an error clk_register will return an
3229 * error code; drivers must test for an error code after calling clk_register.
3230 */
3231struct clk *clk_register(struct device *dev, struct clk_hw *hw)
b2476490 3232{
d1302a36 3233 int i, ret;
d6968fca 3234 struct clk_core *core;
293ba3b4 3235
d6968fca
SB
3236 core = kzalloc(sizeof(*core), GFP_KERNEL);
3237 if (!core) {
293ba3b4
SB
3238 ret = -ENOMEM;
3239 goto fail_out;
3240 }
b2476490 3241
d6968fca
SB
3242 core->name = kstrdup_const(hw->init->name, GFP_KERNEL);
3243 if (!core->name) {
0197b3ea
SK
3244 ret = -ENOMEM;
3245 goto fail_name;
3246 }
29fd2a34
JB
3247
3248 if (WARN_ON(!hw->init->ops)) {
3249 ret = -EINVAL;
3250 goto fail_ops;
3251 }
d6968fca 3252 core->ops = hw->init->ops;
29fd2a34 3253
9a34b453
MS
3254 if (dev && pm_runtime_enabled(dev))
3255 core->dev = dev;
ac2df527 3256 if (dev && dev->driver)
d6968fca
SB
3257 core->owner = dev->driver->owner;
3258 core->hw = hw;
3259 core->flags = hw->init->flags;
3260 core->num_parents = hw->init->num_parents;
9783c0d9
SB
3261 core->min_rate = 0;
3262 core->max_rate = ULONG_MAX;
d6968fca 3263 hw->core = core;
b2476490 3264
d1302a36 3265 /* allocate local copy in case parent_names is __initdata */
d6968fca 3266 core->parent_names = kcalloc(core->num_parents, sizeof(char *),
96a7ed90 3267 GFP_KERNEL);
d1302a36 3268
d6968fca 3269 if (!core->parent_names) {
d1302a36
MT
3270 ret = -ENOMEM;
3271 goto fail_parent_names;
3272 }
3273
3274
3275 /* copy each string name in case parent_names is __initdata */
d6968fca
SB
3276 for (i = 0; i < core->num_parents; i++) {
3277 core->parent_names[i] = kstrdup_const(hw->init->parent_names[i],
0197b3ea 3278 GFP_KERNEL);
d6968fca 3279 if (!core->parent_names[i]) {
d1302a36
MT
3280 ret = -ENOMEM;
3281 goto fail_parent_names_copy;
3282 }
3283 }
3284
176d1169
MY
3285 /* avoid unnecessary string look-ups of clk_core's possible parents. */
3286 core->parents = kcalloc(core->num_parents, sizeof(*core->parents),
3287 GFP_KERNEL);
3288 if (!core->parents) {
3289 ret = -ENOMEM;
3290 goto fail_parents;
3291 };
3292
d6968fca 3293 INIT_HLIST_HEAD(&core->clks);
1c8e6004 3294
035a61c3
TV
3295 hw->clk = __clk_create_clk(hw, NULL, NULL);
3296 if (IS_ERR(hw->clk)) {
035a61c3 3297 ret = PTR_ERR(hw->clk);
176d1169 3298 goto fail_parents;
035a61c3
TV
3299 }
3300
be45ebf2 3301 ret = __clk_core_init(core);
d1302a36 3302 if (!ret)
035a61c3 3303 return hw->clk;
b2476490 3304
1c8e6004 3305 __clk_free_clk(hw->clk);
035a61c3 3306 hw->clk = NULL;
b2476490 3307
176d1169
MY
3308fail_parents:
3309 kfree(core->parents);
d1302a36
MT
3310fail_parent_names_copy:
3311 while (--i >= 0)
d6968fca
SB
3312 kfree_const(core->parent_names[i]);
3313 kfree(core->parent_names);
d1302a36 3314fail_parent_names:
29fd2a34 3315fail_ops:
d6968fca 3316 kfree_const(core->name);
0197b3ea 3317fail_name:
d6968fca 3318 kfree(core);
d1302a36
MT
3319fail_out:
3320 return ERR_PTR(ret);
b2476490
MT
3321}
3322EXPORT_SYMBOL_GPL(clk_register);
3323
4143804c
SB
3324/**
3325 * clk_hw_register - register a clk_hw and return an error code
3326 * @dev: device that is registering this clock
3327 * @hw: link to hardware-specific clock data
3328 *
3329 * clk_hw_register is the primary interface for populating the clock tree with
3330 * new clock nodes. It returns an integer equal to zero indicating success or
3331 * less than zero indicating failure. Drivers must test for an error code after
3332 * calling clk_hw_register().
3333 */
3334int clk_hw_register(struct device *dev, struct clk_hw *hw)
3335{
3336 return PTR_ERR_OR_ZERO(clk_register(dev, hw));
3337}
3338EXPORT_SYMBOL_GPL(clk_hw_register);
3339
6e5ab41b 3340/* Free memory allocated for a clock. */
fcb0ee6a
SN
3341static void __clk_release(struct kref *ref)
3342{
d6968fca
SB
3343 struct clk_core *core = container_of(ref, struct clk_core, ref);
3344 int i = core->num_parents;
fcb0ee6a 3345
496eadf8
KK
3346 lockdep_assert_held(&prepare_lock);
3347
d6968fca 3348 kfree(core->parents);
fcb0ee6a 3349 while (--i >= 0)
d6968fca 3350 kfree_const(core->parent_names[i]);
fcb0ee6a 3351
d6968fca
SB
3352 kfree(core->parent_names);
3353 kfree_const(core->name);
3354 kfree(core);
fcb0ee6a
SN
3355}
3356
3357/*
3358 * Empty clk_ops for unregistered clocks. These are used temporarily
3359 * after clk_unregister() was called on a clock and until last clock
3360 * consumer calls clk_put() and the struct clk object is freed.
3361 */
3362static int clk_nodrv_prepare_enable(struct clk_hw *hw)
3363{
3364 return -ENXIO;
3365}
3366
3367static void clk_nodrv_disable_unprepare(struct clk_hw *hw)
3368{
3369 WARN_ON_ONCE(1);
3370}
3371
3372static int clk_nodrv_set_rate(struct clk_hw *hw, unsigned long rate,
3373 unsigned long parent_rate)
3374{
3375 return -ENXIO;
3376}
3377
3378static int clk_nodrv_set_parent(struct clk_hw *hw, u8 index)
3379{
3380 return -ENXIO;
3381}
3382
3383static const struct clk_ops clk_nodrv_ops = {
3384 .enable = clk_nodrv_prepare_enable,
3385 .disable = clk_nodrv_disable_unprepare,
3386 .prepare = clk_nodrv_prepare_enable,
3387 .unprepare = clk_nodrv_disable_unprepare,
3388 .set_rate = clk_nodrv_set_rate,
3389 .set_parent = clk_nodrv_set_parent,
3390};
3391
1df5c939
MB
3392/**
3393 * clk_unregister - unregister a currently registered clock
3394 * @clk: clock to unregister
1df5c939 3395 */
fcb0ee6a
SN
3396void clk_unregister(struct clk *clk)
3397{
3398 unsigned long flags;
3399
6314b679
SB
3400 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
3401 return;
3402
035a61c3 3403 clk_debug_unregister(clk->core);
fcb0ee6a
SN
3404
3405 clk_prepare_lock();
3406
035a61c3
TV
3407 if (clk->core->ops == &clk_nodrv_ops) {
3408 pr_err("%s: unregistered clock: %s\n", __func__,
3409 clk->core->name);
4106a3d9 3410 goto unlock;
fcb0ee6a
SN
3411 }
3412 /*
3413 * Assign empty clock ops for consumers that might still hold
3414 * a reference to this clock.
3415 */
3416 flags = clk_enable_lock();
035a61c3 3417 clk->core->ops = &clk_nodrv_ops;
fcb0ee6a
SN
3418 clk_enable_unlock(flags);
3419
035a61c3
TV
3420 if (!hlist_empty(&clk->core->children)) {
3421 struct clk_core *child;
874f224c 3422 struct hlist_node *t;
fcb0ee6a
SN
3423
3424 /* Reparent all children to the orphan list. */
035a61c3
TV
3425 hlist_for_each_entry_safe(child, t, &clk->core->children,
3426 child_node)
91baa9ff 3427 clk_core_set_parent_nolock(child, NULL);
fcb0ee6a
SN
3428 }
3429
035a61c3 3430 hlist_del_init(&clk->core->child_node);
fcb0ee6a 3431
035a61c3 3432 if (clk->core->prepare_count)
fcb0ee6a 3433 pr_warn("%s: unregistering prepared clock: %s\n",
035a61c3 3434 __func__, clk->core->name);
e55a839a
JB
3435
3436 if (clk->core->protect_count)
3437 pr_warn("%s: unregistering protected clock: %s\n",
3438 __func__, clk->core->name);
3439
035a61c3 3440 kref_put(&clk->core->ref, __clk_release);
4106a3d9 3441unlock:
fcb0ee6a
SN
3442 clk_prepare_unlock();
3443}
1df5c939
MB
3444EXPORT_SYMBOL_GPL(clk_unregister);
3445
4143804c
SB
3446/**
3447 * clk_hw_unregister - unregister a currently registered clk_hw
3448 * @hw: hardware-specific clock data to unregister
3449 */
3450void clk_hw_unregister(struct clk_hw *hw)
3451{
3452 clk_unregister(hw->clk);
3453}
3454EXPORT_SYMBOL_GPL(clk_hw_unregister);
3455
46c8773a
SB
3456static void devm_clk_release(struct device *dev, void *res)
3457{
293ba3b4 3458 clk_unregister(*(struct clk **)res);
46c8773a
SB
3459}
3460
4143804c
SB
3461static void devm_clk_hw_release(struct device *dev, void *res)
3462{
3463 clk_hw_unregister(*(struct clk_hw **)res);
3464}
3465
46c8773a
SB
3466/**
3467 * devm_clk_register - resource managed clk_register()
3468 * @dev: device that is registering this clock
3469 * @hw: link to hardware-specific clock data
3470 *
3471 * Managed clk_register(). Clocks returned from this function are
3472 * automatically clk_unregister()ed on driver detach. See clk_register() for
3473 * more information.
3474 */
3475struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw)
3476{
3477 struct clk *clk;
293ba3b4 3478 struct clk **clkp;
46c8773a 3479
293ba3b4
SB
3480 clkp = devres_alloc(devm_clk_release, sizeof(*clkp), GFP_KERNEL);
3481 if (!clkp)
46c8773a
SB
3482 return ERR_PTR(-ENOMEM);
3483
293ba3b4
SB
3484 clk = clk_register(dev, hw);
3485 if (!IS_ERR(clk)) {
3486 *clkp = clk;
3487 devres_add(dev, clkp);
46c8773a 3488 } else {
293ba3b4 3489 devres_free(clkp);
46c8773a
SB
3490 }
3491
3492 return clk;
3493}
3494EXPORT_SYMBOL_GPL(devm_clk_register);
3495
4143804c
SB
3496/**
3497 * devm_clk_hw_register - resource managed clk_hw_register()
3498 * @dev: device that is registering this clock
3499 * @hw: link to hardware-specific clock data
3500 *
c47265ad 3501 * Managed clk_hw_register(). Clocks registered by this function are
4143804c
SB
3502 * automatically clk_hw_unregister()ed on driver detach. See clk_hw_register()
3503 * for more information.
3504 */
3505int devm_clk_hw_register(struct device *dev, struct clk_hw *hw)
3506{
3507 struct clk_hw **hwp;
3508 int ret;
3509
3510 hwp = devres_alloc(devm_clk_hw_release, sizeof(*hwp), GFP_KERNEL);
3511 if (!hwp)
3512 return -ENOMEM;
3513
3514 ret = clk_hw_register(dev, hw);
3515 if (!ret) {
3516 *hwp = hw;
3517 devres_add(dev, hwp);
3518 } else {
3519 devres_free(hwp);
3520 }
3521
3522 return ret;
3523}
3524EXPORT_SYMBOL_GPL(devm_clk_hw_register);
3525
46c8773a
SB
3526static int devm_clk_match(struct device *dev, void *res, void *data)
3527{
3528 struct clk *c = res;
3529 if (WARN_ON(!c))
3530 return 0;
3531 return c == data;
3532}
3533
4143804c
SB
3534static int devm_clk_hw_match(struct device *dev, void *res, void *data)
3535{
3536 struct clk_hw *hw = res;
3537
3538 if (WARN_ON(!hw))
3539 return 0;
3540 return hw == data;
3541}
3542
46c8773a
SB
3543/**
3544 * devm_clk_unregister - resource managed clk_unregister()
3545 * @clk: clock to unregister
3546 *
3547 * Deallocate a clock allocated with devm_clk_register(). Normally
3548 * this function will not need to be called and the resource management
3549 * code will ensure that the resource is freed.
3550 */
3551void devm_clk_unregister(struct device *dev, struct clk *clk)
3552{
3553 WARN_ON(devres_release(dev, devm_clk_release, devm_clk_match, clk));
3554}
3555EXPORT_SYMBOL_GPL(devm_clk_unregister);
3556
4143804c
SB
3557/**
3558 * devm_clk_hw_unregister - resource managed clk_hw_unregister()
3559 * @dev: device that is unregistering the hardware-specific clock data
3560 * @hw: link to hardware-specific clock data
3561 *
3562 * Unregister a clk_hw registered with devm_clk_hw_register(). Normally
3563 * this function will not need to be called and the resource management
3564 * code will ensure that the resource is freed.
3565 */
3566void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw)
3567{
3568 WARN_ON(devres_release(dev, devm_clk_hw_release, devm_clk_hw_match,
3569 hw));
3570}
3571EXPORT_SYMBOL_GPL(devm_clk_hw_unregister);
3572
ac2df527
SN
3573/*
3574 * clkdev helpers
3575 */
3576int __clk_get(struct clk *clk)
3577{
035a61c3
TV
3578 struct clk_core *core = !clk ? NULL : clk->core;
3579
3580 if (core) {
3581 if (!try_module_get(core->owner))
00efcb1c 3582 return 0;
ac2df527 3583
035a61c3 3584 kref_get(&core->ref);
00efcb1c 3585 }
ac2df527
SN
3586 return 1;
3587}
3588
365f7a89 3589/* keep in sync with __clk_free_clk */
ac2df527
SN
3590void __clk_put(struct clk *clk)
3591{
10cdfe54
TV
3592 struct module *owner;
3593
00efcb1c 3594 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
ac2df527
SN
3595 return;
3596
fcb0ee6a 3597 clk_prepare_lock();
1c8e6004 3598
55e9b8b7
JB
3599 /*
3600 * Before calling clk_put, all calls to clk_rate_exclusive_get() from a
3601 * given user should be balanced with calls to clk_rate_exclusive_put()
3602 * and by that same consumer
3603 */
3604 if (WARN_ON(clk->exclusive_count)) {
3605 /* We voiced our concern, let's sanitize the situation */
3606 clk->core->protect_count -= (clk->exclusive_count - 1);
3607 clk_core_rate_unprotect(clk->core);
3608 clk->exclusive_count = 0;
3609 }
3610
50595f8b 3611 hlist_del(&clk->clks_node);
ec02ace8
TV
3612 if (clk->min_rate > clk->core->req_rate ||
3613 clk->max_rate < clk->core->req_rate)
3614 clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
3615
1c8e6004
TV
3616 owner = clk->core->owner;
3617 kref_put(&clk->core->ref, __clk_release);
3618
fcb0ee6a
SN
3619 clk_prepare_unlock();
3620
10cdfe54 3621 module_put(owner);
035a61c3 3622
365f7a89 3623 kfree_const(clk->con_id);
035a61c3 3624 kfree(clk);
ac2df527
SN
3625}
3626
b2476490
MT
3627/*** clk rate change notifiers ***/
3628
3629/**
3630 * clk_notifier_register - add a clk rate change notifier
3631 * @clk: struct clk * to watch
3632 * @nb: struct notifier_block * with callback info
3633 *
3634 * Request notification when clk's rate changes. This uses an SRCU
3635 * notifier because we want it to block and notifier unregistrations are
3636 * uncommon. The callbacks associated with the notifier must not
3637 * re-enter into the clk framework by calling any top-level clk APIs;
3638 * this will cause a nested prepare_lock mutex.
3639 *
198bb594
MY
3640 * In all notification cases (pre, post and abort rate change) the original
3641 * clock rate is passed to the callback via struct clk_notifier_data.old_rate
3642 * and the new frequency is passed via struct clk_notifier_data.new_rate.
b2476490 3643 *
b2476490
MT
3644 * clk_notifier_register() must be called from non-atomic context.
3645 * Returns -EINVAL if called with null arguments, -ENOMEM upon
3646 * allocation failure; otherwise, passes along the return value of
3647 * srcu_notifier_chain_register().
3648 */
3649int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
3650{
3651 struct clk_notifier *cn;
3652 int ret = -ENOMEM;
3653
3654 if (!clk || !nb)
3655 return -EINVAL;
3656
eab89f69 3657 clk_prepare_lock();
b2476490
MT
3658
3659 /* search the list of notifiers for this clk */
3660 list_for_each_entry(cn, &clk_notifier_list, node)
3661 if (cn->clk == clk)
3662 break;
3663
3664 /* if clk wasn't in the notifier list, allocate new clk_notifier */
3665 if (cn->clk != clk) {
1808a320 3666 cn = kzalloc(sizeof(*cn), GFP_KERNEL);
b2476490
MT
3667 if (!cn)
3668 goto out;
3669
3670 cn->clk = clk;
3671 srcu_init_notifier_head(&cn->notifier_head);
3672
3673 list_add(&cn->node, &clk_notifier_list);
3674 }
3675
3676 ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
3677
035a61c3 3678 clk->core->notifier_count++;
b2476490
MT
3679
3680out:
eab89f69 3681 clk_prepare_unlock();
b2476490
MT
3682
3683 return ret;
3684}
3685EXPORT_SYMBOL_GPL(clk_notifier_register);
3686
3687/**
3688 * clk_notifier_unregister - remove a clk rate change notifier
3689 * @clk: struct clk *
3690 * @nb: struct notifier_block * with callback info
3691 *
3692 * Request no further notification for changes to 'clk' and frees memory
3693 * allocated in clk_notifier_register.
3694 *
3695 * Returns -EINVAL if called with null arguments; otherwise, passes
3696 * along the return value of srcu_notifier_chain_unregister().
3697 */
3698int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
3699{
3700 struct clk_notifier *cn = NULL;
3701 int ret = -EINVAL;
3702
3703 if (!clk || !nb)
3704 return -EINVAL;
3705
eab89f69 3706 clk_prepare_lock();
b2476490
MT
3707
3708 list_for_each_entry(cn, &clk_notifier_list, node)
3709 if (cn->clk == clk)
3710 break;
3711
3712 if (cn->clk == clk) {
3713 ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
3714
035a61c3 3715 clk->core->notifier_count--;
b2476490
MT
3716
3717 /* XXX the notifier code should handle this better */
3718 if (!cn->notifier_head.head) {
3719 srcu_cleanup_notifier_head(&cn->notifier_head);
72b5322f 3720 list_del(&cn->node);
b2476490
MT
3721 kfree(cn);
3722 }
3723
3724 } else {
3725 ret = -ENOENT;
3726 }
3727
eab89f69 3728 clk_prepare_unlock();
b2476490
MT
3729
3730 return ret;
3731}
3732EXPORT_SYMBOL_GPL(clk_notifier_unregister);
766e6a4e
GL
3733
3734#ifdef CONFIG_OF
3735/**
3736 * struct of_clk_provider - Clock provider registration structure
3737 * @link: Entry in global list of clock providers
3738 * @node: Pointer to device tree node of clock provider
3739 * @get: Get clock callback. Returns NULL or a struct clk for the
3740 * given clock specifier
3741 * @data: context pointer to be passed into @get callback
3742 */
3743struct of_clk_provider {
3744 struct list_head link;
3745
3746 struct device_node *node;
3747 struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
0861e5b8 3748 struct clk_hw *(*get_hw)(struct of_phandle_args *clkspec, void *data);
766e6a4e
GL
3749 void *data;
3750};
3751
f2f6c255
PG
3752static const struct of_device_id __clk_of_table_sentinel
3753 __used __section(__clk_of_table_end);
3754
766e6a4e 3755static LIST_HEAD(of_clk_providers);
d6782c26
SN
3756static DEFINE_MUTEX(of_clk_mutex);
3757
766e6a4e
GL
3758struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
3759 void *data)
3760{
3761 return data;
3762}
3763EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
3764
0861e5b8
SB
3765struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
3766{
3767 return data;
3768}
3769EXPORT_SYMBOL_GPL(of_clk_hw_simple_get);
3770
494bfec9
SG
3771struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
3772{
3773 struct clk_onecell_data *clk_data = data;
3774 unsigned int idx = clkspec->args[0];
3775
3776 if (idx >= clk_data->clk_num) {
7e96353c 3777 pr_err("%s: invalid clock index %u\n", __func__, idx);
494bfec9
SG
3778 return ERR_PTR(-EINVAL);
3779 }
3780
3781 return clk_data->clks[idx];
3782}
3783EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
3784
0861e5b8
SB
3785struct clk_hw *
3786of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
3787{
3788 struct clk_hw_onecell_data *hw_data = data;
3789 unsigned int idx = clkspec->args[0];
3790
3791 if (idx >= hw_data->num) {
3792 pr_err("%s: invalid index %u\n", __func__, idx);
3793 return ERR_PTR(-EINVAL);
3794 }
3795
3796 return hw_data->hws[idx];
3797}
3798EXPORT_SYMBOL_GPL(of_clk_hw_onecell_get);
3799
766e6a4e
GL
3800/**
3801 * of_clk_add_provider() - Register a clock provider for a node
3802 * @np: Device node pointer associated with clock provider
3803 * @clk_src_get: callback for decoding clock
3804 * @data: context pointer for @clk_src_get callback.
3805 */
3806int of_clk_add_provider(struct device_node *np,
3807 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
3808 void *data),
3809 void *data)
3810{
3811 struct of_clk_provider *cp;
86be408b 3812 int ret;
766e6a4e 3813
1808a320 3814 cp = kzalloc(sizeof(*cp), GFP_KERNEL);
766e6a4e
GL
3815 if (!cp)
3816 return -ENOMEM;
3817
3818 cp->node = of_node_get(np);
3819 cp->data = data;
3820 cp->get = clk_src_get;
3821
d6782c26 3822 mutex_lock(&of_clk_mutex);
766e6a4e 3823 list_add(&cp->link, &of_clk_providers);
d6782c26 3824 mutex_unlock(&of_clk_mutex);
16673931 3825 pr_debug("Added clock from %pOF\n", np);
766e6a4e 3826
86be408b
SN
3827 ret = of_clk_set_defaults(np, true);
3828 if (ret < 0)
3829 of_clk_del_provider(np);
3830
3831 return ret;
766e6a4e
GL
3832}
3833EXPORT_SYMBOL_GPL(of_clk_add_provider);
3834
0861e5b8
SB
3835/**
3836 * of_clk_add_hw_provider() - Register a clock provider for a node
3837 * @np: Device node pointer associated with clock provider
3838 * @get: callback for decoding clk_hw
3839 * @data: context pointer for @get callback.
3840 */
3841int of_clk_add_hw_provider(struct device_node *np,
3842 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
3843 void *data),
3844 void *data)
3845{
3846 struct of_clk_provider *cp;
3847 int ret;
3848
3849 cp = kzalloc(sizeof(*cp), GFP_KERNEL);
3850 if (!cp)
3851 return -ENOMEM;
3852
3853 cp->node = of_node_get(np);
3854 cp->data = data;
3855 cp->get_hw = get;
3856
3857 mutex_lock(&of_clk_mutex);
3858 list_add(&cp->link, &of_clk_providers);
3859 mutex_unlock(&of_clk_mutex);
16673931 3860 pr_debug("Added clk_hw provider from %pOF\n", np);
0861e5b8
SB
3861
3862 ret = of_clk_set_defaults(np, true);
3863 if (ret < 0)
3864 of_clk_del_provider(np);
3865
3866 return ret;
3867}
3868EXPORT_SYMBOL_GPL(of_clk_add_hw_provider);
3869
aa795c41
SB
3870static void devm_of_clk_release_provider(struct device *dev, void *res)
3871{
3872 of_clk_del_provider(*(struct device_node **)res);
3873}
3874
3875int devm_of_clk_add_hw_provider(struct device *dev,
3876 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
3877 void *data),
3878 void *data)
3879{
3880 struct device_node **ptr, *np;
3881 int ret;
3882
3883 ptr = devres_alloc(devm_of_clk_release_provider, sizeof(*ptr),
3884 GFP_KERNEL);
3885 if (!ptr)
3886 return -ENOMEM;
3887
3888 np = dev->of_node;
3889 ret = of_clk_add_hw_provider(np, get, data);
3890 if (!ret) {
3891 *ptr = np;
3892 devres_add(dev, ptr);
3893 } else {
3894 devres_free(ptr);
3895 }
3896
3897 return ret;
3898}
3899EXPORT_SYMBOL_GPL(devm_of_clk_add_hw_provider);
3900
766e6a4e
GL
3901/**
3902 * of_clk_del_provider() - Remove a previously registered clock provider
3903 * @np: Device node pointer associated with clock provider
3904 */
3905void of_clk_del_provider(struct device_node *np)
3906{
3907 struct of_clk_provider *cp;
3908
d6782c26 3909 mutex_lock(&of_clk_mutex);
766e6a4e
GL
3910 list_for_each_entry(cp, &of_clk_providers, link) {
3911 if (cp->node == np) {
3912 list_del(&cp->link);
3913 of_node_put(cp->node);
3914 kfree(cp);
3915 break;
3916 }
3917 }
d6782c26 3918 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
3919}
3920EXPORT_SYMBOL_GPL(of_clk_del_provider);
3921
aa795c41
SB
3922static int devm_clk_provider_match(struct device *dev, void *res, void *data)
3923{
3924 struct device_node **np = res;
3925
3926 if (WARN_ON(!np || !*np))
3927 return 0;
3928
3929 return *np == data;
3930}
3931
3932void devm_of_clk_del_provider(struct device *dev)
3933{
3934 int ret;
3935
3936 ret = devres_release(dev, devm_of_clk_release_provider,
3937 devm_clk_provider_match, dev->of_node);
3938
3939 WARN_ON(ret);
3940}
3941EXPORT_SYMBOL(devm_of_clk_del_provider);
3942
0861e5b8
SB
3943static struct clk_hw *
3944__of_clk_get_hw_from_provider(struct of_clk_provider *provider,
3945 struct of_phandle_args *clkspec)
3946{
3947 struct clk *clk;
0861e5b8 3948
74002fcd
SB
3949 if (provider->get_hw)
3950 return provider->get_hw(clkspec, provider->data);
0861e5b8 3951
74002fcd
SB
3952 clk = provider->get(clkspec, provider->data);
3953 if (IS_ERR(clk))
3954 return ERR_CAST(clk);
3955 return __clk_get_hw(clk);
0861e5b8
SB
3956}
3957
73e0e496
SB
3958struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
3959 const char *dev_id, const char *con_id)
766e6a4e
GL
3960{
3961 struct of_clk_provider *provider;
a34cd466 3962 struct clk *clk = ERR_PTR(-EPROBE_DEFER);
f155d15b 3963 struct clk_hw *hw;
766e6a4e 3964
306c342f
SB
3965 if (!clkspec)
3966 return ERR_PTR(-EINVAL);
3967
766e6a4e 3968 /* Check if we have such a provider in our array */
306c342f 3969 mutex_lock(&of_clk_mutex);
766e6a4e 3970 list_for_each_entry(provider, &of_clk_providers, link) {
f155d15b 3971 if (provider->node == clkspec->np) {
0861e5b8 3972 hw = __of_clk_get_hw_from_provider(provider, clkspec);
0861e5b8 3973 clk = __clk_create_clk(hw, dev_id, con_id);
f155d15b 3974 }
73e0e496 3975
f155d15b
SB
3976 if (!IS_ERR(clk)) {
3977 if (!__clk_get(clk)) {
73e0e496
SB
3978 __clk_free_clk(clk);
3979 clk = ERR_PTR(-ENOENT);
3980 }
3981
766e6a4e 3982 break;
73e0e496 3983 }
766e6a4e 3984 }
306c342f 3985 mutex_unlock(&of_clk_mutex);
d6782c26
SN
3986
3987 return clk;
3988}
3989
306c342f
SB
3990/**
3991 * of_clk_get_from_provider() - Lookup a clock from a clock provider
3992 * @clkspec: pointer to a clock specifier data structure
3993 *
3994 * This function looks up a struct clk from the registered list of clock
3995 * providers, an input is a clock specifier data structure as returned
3996 * from the of_parse_phandle_with_args() function call.
3997 */
d6782c26
SN
3998struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
3999{
306c342f 4000 return __of_clk_get_from_provider(clkspec, NULL, __func__);
766e6a4e 4001}
fb4dd222 4002EXPORT_SYMBOL_GPL(of_clk_get_from_provider);
766e6a4e 4003
929e7f3b
SB
4004/**
4005 * of_clk_get_parent_count() - Count the number of clocks a device node has
4006 * @np: device node to count
4007 *
4008 * Returns: The number of clocks that are possible parents of this node
4009 */
4010unsigned int of_clk_get_parent_count(struct device_node *np)
f6102742 4011{
929e7f3b
SB
4012 int count;
4013
4014 count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
4015 if (count < 0)
4016 return 0;
4017
4018 return count;
f6102742
MT
4019}
4020EXPORT_SYMBOL_GPL(of_clk_get_parent_count);
4021
766e6a4e
GL
4022const char *of_clk_get_parent_name(struct device_node *np, int index)
4023{
4024 struct of_phandle_args clkspec;
7a0fc1a3 4025 struct property *prop;
766e6a4e 4026 const char *clk_name;
7a0fc1a3
BD
4027 const __be32 *vp;
4028 u32 pv;
766e6a4e 4029 int rc;
7a0fc1a3 4030 int count;
0a4807c2 4031 struct clk *clk;
766e6a4e 4032
766e6a4e
GL
4033 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
4034 &clkspec);
4035 if (rc)
4036 return NULL;
4037
7a0fc1a3
BD
4038 index = clkspec.args_count ? clkspec.args[0] : 0;
4039 count = 0;
4040
4041 /* if there is an indices property, use it to transfer the index
4042 * specified into an array offset for the clock-output-names property.
4043 */
4044 of_property_for_each_u32(clkspec.np, "clock-indices", prop, vp, pv) {
4045 if (index == pv) {
4046 index = count;
4047 break;
4048 }
4049 count++;
4050 }
8da411cc
MY
4051 /* We went off the end of 'clock-indices' without finding it */
4052 if (prop && !vp)
4053 return NULL;
7a0fc1a3 4054
766e6a4e 4055 if (of_property_read_string_index(clkspec.np, "clock-output-names",
7a0fc1a3 4056 index,
0a4807c2
SB
4057 &clk_name) < 0) {
4058 /*
4059 * Best effort to get the name if the clock has been
4060 * registered with the framework. If the clock isn't
4061 * registered, we return the node name as the name of
4062 * the clock as long as #clock-cells = 0.
4063 */
4064 clk = of_clk_get_from_provider(&clkspec);
4065 if (IS_ERR(clk)) {
4066 if (clkspec.args_count == 0)
4067 clk_name = clkspec.np->name;
4068 else
4069 clk_name = NULL;
4070 } else {
4071 clk_name = __clk_get_name(clk);
4072 clk_put(clk);
4073 }
4074 }
4075
766e6a4e
GL
4076
4077 of_node_put(clkspec.np);
4078 return clk_name;
4079}
4080EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
4081
2e61dfb3
DN
4082/**
4083 * of_clk_parent_fill() - Fill @parents with names of @np's parents and return
4084 * number of parents
4085 * @np: Device node pointer associated with clock provider
4086 * @parents: pointer to char array that hold the parents' names
4087 * @size: size of the @parents array
4088 *
4089 * Return: number of parents for the clock node.
4090 */
4091int of_clk_parent_fill(struct device_node *np, const char **parents,
4092 unsigned int size)
4093{
4094 unsigned int i = 0;
4095
4096 while (i < size && (parents[i] = of_clk_get_parent_name(np, i)) != NULL)
4097 i++;
4098
4099 return i;
4100}
4101EXPORT_SYMBOL_GPL(of_clk_parent_fill);
4102
1771b10d 4103struct clock_provider {
a5970433 4104 void (*clk_init_cb)(struct device_node *);
1771b10d
GC
4105 struct device_node *np;
4106 struct list_head node;
4107};
4108
1771b10d
GC
4109/*
4110 * This function looks for a parent clock. If there is one, then it
4111 * checks that the provider for this parent clock was initialized, in
4112 * this case the parent clock will be ready.
4113 */
4114static int parent_ready(struct device_node *np)
4115{
4116 int i = 0;
4117
4118 while (true) {
4119 struct clk *clk = of_clk_get(np, i);
4120
4121 /* this parent is ready we can check the next one */
4122 if (!IS_ERR(clk)) {
4123 clk_put(clk);
4124 i++;
4125 continue;
4126 }
4127
4128 /* at least one parent is not ready, we exit now */
4129 if (PTR_ERR(clk) == -EPROBE_DEFER)
4130 return 0;
4131
4132 /*
4133 * Here we make assumption that the device tree is
4134 * written correctly. So an error means that there is
4135 * no more parent. As we didn't exit yet, then the
4136 * previous parent are ready. If there is no clock
4137 * parent, no need to wait for them, then we can
4138 * consider their absence as being ready
4139 */
4140 return 1;
4141 }
4142}
4143
d56f8994
LJ
4144/**
4145 * of_clk_detect_critical() - set CLK_IS_CRITICAL flag from Device Tree
4146 * @np: Device node pointer associated with clock provider
4147 * @index: clock index
f7ae7503 4148 * @flags: pointer to top-level framework flags
d56f8994
LJ
4149 *
4150 * Detects if the clock-critical property exists and, if so, sets the
4151 * corresponding CLK_IS_CRITICAL flag.
4152 *
4153 * Do not use this function. It exists only for legacy Device Tree
4154 * bindings, such as the one-clock-per-node style that are outdated.
4155 * Those bindings typically put all clock data into .dts and the Linux
4156 * driver has no clock data, thus making it impossible to set this flag
4157 * correctly from the driver. Only those drivers may call
4158 * of_clk_detect_critical from their setup functions.
4159 *
4160 * Return: error code or zero on success
4161 */
4162int of_clk_detect_critical(struct device_node *np,
4163 int index, unsigned long *flags)
4164{
4165 struct property *prop;
4166 const __be32 *cur;
4167 uint32_t idx;
4168
4169 if (!np || !flags)
4170 return -EINVAL;
4171
4172 of_property_for_each_u32(np, "clock-critical", prop, cur, idx)
4173 if (index == idx)
4174 *flags |= CLK_IS_CRITICAL;
4175
4176 return 0;
4177}
4178
766e6a4e
GL
4179/**
4180 * of_clk_init() - Scan and init clock providers from the DT
4181 * @matches: array of compatible values and init functions for providers.
4182 *
1771b10d 4183 * This function scans the device tree for matching clock providers
e5ca8fb4 4184 * and calls their initialization functions. It also does it by trying
1771b10d 4185 * to follow the dependencies.
766e6a4e
GL
4186 */
4187void __init of_clk_init(const struct of_device_id *matches)
4188{
7f7ed584 4189 const struct of_device_id *match;
766e6a4e 4190 struct device_node *np;
1771b10d
GC
4191 struct clock_provider *clk_provider, *next;
4192 bool is_init_done;
4193 bool force = false;
2573a02a 4194 LIST_HEAD(clk_provider_list);
766e6a4e 4195
f2f6c255 4196 if (!matches)
819b4861 4197 matches = &__clk_of_table;
f2f6c255 4198
1771b10d 4199 /* First prepare the list of the clocks providers */
7f7ed584 4200 for_each_matching_node_and_match(np, matches, &match) {
2e3b19f1
SB
4201 struct clock_provider *parent;
4202
3e5dd6f6
GU
4203 if (!of_device_is_available(np))
4204 continue;
4205
2e3b19f1
SB
4206 parent = kzalloc(sizeof(*parent), GFP_KERNEL);
4207 if (!parent) {
4208 list_for_each_entry_safe(clk_provider, next,
4209 &clk_provider_list, node) {
4210 list_del(&clk_provider->node);
6bc9d9d6 4211 of_node_put(clk_provider->np);
2e3b19f1
SB
4212 kfree(clk_provider);
4213 }
6bc9d9d6 4214 of_node_put(np);
2e3b19f1
SB
4215 return;
4216 }
1771b10d
GC
4217
4218 parent->clk_init_cb = match->data;
6bc9d9d6 4219 parent->np = of_node_get(np);
3f6d439f 4220 list_add_tail(&parent->node, &clk_provider_list);
1771b10d
GC
4221 }
4222
4223 while (!list_empty(&clk_provider_list)) {
4224 is_init_done = false;
4225 list_for_each_entry_safe(clk_provider, next,
4226 &clk_provider_list, node) {
4227 if (force || parent_ready(clk_provider->np)) {
86be408b 4228
989eafd0
RRD
4229 /* Don't populate platform devices */
4230 of_node_set_flag(clk_provider->np,
4231 OF_POPULATED);
4232
1771b10d 4233 clk_provider->clk_init_cb(clk_provider->np);
86be408b
SN
4234 of_clk_set_defaults(clk_provider->np, true);
4235
1771b10d 4236 list_del(&clk_provider->node);
6bc9d9d6 4237 of_node_put(clk_provider->np);
1771b10d
GC
4238 kfree(clk_provider);
4239 is_init_done = true;
4240 }
4241 }
4242
4243 /*
e5ca8fb4 4244 * We didn't manage to initialize any of the
1771b10d
GC
4245 * remaining providers during the last loop, so now we
4246 * initialize all the remaining ones unconditionally
4247 * in case the clock parent was not mandatory
4248 */
4249 if (!is_init_done)
4250 force = true;
766e6a4e
GL
4251 }
4252}
4253#endif