]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/clk/clk.c
clk: at91: pmc: Wait for clocks when resuming
[mirror_ubuntu-bionic-kernel.git] / drivers / clk / clk.c
CommitLineData
b2476490
MT
1/*
2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Standard functionality for the common clock API. See Documentation/clk.txt
10 */
11
3c373117 12#include <linux/clk.h>
b09d6d99 13#include <linux/clk-provider.h>
86be408b 14#include <linux/clk/clk-conf.h>
b2476490
MT
15#include <linux/module.h>
16#include <linux/mutex.h>
17#include <linux/spinlock.h>
18#include <linux/err.h>
19#include <linux/list.h>
20#include <linux/slab.h>
766e6a4e 21#include <linux/of.h>
46c8773a 22#include <linux/device.h>
f2f6c255 23#include <linux/init.h>
9a34b453 24#include <linux/pm_runtime.h>
533ddeb1 25#include <linux/sched.h>
562ef0b0 26#include <linux/clkdev.h>
b2476490 27
d6782c26
SN
28#include "clk.h"
29
b2476490
MT
30static DEFINE_SPINLOCK(enable_lock);
31static DEFINE_MUTEX(prepare_lock);
32
533ddeb1
MT
33static struct task_struct *prepare_owner;
34static struct task_struct *enable_owner;
35
36static int prepare_refcnt;
37static int enable_refcnt;
38
b2476490
MT
39static HLIST_HEAD(clk_root_list);
40static HLIST_HEAD(clk_orphan_list);
41static LIST_HEAD(clk_notifier_list);
42
b09d6d99
MT
43/*** private data structures ***/
44
45struct clk_core {
46 const char *name;
47 const struct clk_ops *ops;
48 struct clk_hw *hw;
49 struct module *owner;
9a34b453 50 struct device *dev;
b09d6d99
MT
51 struct clk_core *parent;
52 const char **parent_names;
53 struct clk_core **parents;
54 u8 num_parents;
55 u8 new_parent_index;
56 unsigned long rate;
1c8e6004 57 unsigned long req_rate;
b09d6d99
MT
58 unsigned long new_rate;
59 struct clk_core *new_parent;
60 struct clk_core *new_child;
61 unsigned long flags;
e6500344 62 bool orphan;
b09d6d99
MT
63 unsigned int enable_count;
64 unsigned int prepare_count;
9783c0d9
SB
65 unsigned long min_rate;
66 unsigned long max_rate;
b09d6d99
MT
67 unsigned long accuracy;
68 int phase;
69 struct hlist_head children;
70 struct hlist_node child_node;
1c8e6004 71 struct hlist_head clks;
b09d6d99
MT
72 unsigned int notifier_count;
73#ifdef CONFIG_DEBUG_FS
74 struct dentry *dentry;
8c9a8a8f 75 struct hlist_node debug_node;
b09d6d99
MT
76#endif
77 struct kref ref;
78};
79
dfc202ea
SB
80#define CREATE_TRACE_POINTS
81#include <trace/events/clk.h>
82
b09d6d99
MT
83struct clk {
84 struct clk_core *core;
85 const char *dev_id;
86 const char *con_id;
1c8e6004
TV
87 unsigned long min_rate;
88 unsigned long max_rate;
50595f8b 89 struct hlist_node clks_node;
b09d6d99
MT
90};
91
9a34b453
MS
92/*** runtime pm ***/
93static int clk_pm_runtime_get(struct clk_core *core)
94{
95 int ret = 0;
96
97 if (!core->dev)
98 return 0;
99
100 ret = pm_runtime_get_sync(core->dev);
101 return ret < 0 ? ret : 0;
102}
103
104static void clk_pm_runtime_put(struct clk_core *core)
105{
106 if (!core->dev)
107 return;
108
109 pm_runtime_put_sync(core->dev);
110}
111
eab89f69
MT
112/*** locking ***/
113static void clk_prepare_lock(void)
114{
533ddeb1
MT
115 if (!mutex_trylock(&prepare_lock)) {
116 if (prepare_owner == current) {
117 prepare_refcnt++;
118 return;
119 }
120 mutex_lock(&prepare_lock);
121 }
122 WARN_ON_ONCE(prepare_owner != NULL);
123 WARN_ON_ONCE(prepare_refcnt != 0);
124 prepare_owner = current;
125 prepare_refcnt = 1;
eab89f69
MT
126}
127
128static void clk_prepare_unlock(void)
129{
533ddeb1
MT
130 WARN_ON_ONCE(prepare_owner != current);
131 WARN_ON_ONCE(prepare_refcnt == 0);
132
133 if (--prepare_refcnt)
134 return;
135 prepare_owner = NULL;
eab89f69
MT
136 mutex_unlock(&prepare_lock);
137}
138
139static unsigned long clk_enable_lock(void)
a57aa185 140 __acquires(enable_lock)
eab89f69
MT
141{
142 unsigned long flags;
533ddeb1
MT
143
144 if (!spin_trylock_irqsave(&enable_lock, flags)) {
145 if (enable_owner == current) {
146 enable_refcnt++;
a57aa185 147 __acquire(enable_lock);
533ddeb1
MT
148 return flags;
149 }
150 spin_lock_irqsave(&enable_lock, flags);
151 }
152 WARN_ON_ONCE(enable_owner != NULL);
153 WARN_ON_ONCE(enable_refcnt != 0);
154 enable_owner = current;
155 enable_refcnt = 1;
eab89f69
MT
156 return flags;
157}
158
159static void clk_enable_unlock(unsigned long flags)
a57aa185 160 __releases(enable_lock)
eab89f69 161{
533ddeb1
MT
162 WARN_ON_ONCE(enable_owner != current);
163 WARN_ON_ONCE(enable_refcnt == 0);
164
a57aa185
SB
165 if (--enable_refcnt) {
166 __release(enable_lock);
533ddeb1 167 return;
a57aa185 168 }
533ddeb1 169 enable_owner = NULL;
eab89f69
MT
170 spin_unlock_irqrestore(&enable_lock, flags);
171}
172
4dff95dc
SB
173static bool clk_core_is_prepared(struct clk_core *core)
174{
9a34b453
MS
175 bool ret = false;
176
4dff95dc
SB
177 /*
178 * .is_prepared is optional for clocks that can prepare
179 * fall back to software usage counter if it is missing
180 */
181 if (!core->ops->is_prepared)
182 return core->prepare_count;
b2476490 183
9a34b453
MS
184 if (!clk_pm_runtime_get(core)) {
185 ret = core->ops->is_prepared(core->hw);
186 clk_pm_runtime_put(core);
187 }
188
189 return ret;
4dff95dc 190}
b2476490 191
4dff95dc
SB
192static bool clk_core_is_enabled(struct clk_core *core)
193{
9a34b453
MS
194 bool ret = false;
195
4dff95dc
SB
196 /*
197 * .is_enabled is only mandatory for clocks that gate
198 * fall back to software usage counter if .is_enabled is missing
199 */
200 if (!core->ops->is_enabled)
201 return core->enable_count;
6b44c854 202
9a34b453
MS
203 /*
204 * Check if clock controller's device is runtime active before
205 * calling .is_enabled callback. If not, assume that clock is
206 * disabled, because we might be called from atomic context, from
207 * which pm_runtime_get() is not allowed.
208 * This function is called mainly from clk_disable_unused_subtree,
209 * which ensures proper runtime pm activation of controller before
210 * taking enable spinlock, but the below check is needed if one tries
211 * to call it from other places.
212 */
213 if (core->dev) {
214 pm_runtime_get_noresume(core->dev);
215 if (!pm_runtime_active(core->dev)) {
216 ret = false;
217 goto done;
218 }
219 }
220
221 ret = core->ops->is_enabled(core->hw);
222done:
756efe13
DA
223 if (core->dev)
224 pm_runtime_put(core->dev);
9a34b453
MS
225
226 return ret;
4dff95dc 227}
6b44c854 228
4dff95dc 229/*** helper functions ***/
1af599df 230
b76281cb 231const char *__clk_get_name(const struct clk *clk)
1af599df 232{
4dff95dc 233 return !clk ? NULL : clk->core->name;
1af599df 234}
4dff95dc 235EXPORT_SYMBOL_GPL(__clk_get_name);
1af599df 236
e7df6f6e 237const char *clk_hw_get_name(const struct clk_hw *hw)
1a9c069c
SB
238{
239 return hw->core->name;
240}
241EXPORT_SYMBOL_GPL(clk_hw_get_name);
242
4dff95dc
SB
243struct clk_hw *__clk_get_hw(struct clk *clk)
244{
245 return !clk ? NULL : clk->core->hw;
246}
247EXPORT_SYMBOL_GPL(__clk_get_hw);
1af599df 248
e7df6f6e 249unsigned int clk_hw_get_num_parents(const struct clk_hw *hw)
1a9c069c
SB
250{
251 return hw->core->num_parents;
252}
253EXPORT_SYMBOL_GPL(clk_hw_get_num_parents);
254
e7df6f6e 255struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw)
1a9c069c
SB
256{
257 return hw->core->parent ? hw->core->parent->hw : NULL;
258}
259EXPORT_SYMBOL_GPL(clk_hw_get_parent);
260
4dff95dc
SB
261static struct clk_core *__clk_lookup_subtree(const char *name,
262 struct clk_core *core)
bddca894 263{
035a61c3 264 struct clk_core *child;
4dff95dc 265 struct clk_core *ret;
bddca894 266
4dff95dc
SB
267 if (!strcmp(core->name, name))
268 return core;
bddca894 269
4dff95dc
SB
270 hlist_for_each_entry(child, &core->children, child_node) {
271 ret = __clk_lookup_subtree(name, child);
272 if (ret)
273 return ret;
bddca894
PG
274 }
275
4dff95dc 276 return NULL;
bddca894
PG
277}
278
4dff95dc 279static struct clk_core *clk_core_lookup(const char *name)
bddca894 280{
4dff95dc
SB
281 struct clk_core *root_clk;
282 struct clk_core *ret;
bddca894 283
4dff95dc
SB
284 if (!name)
285 return NULL;
bddca894 286
4dff95dc
SB
287 /* search the 'proper' clk tree first */
288 hlist_for_each_entry(root_clk, &clk_root_list, child_node) {
289 ret = __clk_lookup_subtree(name, root_clk);
290 if (ret)
291 return ret;
bddca894
PG
292 }
293
4dff95dc
SB
294 /* if not found, then search the orphan tree */
295 hlist_for_each_entry(root_clk, &clk_orphan_list, child_node) {
296 ret = __clk_lookup_subtree(name, root_clk);
297 if (ret)
298 return ret;
299 }
bddca894 300
4dff95dc 301 return NULL;
bddca894
PG
302}
303
4dff95dc
SB
304static struct clk_core *clk_core_get_parent_by_index(struct clk_core *core,
305 u8 index)
bddca894 306{
4dff95dc
SB
307 if (!core || index >= core->num_parents)
308 return NULL;
88cfbef2
MY
309
310 if (!core->parents[index])
311 core->parents[index] =
312 clk_core_lookup(core->parent_names[index]);
313
314 return core->parents[index];
bddca894
PG
315}
316
e7df6f6e
SB
317struct clk_hw *
318clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index)
1a9c069c
SB
319{
320 struct clk_core *parent;
321
322 parent = clk_core_get_parent_by_index(hw->core, index);
323
324 return !parent ? NULL : parent->hw;
325}
326EXPORT_SYMBOL_GPL(clk_hw_get_parent_by_index);
327
4dff95dc
SB
328unsigned int __clk_get_enable_count(struct clk *clk)
329{
330 return !clk ? 0 : clk->core->enable_count;
331}
b2476490 332
4dff95dc
SB
333static unsigned long clk_core_get_rate_nolock(struct clk_core *core)
334{
335 unsigned long ret;
b2476490 336
4dff95dc
SB
337 if (!core) {
338 ret = 0;
339 goto out;
340 }
b2476490 341
4dff95dc 342 ret = core->rate;
b2476490 343
47b0eeb3 344 if (!core->num_parents)
4dff95dc 345 goto out;
c646cbf1 346
4dff95dc
SB
347 if (!core->parent)
348 ret = 0;
b2476490 349
b2476490
MT
350out:
351 return ret;
352}
353
e7df6f6e 354unsigned long clk_hw_get_rate(const struct clk_hw *hw)
1a9c069c
SB
355{
356 return clk_core_get_rate_nolock(hw->core);
357}
358EXPORT_SYMBOL_GPL(clk_hw_get_rate);
359
4dff95dc
SB
360static unsigned long __clk_get_accuracy(struct clk_core *core)
361{
362 if (!core)
363 return 0;
b2476490 364
4dff95dc 365 return core->accuracy;
b2476490
MT
366}
367
4dff95dc 368unsigned long __clk_get_flags(struct clk *clk)
fcb0ee6a 369{
4dff95dc 370 return !clk ? 0 : clk->core->flags;
fcb0ee6a 371}
4dff95dc 372EXPORT_SYMBOL_GPL(__clk_get_flags);
fcb0ee6a 373
e7df6f6e 374unsigned long clk_hw_get_flags(const struct clk_hw *hw)
1a9c069c
SB
375{
376 return hw->core->flags;
377}
378EXPORT_SYMBOL_GPL(clk_hw_get_flags);
379
e7df6f6e 380bool clk_hw_is_prepared(const struct clk_hw *hw)
1a9c069c
SB
381{
382 return clk_core_is_prepared(hw->core);
383}
384
be68bf88
JE
385bool clk_hw_is_enabled(const struct clk_hw *hw)
386{
387 return clk_core_is_enabled(hw->core);
388}
389
4dff95dc 390bool __clk_is_enabled(struct clk *clk)
b2476490 391{
4dff95dc
SB
392 if (!clk)
393 return false;
b2476490 394
4dff95dc
SB
395 return clk_core_is_enabled(clk->core);
396}
397EXPORT_SYMBOL_GPL(__clk_is_enabled);
b2476490 398
4dff95dc
SB
399static bool mux_is_better_rate(unsigned long rate, unsigned long now,
400 unsigned long best, unsigned long flags)
401{
402 if (flags & CLK_MUX_ROUND_CLOSEST)
403 return abs(now - rate) < abs(best - rate);
1af599df 404
4dff95dc
SB
405 return now <= rate && now > best;
406}
bddca894 407
0817b62c
BB
408static int
409clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req,
4dff95dc
SB
410 unsigned long flags)
411{
412 struct clk_core *core = hw->core, *parent, *best_parent = NULL;
0817b62c
BB
413 int i, num_parents, ret;
414 unsigned long best = 0;
415 struct clk_rate_request parent_req = *req;
b2476490 416
4dff95dc
SB
417 /* if NO_REPARENT flag set, pass through to current parent */
418 if (core->flags & CLK_SET_RATE_NO_REPARENT) {
419 parent = core->parent;
0817b62c
BB
420 if (core->flags & CLK_SET_RATE_PARENT) {
421 ret = __clk_determine_rate(parent ? parent->hw : NULL,
422 &parent_req);
423 if (ret)
424 return ret;
425
426 best = parent_req.rate;
427 } else if (parent) {
4dff95dc 428 best = clk_core_get_rate_nolock(parent);
0817b62c 429 } else {
4dff95dc 430 best = clk_core_get_rate_nolock(core);
0817b62c
BB
431 }
432
4dff95dc
SB
433 goto out;
434 }
b2476490 435
4dff95dc
SB
436 /* find the parent that can provide the fastest rate <= rate */
437 num_parents = core->num_parents;
438 for (i = 0; i < num_parents; i++) {
439 parent = clk_core_get_parent_by_index(core, i);
440 if (!parent)
441 continue;
0817b62c
BB
442
443 if (core->flags & CLK_SET_RATE_PARENT) {
444 parent_req = *req;
445 ret = __clk_determine_rate(parent->hw, &parent_req);
446 if (ret)
447 continue;
448 } else {
449 parent_req.rate = clk_core_get_rate_nolock(parent);
450 }
451
452 if (mux_is_better_rate(req->rate, parent_req.rate,
453 best, flags)) {
4dff95dc 454 best_parent = parent;
0817b62c 455 best = parent_req.rate;
4dff95dc
SB
456 }
457 }
b2476490 458
57d866e6
BB
459 if (!best_parent)
460 return -EINVAL;
461
4dff95dc
SB
462out:
463 if (best_parent)
0817b62c
BB
464 req->best_parent_hw = best_parent->hw;
465 req->best_parent_rate = best;
466 req->rate = best;
b2476490 467
0817b62c 468 return 0;
b33d212f 469}
4dff95dc
SB
470
471struct clk *__clk_lookup(const char *name)
fcb0ee6a 472{
4dff95dc
SB
473 struct clk_core *core = clk_core_lookup(name);
474
475 return !core ? NULL : core->hw->clk;
fcb0ee6a 476}
b2476490 477
4dff95dc
SB
478static void clk_core_get_boundaries(struct clk_core *core,
479 unsigned long *min_rate,
480 unsigned long *max_rate)
1c155b3d 481{
4dff95dc 482 struct clk *clk_user;
1c155b3d 483
9783c0d9
SB
484 *min_rate = core->min_rate;
485 *max_rate = core->max_rate;
496eadf8 486
4dff95dc
SB
487 hlist_for_each_entry(clk_user, &core->clks, clks_node)
488 *min_rate = max(*min_rate, clk_user->min_rate);
1c155b3d 489
4dff95dc
SB
490 hlist_for_each_entry(clk_user, &core->clks, clks_node)
491 *max_rate = min(*max_rate, clk_user->max_rate);
492}
1c155b3d 493
9783c0d9
SB
494void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
495 unsigned long max_rate)
496{
497 hw->core->min_rate = min_rate;
498 hw->core->max_rate = max_rate;
499}
500EXPORT_SYMBOL_GPL(clk_hw_set_rate_range);
501
4dff95dc
SB
502/*
503 * Helper for finding best parent to provide a given frequency. This can be used
504 * directly as a determine_rate callback (e.g. for a mux), or from a more
505 * complex clock that may combine a mux with other operations.
506 */
0817b62c
BB
507int __clk_mux_determine_rate(struct clk_hw *hw,
508 struct clk_rate_request *req)
4dff95dc 509{
0817b62c 510 return clk_mux_determine_rate_flags(hw, req, 0);
1c155b3d 511}
4dff95dc 512EXPORT_SYMBOL_GPL(__clk_mux_determine_rate);
1c155b3d 513
0817b62c
BB
514int __clk_mux_determine_rate_closest(struct clk_hw *hw,
515 struct clk_rate_request *req)
b2476490 516{
0817b62c 517 return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST);
4dff95dc
SB
518}
519EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
b2476490 520
4dff95dc 521/*** clk api ***/
496eadf8 522
4dff95dc
SB
523static void clk_core_unprepare(struct clk_core *core)
524{
a6334725
SB
525 lockdep_assert_held(&prepare_lock);
526
4dff95dc
SB
527 if (!core)
528 return;
b2476490 529
4dff95dc
SB
530 if (WARN_ON(core->prepare_count == 0))
531 return;
b2476490 532
2e20fbf5
LJ
533 if (WARN_ON(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL))
534 return;
535
4dff95dc
SB
536 if (--core->prepare_count > 0)
537 return;
b2476490 538
4dff95dc 539 WARN_ON(core->enable_count > 0);
b2476490 540
4dff95dc 541 trace_clk_unprepare(core);
b2476490 542
4dff95dc
SB
543 if (core->ops->unprepare)
544 core->ops->unprepare(core->hw);
545
9a34b453
MS
546 clk_pm_runtime_put(core);
547
4dff95dc
SB
548 trace_clk_unprepare_complete(core);
549 clk_core_unprepare(core->parent);
b2476490
MT
550}
551
a6adc30b
DA
552static void clk_core_unprepare_lock(struct clk_core *core)
553{
554 clk_prepare_lock();
555 clk_core_unprepare(core);
556 clk_prepare_unlock();
557}
558
4dff95dc
SB
559/**
560 * clk_unprepare - undo preparation of a clock source
561 * @clk: the clk being unprepared
562 *
563 * clk_unprepare may sleep, which differentiates it from clk_disable. In a
564 * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
565 * if the operation may sleep. One example is a clk which is accessed over
566 * I2c. In the complex case a clk gate operation may require a fast and a slow
567 * part. It is this reason that clk_unprepare and clk_disable are not mutually
568 * exclusive. In fact clk_disable must be called before clk_unprepare.
569 */
570void clk_unprepare(struct clk *clk)
1e435256 571{
4dff95dc
SB
572 if (IS_ERR_OR_NULL(clk))
573 return;
574
a6adc30b 575 clk_core_unprepare_lock(clk->core);
1e435256 576}
4dff95dc 577EXPORT_SYMBOL_GPL(clk_unprepare);
1e435256 578
4dff95dc 579static int clk_core_prepare(struct clk_core *core)
b2476490 580{
4dff95dc 581 int ret = 0;
b2476490 582
a6334725
SB
583 lockdep_assert_held(&prepare_lock);
584
4dff95dc 585 if (!core)
1e435256 586 return 0;
1e435256 587
4dff95dc 588 if (core->prepare_count == 0) {
9a34b453 589 ret = clk_pm_runtime_get(core);
4dff95dc
SB
590 if (ret)
591 return ret;
b2476490 592
9a34b453
MS
593 ret = clk_core_prepare(core->parent);
594 if (ret)
595 goto runtime_put;
596
4dff95dc 597 trace_clk_prepare(core);
b2476490 598
4dff95dc
SB
599 if (core->ops->prepare)
600 ret = core->ops->prepare(core->hw);
b2476490 601
4dff95dc 602 trace_clk_prepare_complete(core);
1c155b3d 603
9a34b453
MS
604 if (ret)
605 goto unprepare;
4dff95dc 606 }
1c155b3d 607
4dff95dc 608 core->prepare_count++;
b2476490
MT
609
610 return 0;
9a34b453
MS
611unprepare:
612 clk_core_unprepare(core->parent);
613runtime_put:
614 clk_pm_runtime_put(core);
615 return ret;
b2476490 616}
b2476490 617
a6adc30b
DA
618static int clk_core_prepare_lock(struct clk_core *core)
619{
620 int ret;
621
622 clk_prepare_lock();
623 ret = clk_core_prepare(core);
624 clk_prepare_unlock();
625
626 return ret;
627}
628
4dff95dc
SB
629/**
630 * clk_prepare - prepare a clock source
631 * @clk: the clk being prepared
632 *
633 * clk_prepare may sleep, which differentiates it from clk_enable. In a simple
634 * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
635 * operation may sleep. One example is a clk which is accessed over I2c. In
636 * the complex case a clk ungate operation may require a fast and a slow part.
637 * It is this reason that clk_prepare and clk_enable are not mutually
638 * exclusive. In fact clk_prepare must be called before clk_enable.
639 * Returns 0 on success, -EERROR otherwise.
640 */
641int clk_prepare(struct clk *clk)
b2476490 642{
4dff95dc
SB
643 if (!clk)
644 return 0;
b2476490 645
a6adc30b 646 return clk_core_prepare_lock(clk->core);
b2476490 647}
4dff95dc 648EXPORT_SYMBOL_GPL(clk_prepare);
b2476490 649
4dff95dc 650static void clk_core_disable(struct clk_core *core)
b2476490 651{
a6334725
SB
652 lockdep_assert_held(&enable_lock);
653
4dff95dc
SB
654 if (!core)
655 return;
035a61c3 656
4dff95dc
SB
657 if (WARN_ON(core->enable_count == 0))
658 return;
b2476490 659
2e20fbf5
LJ
660 if (WARN_ON(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL))
661 return;
662
4dff95dc
SB
663 if (--core->enable_count > 0)
664 return;
035a61c3 665
2f87a6ea 666 trace_clk_disable_rcuidle(core);
035a61c3 667
4dff95dc
SB
668 if (core->ops->disable)
669 core->ops->disable(core->hw);
035a61c3 670
2f87a6ea 671 trace_clk_disable_complete_rcuidle(core);
035a61c3 672
4dff95dc 673 clk_core_disable(core->parent);
035a61c3 674}
7ef3dcc8 675
a6adc30b
DA
676static void clk_core_disable_lock(struct clk_core *core)
677{
678 unsigned long flags;
679
680 flags = clk_enable_lock();
681 clk_core_disable(core);
682 clk_enable_unlock(flags);
683}
684
4dff95dc
SB
685/**
686 * clk_disable - gate a clock
687 * @clk: the clk being gated
688 *
689 * clk_disable must not sleep, which differentiates it from clk_unprepare. In
690 * a simple case, clk_disable can be used instead of clk_unprepare to gate a
691 * clk if the operation is fast and will never sleep. One example is a
692 * SoC-internal clk which is controlled via simple register writes. In the
693 * complex case a clk gate operation may require a fast and a slow part. It is
694 * this reason that clk_unprepare and clk_disable are not mutually exclusive.
695 * In fact clk_disable must be called before clk_unprepare.
696 */
697void clk_disable(struct clk *clk)
b2476490 698{
4dff95dc
SB
699 if (IS_ERR_OR_NULL(clk))
700 return;
701
a6adc30b 702 clk_core_disable_lock(clk->core);
b2476490 703}
4dff95dc 704EXPORT_SYMBOL_GPL(clk_disable);
b2476490 705
4dff95dc 706static int clk_core_enable(struct clk_core *core)
b2476490 707{
4dff95dc 708 int ret = 0;
b2476490 709
a6334725
SB
710 lockdep_assert_held(&enable_lock);
711
4dff95dc
SB
712 if (!core)
713 return 0;
b2476490 714
4dff95dc
SB
715 if (WARN_ON(core->prepare_count == 0))
716 return -ESHUTDOWN;
b2476490 717
4dff95dc
SB
718 if (core->enable_count == 0) {
719 ret = clk_core_enable(core->parent);
b2476490 720
4dff95dc
SB
721 if (ret)
722 return ret;
b2476490 723
f17a0dd1 724 trace_clk_enable_rcuidle(core);
035a61c3 725
4dff95dc
SB
726 if (core->ops->enable)
727 ret = core->ops->enable(core->hw);
035a61c3 728
f17a0dd1 729 trace_clk_enable_complete_rcuidle(core);
4dff95dc
SB
730
731 if (ret) {
732 clk_core_disable(core->parent);
733 return ret;
734 }
735 }
736
737 core->enable_count++;
738 return 0;
035a61c3 739}
b2476490 740
a6adc30b
DA
741static int clk_core_enable_lock(struct clk_core *core)
742{
743 unsigned long flags;
744 int ret;
745
746 flags = clk_enable_lock();
747 ret = clk_core_enable(core);
748 clk_enable_unlock(flags);
749
750 return ret;
751}
752
4dff95dc
SB
753/**
754 * clk_enable - ungate a clock
755 * @clk: the clk being ungated
756 *
757 * clk_enable must not sleep, which differentiates it from clk_prepare. In a
758 * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
759 * if the operation will never sleep. One example is a SoC-internal clk which
760 * is controlled via simple register writes. In the complex case a clk ungate
761 * operation may require a fast and a slow part. It is this reason that
762 * clk_enable and clk_prepare are not mutually exclusive. In fact clk_prepare
763 * must be called before clk_enable. Returns 0 on success, -EERROR
764 * otherwise.
765 */
766int clk_enable(struct clk *clk)
5279fc40 767{
4dff95dc 768 if (!clk)
5279fc40
BB
769 return 0;
770
a6adc30b
DA
771 return clk_core_enable_lock(clk->core);
772}
773EXPORT_SYMBOL_GPL(clk_enable);
774
775static int clk_core_prepare_enable(struct clk_core *core)
776{
777 int ret;
778
779 ret = clk_core_prepare_lock(core);
780 if (ret)
781 return ret;
782
783 ret = clk_core_enable_lock(core);
784 if (ret)
785 clk_core_unprepare_lock(core);
5279fc40 786
4dff95dc 787 return ret;
b2476490 788}
a6adc30b
DA
789
790static void clk_core_disable_unprepare(struct clk_core *core)
791{
792 clk_core_disable_lock(core);
793 clk_core_unprepare_lock(core);
794}
b2476490 795
7ec986ef
DA
796static void clk_unprepare_unused_subtree(struct clk_core *core)
797{
798 struct clk_core *child;
799
800 lockdep_assert_held(&prepare_lock);
801
802 hlist_for_each_entry(child, &core->children, child_node)
803 clk_unprepare_unused_subtree(child);
804
805 if (core->prepare_count)
806 return;
807
808 if (core->flags & CLK_IGNORE_UNUSED)
809 return;
810
9a34b453
MS
811 if (clk_pm_runtime_get(core))
812 return;
813
7ec986ef
DA
814 if (clk_core_is_prepared(core)) {
815 trace_clk_unprepare(core);
816 if (core->ops->unprepare_unused)
817 core->ops->unprepare_unused(core->hw);
818 else if (core->ops->unprepare)
819 core->ops->unprepare(core->hw);
820 trace_clk_unprepare_complete(core);
821 }
9a34b453
MS
822
823 clk_pm_runtime_put(core);
7ec986ef
DA
824}
825
826static void clk_disable_unused_subtree(struct clk_core *core)
827{
828 struct clk_core *child;
829 unsigned long flags;
830
831 lockdep_assert_held(&prepare_lock);
832
833 hlist_for_each_entry(child, &core->children, child_node)
834 clk_disable_unused_subtree(child);
835
a4b3518d
DA
836 if (core->flags & CLK_OPS_PARENT_ENABLE)
837 clk_core_prepare_enable(core->parent);
838
9a34b453
MS
839 if (clk_pm_runtime_get(core))
840 goto unprepare_out;
841
7ec986ef
DA
842 flags = clk_enable_lock();
843
844 if (core->enable_count)
845 goto unlock_out;
846
847 if (core->flags & CLK_IGNORE_UNUSED)
848 goto unlock_out;
849
850 /*
851 * some gate clocks have special needs during the disable-unused
852 * sequence. call .disable_unused if available, otherwise fall
853 * back to .disable
854 */
855 if (clk_core_is_enabled(core)) {
856 trace_clk_disable(core);
857 if (core->ops->disable_unused)
858 core->ops->disable_unused(core->hw);
859 else if (core->ops->disable)
860 core->ops->disable(core->hw);
861 trace_clk_disable_complete(core);
862 }
863
864unlock_out:
865 clk_enable_unlock(flags);
9a34b453
MS
866 clk_pm_runtime_put(core);
867unprepare_out:
a4b3518d
DA
868 if (core->flags & CLK_OPS_PARENT_ENABLE)
869 clk_core_disable_unprepare(core->parent);
7ec986ef
DA
870}
871
872static bool clk_ignore_unused;
873static int __init clk_ignore_unused_setup(char *__unused)
874{
875 clk_ignore_unused = true;
876 return 1;
877}
878__setup("clk_ignore_unused", clk_ignore_unused_setup);
879
880static int clk_disable_unused(void)
881{
882 struct clk_core *core;
883
884 if (clk_ignore_unused) {
885 pr_warn("clk: Not disabling unused clocks\n");
886 return 0;
887 }
888
889 clk_prepare_lock();
890
891 hlist_for_each_entry(core, &clk_root_list, child_node)
892 clk_disable_unused_subtree(core);
893
894 hlist_for_each_entry(core, &clk_orphan_list, child_node)
895 clk_disable_unused_subtree(core);
896
897 hlist_for_each_entry(core, &clk_root_list, child_node)
898 clk_unprepare_unused_subtree(core);
899
900 hlist_for_each_entry(core, &clk_orphan_list, child_node)
901 clk_unprepare_unused_subtree(core);
902
903 clk_prepare_unlock();
904
905 return 0;
906}
907late_initcall_sync(clk_disable_unused);
908
0817b62c
BB
909static int clk_core_round_rate_nolock(struct clk_core *core,
910 struct clk_rate_request *req)
3d6ee287 911{
4dff95dc 912 struct clk_core *parent;
0817b62c 913 long rate;
4dff95dc
SB
914
915 lockdep_assert_held(&prepare_lock);
3d6ee287 916
d6968fca 917 if (!core)
4dff95dc 918 return 0;
3d6ee287 919
4dff95dc 920 parent = core->parent;
0817b62c
BB
921 if (parent) {
922 req->best_parent_hw = parent->hw;
923 req->best_parent_rate = parent->rate;
924 } else {
925 req->best_parent_hw = NULL;
926 req->best_parent_rate = 0;
927 }
3d6ee287 928
4dff95dc 929 if (core->ops->determine_rate) {
0817b62c
BB
930 return core->ops->determine_rate(core->hw, req);
931 } else if (core->ops->round_rate) {
932 rate = core->ops->round_rate(core->hw, req->rate,
933 &req->best_parent_rate);
934 if (rate < 0)
935 return rate;
936
937 req->rate = rate;
938 } else if (core->flags & CLK_SET_RATE_PARENT) {
939 return clk_core_round_rate_nolock(parent, req);
940 } else {
941 req->rate = core->rate;
942 }
943
944 return 0;
3d6ee287
UH
945}
946
4dff95dc
SB
947/**
948 * __clk_determine_rate - get the closest rate actually supported by a clock
949 * @hw: determine the rate of this clock
2d5b520c 950 * @req: target rate request
4dff95dc 951 *
6e5ab41b 952 * Useful for clk_ops such as .set_rate and .determine_rate.
4dff95dc 953 */
0817b62c 954int __clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
035a61c3 955{
0817b62c
BB
956 if (!hw) {
957 req->rate = 0;
4dff95dc 958 return 0;
0817b62c 959 }
035a61c3 960
0817b62c 961 return clk_core_round_rate_nolock(hw->core, req);
035a61c3 962}
4dff95dc 963EXPORT_SYMBOL_GPL(__clk_determine_rate);
035a61c3 964
1a9c069c
SB
965unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate)
966{
967 int ret;
968 struct clk_rate_request req;
969
970 clk_core_get_boundaries(hw->core, &req.min_rate, &req.max_rate);
971 req.rate = rate;
972
973 ret = clk_core_round_rate_nolock(hw->core, &req);
974 if (ret)
975 return 0;
976
977 return req.rate;
978}
979EXPORT_SYMBOL_GPL(clk_hw_round_rate);
980
4dff95dc
SB
981/**
982 * clk_round_rate - round the given rate for a clk
983 * @clk: the clk for which we are rounding a rate
984 * @rate: the rate which is to be rounded
985 *
986 * Takes in a rate as input and rounds it to a rate that the clk can actually
987 * use which is then returned. If clk doesn't support round_rate operation
988 * then the parent rate is returned.
989 */
990long clk_round_rate(struct clk *clk, unsigned long rate)
035a61c3 991{
fc4a05d4
SB
992 struct clk_rate_request req;
993 int ret;
4dff95dc 994
035a61c3 995 if (!clk)
4dff95dc 996 return 0;
035a61c3 997
4dff95dc 998 clk_prepare_lock();
fc4a05d4
SB
999
1000 clk_core_get_boundaries(clk->core, &req.min_rate, &req.max_rate);
1001 req.rate = rate;
1002
1003 ret = clk_core_round_rate_nolock(clk->core, &req);
4dff95dc
SB
1004 clk_prepare_unlock();
1005
fc4a05d4
SB
1006 if (ret)
1007 return ret;
1008
1009 return req.rate;
035a61c3 1010}
4dff95dc 1011EXPORT_SYMBOL_GPL(clk_round_rate);
b2476490 1012
4dff95dc
SB
1013/**
1014 * __clk_notify - call clk notifier chain
1015 * @core: clk that is changing rate
1016 * @msg: clk notifier type (see include/linux/clk.h)
1017 * @old_rate: old clk rate
1018 * @new_rate: new clk rate
1019 *
1020 * Triggers a notifier call chain on the clk rate-change notification
1021 * for 'clk'. Passes a pointer to the struct clk and the previous
1022 * and current rates to the notifier callback. Intended to be called by
1023 * internal clock code only. Returns NOTIFY_DONE from the last driver
1024 * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
1025 * a driver returns that.
1026 */
1027static int __clk_notify(struct clk_core *core, unsigned long msg,
1028 unsigned long old_rate, unsigned long new_rate)
b2476490 1029{
4dff95dc
SB
1030 struct clk_notifier *cn;
1031 struct clk_notifier_data cnd;
1032 int ret = NOTIFY_DONE;
b2476490 1033
4dff95dc
SB
1034 cnd.old_rate = old_rate;
1035 cnd.new_rate = new_rate;
b2476490 1036
4dff95dc
SB
1037 list_for_each_entry(cn, &clk_notifier_list, node) {
1038 if (cn->clk->core == core) {
1039 cnd.clk = cn->clk;
1040 ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
1041 &cnd);
17c34c56
PDS
1042 if (ret & NOTIFY_STOP_MASK)
1043 return ret;
4dff95dc 1044 }
b2476490
MT
1045 }
1046
4dff95dc 1047 return ret;
b2476490
MT
1048}
1049
4dff95dc
SB
1050/**
1051 * __clk_recalc_accuracies
1052 * @core: first clk in the subtree
1053 *
1054 * Walks the subtree of clks starting with clk and recalculates accuracies as
1055 * it goes. Note that if a clk does not implement the .recalc_accuracy
6e5ab41b 1056 * callback then it is assumed that the clock will take on the accuracy of its
4dff95dc 1057 * parent.
4dff95dc
SB
1058 */
1059static void __clk_recalc_accuracies(struct clk_core *core)
b2476490 1060{
4dff95dc
SB
1061 unsigned long parent_accuracy = 0;
1062 struct clk_core *child;
b2476490 1063
4dff95dc 1064 lockdep_assert_held(&prepare_lock);
b2476490 1065
4dff95dc
SB
1066 if (core->parent)
1067 parent_accuracy = core->parent->accuracy;
b2476490 1068
4dff95dc
SB
1069 if (core->ops->recalc_accuracy)
1070 core->accuracy = core->ops->recalc_accuracy(core->hw,
1071 parent_accuracy);
1072 else
1073 core->accuracy = parent_accuracy;
b2476490 1074
4dff95dc
SB
1075 hlist_for_each_entry(child, &core->children, child_node)
1076 __clk_recalc_accuracies(child);
b2476490
MT
1077}
1078
4dff95dc 1079static long clk_core_get_accuracy(struct clk_core *core)
e366fdd7 1080{
4dff95dc 1081 unsigned long accuracy;
15a02c1f 1082
4dff95dc
SB
1083 clk_prepare_lock();
1084 if (core && (core->flags & CLK_GET_ACCURACY_NOCACHE))
1085 __clk_recalc_accuracies(core);
15a02c1f 1086
4dff95dc
SB
1087 accuracy = __clk_get_accuracy(core);
1088 clk_prepare_unlock();
e366fdd7 1089
4dff95dc 1090 return accuracy;
e366fdd7 1091}
15a02c1f 1092
4dff95dc
SB
1093/**
1094 * clk_get_accuracy - return the accuracy of clk
1095 * @clk: the clk whose accuracy is being returned
1096 *
1097 * Simply returns the cached accuracy of the clk, unless
1098 * CLK_GET_ACCURACY_NOCACHE flag is set, which means a recalc_rate will be
1099 * issued.
1100 * If clk is NULL then returns 0.
1101 */
1102long clk_get_accuracy(struct clk *clk)
035a61c3 1103{
4dff95dc
SB
1104 if (!clk)
1105 return 0;
035a61c3 1106
4dff95dc 1107 return clk_core_get_accuracy(clk->core);
035a61c3 1108}
4dff95dc 1109EXPORT_SYMBOL_GPL(clk_get_accuracy);
035a61c3 1110
4dff95dc
SB
1111static unsigned long clk_recalc(struct clk_core *core,
1112 unsigned long parent_rate)
1c8e6004 1113{
9a34b453
MS
1114 unsigned long rate = parent_rate;
1115
1116 if (core->ops->recalc_rate && !clk_pm_runtime_get(core)) {
1117 rate = core->ops->recalc_rate(core->hw, parent_rate);
1118 clk_pm_runtime_put(core);
1119 }
1120 return rate;
1c8e6004
TV
1121}
1122
4dff95dc
SB
1123/**
1124 * __clk_recalc_rates
1125 * @core: first clk in the subtree
1126 * @msg: notification type (see include/linux/clk.h)
1127 *
1128 * Walks the subtree of clks starting with clk and recalculates rates as it
1129 * goes. Note that if a clk does not implement the .recalc_rate callback then
1130 * it is assumed that the clock will take on the rate of its parent.
1131 *
1132 * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
1133 * if necessary.
15a02c1f 1134 */
4dff95dc 1135static void __clk_recalc_rates(struct clk_core *core, unsigned long msg)
15a02c1f 1136{
4dff95dc
SB
1137 unsigned long old_rate;
1138 unsigned long parent_rate = 0;
1139 struct clk_core *child;
e366fdd7 1140
4dff95dc 1141 lockdep_assert_held(&prepare_lock);
15a02c1f 1142
4dff95dc 1143 old_rate = core->rate;
b2476490 1144
4dff95dc
SB
1145 if (core->parent)
1146 parent_rate = core->parent->rate;
b2476490 1147
4dff95dc 1148 core->rate = clk_recalc(core, parent_rate);
b2476490 1149
4dff95dc
SB
1150 /*
1151 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
1152 * & ABORT_RATE_CHANGE notifiers
1153 */
1154 if (core->notifier_count && msg)
1155 __clk_notify(core, msg, old_rate, core->rate);
b2476490 1156
4dff95dc
SB
1157 hlist_for_each_entry(child, &core->children, child_node)
1158 __clk_recalc_rates(child, msg);
1159}
b2476490 1160
4dff95dc
SB
1161static unsigned long clk_core_get_rate(struct clk_core *core)
1162{
1163 unsigned long rate;
dfc202ea 1164
4dff95dc 1165 clk_prepare_lock();
b2476490 1166
4dff95dc
SB
1167 if (core && (core->flags & CLK_GET_RATE_NOCACHE))
1168 __clk_recalc_rates(core, 0);
1169
1170 rate = clk_core_get_rate_nolock(core);
1171 clk_prepare_unlock();
1172
1173 return rate;
b2476490
MT
1174}
1175
1176/**
4dff95dc
SB
1177 * clk_get_rate - return the rate of clk
1178 * @clk: the clk whose rate is being returned
b2476490 1179 *
4dff95dc
SB
1180 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1181 * is set, which means a recalc_rate will be issued.
1182 * If clk is NULL then returns 0.
b2476490 1183 */
4dff95dc 1184unsigned long clk_get_rate(struct clk *clk)
b2476490 1185{
4dff95dc
SB
1186 if (!clk)
1187 return 0;
63589e92 1188
4dff95dc 1189 return clk_core_get_rate(clk->core);
b2476490 1190}
4dff95dc 1191EXPORT_SYMBOL_GPL(clk_get_rate);
b2476490 1192
4dff95dc
SB
1193static int clk_fetch_parent_index(struct clk_core *core,
1194 struct clk_core *parent)
b2476490 1195{
4dff95dc 1196 int i;
b2476490 1197
508f884a
MY
1198 if (!parent)
1199 return -EINVAL;
1200
470b5e2f
MY
1201 for (i = 0; i < core->num_parents; i++)
1202 if (clk_core_get_parent_by_index(core, i) == parent)
4dff95dc 1203 return i;
b2476490 1204
4dff95dc 1205 return -EINVAL;
b2476490
MT
1206}
1207
e6500344
HS
1208/*
1209 * Update the orphan status of @core and all its children.
1210 */
1211static void clk_core_update_orphan_status(struct clk_core *core, bool is_orphan)
1212{
1213 struct clk_core *child;
1214
1215 core->orphan = is_orphan;
1216
1217 hlist_for_each_entry(child, &core->children, child_node)
1218 clk_core_update_orphan_status(child, is_orphan);
1219}
1220
4dff95dc 1221static void clk_reparent(struct clk_core *core, struct clk_core *new_parent)
b2476490 1222{
e6500344
HS
1223 bool was_orphan = core->orphan;
1224
4dff95dc 1225 hlist_del(&core->child_node);
035a61c3 1226
4dff95dc 1227 if (new_parent) {
e6500344
HS
1228 bool becomes_orphan = new_parent->orphan;
1229
4dff95dc
SB
1230 /* avoid duplicate POST_RATE_CHANGE notifications */
1231 if (new_parent->new_child == core)
1232 new_parent->new_child = NULL;
b2476490 1233
4dff95dc 1234 hlist_add_head(&core->child_node, &new_parent->children);
e6500344
HS
1235
1236 if (was_orphan != becomes_orphan)
1237 clk_core_update_orphan_status(core, becomes_orphan);
4dff95dc
SB
1238 } else {
1239 hlist_add_head(&core->child_node, &clk_orphan_list);
e6500344
HS
1240 if (!was_orphan)
1241 clk_core_update_orphan_status(core, true);
4dff95dc 1242 }
dfc202ea 1243
4dff95dc 1244 core->parent = new_parent;
035a61c3
TV
1245}
1246
4dff95dc
SB
1247static struct clk_core *__clk_set_parent_before(struct clk_core *core,
1248 struct clk_core *parent)
b2476490
MT
1249{
1250 unsigned long flags;
4dff95dc 1251 struct clk_core *old_parent = core->parent;
b2476490 1252
4dff95dc 1253 /*
fc8726a2
DA
1254 * 1. enable parents for CLK_OPS_PARENT_ENABLE clock
1255 *
1256 * 2. Migrate prepare state between parents and prevent race with
4dff95dc
SB
1257 * clk_enable().
1258 *
1259 * If the clock is not prepared, then a race with
1260 * clk_enable/disable() is impossible since we already have the
1261 * prepare lock (future calls to clk_enable() need to be preceded by
1262 * a clk_prepare()).
1263 *
1264 * If the clock is prepared, migrate the prepared state to the new
1265 * parent and also protect against a race with clk_enable() by
1266 * forcing the clock and the new parent on. This ensures that all
1267 * future calls to clk_enable() are practically NOPs with respect to
1268 * hardware and software states.
1269 *
1270 * See also: Comment for clk_set_parent() below.
1271 */
fc8726a2
DA
1272
1273 /* enable old_parent & parent if CLK_OPS_PARENT_ENABLE is set */
1274 if (core->flags & CLK_OPS_PARENT_ENABLE) {
1275 clk_core_prepare_enable(old_parent);
1276 clk_core_prepare_enable(parent);
1277 }
1278
1279 /* migrate prepare count if > 0 */
4dff95dc 1280 if (core->prepare_count) {
fc8726a2
DA
1281 clk_core_prepare_enable(parent);
1282 clk_core_enable_lock(core);
4dff95dc 1283 }
63589e92 1284
4dff95dc 1285 /* update the clk tree topology */
eab89f69 1286 flags = clk_enable_lock();
4dff95dc 1287 clk_reparent(core, parent);
eab89f69 1288 clk_enable_unlock(flags);
4dff95dc
SB
1289
1290 return old_parent;
b2476490 1291}
b2476490 1292
4dff95dc
SB
1293static void __clk_set_parent_after(struct clk_core *core,
1294 struct clk_core *parent,
1295 struct clk_core *old_parent)
b2476490 1296{
4dff95dc
SB
1297 /*
1298 * Finish the migration of prepare state and undo the changes done
1299 * for preventing a race with clk_enable().
1300 */
1301 if (core->prepare_count) {
fc8726a2
DA
1302 clk_core_disable_lock(core);
1303 clk_core_disable_unprepare(old_parent);
1304 }
1305
1306 /* re-balance ref counting if CLK_OPS_PARENT_ENABLE is set */
1307 if (core->flags & CLK_OPS_PARENT_ENABLE) {
1308 clk_core_disable_unprepare(parent);
1309 clk_core_disable_unprepare(old_parent);
4dff95dc
SB
1310 }
1311}
b2476490 1312
4dff95dc
SB
1313static int __clk_set_parent(struct clk_core *core, struct clk_core *parent,
1314 u8 p_index)
1315{
1316 unsigned long flags;
1317 int ret = 0;
1318 struct clk_core *old_parent;
b2476490 1319
4dff95dc 1320 old_parent = __clk_set_parent_before(core, parent);
b2476490 1321
4dff95dc 1322 trace_clk_set_parent(core, parent);
b2476490 1323
4dff95dc
SB
1324 /* change clock input source */
1325 if (parent && core->ops->set_parent)
1326 ret = core->ops->set_parent(core->hw, p_index);
dfc202ea 1327
4dff95dc 1328 trace_clk_set_parent_complete(core, parent);
dfc202ea 1329
4dff95dc
SB
1330 if (ret) {
1331 flags = clk_enable_lock();
1332 clk_reparent(core, old_parent);
1333 clk_enable_unlock(flags);
c660b2eb 1334 __clk_set_parent_after(core, old_parent, parent);
dfc202ea 1335
4dff95dc 1336 return ret;
b2476490
MT
1337 }
1338
4dff95dc
SB
1339 __clk_set_parent_after(core, parent, old_parent);
1340
b2476490
MT
1341 return 0;
1342}
1343
1344/**
4dff95dc
SB
1345 * __clk_speculate_rates
1346 * @core: first clk in the subtree
1347 * @parent_rate: the "future" rate of clk's parent
b2476490 1348 *
4dff95dc
SB
1349 * Walks the subtree of clks starting with clk, speculating rates as it
1350 * goes and firing off PRE_RATE_CHANGE notifications as necessary.
1351 *
1352 * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
1353 * pre-rate change notifications and returns early if no clks in the
1354 * subtree have subscribed to the notifications. Note that if a clk does not
1355 * implement the .recalc_rate callback then it is assumed that the clock will
1356 * take on the rate of its parent.
b2476490 1357 */
4dff95dc
SB
1358static int __clk_speculate_rates(struct clk_core *core,
1359 unsigned long parent_rate)
b2476490 1360{
4dff95dc
SB
1361 struct clk_core *child;
1362 unsigned long new_rate;
1363 int ret = NOTIFY_DONE;
b2476490 1364
4dff95dc 1365 lockdep_assert_held(&prepare_lock);
864e160a 1366
4dff95dc
SB
1367 new_rate = clk_recalc(core, parent_rate);
1368
1369 /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */
1370 if (core->notifier_count)
1371 ret = __clk_notify(core, PRE_RATE_CHANGE, core->rate, new_rate);
1372
1373 if (ret & NOTIFY_STOP_MASK) {
1374 pr_debug("%s: clk notifier callback for clock %s aborted with error %d\n",
1375 __func__, core->name, ret);
1376 goto out;
1377 }
1378
1379 hlist_for_each_entry(child, &core->children, child_node) {
1380 ret = __clk_speculate_rates(child, new_rate);
1381 if (ret & NOTIFY_STOP_MASK)
1382 break;
1383 }
b2476490 1384
4dff95dc 1385out:
b2476490
MT
1386 return ret;
1387}
b2476490 1388
4dff95dc
SB
1389static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate,
1390 struct clk_core *new_parent, u8 p_index)
b2476490 1391{
4dff95dc 1392 struct clk_core *child;
b2476490 1393
4dff95dc
SB
1394 core->new_rate = new_rate;
1395 core->new_parent = new_parent;
1396 core->new_parent_index = p_index;
1397 /* include clk in new parent's PRE_RATE_CHANGE notifications */
1398 core->new_child = NULL;
1399 if (new_parent && new_parent != core->parent)
1400 new_parent->new_child = core;
496eadf8 1401
4dff95dc
SB
1402 hlist_for_each_entry(child, &core->children, child_node) {
1403 child->new_rate = clk_recalc(child, new_rate);
1404 clk_calc_subtree(child, child->new_rate, NULL, 0);
1405 }
1406}
b2476490 1407
4dff95dc
SB
1408/*
1409 * calculate the new rates returning the topmost clock that has to be
1410 * changed.
1411 */
1412static struct clk_core *clk_calc_new_rates(struct clk_core *core,
1413 unsigned long rate)
1414{
1415 struct clk_core *top = core;
1416 struct clk_core *old_parent, *parent;
4dff95dc
SB
1417 unsigned long best_parent_rate = 0;
1418 unsigned long new_rate;
1419 unsigned long min_rate;
1420 unsigned long max_rate;
1421 int p_index = 0;
1422 long ret;
1423
1424 /* sanity */
1425 if (IS_ERR_OR_NULL(core))
1426 return NULL;
1427
1428 /* save parent rate, if it exists */
1429 parent = old_parent = core->parent;
71472c0c 1430 if (parent)
4dff95dc 1431 best_parent_rate = parent->rate;
71472c0c 1432
4dff95dc
SB
1433 clk_core_get_boundaries(core, &min_rate, &max_rate);
1434
1435 /* find the closest rate and parent clk/rate */
d6968fca 1436 if (core->ops->determine_rate) {
0817b62c
BB
1437 struct clk_rate_request req;
1438
1439 req.rate = rate;
1440 req.min_rate = min_rate;
1441 req.max_rate = max_rate;
1442 if (parent) {
1443 req.best_parent_hw = parent->hw;
1444 req.best_parent_rate = parent->rate;
1445 } else {
1446 req.best_parent_hw = NULL;
1447 req.best_parent_rate = 0;
1448 }
1449
1450 ret = core->ops->determine_rate(core->hw, &req);
4dff95dc
SB
1451 if (ret < 0)
1452 return NULL;
1c8e6004 1453
0817b62c
BB
1454 best_parent_rate = req.best_parent_rate;
1455 new_rate = req.rate;
1456 parent = req.best_parent_hw ? req.best_parent_hw->core : NULL;
4dff95dc
SB
1457 } else if (core->ops->round_rate) {
1458 ret = core->ops->round_rate(core->hw, rate,
0817b62c 1459 &best_parent_rate);
4dff95dc
SB
1460 if (ret < 0)
1461 return NULL;
035a61c3 1462
4dff95dc
SB
1463 new_rate = ret;
1464 if (new_rate < min_rate || new_rate > max_rate)
1465 return NULL;
1466 } else if (!parent || !(core->flags & CLK_SET_RATE_PARENT)) {
1467 /* pass-through clock without adjustable parent */
1468 core->new_rate = core->rate;
1469 return NULL;
1470 } else {
1471 /* pass-through clock with adjustable parent */
1472 top = clk_calc_new_rates(parent, rate);
1473 new_rate = parent->new_rate;
1474 goto out;
1475 }
1c8e6004 1476
4dff95dc
SB
1477 /* some clocks must be gated to change parent */
1478 if (parent != old_parent &&
1479 (core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
1480 pr_debug("%s: %s not gated but wants to reparent\n",
1481 __func__, core->name);
1482 return NULL;
1483 }
b2476490 1484
4dff95dc
SB
1485 /* try finding the new parent index */
1486 if (parent && core->num_parents > 1) {
1487 p_index = clk_fetch_parent_index(core, parent);
1488 if (p_index < 0) {
1489 pr_debug("%s: clk %s can not be parent of clk %s\n",
1490 __func__, parent->name, core->name);
1491 return NULL;
1492 }
1493 }
b2476490 1494
4dff95dc
SB
1495 if ((core->flags & CLK_SET_RATE_PARENT) && parent &&
1496 best_parent_rate != parent->rate)
1497 top = clk_calc_new_rates(parent, best_parent_rate);
035a61c3 1498
4dff95dc
SB
1499out:
1500 clk_calc_subtree(core, new_rate, parent, p_index);
b2476490 1501
4dff95dc 1502 return top;
b2476490 1503}
b2476490 1504
4dff95dc
SB
1505/*
1506 * Notify about rate changes in a subtree. Always walk down the whole tree
1507 * so that in case of an error we can walk down the whole tree again and
1508 * abort the change.
b2476490 1509 */
4dff95dc
SB
1510static struct clk_core *clk_propagate_rate_change(struct clk_core *core,
1511 unsigned long event)
b2476490 1512{
4dff95dc 1513 struct clk_core *child, *tmp_clk, *fail_clk = NULL;
b2476490
MT
1514 int ret = NOTIFY_DONE;
1515
4dff95dc
SB
1516 if (core->rate == core->new_rate)
1517 return NULL;
b2476490 1518
4dff95dc
SB
1519 if (core->notifier_count) {
1520 ret = __clk_notify(core, event, core->rate, core->new_rate);
1521 if (ret & NOTIFY_STOP_MASK)
1522 fail_clk = core;
b2476490
MT
1523 }
1524
4dff95dc
SB
1525 hlist_for_each_entry(child, &core->children, child_node) {
1526 /* Skip children who will be reparented to another clock */
1527 if (child->new_parent && child->new_parent != core)
1528 continue;
1529 tmp_clk = clk_propagate_rate_change(child, event);
1530 if (tmp_clk)
1531 fail_clk = tmp_clk;
1532 }
5279fc40 1533
4dff95dc
SB
1534 /* handle the new child who might not be in core->children yet */
1535 if (core->new_child) {
1536 tmp_clk = clk_propagate_rate_change(core->new_child, event);
1537 if (tmp_clk)
1538 fail_clk = tmp_clk;
1539 }
5279fc40 1540
4dff95dc 1541 return fail_clk;
5279fc40
BB
1542}
1543
4dff95dc
SB
1544/*
1545 * walk down a subtree and set the new rates notifying the rate
1546 * change on the way
1547 */
1548static void clk_change_rate(struct clk_core *core)
035a61c3 1549{
4dff95dc
SB
1550 struct clk_core *child;
1551 struct hlist_node *tmp;
1552 unsigned long old_rate;
1553 unsigned long best_parent_rate = 0;
1554 bool skip_set_rate = false;
1555 struct clk_core *old_parent;
fc8726a2 1556 struct clk_core *parent = NULL;
035a61c3 1557
4dff95dc 1558 old_rate = core->rate;
035a61c3 1559
fc8726a2
DA
1560 if (core->new_parent) {
1561 parent = core->new_parent;
4dff95dc 1562 best_parent_rate = core->new_parent->rate;
fc8726a2
DA
1563 } else if (core->parent) {
1564 parent = core->parent;
4dff95dc 1565 best_parent_rate = core->parent->rate;
fc8726a2 1566 }
035a61c3 1567
588fb54b
MS
1568 if (clk_pm_runtime_get(core))
1569 return;
1570
2eb8c710
HS
1571 if (core->flags & CLK_SET_RATE_UNGATE) {
1572 unsigned long flags;
1573
1574 clk_core_prepare(core);
1575 flags = clk_enable_lock();
1576 clk_core_enable(core);
1577 clk_enable_unlock(flags);
1578 }
1579
4dff95dc
SB
1580 if (core->new_parent && core->new_parent != core->parent) {
1581 old_parent = __clk_set_parent_before(core, core->new_parent);
1582 trace_clk_set_parent(core, core->new_parent);
5279fc40 1583
4dff95dc
SB
1584 if (core->ops->set_rate_and_parent) {
1585 skip_set_rate = true;
1586 core->ops->set_rate_and_parent(core->hw, core->new_rate,
1587 best_parent_rate,
1588 core->new_parent_index);
1589 } else if (core->ops->set_parent) {
1590 core->ops->set_parent(core->hw, core->new_parent_index);
1591 }
5279fc40 1592
4dff95dc
SB
1593 trace_clk_set_parent_complete(core, core->new_parent);
1594 __clk_set_parent_after(core, core->new_parent, old_parent);
1595 }
8f2c2db1 1596
fc8726a2
DA
1597 if (core->flags & CLK_OPS_PARENT_ENABLE)
1598 clk_core_prepare_enable(parent);
1599
4dff95dc 1600 trace_clk_set_rate(core, core->new_rate);
b2476490 1601
4dff95dc
SB
1602 if (!skip_set_rate && core->ops->set_rate)
1603 core->ops->set_rate(core->hw, core->new_rate, best_parent_rate);
496eadf8 1604
4dff95dc 1605 trace_clk_set_rate_complete(core, core->new_rate);
b2476490 1606
4dff95dc 1607 core->rate = clk_recalc(core, best_parent_rate);
b2476490 1608
2eb8c710
HS
1609 if (core->flags & CLK_SET_RATE_UNGATE) {
1610 unsigned long flags;
1611
1612 flags = clk_enable_lock();
1613 clk_core_disable(core);
1614 clk_enable_unlock(flags);
1615 clk_core_unprepare(core);
1616 }
1617
fc8726a2
DA
1618 if (core->flags & CLK_OPS_PARENT_ENABLE)
1619 clk_core_disable_unprepare(parent);
1620
4dff95dc
SB
1621 if (core->notifier_count && old_rate != core->rate)
1622 __clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate);
b2476490 1623
85e88fab
MT
1624 if (core->flags & CLK_RECALC_NEW_RATES)
1625 (void)clk_calc_new_rates(core, core->new_rate);
d8d91987 1626
b2476490 1627 /*
4dff95dc
SB
1628 * Use safe iteration, as change_rate can actually swap parents
1629 * for certain clock types.
b2476490 1630 */
4dff95dc
SB
1631 hlist_for_each_entry_safe(child, tmp, &core->children, child_node) {
1632 /* Skip children who will be reparented to another clock */
1633 if (child->new_parent && child->new_parent != core)
1634 continue;
1635 clk_change_rate(child);
1636 }
b2476490 1637
4dff95dc
SB
1638 /* handle the new child who might not be in core->children yet */
1639 if (core->new_child)
1640 clk_change_rate(core->new_child);
588fb54b
MS
1641
1642 clk_pm_runtime_put(core);
b2476490
MT
1643}
1644
6af57a44
JB
1645static unsigned long clk_core_req_round_rate_nolock(struct clk_core *core,
1646 unsigned long req_rate)
1647{
1648 int ret;
1649 struct clk_rate_request req;
1650
1651 lockdep_assert_held(&prepare_lock);
1652
1653 if (!core)
1654 return 0;
1655
1656 clk_core_get_boundaries(core, &req.min_rate, &req.max_rate);
1657 req.rate = req_rate;
1658
1659 ret = clk_core_round_rate_nolock(core, &req);
1660
1661 return ret ? 0 : req.rate;
1662}
1663
4dff95dc
SB
1664static int clk_core_set_rate_nolock(struct clk_core *core,
1665 unsigned long req_rate)
a093bde2 1666{
4dff95dc 1667 struct clk_core *top, *fail_clk;
6af57a44 1668 unsigned long rate;
9a34b453 1669 int ret = 0;
a093bde2 1670
4dff95dc
SB
1671 if (!core)
1672 return 0;
a093bde2 1673
6af57a44
JB
1674 rate = clk_core_req_round_rate_nolock(core, req_rate);
1675
4dff95dc
SB
1676 /* bail early if nothing to do */
1677 if (rate == clk_core_get_rate_nolock(core))
1678 return 0;
a093bde2 1679
4dff95dc
SB
1680 if ((core->flags & CLK_SET_RATE_GATE) && core->prepare_count)
1681 return -EBUSY;
a093bde2 1682
4dff95dc 1683 /* calculate new rates and get the topmost changed clock */
6af57a44 1684 top = clk_calc_new_rates(core, req_rate);
4dff95dc
SB
1685 if (!top)
1686 return -EINVAL;
1687
9a34b453
MS
1688 ret = clk_pm_runtime_get(core);
1689 if (ret)
1690 return ret;
1691
4dff95dc
SB
1692 /* notify that we are about to change rates */
1693 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
1694 if (fail_clk) {
1695 pr_debug("%s: failed to set %s rate\n", __func__,
1696 fail_clk->name);
1697 clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
9a34b453
MS
1698 ret = -EBUSY;
1699 goto err;
4dff95dc
SB
1700 }
1701
1702 /* change the rates */
1703 clk_change_rate(top);
1704
1705 core->req_rate = req_rate;
9a34b453
MS
1706err:
1707 clk_pm_runtime_put(core);
4dff95dc 1708
9a34b453 1709 return ret;
a093bde2 1710}
035a61c3
TV
1711
1712/**
4dff95dc
SB
1713 * clk_set_rate - specify a new rate for clk
1714 * @clk: the clk whose rate is being changed
1715 * @rate: the new rate for clk
035a61c3 1716 *
4dff95dc
SB
1717 * In the simplest case clk_set_rate will only adjust the rate of clk.
1718 *
1719 * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to
1720 * propagate up to clk's parent; whether or not this happens depends on the
1721 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
1722 * after calling .round_rate then upstream parent propagation is ignored. If
1723 * *parent_rate comes back with a new rate for clk's parent then we propagate
1724 * up to clk's parent and set its rate. Upward propagation will continue
1725 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
1726 * .round_rate stops requesting changes to clk's parent_rate.
1727 *
1728 * Rate changes are accomplished via tree traversal that also recalculates the
1729 * rates for the clocks and fires off POST_RATE_CHANGE notifiers.
1730 *
1731 * Returns 0 on success, -EERROR otherwise.
035a61c3 1732 */
4dff95dc 1733int clk_set_rate(struct clk *clk, unsigned long rate)
035a61c3 1734{
4dff95dc
SB
1735 int ret;
1736
035a61c3
TV
1737 if (!clk)
1738 return 0;
1739
4dff95dc
SB
1740 /* prevent racing with updates to the clock topology */
1741 clk_prepare_lock();
da0f0b2c 1742
4dff95dc 1743 ret = clk_core_set_rate_nolock(clk->core, rate);
da0f0b2c 1744
4dff95dc 1745 clk_prepare_unlock();
4935b22c 1746
4dff95dc 1747 return ret;
4935b22c 1748}
4dff95dc 1749EXPORT_SYMBOL_GPL(clk_set_rate);
4935b22c 1750
4dff95dc
SB
1751/**
1752 * clk_set_rate_range - set a rate range for a clock source
1753 * @clk: clock source
1754 * @min: desired minimum clock rate in Hz, inclusive
1755 * @max: desired maximum clock rate in Hz, inclusive
1756 *
1757 * Returns success (0) or negative errno.
1758 */
1759int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
4935b22c 1760{
4dff95dc 1761 int ret = 0;
4935b22c 1762
4dff95dc
SB
1763 if (!clk)
1764 return 0;
903efc55 1765
4dff95dc
SB
1766 if (min > max) {
1767 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n",
1768 __func__, clk->core->name, clk->dev_id, clk->con_id,
1769 min, max);
1770 return -EINVAL;
903efc55 1771 }
4935b22c 1772
4dff95dc 1773 clk_prepare_lock();
4935b22c 1774
4dff95dc
SB
1775 if (min != clk->min_rate || max != clk->max_rate) {
1776 clk->min_rate = min;
1777 clk->max_rate = max;
1778 ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
4935b22c
JH
1779 }
1780
4dff95dc 1781 clk_prepare_unlock();
4935b22c 1782
4dff95dc 1783 return ret;
3fa2252b 1784}
4dff95dc 1785EXPORT_SYMBOL_GPL(clk_set_rate_range);
3fa2252b 1786
4dff95dc
SB
1787/**
1788 * clk_set_min_rate - set a minimum clock rate for a clock source
1789 * @clk: clock source
1790 * @rate: desired minimum clock rate in Hz, inclusive
1791 *
1792 * Returns success (0) or negative errno.
1793 */
1794int clk_set_min_rate(struct clk *clk, unsigned long rate)
3fa2252b 1795{
4dff95dc
SB
1796 if (!clk)
1797 return 0;
1798
1799 return clk_set_rate_range(clk, rate, clk->max_rate);
3fa2252b 1800}
4dff95dc 1801EXPORT_SYMBOL_GPL(clk_set_min_rate);
3fa2252b 1802
4dff95dc
SB
1803/**
1804 * clk_set_max_rate - set a maximum clock rate for a clock source
1805 * @clk: clock source
1806 * @rate: desired maximum clock rate in Hz, inclusive
1807 *
1808 * Returns success (0) or negative errno.
1809 */
1810int clk_set_max_rate(struct clk *clk, unsigned long rate)
3fa2252b 1811{
4dff95dc
SB
1812 if (!clk)
1813 return 0;
4935b22c 1814
4dff95dc 1815 return clk_set_rate_range(clk, clk->min_rate, rate);
4935b22c 1816}
4dff95dc 1817EXPORT_SYMBOL_GPL(clk_set_max_rate);
4935b22c 1818
b2476490 1819/**
4dff95dc
SB
1820 * clk_get_parent - return the parent of a clk
1821 * @clk: the clk whose parent gets returned
b2476490 1822 *
4dff95dc 1823 * Simply returns clk->parent. Returns NULL if clk is NULL.
b2476490 1824 */
4dff95dc 1825struct clk *clk_get_parent(struct clk *clk)
b2476490 1826{
4dff95dc 1827 struct clk *parent;
b2476490 1828
fc4a05d4
SB
1829 if (!clk)
1830 return NULL;
1831
4dff95dc 1832 clk_prepare_lock();
fc4a05d4
SB
1833 /* TODO: Create a per-user clk and change callers to call clk_put */
1834 parent = !clk->core->parent ? NULL : clk->core->parent->hw->clk;
4dff95dc 1835 clk_prepare_unlock();
496eadf8 1836
4dff95dc
SB
1837 return parent;
1838}
1839EXPORT_SYMBOL_GPL(clk_get_parent);
b2476490 1840
4dff95dc
SB
1841static struct clk_core *__clk_init_parent(struct clk_core *core)
1842{
5146e0b0 1843 u8 index = 0;
4dff95dc 1844
2430a94d 1845 if (core->num_parents > 1 && core->ops->get_parent)
5146e0b0 1846 index = core->ops->get_parent(core->hw);
b2476490 1847
5146e0b0 1848 return clk_core_get_parent_by_index(core, index);
b2476490
MT
1849}
1850
4dff95dc
SB
1851static void clk_core_reparent(struct clk_core *core,
1852 struct clk_core *new_parent)
b2476490 1853{
4dff95dc
SB
1854 clk_reparent(core, new_parent);
1855 __clk_recalc_accuracies(core);
1856 __clk_recalc_rates(core, POST_RATE_CHANGE);
b2476490
MT
1857}
1858
42c86547
TV
1859void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent)
1860{
1861 if (!hw)
1862 return;
1863
1864 clk_core_reparent(hw->core, !new_parent ? NULL : new_parent->core);
1865}
1866
4dff95dc
SB
1867/**
1868 * clk_has_parent - check if a clock is a possible parent for another
1869 * @clk: clock source
1870 * @parent: parent clock source
1871 *
1872 * This function can be used in drivers that need to check that a clock can be
1873 * the parent of another without actually changing the parent.
1874 *
1875 * Returns true if @parent is a possible parent for @clk, false otherwise.
b2476490 1876 */
4dff95dc 1877bool clk_has_parent(struct clk *clk, struct clk *parent)
b2476490 1878{
4dff95dc
SB
1879 struct clk_core *core, *parent_core;
1880 unsigned int i;
b2476490 1881
4dff95dc
SB
1882 /* NULL clocks should be nops, so return success if either is NULL. */
1883 if (!clk || !parent)
1884 return true;
7452b219 1885
4dff95dc
SB
1886 core = clk->core;
1887 parent_core = parent->core;
71472c0c 1888
4dff95dc
SB
1889 /* Optimize for the case where the parent is already the parent. */
1890 if (core->parent == parent_core)
1891 return true;
1c8e6004 1892
4dff95dc
SB
1893 for (i = 0; i < core->num_parents; i++)
1894 if (strcmp(core->parent_names[i], parent_core->name) == 0)
1895 return true;
03bc10ab 1896
4dff95dc
SB
1897 return false;
1898}
1899EXPORT_SYMBOL_GPL(clk_has_parent);
03bc10ab 1900
4dff95dc
SB
1901static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
1902{
1903 int ret = 0;
1904 int p_index = 0;
1905 unsigned long p_rate = 0;
1906
1907 if (!core)
1908 return 0;
1909
1910 /* prevent racing with updates to the clock topology */
1911 clk_prepare_lock();
1912
1913 if (core->parent == parent)
1914 goto out;
1915
1916 /* verify ops for for multi-parent clks */
1917 if ((core->num_parents > 1) && (!core->ops->set_parent)) {
1918 ret = -ENOSYS;
63f5c3b2 1919 goto out;
7452b219
MT
1920 }
1921
4dff95dc
SB
1922 /* check that we are allowed to re-parent if the clock is in use */
1923 if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
1924 ret = -EBUSY;
1925 goto out;
b2476490
MT
1926 }
1927
71472c0c 1928 /* try finding the new parent index */
4dff95dc 1929 if (parent) {
d6968fca 1930 p_index = clk_fetch_parent_index(core, parent);
f1c8b2ed 1931 if (p_index < 0) {
71472c0c 1932 pr_debug("%s: clk %s can not be parent of clk %s\n",
4dff95dc
SB
1933 __func__, parent->name, core->name);
1934 ret = p_index;
1935 goto out;
71472c0c 1936 }
e8f0e68e 1937 p_rate = parent->rate;
b2476490
MT
1938 }
1939
9a34b453
MS
1940 ret = clk_pm_runtime_get(core);
1941 if (ret)
1942 goto out;
1943
4dff95dc
SB
1944 /* propagate PRE_RATE_CHANGE notifications */
1945 ret = __clk_speculate_rates(core, p_rate);
b2476490 1946
4dff95dc
SB
1947 /* abort if a driver objects */
1948 if (ret & NOTIFY_STOP_MASK)
9a34b453 1949 goto runtime_put;
b2476490 1950
4dff95dc
SB
1951 /* do the re-parent */
1952 ret = __clk_set_parent(core, parent, p_index);
b2476490 1953
4dff95dc
SB
1954 /* propagate rate an accuracy recalculation accordingly */
1955 if (ret) {
1956 __clk_recalc_rates(core, ABORT_RATE_CHANGE);
1957 } else {
1958 __clk_recalc_rates(core, POST_RATE_CHANGE);
1959 __clk_recalc_accuracies(core);
b2476490
MT
1960 }
1961
9a34b453
MS
1962runtime_put:
1963 clk_pm_runtime_put(core);
4dff95dc
SB
1964out:
1965 clk_prepare_unlock();
71472c0c 1966
4dff95dc
SB
1967 return ret;
1968}
b2476490 1969
4dff95dc
SB
1970/**
1971 * clk_set_parent - switch the parent of a mux clk
1972 * @clk: the mux clk whose input we are switching
1973 * @parent: the new input to clk
1974 *
1975 * Re-parent clk to use parent as its new input source. If clk is in
1976 * prepared state, the clk will get enabled for the duration of this call. If
1977 * that's not acceptable for a specific clk (Eg: the consumer can't handle
1978 * that, the reparenting is glitchy in hardware, etc), use the
1979 * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
1980 *
1981 * After successfully changing clk's parent clk_set_parent will update the
1982 * clk topology, sysfs topology and propagate rate recalculation via
1983 * __clk_recalc_rates.
1984 *
1985 * Returns 0 on success, -EERROR otherwise.
1986 */
1987int clk_set_parent(struct clk *clk, struct clk *parent)
1988{
1989 if (!clk)
1990 return 0;
1991
1992 return clk_core_set_parent(clk->core, parent ? parent->core : NULL);
b2476490 1993}
4dff95dc 1994EXPORT_SYMBOL_GPL(clk_set_parent);
b2476490 1995
4dff95dc
SB
1996/**
1997 * clk_set_phase - adjust the phase shift of a clock signal
1998 * @clk: clock signal source
1999 * @degrees: number of degrees the signal is shifted
2000 *
2001 * Shifts the phase of a clock signal by the specified
2002 * degrees. Returns 0 on success, -EERROR otherwise.
2003 *
2004 * This function makes no distinction about the input or reference
2005 * signal that we adjust the clock signal phase against. For example
2006 * phase locked-loop clock signal generators we may shift phase with
2007 * respect to feedback clock signal input, but for other cases the
2008 * clock phase may be shifted with respect to some other, unspecified
2009 * signal.
2010 *
2011 * Additionally the concept of phase shift does not propagate through
2012 * the clock tree hierarchy, which sets it apart from clock rates and
2013 * clock accuracy. A parent clock phase attribute does not have an
2014 * impact on the phase attribute of a child clock.
b2476490 2015 */
4dff95dc 2016int clk_set_phase(struct clk *clk, int degrees)
b2476490 2017{
4dff95dc 2018 int ret = -EINVAL;
b2476490 2019
4dff95dc
SB
2020 if (!clk)
2021 return 0;
b2476490 2022
4dff95dc
SB
2023 /* sanity check degrees */
2024 degrees %= 360;
2025 if (degrees < 0)
2026 degrees += 360;
bf47b4fd 2027
4dff95dc 2028 clk_prepare_lock();
3fa2252b 2029
4dff95dc 2030 trace_clk_set_phase(clk->core, degrees);
3fa2252b 2031
4dff95dc
SB
2032 if (clk->core->ops->set_phase)
2033 ret = clk->core->ops->set_phase(clk->core->hw, degrees);
3fa2252b 2034
4dff95dc 2035 trace_clk_set_phase_complete(clk->core, degrees);
dfc202ea 2036
4dff95dc
SB
2037 if (!ret)
2038 clk->core->phase = degrees;
b2476490 2039
4dff95dc 2040 clk_prepare_unlock();
dfc202ea 2041
4dff95dc
SB
2042 return ret;
2043}
2044EXPORT_SYMBOL_GPL(clk_set_phase);
b2476490 2045
4dff95dc
SB
2046static int clk_core_get_phase(struct clk_core *core)
2047{
2048 int ret;
b2476490 2049
4dff95dc
SB
2050 clk_prepare_lock();
2051 ret = core->phase;
2052 clk_prepare_unlock();
71472c0c 2053
4dff95dc 2054 return ret;
b2476490
MT
2055}
2056
4dff95dc
SB
2057/**
2058 * clk_get_phase - return the phase shift of a clock signal
2059 * @clk: clock signal source
2060 *
2061 * Returns the phase shift of a clock node in degrees, otherwise returns
2062 * -EERROR.
2063 */
2064int clk_get_phase(struct clk *clk)
1c8e6004 2065{
4dff95dc 2066 if (!clk)
1c8e6004
TV
2067 return 0;
2068
4dff95dc
SB
2069 return clk_core_get_phase(clk->core);
2070}
2071EXPORT_SYMBOL_GPL(clk_get_phase);
1c8e6004 2072
4dff95dc
SB
2073/**
2074 * clk_is_match - check if two clk's point to the same hardware clock
2075 * @p: clk compared against q
2076 * @q: clk compared against p
2077 *
2078 * Returns true if the two struct clk pointers both point to the same hardware
2079 * clock node. Put differently, returns true if struct clk *p and struct clk *q
2080 * share the same struct clk_core object.
2081 *
2082 * Returns false otherwise. Note that two NULL clks are treated as matching.
2083 */
2084bool clk_is_match(const struct clk *p, const struct clk *q)
2085{
2086 /* trivial case: identical struct clk's or both NULL */
2087 if (p == q)
2088 return true;
1c8e6004 2089
3fe003f9 2090 /* true if clk->core pointers match. Avoid dereferencing garbage */
4dff95dc
SB
2091 if (!IS_ERR_OR_NULL(p) && !IS_ERR_OR_NULL(q))
2092 if (p->core == q->core)
2093 return true;
1c8e6004 2094
4dff95dc
SB
2095 return false;
2096}
2097EXPORT_SYMBOL_GPL(clk_is_match);
1c8e6004 2098
4dff95dc 2099/*** debugfs support ***/
1c8e6004 2100
4dff95dc
SB
2101#ifdef CONFIG_DEBUG_FS
2102#include <linux/debugfs.h>
1c8e6004 2103
4dff95dc
SB
2104static struct dentry *rootdir;
2105static int inited = 0;
2106static DEFINE_MUTEX(clk_debug_lock);
2107static HLIST_HEAD(clk_debug_list);
1c8e6004 2108
4dff95dc
SB
2109static struct hlist_head *all_lists[] = {
2110 &clk_root_list,
2111 &clk_orphan_list,
2112 NULL,
2113};
2114
2115static struct hlist_head *orphan_list[] = {
2116 &clk_orphan_list,
2117 NULL,
2118};
2119
2120static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
2121 int level)
b2476490 2122{
4dff95dc
SB
2123 if (!c)
2124 return;
b2476490 2125
4dff95dc
SB
2126 seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n",
2127 level * 3 + 1, "",
2128 30 - level * 3, c->name,
2129 c->enable_count, c->prepare_count, clk_core_get_rate(c),
2130 clk_core_get_accuracy(c), clk_core_get_phase(c));
2131}
89ac8d7a 2132
4dff95dc
SB
2133static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
2134 int level)
2135{
2136 struct clk_core *child;
b2476490 2137
4dff95dc
SB
2138 if (!c)
2139 return;
b2476490 2140
4dff95dc 2141 clk_summary_show_one(s, c, level);
0e1c0301 2142
4dff95dc
SB
2143 hlist_for_each_entry(child, &c->children, child_node)
2144 clk_summary_show_subtree(s, child, level + 1);
1c8e6004 2145}
b2476490 2146
4dff95dc 2147static int clk_summary_show(struct seq_file *s, void *data)
1c8e6004 2148{
4dff95dc
SB
2149 struct clk_core *c;
2150 struct hlist_head **lists = (struct hlist_head **)s->private;
1c8e6004 2151
4dff95dc
SB
2152 seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n");
2153 seq_puts(s, "----------------------------------------------------------------------------------------\n");
b2476490 2154
1c8e6004
TV
2155 clk_prepare_lock();
2156
4dff95dc
SB
2157 for (; *lists; lists++)
2158 hlist_for_each_entry(c, *lists, child_node)
2159 clk_summary_show_subtree(s, c, 0);
b2476490 2160
eab89f69 2161 clk_prepare_unlock();
b2476490 2162
4dff95dc 2163 return 0;
b2476490 2164}
1c8e6004 2165
1c8e6004 2166
4dff95dc 2167static int clk_summary_open(struct inode *inode, struct file *file)
1c8e6004 2168{
4dff95dc 2169 return single_open(file, clk_summary_show, inode->i_private);
1c8e6004 2170}
b2476490 2171
4dff95dc
SB
2172static const struct file_operations clk_summary_fops = {
2173 .open = clk_summary_open,
2174 .read = seq_read,
2175 .llseek = seq_lseek,
2176 .release = single_release,
2177};
b2476490 2178
4dff95dc
SB
2179static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
2180{
2181 if (!c)
2182 return;
b2476490 2183
7cb81136 2184 /* This should be JSON format, i.e. elements separated with a comma */
4dff95dc
SB
2185 seq_printf(s, "\"%s\": { ", c->name);
2186 seq_printf(s, "\"enable_count\": %d,", c->enable_count);
2187 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
7cb81136
SW
2188 seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
2189 seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
4dff95dc 2190 seq_printf(s, "\"phase\": %d", clk_core_get_phase(c));
b2476490 2191}
b2476490 2192
4dff95dc 2193static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
b2476490 2194{
4dff95dc 2195 struct clk_core *child;
b2476490 2196
4dff95dc
SB
2197 if (!c)
2198 return;
b2476490 2199
4dff95dc 2200 clk_dump_one(s, c, level);
b2476490 2201
4dff95dc 2202 hlist_for_each_entry(child, &c->children, child_node) {
4d327586 2203 seq_putc(s, ',');
4dff95dc 2204 clk_dump_subtree(s, child, level + 1);
b2476490
MT
2205 }
2206
4d327586 2207 seq_putc(s, '}');
b2476490
MT
2208}
2209
4dff95dc 2210static int clk_dump(struct seq_file *s, void *data)
4e88f3de 2211{
4dff95dc
SB
2212 struct clk_core *c;
2213 bool first_node = true;
2214 struct hlist_head **lists = (struct hlist_head **)s->private;
4e88f3de 2215
4d327586 2216 seq_putc(s, '{');
4dff95dc 2217 clk_prepare_lock();
035a61c3 2218
4dff95dc
SB
2219 for (; *lists; lists++) {
2220 hlist_for_each_entry(c, *lists, child_node) {
2221 if (!first_node)
4d327586 2222 seq_putc(s, ',');
4dff95dc
SB
2223 first_node = false;
2224 clk_dump_subtree(s, c, 0);
2225 }
2226 }
4e88f3de 2227
4dff95dc 2228 clk_prepare_unlock();
4e88f3de 2229
70e9f4dd 2230 seq_puts(s, "}\n");
4dff95dc 2231 return 0;
4e88f3de 2232}
4e88f3de 2233
4dff95dc
SB
2234
2235static int clk_dump_open(struct inode *inode, struct file *file)
b2476490 2236{
4dff95dc
SB
2237 return single_open(file, clk_dump, inode->i_private);
2238}
b2476490 2239
4dff95dc
SB
2240static const struct file_operations clk_dump_fops = {
2241 .open = clk_dump_open,
2242 .read = seq_read,
2243 .llseek = seq_lseek,
2244 .release = single_release,
2245};
89ac8d7a 2246
92031575
PDS
2247static int possible_parents_dump(struct seq_file *s, void *data)
2248{
2249 struct clk_core *core = s->private;
2250 int i;
2251
2252 for (i = 0; i < core->num_parents - 1; i++)
2253 seq_printf(s, "%s ", core->parent_names[i]);
2254
2255 seq_printf(s, "%s\n", core->parent_names[i]);
2256
2257 return 0;
2258}
2259
2260static int possible_parents_open(struct inode *inode, struct file *file)
2261{
2262 return single_open(file, possible_parents_dump, inode->i_private);
2263}
2264
2265static const struct file_operations possible_parents_fops = {
2266 .open = possible_parents_open,
2267 .read = seq_read,
2268 .llseek = seq_lseek,
2269 .release = single_release,
2270};
2271
4dff95dc
SB
2272static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
2273{
2274 struct dentry *d;
2275 int ret = -ENOMEM;
b2476490 2276
4dff95dc
SB
2277 if (!core || !pdentry) {
2278 ret = -EINVAL;
b2476490 2279 goto out;
4dff95dc 2280 }
b2476490 2281
4dff95dc
SB
2282 d = debugfs_create_dir(core->name, pdentry);
2283 if (!d)
b61c43c0 2284 goto out;
b61c43c0 2285
4dff95dc
SB
2286 core->dentry = d;
2287
2288 d = debugfs_create_u32("clk_rate", S_IRUGO, core->dentry,
2289 (u32 *)&core->rate);
2290 if (!d)
2291 goto err_out;
2292
2293 d = debugfs_create_u32("clk_accuracy", S_IRUGO, core->dentry,
2294 (u32 *)&core->accuracy);
2295 if (!d)
2296 goto err_out;
2297
2298 d = debugfs_create_u32("clk_phase", S_IRUGO, core->dentry,
2299 (u32 *)&core->phase);
2300 if (!d)
2301 goto err_out;
031dcc9b 2302
4dff95dc
SB
2303 d = debugfs_create_x32("clk_flags", S_IRUGO, core->dentry,
2304 (u32 *)&core->flags);
2305 if (!d)
2306 goto err_out;
031dcc9b 2307
4dff95dc
SB
2308 d = debugfs_create_u32("clk_prepare_count", S_IRUGO, core->dentry,
2309 (u32 *)&core->prepare_count);
2310 if (!d)
2311 goto err_out;
b2476490 2312
4dff95dc
SB
2313 d = debugfs_create_u32("clk_enable_count", S_IRUGO, core->dentry,
2314 (u32 *)&core->enable_count);
2315 if (!d)
2316 goto err_out;
b2476490 2317
4dff95dc
SB
2318 d = debugfs_create_u32("clk_notifier_count", S_IRUGO, core->dentry,
2319 (u32 *)&core->notifier_count);
2320 if (!d)
2321 goto err_out;
b2476490 2322
92031575
PDS
2323 if (core->num_parents > 1) {
2324 d = debugfs_create_file("clk_possible_parents", S_IRUGO,
2325 core->dentry, core, &possible_parents_fops);
2326 if (!d)
2327 goto err_out;
2328 }
2329
4dff95dc
SB
2330 if (core->ops->debug_init) {
2331 ret = core->ops->debug_init(core->hw, core->dentry);
2332 if (ret)
2333 goto err_out;
5279fc40 2334 }
b2476490 2335
4dff95dc
SB
2336 ret = 0;
2337 goto out;
b2476490 2338
4dff95dc
SB
2339err_out:
2340 debugfs_remove_recursive(core->dentry);
2341 core->dentry = NULL;
2342out:
b2476490
MT
2343 return ret;
2344}
035a61c3
TV
2345
2346/**
6e5ab41b
SB
2347 * clk_debug_register - add a clk node to the debugfs clk directory
2348 * @core: the clk being added to the debugfs clk directory
035a61c3 2349 *
6e5ab41b
SB
2350 * Dynamically adds a clk to the debugfs clk directory if debugfs has been
2351 * initialized. Otherwise it bails out early since the debugfs clk directory
4dff95dc 2352 * will be created lazily by clk_debug_init as part of a late_initcall.
035a61c3 2353 */
4dff95dc 2354static int clk_debug_register(struct clk_core *core)
035a61c3 2355{
4dff95dc 2356 int ret = 0;
035a61c3 2357
4dff95dc
SB
2358 mutex_lock(&clk_debug_lock);
2359 hlist_add_head(&core->debug_node, &clk_debug_list);
2360
2361 if (!inited)
2362 goto unlock;
2363
2364 ret = clk_debug_create_one(core, rootdir);
2365unlock:
2366 mutex_unlock(&clk_debug_lock);
2367
2368 return ret;
035a61c3 2369}
b2476490 2370
4dff95dc 2371 /**
6e5ab41b
SB
2372 * clk_debug_unregister - remove a clk node from the debugfs clk directory
2373 * @core: the clk being removed from the debugfs clk directory
e59c5371 2374 *
6e5ab41b
SB
2375 * Dynamically removes a clk and all its child nodes from the
2376 * debugfs clk directory if clk->dentry points to debugfs created by
706d5c73 2377 * clk_debug_register in __clk_core_init.
e59c5371 2378 */
4dff95dc 2379static void clk_debug_unregister(struct clk_core *core)
e59c5371 2380{
4dff95dc
SB
2381 mutex_lock(&clk_debug_lock);
2382 hlist_del_init(&core->debug_node);
2383 debugfs_remove_recursive(core->dentry);
2384 core->dentry = NULL;
2385 mutex_unlock(&clk_debug_lock);
2386}
e59c5371 2387
4dff95dc
SB
2388struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
2389 void *data, const struct file_operations *fops)
2390{
2391 struct dentry *d = NULL;
e59c5371 2392
4dff95dc
SB
2393 if (hw->core->dentry)
2394 d = debugfs_create_file(name, mode, hw->core->dentry, data,
2395 fops);
e59c5371 2396
4dff95dc
SB
2397 return d;
2398}
2399EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
e59c5371 2400
4dff95dc 2401/**
6e5ab41b 2402 * clk_debug_init - lazily populate the debugfs clk directory
4dff95dc 2403 *
6e5ab41b
SB
2404 * clks are often initialized very early during boot before memory can be
2405 * dynamically allocated and well before debugfs is setup. This function
2406 * populates the debugfs clk directory once at boot-time when we know that
2407 * debugfs is setup. It should only be called once at boot-time, all other clks
2408 * added dynamically will be done so with clk_debug_register.
4dff95dc
SB
2409 */
2410static int __init clk_debug_init(void)
2411{
2412 struct clk_core *core;
2413 struct dentry *d;
dfc202ea 2414
4dff95dc 2415 rootdir = debugfs_create_dir("clk", NULL);
e59c5371 2416
4dff95dc
SB
2417 if (!rootdir)
2418 return -ENOMEM;
dfc202ea 2419
4dff95dc
SB
2420 d = debugfs_create_file("clk_summary", S_IRUGO, rootdir, &all_lists,
2421 &clk_summary_fops);
2422 if (!d)
2423 return -ENOMEM;
e59c5371 2424
4dff95dc
SB
2425 d = debugfs_create_file("clk_dump", S_IRUGO, rootdir, &all_lists,
2426 &clk_dump_fops);
2427 if (!d)
2428 return -ENOMEM;
e59c5371 2429
4dff95dc
SB
2430 d = debugfs_create_file("clk_orphan_summary", S_IRUGO, rootdir,
2431 &orphan_list, &clk_summary_fops);
2432 if (!d)
2433 return -ENOMEM;
e59c5371 2434
4dff95dc
SB
2435 d = debugfs_create_file("clk_orphan_dump", S_IRUGO, rootdir,
2436 &orphan_list, &clk_dump_fops);
2437 if (!d)
2438 return -ENOMEM;
e59c5371 2439
4dff95dc
SB
2440 mutex_lock(&clk_debug_lock);
2441 hlist_for_each_entry(core, &clk_debug_list, debug_node)
2442 clk_debug_create_one(core, rootdir);
e59c5371 2443
4dff95dc
SB
2444 inited = 1;
2445 mutex_unlock(&clk_debug_lock);
e59c5371 2446
4dff95dc
SB
2447 return 0;
2448}
2449late_initcall(clk_debug_init);
2450#else
2451static inline int clk_debug_register(struct clk_core *core) { return 0; }
2452static inline void clk_debug_reparent(struct clk_core *core,
2453 struct clk_core *new_parent)
035a61c3 2454{
035a61c3 2455}
4dff95dc 2456static inline void clk_debug_unregister(struct clk_core *core)
3d3801ef 2457{
3d3801ef 2458}
4dff95dc 2459#endif
3d3801ef 2460
b2476490 2461/**
be45ebf2 2462 * __clk_core_init - initialize the data structures in a struct clk_core
d35c80c2 2463 * @core: clk_core being initialized
b2476490 2464 *
035a61c3 2465 * Initializes the lists in struct clk_core, queries the hardware for the
b2476490 2466 * parent and rate and sets them both.
b2476490 2467 */
be45ebf2 2468static int __clk_core_init(struct clk_core *core)
b2476490 2469{
9a34b453 2470 int i, ret;
035a61c3 2471 struct clk_core *orphan;
b67bfe0d 2472 struct hlist_node *tmp2;
1c8e6004 2473 unsigned long rate;
b2476490 2474
d35c80c2 2475 if (!core)
d1302a36 2476 return -EINVAL;
b2476490 2477
eab89f69 2478 clk_prepare_lock();
b2476490 2479
9a34b453
MS
2480 ret = clk_pm_runtime_get(core);
2481 if (ret)
2482 goto unlock;
2483
b2476490 2484 /* check to see if a clock with this name is already registered */
d6968fca 2485 if (clk_core_lookup(core->name)) {
d1302a36 2486 pr_debug("%s: clk %s already initialized\n",
d6968fca 2487 __func__, core->name);
d1302a36 2488 ret = -EEXIST;
b2476490 2489 goto out;
d1302a36 2490 }
b2476490 2491
d4d7e3dd 2492 /* check that clk_ops are sane. See Documentation/clk.txt */
d6968fca
SB
2493 if (core->ops->set_rate &&
2494 !((core->ops->round_rate || core->ops->determine_rate) &&
2495 core->ops->recalc_rate)) {
c44fccb5
MY
2496 pr_err("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
2497 __func__, core->name);
d1302a36 2498 ret = -EINVAL;
d4d7e3dd
MT
2499 goto out;
2500 }
2501
d6968fca 2502 if (core->ops->set_parent && !core->ops->get_parent) {
c44fccb5
MY
2503 pr_err("%s: %s must implement .get_parent & .set_parent\n",
2504 __func__, core->name);
d1302a36 2505 ret = -EINVAL;
d4d7e3dd
MT
2506 goto out;
2507 }
2508
3c8e77dd
MY
2509 if (core->num_parents > 1 && !core->ops->get_parent) {
2510 pr_err("%s: %s must implement .get_parent as it has multi parents\n",
2511 __func__, core->name);
2512 ret = -EINVAL;
2513 goto out;
2514 }
2515
d6968fca
SB
2516 if (core->ops->set_rate_and_parent &&
2517 !(core->ops->set_parent && core->ops->set_rate)) {
c44fccb5 2518 pr_err("%s: %s must implement .set_parent & .set_rate\n",
d6968fca 2519 __func__, core->name);
3fa2252b
SB
2520 ret = -EINVAL;
2521 goto out;
2522 }
2523
b2476490 2524 /* throw a WARN if any entries in parent_names are NULL */
d6968fca
SB
2525 for (i = 0; i < core->num_parents; i++)
2526 WARN(!core->parent_names[i],
b2476490 2527 "%s: invalid NULL in %s's .parent_names\n",
d6968fca 2528 __func__, core->name);
b2476490 2529
d6968fca 2530 core->parent = __clk_init_parent(core);
b2476490
MT
2531
2532 /*
706d5c73
SB
2533 * Populate core->parent if parent has already been clk_core_init'd. If
2534 * parent has not yet been clk_core_init'd then place clk in the orphan
47b0eeb3 2535 * list. If clk doesn't have any parents then place it in the root
b2476490
MT
2536 * clk list.
2537 *
2538 * Every time a new clk is clk_init'd then we walk the list of orphan
2539 * clocks and re-parent any that are children of the clock currently
2540 * being clk_init'd.
2541 */
e6500344 2542 if (core->parent) {
d6968fca
SB
2543 hlist_add_head(&core->child_node,
2544 &core->parent->children);
e6500344 2545 core->orphan = core->parent->orphan;
47b0eeb3 2546 } else if (!core->num_parents) {
d6968fca 2547 hlist_add_head(&core->child_node, &clk_root_list);
e6500344
HS
2548 core->orphan = false;
2549 } else {
d6968fca 2550 hlist_add_head(&core->child_node, &clk_orphan_list);
e6500344
HS
2551 core->orphan = true;
2552 }
b2476490 2553
5279fc40
BB
2554 /*
2555 * Set clk's accuracy. The preferred method is to use
2556 * .recalc_accuracy. For simple clocks and lazy developers the default
2557 * fallback is to use the parent's accuracy. If a clock doesn't have a
2558 * parent (or is orphaned) then accuracy is set to zero (perfect
2559 * clock).
2560 */
d6968fca
SB
2561 if (core->ops->recalc_accuracy)
2562 core->accuracy = core->ops->recalc_accuracy(core->hw,
2563 __clk_get_accuracy(core->parent));
2564 else if (core->parent)
2565 core->accuracy = core->parent->accuracy;
5279fc40 2566 else
d6968fca 2567 core->accuracy = 0;
5279fc40 2568
9824cf73
MR
2569 /*
2570 * Set clk's phase.
2571 * Since a phase is by definition relative to its parent, just
2572 * query the current clock phase, or just assume it's in phase.
2573 */
d6968fca
SB
2574 if (core->ops->get_phase)
2575 core->phase = core->ops->get_phase(core->hw);
9824cf73 2576 else
d6968fca 2577 core->phase = 0;
9824cf73 2578
b2476490
MT
2579 /*
2580 * Set clk's rate. The preferred method is to use .recalc_rate. For
2581 * simple clocks and lazy developers the default fallback is to use the
2582 * parent's rate. If a clock doesn't have a parent (or is orphaned)
2583 * then rate is set to zero.
2584 */
d6968fca
SB
2585 if (core->ops->recalc_rate)
2586 rate = core->ops->recalc_rate(core->hw,
2587 clk_core_get_rate_nolock(core->parent));
2588 else if (core->parent)
2589 rate = core->parent->rate;
b2476490 2590 else
1c8e6004 2591 rate = 0;
d6968fca 2592 core->rate = core->req_rate = rate;
b2476490
MT
2593
2594 /*
0e8f6e49
MY
2595 * walk the list of orphan clocks and reparent any that newly finds a
2596 * parent.
b2476490 2597 */
b67bfe0d 2598 hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
0e8f6e49 2599 struct clk_core *parent = __clk_init_parent(orphan);
1f61e5f1 2600
904e6ead
MT
2601 /*
2602 * we could call __clk_set_parent, but that would result in a
2603 * redundant call to the .set_rate op, if it exists
2604 */
2605 if (parent) {
2606 __clk_set_parent_before(orphan, parent);
2607 __clk_set_parent_after(orphan, parent, NULL);
2608 __clk_recalc_accuracies(orphan);
2609 __clk_recalc_rates(orphan, 0);
2610 }
0e8f6e49 2611 }
b2476490
MT
2612
2613 /*
2614 * optional platform-specific magic
2615 *
2616 * The .init callback is not used by any of the basic clock types, but
2617 * exists for weird hardware that must perform initialization magic.
2618 * Please consider other ways of solving initialization problems before
24ee1a08 2619 * using this callback, as its use is discouraged.
b2476490 2620 */
d6968fca
SB
2621 if (core->ops->init)
2622 core->ops->init(core->hw);
b2476490 2623
32b9b109 2624 if (core->flags & CLK_IS_CRITICAL) {
ef56b79b
MR
2625 unsigned long flags;
2626
32b9b109 2627 clk_core_prepare(core);
ef56b79b
MR
2628
2629 flags = clk_enable_lock();
32b9b109 2630 clk_core_enable(core);
ef56b79b 2631 clk_enable_unlock(flags);
32b9b109
LJ
2632 }
2633
d6968fca 2634 kref_init(&core->ref);
b2476490 2635out:
9a34b453
MS
2636 clk_pm_runtime_put(core);
2637unlock:
eab89f69 2638 clk_prepare_unlock();
b2476490 2639
89f7e9de 2640 if (!ret)
d6968fca 2641 clk_debug_register(core);
89f7e9de 2642
d1302a36 2643 return ret;
b2476490
MT
2644}
2645
035a61c3
TV
2646struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
2647 const char *con_id)
0197b3ea 2648{
0197b3ea
SK
2649 struct clk *clk;
2650
035a61c3 2651 /* This is to allow this function to be chained to others */
c1de1357 2652 if (IS_ERR_OR_NULL(hw))
8a23133c 2653 return ERR_CAST(hw);
0197b3ea 2654
035a61c3
TV
2655 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
2656 if (!clk)
2657 return ERR_PTR(-ENOMEM);
2658
2659 clk->core = hw->core;
2660 clk->dev_id = dev_id;
253160a8 2661 clk->con_id = kstrdup_const(con_id, GFP_KERNEL);
1c8e6004
TV
2662 clk->max_rate = ULONG_MAX;
2663
2664 clk_prepare_lock();
50595f8b 2665 hlist_add_head(&clk->clks_node, &hw->core->clks);
1c8e6004 2666 clk_prepare_unlock();
0197b3ea
SK
2667
2668 return clk;
2669}
035a61c3 2670
73e0e496 2671void __clk_free_clk(struct clk *clk)
1c8e6004
TV
2672{
2673 clk_prepare_lock();
50595f8b 2674 hlist_del(&clk->clks_node);
1c8e6004
TV
2675 clk_prepare_unlock();
2676
253160a8 2677 kfree_const(clk->con_id);
1c8e6004
TV
2678 kfree(clk);
2679}
0197b3ea 2680
293ba3b4
SB
2681/**
2682 * clk_register - allocate a new clock, register it and return an opaque cookie
2683 * @dev: device that is registering this clock
2684 * @hw: link to hardware-specific clock data
2685 *
2686 * clk_register is the primary interface for populating the clock tree with new
2687 * clock nodes. It returns a pointer to the newly allocated struct clk which
a59a5163 2688 * cannot be dereferenced by driver code but may be used in conjunction with the
293ba3b4
SB
2689 * rest of the clock API. In the event of an error clk_register will return an
2690 * error code; drivers must test for an error code after calling clk_register.
2691 */
2692struct clk *clk_register(struct device *dev, struct clk_hw *hw)
b2476490 2693{
d1302a36 2694 int i, ret;
d6968fca 2695 struct clk_core *core;
293ba3b4 2696
d6968fca
SB
2697 core = kzalloc(sizeof(*core), GFP_KERNEL);
2698 if (!core) {
293ba3b4
SB
2699 ret = -ENOMEM;
2700 goto fail_out;
2701 }
b2476490 2702
d6968fca
SB
2703 core->name = kstrdup_const(hw->init->name, GFP_KERNEL);
2704 if (!core->name) {
0197b3ea
SK
2705 ret = -ENOMEM;
2706 goto fail_name;
2707 }
0690e62b
JB
2708
2709 if (WARN_ON(!hw->init->ops)) {
2710 ret = -EINVAL;
2711 goto fail_ops;
2712 }
d6968fca 2713 core->ops = hw->init->ops;
0690e62b 2714
9a34b453
MS
2715 if (dev && pm_runtime_enabled(dev))
2716 core->dev = dev;
ac2df527 2717 if (dev && dev->driver)
d6968fca
SB
2718 core->owner = dev->driver->owner;
2719 core->hw = hw;
2720 core->flags = hw->init->flags;
2721 core->num_parents = hw->init->num_parents;
9783c0d9
SB
2722 core->min_rate = 0;
2723 core->max_rate = ULONG_MAX;
d6968fca 2724 hw->core = core;
b2476490 2725
d1302a36 2726 /* allocate local copy in case parent_names is __initdata */
d6968fca 2727 core->parent_names = kcalloc(core->num_parents, sizeof(char *),
96a7ed90 2728 GFP_KERNEL);
d1302a36 2729
d6968fca 2730 if (!core->parent_names) {
d1302a36
MT
2731 ret = -ENOMEM;
2732 goto fail_parent_names;
2733 }
2734
2735
2736 /* copy each string name in case parent_names is __initdata */
d6968fca
SB
2737 for (i = 0; i < core->num_parents; i++) {
2738 core->parent_names[i] = kstrdup_const(hw->init->parent_names[i],
0197b3ea 2739 GFP_KERNEL);
d6968fca 2740 if (!core->parent_names[i]) {
d1302a36
MT
2741 ret = -ENOMEM;
2742 goto fail_parent_names_copy;
2743 }
2744 }
2745
176d1169
MY
2746 /* avoid unnecessary string look-ups of clk_core's possible parents. */
2747 core->parents = kcalloc(core->num_parents, sizeof(*core->parents),
2748 GFP_KERNEL);
2749 if (!core->parents) {
2750 ret = -ENOMEM;
2751 goto fail_parents;
2752 };
2753
d6968fca 2754 INIT_HLIST_HEAD(&core->clks);
1c8e6004 2755
035a61c3
TV
2756 hw->clk = __clk_create_clk(hw, NULL, NULL);
2757 if (IS_ERR(hw->clk)) {
035a61c3 2758 ret = PTR_ERR(hw->clk);
176d1169 2759 goto fail_parents;
035a61c3
TV
2760 }
2761
be45ebf2 2762 ret = __clk_core_init(core);
d1302a36 2763 if (!ret)
035a61c3 2764 return hw->clk;
b2476490 2765
1c8e6004 2766 __clk_free_clk(hw->clk);
035a61c3 2767 hw->clk = NULL;
b2476490 2768
176d1169
MY
2769fail_parents:
2770 kfree(core->parents);
d1302a36
MT
2771fail_parent_names_copy:
2772 while (--i >= 0)
d6968fca
SB
2773 kfree_const(core->parent_names[i]);
2774 kfree(core->parent_names);
d1302a36 2775fail_parent_names:
0690e62b 2776fail_ops:
d6968fca 2777 kfree_const(core->name);
0197b3ea 2778fail_name:
d6968fca 2779 kfree(core);
d1302a36
MT
2780fail_out:
2781 return ERR_PTR(ret);
b2476490
MT
2782}
2783EXPORT_SYMBOL_GPL(clk_register);
2784
4143804c
SB
2785/**
2786 * clk_hw_register - register a clk_hw and return an error code
2787 * @dev: device that is registering this clock
2788 * @hw: link to hardware-specific clock data
2789 *
2790 * clk_hw_register is the primary interface for populating the clock tree with
2791 * new clock nodes. It returns an integer equal to zero indicating success or
2792 * less than zero indicating failure. Drivers must test for an error code after
2793 * calling clk_hw_register().
2794 */
2795int clk_hw_register(struct device *dev, struct clk_hw *hw)
2796{
2797 return PTR_ERR_OR_ZERO(clk_register(dev, hw));
2798}
2799EXPORT_SYMBOL_GPL(clk_hw_register);
2800
6e5ab41b 2801/* Free memory allocated for a clock. */
fcb0ee6a
SN
2802static void __clk_release(struct kref *ref)
2803{
d6968fca
SB
2804 struct clk_core *core = container_of(ref, struct clk_core, ref);
2805 int i = core->num_parents;
fcb0ee6a 2806
496eadf8
KK
2807 lockdep_assert_held(&prepare_lock);
2808
d6968fca 2809 kfree(core->parents);
fcb0ee6a 2810 while (--i >= 0)
d6968fca 2811 kfree_const(core->parent_names[i]);
fcb0ee6a 2812
d6968fca
SB
2813 kfree(core->parent_names);
2814 kfree_const(core->name);
2815 kfree(core);
fcb0ee6a
SN
2816}
2817
2818/*
2819 * Empty clk_ops for unregistered clocks. These are used temporarily
2820 * after clk_unregister() was called on a clock and until last clock
2821 * consumer calls clk_put() and the struct clk object is freed.
2822 */
2823static int clk_nodrv_prepare_enable(struct clk_hw *hw)
2824{
2825 return -ENXIO;
2826}
2827
2828static void clk_nodrv_disable_unprepare(struct clk_hw *hw)
2829{
2830 WARN_ON_ONCE(1);
2831}
2832
2833static int clk_nodrv_set_rate(struct clk_hw *hw, unsigned long rate,
2834 unsigned long parent_rate)
2835{
2836 return -ENXIO;
2837}
2838
2839static int clk_nodrv_set_parent(struct clk_hw *hw, u8 index)
2840{
2841 return -ENXIO;
2842}
2843
2844static const struct clk_ops clk_nodrv_ops = {
2845 .enable = clk_nodrv_prepare_enable,
2846 .disable = clk_nodrv_disable_unprepare,
2847 .prepare = clk_nodrv_prepare_enable,
2848 .unprepare = clk_nodrv_disable_unprepare,
2849 .set_rate = clk_nodrv_set_rate,
2850 .set_parent = clk_nodrv_set_parent,
2851};
2852
1df5c939
MB
2853/**
2854 * clk_unregister - unregister a currently registered clock
2855 * @clk: clock to unregister
1df5c939 2856 */
fcb0ee6a
SN
2857void clk_unregister(struct clk *clk)
2858{
2859 unsigned long flags;
2860
6314b679
SB
2861 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
2862 return;
2863
035a61c3 2864 clk_debug_unregister(clk->core);
fcb0ee6a
SN
2865
2866 clk_prepare_lock();
2867
035a61c3
TV
2868 if (clk->core->ops == &clk_nodrv_ops) {
2869 pr_err("%s: unregistered clock: %s\n", __func__,
2870 clk->core->name);
4106a3d9 2871 goto unlock;
fcb0ee6a
SN
2872 }
2873 /*
2874 * Assign empty clock ops for consumers that might still hold
2875 * a reference to this clock.
2876 */
2877 flags = clk_enable_lock();
035a61c3 2878 clk->core->ops = &clk_nodrv_ops;
fcb0ee6a
SN
2879 clk_enable_unlock(flags);
2880
035a61c3
TV
2881 if (!hlist_empty(&clk->core->children)) {
2882 struct clk_core *child;
874f224c 2883 struct hlist_node *t;
fcb0ee6a
SN
2884
2885 /* Reparent all children to the orphan list. */
035a61c3
TV
2886 hlist_for_each_entry_safe(child, t, &clk->core->children,
2887 child_node)
2888 clk_core_set_parent(child, NULL);
fcb0ee6a
SN
2889 }
2890
035a61c3 2891 hlist_del_init(&clk->core->child_node);
fcb0ee6a 2892
035a61c3 2893 if (clk->core->prepare_count)
fcb0ee6a 2894 pr_warn("%s: unregistering prepared clock: %s\n",
035a61c3
TV
2895 __func__, clk->core->name);
2896 kref_put(&clk->core->ref, __clk_release);
4106a3d9 2897unlock:
fcb0ee6a
SN
2898 clk_prepare_unlock();
2899}
1df5c939
MB
2900EXPORT_SYMBOL_GPL(clk_unregister);
2901
4143804c
SB
2902/**
2903 * clk_hw_unregister - unregister a currently registered clk_hw
2904 * @hw: hardware-specific clock data to unregister
2905 */
2906void clk_hw_unregister(struct clk_hw *hw)
2907{
2908 clk_unregister(hw->clk);
2909}
2910EXPORT_SYMBOL_GPL(clk_hw_unregister);
2911
46c8773a
SB
2912static void devm_clk_release(struct device *dev, void *res)
2913{
293ba3b4 2914 clk_unregister(*(struct clk **)res);
46c8773a
SB
2915}
2916
4143804c
SB
2917static void devm_clk_hw_release(struct device *dev, void *res)
2918{
2919 clk_hw_unregister(*(struct clk_hw **)res);
2920}
2921
46c8773a
SB
2922/**
2923 * devm_clk_register - resource managed clk_register()
2924 * @dev: device that is registering this clock
2925 * @hw: link to hardware-specific clock data
2926 *
2927 * Managed clk_register(). Clocks returned from this function are
2928 * automatically clk_unregister()ed on driver detach. See clk_register() for
2929 * more information.
2930 */
2931struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw)
2932{
2933 struct clk *clk;
293ba3b4 2934 struct clk **clkp;
46c8773a 2935
293ba3b4
SB
2936 clkp = devres_alloc(devm_clk_release, sizeof(*clkp), GFP_KERNEL);
2937 if (!clkp)
46c8773a
SB
2938 return ERR_PTR(-ENOMEM);
2939
293ba3b4
SB
2940 clk = clk_register(dev, hw);
2941 if (!IS_ERR(clk)) {
2942 *clkp = clk;
2943 devres_add(dev, clkp);
46c8773a 2944 } else {
293ba3b4 2945 devres_free(clkp);
46c8773a
SB
2946 }
2947
2948 return clk;
2949}
2950EXPORT_SYMBOL_GPL(devm_clk_register);
2951
4143804c
SB
2952/**
2953 * devm_clk_hw_register - resource managed clk_hw_register()
2954 * @dev: device that is registering this clock
2955 * @hw: link to hardware-specific clock data
2956 *
c47265ad 2957 * Managed clk_hw_register(). Clocks registered by this function are
4143804c
SB
2958 * automatically clk_hw_unregister()ed on driver detach. See clk_hw_register()
2959 * for more information.
2960 */
2961int devm_clk_hw_register(struct device *dev, struct clk_hw *hw)
2962{
2963 struct clk_hw **hwp;
2964 int ret;
2965
2966 hwp = devres_alloc(devm_clk_hw_release, sizeof(*hwp), GFP_KERNEL);
2967 if (!hwp)
2968 return -ENOMEM;
2969
2970 ret = clk_hw_register(dev, hw);
2971 if (!ret) {
2972 *hwp = hw;
2973 devres_add(dev, hwp);
2974 } else {
2975 devres_free(hwp);
2976 }
2977
2978 return ret;
2979}
2980EXPORT_SYMBOL_GPL(devm_clk_hw_register);
2981
46c8773a
SB
2982static int devm_clk_match(struct device *dev, void *res, void *data)
2983{
2984 struct clk *c = res;
2985 if (WARN_ON(!c))
2986 return 0;
2987 return c == data;
2988}
2989
4143804c
SB
2990static int devm_clk_hw_match(struct device *dev, void *res, void *data)
2991{
2992 struct clk_hw *hw = res;
2993
2994 if (WARN_ON(!hw))
2995 return 0;
2996 return hw == data;
2997}
2998
46c8773a
SB
2999/**
3000 * devm_clk_unregister - resource managed clk_unregister()
3001 * @clk: clock to unregister
3002 *
3003 * Deallocate a clock allocated with devm_clk_register(). Normally
3004 * this function will not need to be called and the resource management
3005 * code will ensure that the resource is freed.
3006 */
3007void devm_clk_unregister(struct device *dev, struct clk *clk)
3008{
3009 WARN_ON(devres_release(dev, devm_clk_release, devm_clk_match, clk));
3010}
3011EXPORT_SYMBOL_GPL(devm_clk_unregister);
3012
4143804c
SB
3013/**
3014 * devm_clk_hw_unregister - resource managed clk_hw_unregister()
3015 * @dev: device that is unregistering the hardware-specific clock data
3016 * @hw: link to hardware-specific clock data
3017 *
3018 * Unregister a clk_hw registered with devm_clk_hw_register(). Normally
3019 * this function will not need to be called and the resource management
3020 * code will ensure that the resource is freed.
3021 */
3022void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw)
3023{
3024 WARN_ON(devres_release(dev, devm_clk_hw_release, devm_clk_hw_match,
3025 hw));
3026}
3027EXPORT_SYMBOL_GPL(devm_clk_hw_unregister);
3028
ac2df527
SN
3029/*
3030 * clkdev helpers
3031 */
3032int __clk_get(struct clk *clk)
3033{
035a61c3
TV
3034 struct clk_core *core = !clk ? NULL : clk->core;
3035
3036 if (core) {
3037 if (!try_module_get(core->owner))
00efcb1c 3038 return 0;
ac2df527 3039
035a61c3 3040 kref_get(&core->ref);
00efcb1c 3041 }
ac2df527
SN
3042 return 1;
3043}
3044
3045void __clk_put(struct clk *clk)
3046{
10cdfe54
TV
3047 struct module *owner;
3048
00efcb1c 3049 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
ac2df527
SN
3050 return;
3051
fcb0ee6a 3052 clk_prepare_lock();
1c8e6004 3053
50595f8b 3054 hlist_del(&clk->clks_node);
ec02ace8
TV
3055 if (clk->min_rate > clk->core->req_rate ||
3056 clk->max_rate < clk->core->req_rate)
3057 clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
3058
1c8e6004
TV
3059 owner = clk->core->owner;
3060 kref_put(&clk->core->ref, __clk_release);
3061
fcb0ee6a
SN
3062 clk_prepare_unlock();
3063
10cdfe54 3064 module_put(owner);
035a61c3 3065
035a61c3 3066 kfree(clk);
ac2df527
SN
3067}
3068
b2476490
MT
3069/*** clk rate change notifiers ***/
3070
3071/**
3072 * clk_notifier_register - add a clk rate change notifier
3073 * @clk: struct clk * to watch
3074 * @nb: struct notifier_block * with callback info
3075 *
3076 * Request notification when clk's rate changes. This uses an SRCU
3077 * notifier because we want it to block and notifier unregistrations are
3078 * uncommon. The callbacks associated with the notifier must not
3079 * re-enter into the clk framework by calling any top-level clk APIs;
3080 * this will cause a nested prepare_lock mutex.
3081 *
198bb594
MY
3082 * In all notification cases (pre, post and abort rate change) the original
3083 * clock rate is passed to the callback via struct clk_notifier_data.old_rate
3084 * and the new frequency is passed via struct clk_notifier_data.new_rate.
b2476490 3085 *
b2476490
MT
3086 * clk_notifier_register() must be called from non-atomic context.
3087 * Returns -EINVAL if called with null arguments, -ENOMEM upon
3088 * allocation failure; otherwise, passes along the return value of
3089 * srcu_notifier_chain_register().
3090 */
3091int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
3092{
3093 struct clk_notifier *cn;
3094 int ret = -ENOMEM;
3095
3096 if (!clk || !nb)
3097 return -EINVAL;
3098
eab89f69 3099 clk_prepare_lock();
b2476490
MT
3100
3101 /* search the list of notifiers for this clk */
3102 list_for_each_entry(cn, &clk_notifier_list, node)
3103 if (cn->clk == clk)
3104 break;
3105
3106 /* if clk wasn't in the notifier list, allocate new clk_notifier */
3107 if (cn->clk != clk) {
1808a320 3108 cn = kzalloc(sizeof(*cn), GFP_KERNEL);
b2476490
MT
3109 if (!cn)
3110 goto out;
3111
3112 cn->clk = clk;
3113 srcu_init_notifier_head(&cn->notifier_head);
3114
3115 list_add(&cn->node, &clk_notifier_list);
3116 }
3117
3118 ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
3119
035a61c3 3120 clk->core->notifier_count++;
b2476490
MT
3121
3122out:
eab89f69 3123 clk_prepare_unlock();
b2476490
MT
3124
3125 return ret;
3126}
3127EXPORT_SYMBOL_GPL(clk_notifier_register);
3128
3129/**
3130 * clk_notifier_unregister - remove a clk rate change notifier
3131 * @clk: struct clk *
3132 * @nb: struct notifier_block * with callback info
3133 *
3134 * Request no further notification for changes to 'clk' and frees memory
3135 * allocated in clk_notifier_register.
3136 *
3137 * Returns -EINVAL if called with null arguments; otherwise, passes
3138 * along the return value of srcu_notifier_chain_unregister().
3139 */
3140int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
3141{
3142 struct clk_notifier *cn = NULL;
3143 int ret = -EINVAL;
3144
3145 if (!clk || !nb)
3146 return -EINVAL;
3147
eab89f69 3148 clk_prepare_lock();
b2476490
MT
3149
3150 list_for_each_entry(cn, &clk_notifier_list, node)
3151 if (cn->clk == clk)
3152 break;
3153
3154 if (cn->clk == clk) {
3155 ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
3156
035a61c3 3157 clk->core->notifier_count--;
b2476490
MT
3158
3159 /* XXX the notifier code should handle this better */
3160 if (!cn->notifier_head.head) {
3161 srcu_cleanup_notifier_head(&cn->notifier_head);
72b5322f 3162 list_del(&cn->node);
b2476490
MT
3163 kfree(cn);
3164 }
3165
3166 } else {
3167 ret = -ENOENT;
3168 }
3169
eab89f69 3170 clk_prepare_unlock();
b2476490
MT
3171
3172 return ret;
3173}
3174EXPORT_SYMBOL_GPL(clk_notifier_unregister);
766e6a4e
GL
3175
3176#ifdef CONFIG_OF
3177/**
3178 * struct of_clk_provider - Clock provider registration structure
3179 * @link: Entry in global list of clock providers
3180 * @node: Pointer to device tree node of clock provider
3181 * @get: Get clock callback. Returns NULL or a struct clk for the
3182 * given clock specifier
3183 * @data: context pointer to be passed into @get callback
3184 */
3185struct of_clk_provider {
3186 struct list_head link;
3187
3188 struct device_node *node;
3189 struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
0861e5b8 3190 struct clk_hw *(*get_hw)(struct of_phandle_args *clkspec, void *data);
766e6a4e
GL
3191 void *data;
3192};
3193
f2f6c255
PG
3194static const struct of_device_id __clk_of_table_sentinel
3195 __used __section(__clk_of_table_end);
3196
766e6a4e 3197static LIST_HEAD(of_clk_providers);
d6782c26
SN
3198static DEFINE_MUTEX(of_clk_mutex);
3199
766e6a4e
GL
3200struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
3201 void *data)
3202{
3203 return data;
3204}
3205EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
3206
0861e5b8
SB
3207struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
3208{
3209 return data;
3210}
3211EXPORT_SYMBOL_GPL(of_clk_hw_simple_get);
3212
494bfec9
SG
3213struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
3214{
3215 struct clk_onecell_data *clk_data = data;
3216 unsigned int idx = clkspec->args[0];
3217
3218 if (idx >= clk_data->clk_num) {
7e96353c 3219 pr_err("%s: invalid clock index %u\n", __func__, idx);
494bfec9
SG
3220 return ERR_PTR(-EINVAL);
3221 }
3222
3223 return clk_data->clks[idx];
3224}
3225EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
3226
0861e5b8
SB
3227struct clk_hw *
3228of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
3229{
3230 struct clk_hw_onecell_data *hw_data = data;
3231 unsigned int idx = clkspec->args[0];
3232
3233 if (idx >= hw_data->num) {
3234 pr_err("%s: invalid index %u\n", __func__, idx);
3235 return ERR_PTR(-EINVAL);
3236 }
3237
3238 return hw_data->hws[idx];
3239}
3240EXPORT_SYMBOL_GPL(of_clk_hw_onecell_get);
3241
766e6a4e
GL
3242/**
3243 * of_clk_add_provider() - Register a clock provider for a node
3244 * @np: Device node pointer associated with clock provider
3245 * @clk_src_get: callback for decoding clock
3246 * @data: context pointer for @clk_src_get callback.
3247 */
3248int of_clk_add_provider(struct device_node *np,
3249 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
3250 void *data),
3251 void *data)
3252{
3253 struct of_clk_provider *cp;
86be408b 3254 int ret;
766e6a4e 3255
1808a320 3256 cp = kzalloc(sizeof(*cp), GFP_KERNEL);
766e6a4e
GL
3257 if (!cp)
3258 return -ENOMEM;
3259
3260 cp->node = of_node_get(np);
3261 cp->data = data;
3262 cp->get = clk_src_get;
3263
d6782c26 3264 mutex_lock(&of_clk_mutex);
766e6a4e 3265 list_add(&cp->link, &of_clk_providers);
d6782c26 3266 mutex_unlock(&of_clk_mutex);
16673931 3267 pr_debug("Added clock from %pOF\n", np);
766e6a4e 3268
86be408b
SN
3269 ret = of_clk_set_defaults(np, true);
3270 if (ret < 0)
3271 of_clk_del_provider(np);
3272
3273 return ret;
766e6a4e
GL
3274}
3275EXPORT_SYMBOL_GPL(of_clk_add_provider);
3276
0861e5b8
SB
3277/**
3278 * of_clk_add_hw_provider() - Register a clock provider for a node
3279 * @np: Device node pointer associated with clock provider
3280 * @get: callback for decoding clk_hw
3281 * @data: context pointer for @get callback.
3282 */
3283int of_clk_add_hw_provider(struct device_node *np,
3284 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
3285 void *data),
3286 void *data)
3287{
3288 struct of_clk_provider *cp;
3289 int ret;
3290
3291 cp = kzalloc(sizeof(*cp), GFP_KERNEL);
3292 if (!cp)
3293 return -ENOMEM;
3294
3295 cp->node = of_node_get(np);
3296 cp->data = data;
3297 cp->get_hw = get;
3298
3299 mutex_lock(&of_clk_mutex);
3300 list_add(&cp->link, &of_clk_providers);
3301 mutex_unlock(&of_clk_mutex);
16673931 3302 pr_debug("Added clk_hw provider from %pOF\n", np);
0861e5b8
SB
3303
3304 ret = of_clk_set_defaults(np, true);
3305 if (ret < 0)
3306 of_clk_del_provider(np);
3307
3308 return ret;
3309}
3310EXPORT_SYMBOL_GPL(of_clk_add_hw_provider);
3311
aa795c41
SB
3312static void devm_of_clk_release_provider(struct device *dev, void *res)
3313{
3314 of_clk_del_provider(*(struct device_node **)res);
3315}
3316
3317int devm_of_clk_add_hw_provider(struct device *dev,
3318 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
3319 void *data),
3320 void *data)
3321{
3322 struct device_node **ptr, *np;
3323 int ret;
3324
3325 ptr = devres_alloc(devm_of_clk_release_provider, sizeof(*ptr),
3326 GFP_KERNEL);
3327 if (!ptr)
3328 return -ENOMEM;
3329
3330 np = dev->of_node;
3331 ret = of_clk_add_hw_provider(np, get, data);
3332 if (!ret) {
3333 *ptr = np;
3334 devres_add(dev, ptr);
3335 } else {
3336 devres_free(ptr);
3337 }
3338
3339 return ret;
3340}
3341EXPORT_SYMBOL_GPL(devm_of_clk_add_hw_provider);
3342
766e6a4e
GL
3343/**
3344 * of_clk_del_provider() - Remove a previously registered clock provider
3345 * @np: Device node pointer associated with clock provider
3346 */
3347void of_clk_del_provider(struct device_node *np)
3348{
3349 struct of_clk_provider *cp;
3350
d6782c26 3351 mutex_lock(&of_clk_mutex);
766e6a4e
GL
3352 list_for_each_entry(cp, &of_clk_providers, link) {
3353 if (cp->node == np) {
3354 list_del(&cp->link);
3355 of_node_put(cp->node);
3356 kfree(cp);
3357 break;
3358 }
3359 }
d6782c26 3360 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
3361}
3362EXPORT_SYMBOL_GPL(of_clk_del_provider);
3363
aa795c41
SB
3364static int devm_clk_provider_match(struct device *dev, void *res, void *data)
3365{
3366 struct device_node **np = res;
3367
3368 if (WARN_ON(!np || !*np))
3369 return 0;
3370
3371 return *np == data;
3372}
3373
3374void devm_of_clk_del_provider(struct device *dev)
3375{
3376 int ret;
3377
3378 ret = devres_release(dev, devm_of_clk_release_provider,
3379 devm_clk_provider_match, dev->of_node);
3380
3381 WARN_ON(ret);
3382}
3383EXPORT_SYMBOL(devm_of_clk_del_provider);
3384
0861e5b8
SB
3385static struct clk_hw *
3386__of_clk_get_hw_from_provider(struct of_clk_provider *provider,
3387 struct of_phandle_args *clkspec)
3388{
3389 struct clk *clk;
0861e5b8 3390
74002fcd
SB
3391 if (provider->get_hw)
3392 return provider->get_hw(clkspec, provider->data);
0861e5b8 3393
74002fcd
SB
3394 clk = provider->get(clkspec, provider->data);
3395 if (IS_ERR(clk))
3396 return ERR_CAST(clk);
3397 return __clk_get_hw(clk);
0861e5b8
SB
3398}
3399
73e0e496
SB
3400struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
3401 const char *dev_id, const char *con_id)
766e6a4e
GL
3402{
3403 struct of_clk_provider *provider;
a34cd466 3404 struct clk *clk = ERR_PTR(-EPROBE_DEFER);
f155d15b 3405 struct clk_hw *hw;
766e6a4e 3406
306c342f
SB
3407 if (!clkspec)
3408 return ERR_PTR(-EINVAL);
3409
766e6a4e 3410 /* Check if we have such a provider in our array */
306c342f 3411 mutex_lock(&of_clk_mutex);
766e6a4e 3412 list_for_each_entry(provider, &of_clk_providers, link) {
f155d15b 3413 if (provider->node == clkspec->np) {
0861e5b8 3414 hw = __of_clk_get_hw_from_provider(provider, clkspec);
0861e5b8 3415 clk = __clk_create_clk(hw, dev_id, con_id);
f155d15b 3416 }
73e0e496 3417
f155d15b
SB
3418 if (!IS_ERR(clk)) {
3419 if (!__clk_get(clk)) {
73e0e496
SB
3420 __clk_free_clk(clk);
3421 clk = ERR_PTR(-ENOENT);
3422 }
3423
766e6a4e 3424 break;
73e0e496 3425 }
766e6a4e 3426 }
306c342f 3427 mutex_unlock(&of_clk_mutex);
d6782c26
SN
3428
3429 return clk;
3430}
3431
306c342f
SB
3432/**
3433 * of_clk_get_from_provider() - Lookup a clock from a clock provider
3434 * @clkspec: pointer to a clock specifier data structure
3435 *
3436 * This function looks up a struct clk from the registered list of clock
3437 * providers, an input is a clock specifier data structure as returned
3438 * from the of_parse_phandle_with_args() function call.
3439 */
d6782c26
SN
3440struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
3441{
306c342f 3442 return __of_clk_get_from_provider(clkspec, NULL, __func__);
766e6a4e 3443}
fb4dd222 3444EXPORT_SYMBOL_GPL(of_clk_get_from_provider);
766e6a4e 3445
929e7f3b
SB
3446/**
3447 * of_clk_get_parent_count() - Count the number of clocks a device node has
3448 * @np: device node to count
3449 *
3450 * Returns: The number of clocks that are possible parents of this node
3451 */
3452unsigned int of_clk_get_parent_count(struct device_node *np)
f6102742 3453{
929e7f3b
SB
3454 int count;
3455
3456 count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
3457 if (count < 0)
3458 return 0;
3459
3460 return count;
f6102742
MT
3461}
3462EXPORT_SYMBOL_GPL(of_clk_get_parent_count);
3463
766e6a4e
GL
3464const char *of_clk_get_parent_name(struct device_node *np, int index)
3465{
3466 struct of_phandle_args clkspec;
7a0fc1a3 3467 struct property *prop;
766e6a4e 3468 const char *clk_name;
7a0fc1a3
BD
3469 const __be32 *vp;
3470 u32 pv;
766e6a4e 3471 int rc;
7a0fc1a3 3472 int count;
0a4807c2 3473 struct clk *clk;
766e6a4e 3474
766e6a4e
GL
3475 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
3476 &clkspec);
3477 if (rc)
3478 return NULL;
3479
7a0fc1a3
BD
3480 index = clkspec.args_count ? clkspec.args[0] : 0;
3481 count = 0;
3482
3483 /* if there is an indices property, use it to transfer the index
3484 * specified into an array offset for the clock-output-names property.
3485 */
3486 of_property_for_each_u32(clkspec.np, "clock-indices", prop, vp, pv) {
3487 if (index == pv) {
3488 index = count;
3489 break;
3490 }
3491 count++;
3492 }
8da411cc
MY
3493 /* We went off the end of 'clock-indices' without finding it */
3494 if (prop && !vp)
3495 return NULL;
7a0fc1a3 3496
766e6a4e 3497 if (of_property_read_string_index(clkspec.np, "clock-output-names",
7a0fc1a3 3498 index,
0a4807c2
SB
3499 &clk_name) < 0) {
3500 /*
3501 * Best effort to get the name if the clock has been
3502 * registered with the framework. If the clock isn't
3503 * registered, we return the node name as the name of
3504 * the clock as long as #clock-cells = 0.
3505 */
3506 clk = of_clk_get_from_provider(&clkspec);
3507 if (IS_ERR(clk)) {
3508 if (clkspec.args_count == 0)
3509 clk_name = clkspec.np->name;
3510 else
3511 clk_name = NULL;
3512 } else {
3513 clk_name = __clk_get_name(clk);
3514 clk_put(clk);
3515 }
3516 }
3517
766e6a4e
GL
3518
3519 of_node_put(clkspec.np);
3520 return clk_name;
3521}
3522EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
3523
2e61dfb3
DN
3524/**
3525 * of_clk_parent_fill() - Fill @parents with names of @np's parents and return
3526 * number of parents
3527 * @np: Device node pointer associated with clock provider
3528 * @parents: pointer to char array that hold the parents' names
3529 * @size: size of the @parents array
3530 *
3531 * Return: number of parents for the clock node.
3532 */
3533int of_clk_parent_fill(struct device_node *np, const char **parents,
3534 unsigned int size)
3535{
3536 unsigned int i = 0;
3537
3538 while (i < size && (parents[i] = of_clk_get_parent_name(np, i)) != NULL)
3539 i++;
3540
3541 return i;
3542}
3543EXPORT_SYMBOL_GPL(of_clk_parent_fill);
3544
1771b10d
GC
3545struct clock_provider {
3546 of_clk_init_cb_t clk_init_cb;
3547 struct device_node *np;
3548 struct list_head node;
3549};
3550
1771b10d
GC
3551/*
3552 * This function looks for a parent clock. If there is one, then it
3553 * checks that the provider for this parent clock was initialized, in
3554 * this case the parent clock will be ready.
3555 */
3556static int parent_ready(struct device_node *np)
3557{
3558 int i = 0;
3559
3560 while (true) {
3561 struct clk *clk = of_clk_get(np, i);
3562
3563 /* this parent is ready we can check the next one */
3564 if (!IS_ERR(clk)) {
3565 clk_put(clk);
3566 i++;
3567 continue;
3568 }
3569
3570 /* at least one parent is not ready, we exit now */
3571 if (PTR_ERR(clk) == -EPROBE_DEFER)
3572 return 0;
3573
3574 /*
3575 * Here we make assumption that the device tree is
3576 * written correctly. So an error means that there is
3577 * no more parent. As we didn't exit yet, then the
3578 * previous parent are ready. If there is no clock
3579 * parent, no need to wait for them, then we can
3580 * consider their absence as being ready
3581 */
3582 return 1;
3583 }
3584}
3585
d56f8994
LJ
3586/**
3587 * of_clk_detect_critical() - set CLK_IS_CRITICAL flag from Device Tree
3588 * @np: Device node pointer associated with clock provider
3589 * @index: clock index
3590 * @flags: pointer to clk_core->flags
3591 *
3592 * Detects if the clock-critical property exists and, if so, sets the
3593 * corresponding CLK_IS_CRITICAL flag.
3594 *
3595 * Do not use this function. It exists only for legacy Device Tree
3596 * bindings, such as the one-clock-per-node style that are outdated.
3597 * Those bindings typically put all clock data into .dts and the Linux
3598 * driver has no clock data, thus making it impossible to set this flag
3599 * correctly from the driver. Only those drivers may call
3600 * of_clk_detect_critical from their setup functions.
3601 *
3602 * Return: error code or zero on success
3603 */
3604int of_clk_detect_critical(struct device_node *np,
3605 int index, unsigned long *flags)
3606{
3607 struct property *prop;
3608 const __be32 *cur;
3609 uint32_t idx;
3610
3611 if (!np || !flags)
3612 return -EINVAL;
3613
3614 of_property_for_each_u32(np, "clock-critical", prop, cur, idx)
3615 if (index == idx)
3616 *flags |= CLK_IS_CRITICAL;
3617
3618 return 0;
3619}
3620
766e6a4e
GL
3621/**
3622 * of_clk_init() - Scan and init clock providers from the DT
3623 * @matches: array of compatible values and init functions for providers.
3624 *
1771b10d 3625 * This function scans the device tree for matching clock providers
e5ca8fb4 3626 * and calls their initialization functions. It also does it by trying
1771b10d 3627 * to follow the dependencies.
766e6a4e
GL
3628 */
3629void __init of_clk_init(const struct of_device_id *matches)
3630{
7f7ed584 3631 const struct of_device_id *match;
766e6a4e 3632 struct device_node *np;
1771b10d
GC
3633 struct clock_provider *clk_provider, *next;
3634 bool is_init_done;
3635 bool force = false;
2573a02a 3636 LIST_HEAD(clk_provider_list);
766e6a4e 3637
f2f6c255 3638 if (!matches)
819b4861 3639 matches = &__clk_of_table;
f2f6c255 3640
1771b10d 3641 /* First prepare the list of the clocks providers */
7f7ed584 3642 for_each_matching_node_and_match(np, matches, &match) {
2e3b19f1
SB
3643 struct clock_provider *parent;
3644
3e5dd6f6
GU
3645 if (!of_device_is_available(np))
3646 continue;
3647
2e3b19f1
SB
3648 parent = kzalloc(sizeof(*parent), GFP_KERNEL);
3649 if (!parent) {
3650 list_for_each_entry_safe(clk_provider, next,
3651 &clk_provider_list, node) {
3652 list_del(&clk_provider->node);
6bc9d9d6 3653 of_node_put(clk_provider->np);
2e3b19f1
SB
3654 kfree(clk_provider);
3655 }
6bc9d9d6 3656 of_node_put(np);
2e3b19f1
SB
3657 return;
3658 }
1771b10d
GC
3659
3660 parent->clk_init_cb = match->data;
6bc9d9d6 3661 parent->np = of_node_get(np);
3f6d439f 3662 list_add_tail(&parent->node, &clk_provider_list);
1771b10d
GC
3663 }
3664
3665 while (!list_empty(&clk_provider_list)) {
3666 is_init_done = false;
3667 list_for_each_entry_safe(clk_provider, next,
3668 &clk_provider_list, node) {
3669 if (force || parent_ready(clk_provider->np)) {
86be408b 3670
989eafd0
RRD
3671 /* Don't populate platform devices */
3672 of_node_set_flag(clk_provider->np,
3673 OF_POPULATED);
3674
1771b10d 3675 clk_provider->clk_init_cb(clk_provider->np);
86be408b
SN
3676 of_clk_set_defaults(clk_provider->np, true);
3677
1771b10d 3678 list_del(&clk_provider->node);
6bc9d9d6 3679 of_node_put(clk_provider->np);
1771b10d
GC
3680 kfree(clk_provider);
3681 is_init_done = true;
3682 }
3683 }
3684
3685 /*
e5ca8fb4 3686 * We didn't manage to initialize any of the
1771b10d
GC
3687 * remaining providers during the last loop, so now we
3688 * initialize all the remaining ones unconditionally
3689 * in case the clock parent was not mandatory
3690 */
3691 if (!is_init_done)
3692 force = true;
766e6a4e
GL
3693 }
3694}
3695#endif