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CommitLineData
b2476490
MT
1/*
2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Standard functionality for the common clock API. See Documentation/clk.txt
10 */
11
3c373117 12#include <linux/clk.h>
b09d6d99 13#include <linux/clk-provider.h>
86be408b 14#include <linux/clk/clk-conf.h>
b2476490
MT
15#include <linux/module.h>
16#include <linux/mutex.h>
17#include <linux/spinlock.h>
18#include <linux/err.h>
19#include <linux/list.h>
20#include <linux/slab.h>
766e6a4e 21#include <linux/of.h>
46c8773a 22#include <linux/device.h>
f2f6c255 23#include <linux/init.h>
533ddeb1 24#include <linux/sched.h>
562ef0b0 25#include <linux/clkdev.h>
b2476490 26
d6782c26
SN
27#include "clk.h"
28
b2476490
MT
29static DEFINE_SPINLOCK(enable_lock);
30static DEFINE_MUTEX(prepare_lock);
31
533ddeb1
MT
32static struct task_struct *prepare_owner;
33static struct task_struct *enable_owner;
34
35static int prepare_refcnt;
36static int enable_refcnt;
37
b2476490
MT
38static HLIST_HEAD(clk_root_list);
39static HLIST_HEAD(clk_orphan_list);
40static LIST_HEAD(clk_notifier_list);
41
b09d6d99
MT
42/*** private data structures ***/
43
44struct clk_core {
45 const char *name;
46 const struct clk_ops *ops;
47 struct clk_hw *hw;
48 struct module *owner;
49 struct clk_core *parent;
50 const char **parent_names;
51 struct clk_core **parents;
52 u8 num_parents;
53 u8 new_parent_index;
54 unsigned long rate;
1c8e6004 55 unsigned long req_rate;
b09d6d99
MT
56 unsigned long new_rate;
57 struct clk_core *new_parent;
58 struct clk_core *new_child;
59 unsigned long flags;
e6500344 60 bool orphan;
b09d6d99
MT
61 unsigned int enable_count;
62 unsigned int prepare_count;
9783c0d9
SB
63 unsigned long min_rate;
64 unsigned long max_rate;
b09d6d99
MT
65 unsigned long accuracy;
66 int phase;
67 struct hlist_head children;
68 struct hlist_node child_node;
1c8e6004 69 struct hlist_head clks;
b09d6d99
MT
70 unsigned int notifier_count;
71#ifdef CONFIG_DEBUG_FS
72 struct dentry *dentry;
8c9a8a8f 73 struct hlist_node debug_node;
b09d6d99
MT
74#endif
75 struct kref ref;
76};
77
dfc202ea
SB
78#define CREATE_TRACE_POINTS
79#include <trace/events/clk.h>
80
b09d6d99
MT
81struct clk {
82 struct clk_core *core;
83 const char *dev_id;
84 const char *con_id;
1c8e6004
TV
85 unsigned long min_rate;
86 unsigned long max_rate;
50595f8b 87 struct hlist_node clks_node;
b09d6d99
MT
88};
89
eab89f69
MT
90/*** locking ***/
91static void clk_prepare_lock(void)
92{
533ddeb1
MT
93 if (!mutex_trylock(&prepare_lock)) {
94 if (prepare_owner == current) {
95 prepare_refcnt++;
96 return;
97 }
98 mutex_lock(&prepare_lock);
99 }
100 WARN_ON_ONCE(prepare_owner != NULL);
101 WARN_ON_ONCE(prepare_refcnt != 0);
102 prepare_owner = current;
103 prepare_refcnt = 1;
eab89f69
MT
104}
105
106static void clk_prepare_unlock(void)
107{
533ddeb1
MT
108 WARN_ON_ONCE(prepare_owner != current);
109 WARN_ON_ONCE(prepare_refcnt == 0);
110
111 if (--prepare_refcnt)
112 return;
113 prepare_owner = NULL;
eab89f69
MT
114 mutex_unlock(&prepare_lock);
115}
116
117static unsigned long clk_enable_lock(void)
a57aa185 118 __acquires(enable_lock)
eab89f69
MT
119{
120 unsigned long flags;
533ddeb1
MT
121
122 if (!spin_trylock_irqsave(&enable_lock, flags)) {
123 if (enable_owner == current) {
124 enable_refcnt++;
a57aa185 125 __acquire(enable_lock);
533ddeb1
MT
126 return flags;
127 }
128 spin_lock_irqsave(&enable_lock, flags);
129 }
130 WARN_ON_ONCE(enable_owner != NULL);
131 WARN_ON_ONCE(enable_refcnt != 0);
132 enable_owner = current;
133 enable_refcnt = 1;
eab89f69
MT
134 return flags;
135}
136
137static void clk_enable_unlock(unsigned long flags)
a57aa185 138 __releases(enable_lock)
eab89f69 139{
533ddeb1
MT
140 WARN_ON_ONCE(enable_owner != current);
141 WARN_ON_ONCE(enable_refcnt == 0);
142
a57aa185
SB
143 if (--enable_refcnt) {
144 __release(enable_lock);
533ddeb1 145 return;
a57aa185 146 }
533ddeb1 147 enable_owner = NULL;
eab89f69
MT
148 spin_unlock_irqrestore(&enable_lock, flags);
149}
150
4dff95dc
SB
151static bool clk_core_is_prepared(struct clk_core *core)
152{
153 /*
154 * .is_prepared is optional for clocks that can prepare
155 * fall back to software usage counter if it is missing
156 */
157 if (!core->ops->is_prepared)
158 return core->prepare_count;
b2476490 159
4dff95dc
SB
160 return core->ops->is_prepared(core->hw);
161}
b2476490 162
4dff95dc
SB
163static bool clk_core_is_enabled(struct clk_core *core)
164{
165 /*
166 * .is_enabled is only mandatory for clocks that gate
167 * fall back to software usage counter if .is_enabled is missing
168 */
169 if (!core->ops->is_enabled)
170 return core->enable_count;
6b44c854 171
4dff95dc
SB
172 return core->ops->is_enabled(core->hw);
173}
6b44c854 174
4dff95dc 175static void clk_unprepare_unused_subtree(struct clk_core *core)
1af599df 176{
4dff95dc
SB
177 struct clk_core *child;
178
179 lockdep_assert_held(&prepare_lock);
180
181 hlist_for_each_entry(child, &core->children, child_node)
182 clk_unprepare_unused_subtree(child);
183
184 if (core->prepare_count)
1af599df
PG
185 return;
186
4dff95dc
SB
187 if (core->flags & CLK_IGNORE_UNUSED)
188 return;
189
190 if (clk_core_is_prepared(core)) {
191 trace_clk_unprepare(core);
192 if (core->ops->unprepare_unused)
193 core->ops->unprepare_unused(core->hw);
194 else if (core->ops->unprepare)
195 core->ops->unprepare(core->hw);
196 trace_clk_unprepare_complete(core);
197 }
1af599df
PG
198}
199
4dff95dc 200static void clk_disable_unused_subtree(struct clk_core *core)
1af599df 201{
035a61c3 202 struct clk_core *child;
4dff95dc 203 unsigned long flags;
1af599df 204
4dff95dc 205 lockdep_assert_held(&prepare_lock);
1af599df 206
4dff95dc
SB
207 hlist_for_each_entry(child, &core->children, child_node)
208 clk_disable_unused_subtree(child);
1af599df 209
4dff95dc
SB
210 flags = clk_enable_lock();
211
212 if (core->enable_count)
213 goto unlock_out;
214
215 if (core->flags & CLK_IGNORE_UNUSED)
216 goto unlock_out;
217
218 /*
219 * some gate clocks have special needs during the disable-unused
220 * sequence. call .disable_unused if available, otherwise fall
221 * back to .disable
222 */
223 if (clk_core_is_enabled(core)) {
224 trace_clk_disable(core);
225 if (core->ops->disable_unused)
226 core->ops->disable_unused(core->hw);
227 else if (core->ops->disable)
228 core->ops->disable(core->hw);
229 trace_clk_disable_complete(core);
230 }
231
232unlock_out:
233 clk_enable_unlock(flags);
1af599df
PG
234}
235
4dff95dc
SB
236static bool clk_ignore_unused;
237static int __init clk_ignore_unused_setup(char *__unused)
1af599df 238{
4dff95dc
SB
239 clk_ignore_unused = true;
240 return 1;
241}
242__setup("clk_ignore_unused", clk_ignore_unused_setup);
1af599df 243
4dff95dc
SB
244static int clk_disable_unused(void)
245{
246 struct clk_core *core;
247
248 if (clk_ignore_unused) {
249 pr_warn("clk: Not disabling unused clocks\n");
250 return 0;
251 }
1af599df 252
eab89f69 253 clk_prepare_lock();
1af599df 254
4dff95dc
SB
255 hlist_for_each_entry(core, &clk_root_list, child_node)
256 clk_disable_unused_subtree(core);
257
258 hlist_for_each_entry(core, &clk_orphan_list, child_node)
259 clk_disable_unused_subtree(core);
260
261 hlist_for_each_entry(core, &clk_root_list, child_node)
262 clk_unprepare_unused_subtree(core);
263
264 hlist_for_each_entry(core, &clk_orphan_list, child_node)
265 clk_unprepare_unused_subtree(core);
1af599df 266
eab89f69 267 clk_prepare_unlock();
1af599df
PG
268
269 return 0;
270}
4dff95dc 271late_initcall_sync(clk_disable_unused);
1af599df 272
4dff95dc 273/*** helper functions ***/
1af599df 274
b76281cb 275const char *__clk_get_name(const struct clk *clk)
1af599df 276{
4dff95dc 277 return !clk ? NULL : clk->core->name;
1af599df 278}
4dff95dc 279EXPORT_SYMBOL_GPL(__clk_get_name);
1af599df 280
e7df6f6e 281const char *clk_hw_get_name(const struct clk_hw *hw)
1a9c069c
SB
282{
283 return hw->core->name;
284}
285EXPORT_SYMBOL_GPL(clk_hw_get_name);
286
4dff95dc
SB
287struct clk_hw *__clk_get_hw(struct clk *clk)
288{
289 return !clk ? NULL : clk->core->hw;
290}
291EXPORT_SYMBOL_GPL(__clk_get_hw);
1af599df 292
e7df6f6e 293unsigned int clk_hw_get_num_parents(const struct clk_hw *hw)
1a9c069c
SB
294{
295 return hw->core->num_parents;
296}
297EXPORT_SYMBOL_GPL(clk_hw_get_num_parents);
298
e7df6f6e 299struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw)
1a9c069c
SB
300{
301 return hw->core->parent ? hw->core->parent->hw : NULL;
302}
303EXPORT_SYMBOL_GPL(clk_hw_get_parent);
304
4dff95dc
SB
305static struct clk_core *__clk_lookup_subtree(const char *name,
306 struct clk_core *core)
bddca894 307{
035a61c3 308 struct clk_core *child;
4dff95dc 309 struct clk_core *ret;
bddca894 310
4dff95dc
SB
311 if (!strcmp(core->name, name))
312 return core;
bddca894 313
4dff95dc
SB
314 hlist_for_each_entry(child, &core->children, child_node) {
315 ret = __clk_lookup_subtree(name, child);
316 if (ret)
317 return ret;
bddca894
PG
318 }
319
4dff95dc 320 return NULL;
bddca894
PG
321}
322
4dff95dc 323static struct clk_core *clk_core_lookup(const char *name)
bddca894 324{
4dff95dc
SB
325 struct clk_core *root_clk;
326 struct clk_core *ret;
bddca894 327
4dff95dc
SB
328 if (!name)
329 return NULL;
bddca894 330
4dff95dc
SB
331 /* search the 'proper' clk tree first */
332 hlist_for_each_entry(root_clk, &clk_root_list, child_node) {
333 ret = __clk_lookup_subtree(name, root_clk);
334 if (ret)
335 return ret;
bddca894
PG
336 }
337
4dff95dc
SB
338 /* if not found, then search the orphan tree */
339 hlist_for_each_entry(root_clk, &clk_orphan_list, child_node) {
340 ret = __clk_lookup_subtree(name, root_clk);
341 if (ret)
342 return ret;
343 }
bddca894 344
4dff95dc 345 return NULL;
bddca894
PG
346}
347
4dff95dc
SB
348static struct clk_core *clk_core_get_parent_by_index(struct clk_core *core,
349 u8 index)
bddca894 350{
4dff95dc
SB
351 if (!core || index >= core->num_parents)
352 return NULL;
88cfbef2
MY
353
354 if (!core->parents[index])
355 core->parents[index] =
356 clk_core_lookup(core->parent_names[index]);
357
358 return core->parents[index];
bddca894
PG
359}
360
e7df6f6e
SB
361struct clk_hw *
362clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index)
1a9c069c
SB
363{
364 struct clk_core *parent;
365
366 parent = clk_core_get_parent_by_index(hw->core, index);
367
368 return !parent ? NULL : parent->hw;
369}
370EXPORT_SYMBOL_GPL(clk_hw_get_parent_by_index);
371
4dff95dc
SB
372unsigned int __clk_get_enable_count(struct clk *clk)
373{
374 return !clk ? 0 : clk->core->enable_count;
375}
b2476490 376
4dff95dc
SB
377static unsigned long clk_core_get_rate_nolock(struct clk_core *core)
378{
379 unsigned long ret;
b2476490 380
4dff95dc
SB
381 if (!core) {
382 ret = 0;
383 goto out;
384 }
b2476490 385
4dff95dc 386 ret = core->rate;
b2476490 387
47b0eeb3 388 if (!core->num_parents)
4dff95dc 389 goto out;
c646cbf1 390
4dff95dc
SB
391 if (!core->parent)
392 ret = 0;
b2476490 393
b2476490
MT
394out:
395 return ret;
396}
397
e7df6f6e 398unsigned long clk_hw_get_rate(const struct clk_hw *hw)
1a9c069c
SB
399{
400 return clk_core_get_rate_nolock(hw->core);
401}
402EXPORT_SYMBOL_GPL(clk_hw_get_rate);
403
4dff95dc
SB
404static unsigned long __clk_get_accuracy(struct clk_core *core)
405{
406 if (!core)
407 return 0;
b2476490 408
4dff95dc 409 return core->accuracy;
b2476490
MT
410}
411
4dff95dc 412unsigned long __clk_get_flags(struct clk *clk)
fcb0ee6a 413{
4dff95dc 414 return !clk ? 0 : clk->core->flags;
fcb0ee6a 415}
4dff95dc 416EXPORT_SYMBOL_GPL(__clk_get_flags);
fcb0ee6a 417
e7df6f6e 418unsigned long clk_hw_get_flags(const struct clk_hw *hw)
1a9c069c
SB
419{
420 return hw->core->flags;
421}
422EXPORT_SYMBOL_GPL(clk_hw_get_flags);
423
e7df6f6e 424bool clk_hw_is_prepared(const struct clk_hw *hw)
1a9c069c
SB
425{
426 return clk_core_is_prepared(hw->core);
427}
428
be68bf88
JE
429bool clk_hw_is_enabled(const struct clk_hw *hw)
430{
431 return clk_core_is_enabled(hw->core);
432}
433
4dff95dc 434bool __clk_is_enabled(struct clk *clk)
b2476490 435{
4dff95dc
SB
436 if (!clk)
437 return false;
b2476490 438
4dff95dc
SB
439 return clk_core_is_enabled(clk->core);
440}
441EXPORT_SYMBOL_GPL(__clk_is_enabled);
b2476490 442
4dff95dc
SB
443static bool mux_is_better_rate(unsigned long rate, unsigned long now,
444 unsigned long best, unsigned long flags)
445{
446 if (flags & CLK_MUX_ROUND_CLOSEST)
447 return abs(now - rate) < abs(best - rate);
1af599df 448
4dff95dc
SB
449 return now <= rate && now > best;
450}
bddca894 451
0817b62c
BB
452static int
453clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req,
4dff95dc
SB
454 unsigned long flags)
455{
456 struct clk_core *core = hw->core, *parent, *best_parent = NULL;
0817b62c
BB
457 int i, num_parents, ret;
458 unsigned long best = 0;
459 struct clk_rate_request parent_req = *req;
b2476490 460
4dff95dc
SB
461 /* if NO_REPARENT flag set, pass through to current parent */
462 if (core->flags & CLK_SET_RATE_NO_REPARENT) {
463 parent = core->parent;
0817b62c
BB
464 if (core->flags & CLK_SET_RATE_PARENT) {
465 ret = __clk_determine_rate(parent ? parent->hw : NULL,
466 &parent_req);
467 if (ret)
468 return ret;
469
470 best = parent_req.rate;
471 } else if (parent) {
4dff95dc 472 best = clk_core_get_rate_nolock(parent);
0817b62c 473 } else {
4dff95dc 474 best = clk_core_get_rate_nolock(core);
0817b62c
BB
475 }
476
4dff95dc
SB
477 goto out;
478 }
b2476490 479
4dff95dc
SB
480 /* find the parent that can provide the fastest rate <= rate */
481 num_parents = core->num_parents;
482 for (i = 0; i < num_parents; i++) {
483 parent = clk_core_get_parent_by_index(core, i);
484 if (!parent)
485 continue;
0817b62c
BB
486
487 if (core->flags & CLK_SET_RATE_PARENT) {
488 parent_req = *req;
489 ret = __clk_determine_rate(parent->hw, &parent_req);
490 if (ret)
491 continue;
492 } else {
493 parent_req.rate = clk_core_get_rate_nolock(parent);
494 }
495
496 if (mux_is_better_rate(req->rate, parent_req.rate,
497 best, flags)) {
4dff95dc 498 best_parent = parent;
0817b62c 499 best = parent_req.rate;
4dff95dc
SB
500 }
501 }
b2476490 502
57d866e6
BB
503 if (!best_parent)
504 return -EINVAL;
505
4dff95dc
SB
506out:
507 if (best_parent)
0817b62c
BB
508 req->best_parent_hw = best_parent->hw;
509 req->best_parent_rate = best;
510 req->rate = best;
b2476490 511
0817b62c 512 return 0;
b33d212f 513}
4dff95dc
SB
514
515struct clk *__clk_lookup(const char *name)
fcb0ee6a 516{
4dff95dc
SB
517 struct clk_core *core = clk_core_lookup(name);
518
519 return !core ? NULL : core->hw->clk;
fcb0ee6a 520}
b2476490 521
4dff95dc
SB
522static void clk_core_get_boundaries(struct clk_core *core,
523 unsigned long *min_rate,
524 unsigned long *max_rate)
1c155b3d 525{
4dff95dc 526 struct clk *clk_user;
1c155b3d 527
9783c0d9
SB
528 *min_rate = core->min_rate;
529 *max_rate = core->max_rate;
496eadf8 530
4dff95dc
SB
531 hlist_for_each_entry(clk_user, &core->clks, clks_node)
532 *min_rate = max(*min_rate, clk_user->min_rate);
1c155b3d 533
4dff95dc
SB
534 hlist_for_each_entry(clk_user, &core->clks, clks_node)
535 *max_rate = min(*max_rate, clk_user->max_rate);
536}
1c155b3d 537
9783c0d9
SB
538void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
539 unsigned long max_rate)
540{
541 hw->core->min_rate = min_rate;
542 hw->core->max_rate = max_rate;
543}
544EXPORT_SYMBOL_GPL(clk_hw_set_rate_range);
545
4dff95dc
SB
546/*
547 * Helper for finding best parent to provide a given frequency. This can be used
548 * directly as a determine_rate callback (e.g. for a mux), or from a more
549 * complex clock that may combine a mux with other operations.
550 */
0817b62c
BB
551int __clk_mux_determine_rate(struct clk_hw *hw,
552 struct clk_rate_request *req)
4dff95dc 553{
0817b62c 554 return clk_mux_determine_rate_flags(hw, req, 0);
1c155b3d 555}
4dff95dc 556EXPORT_SYMBOL_GPL(__clk_mux_determine_rate);
1c155b3d 557
0817b62c
BB
558int __clk_mux_determine_rate_closest(struct clk_hw *hw,
559 struct clk_rate_request *req)
b2476490 560{
0817b62c 561 return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST);
4dff95dc
SB
562}
563EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
b2476490 564
4dff95dc 565/*** clk api ***/
496eadf8 566
4dff95dc
SB
567static void clk_core_unprepare(struct clk_core *core)
568{
a6334725
SB
569 lockdep_assert_held(&prepare_lock);
570
4dff95dc
SB
571 if (!core)
572 return;
b2476490 573
4dff95dc
SB
574 if (WARN_ON(core->prepare_count == 0))
575 return;
b2476490 576
2e20fbf5
LJ
577 if (WARN_ON(core->prepare_count == 1 && core->flags & CLK_IS_CRITICAL))
578 return;
579
4dff95dc
SB
580 if (--core->prepare_count > 0)
581 return;
b2476490 582
4dff95dc 583 WARN_ON(core->enable_count > 0);
b2476490 584
4dff95dc 585 trace_clk_unprepare(core);
b2476490 586
4dff95dc
SB
587 if (core->ops->unprepare)
588 core->ops->unprepare(core->hw);
589
590 trace_clk_unprepare_complete(core);
591 clk_core_unprepare(core->parent);
b2476490
MT
592}
593
4dff95dc
SB
594/**
595 * clk_unprepare - undo preparation of a clock source
596 * @clk: the clk being unprepared
597 *
598 * clk_unprepare may sleep, which differentiates it from clk_disable. In a
599 * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
600 * if the operation may sleep. One example is a clk which is accessed over
601 * I2c. In the complex case a clk gate operation may require a fast and a slow
602 * part. It is this reason that clk_unprepare and clk_disable are not mutually
603 * exclusive. In fact clk_disable must be called before clk_unprepare.
604 */
605void clk_unprepare(struct clk *clk)
1e435256 606{
4dff95dc
SB
607 if (IS_ERR_OR_NULL(clk))
608 return;
609
610 clk_prepare_lock();
611 clk_core_unprepare(clk->core);
612 clk_prepare_unlock();
1e435256 613}
4dff95dc 614EXPORT_SYMBOL_GPL(clk_unprepare);
1e435256 615
4dff95dc 616static int clk_core_prepare(struct clk_core *core)
b2476490 617{
4dff95dc 618 int ret = 0;
b2476490 619
a6334725
SB
620 lockdep_assert_held(&prepare_lock);
621
4dff95dc 622 if (!core)
1e435256 623 return 0;
1e435256 624
4dff95dc
SB
625 if (core->prepare_count == 0) {
626 ret = clk_core_prepare(core->parent);
627 if (ret)
628 return ret;
b2476490 629
4dff95dc 630 trace_clk_prepare(core);
b2476490 631
4dff95dc
SB
632 if (core->ops->prepare)
633 ret = core->ops->prepare(core->hw);
b2476490 634
4dff95dc 635 trace_clk_prepare_complete(core);
1c155b3d 636
4dff95dc
SB
637 if (ret) {
638 clk_core_unprepare(core->parent);
639 return ret;
640 }
641 }
1c155b3d 642
4dff95dc 643 core->prepare_count++;
b2476490
MT
644
645 return 0;
646}
b2476490 647
4dff95dc
SB
648/**
649 * clk_prepare - prepare a clock source
650 * @clk: the clk being prepared
651 *
652 * clk_prepare may sleep, which differentiates it from clk_enable. In a simple
653 * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
654 * operation may sleep. One example is a clk which is accessed over I2c. In
655 * the complex case a clk ungate operation may require a fast and a slow part.
656 * It is this reason that clk_prepare and clk_enable are not mutually
657 * exclusive. In fact clk_prepare must be called before clk_enable.
658 * Returns 0 on success, -EERROR otherwise.
659 */
660int clk_prepare(struct clk *clk)
b2476490 661{
4dff95dc 662 int ret;
b2476490 663
4dff95dc
SB
664 if (!clk)
665 return 0;
b2476490 666
4dff95dc
SB
667 clk_prepare_lock();
668 ret = clk_core_prepare(clk->core);
669 clk_prepare_unlock();
670
671 return ret;
b2476490 672}
4dff95dc 673EXPORT_SYMBOL_GPL(clk_prepare);
b2476490 674
4dff95dc 675static void clk_core_disable(struct clk_core *core)
b2476490 676{
a6334725
SB
677 lockdep_assert_held(&enable_lock);
678
4dff95dc
SB
679 if (!core)
680 return;
035a61c3 681
4dff95dc
SB
682 if (WARN_ON(core->enable_count == 0))
683 return;
b2476490 684
2e20fbf5
LJ
685 if (WARN_ON(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL))
686 return;
687
4dff95dc
SB
688 if (--core->enable_count > 0)
689 return;
035a61c3 690
2f87a6ea 691 trace_clk_disable_rcuidle(core);
035a61c3 692
4dff95dc
SB
693 if (core->ops->disable)
694 core->ops->disable(core->hw);
035a61c3 695
2f87a6ea 696 trace_clk_disable_complete_rcuidle(core);
035a61c3 697
4dff95dc 698 clk_core_disable(core->parent);
035a61c3 699}
7ef3dcc8 700
4dff95dc
SB
701/**
702 * clk_disable - gate a clock
703 * @clk: the clk being gated
704 *
705 * clk_disable must not sleep, which differentiates it from clk_unprepare. In
706 * a simple case, clk_disable can be used instead of clk_unprepare to gate a
707 * clk if the operation is fast and will never sleep. One example is a
708 * SoC-internal clk which is controlled via simple register writes. In the
709 * complex case a clk gate operation may require a fast and a slow part. It is
710 * this reason that clk_unprepare and clk_disable are not mutually exclusive.
711 * In fact clk_disable must be called before clk_unprepare.
712 */
713void clk_disable(struct clk *clk)
b2476490 714{
4dff95dc
SB
715 unsigned long flags;
716
717 if (IS_ERR_OR_NULL(clk))
718 return;
719
720 flags = clk_enable_lock();
721 clk_core_disable(clk->core);
722 clk_enable_unlock(flags);
b2476490 723}
4dff95dc 724EXPORT_SYMBOL_GPL(clk_disable);
b2476490 725
4dff95dc 726static int clk_core_enable(struct clk_core *core)
b2476490 727{
4dff95dc 728 int ret = 0;
b2476490 729
a6334725
SB
730 lockdep_assert_held(&enable_lock);
731
4dff95dc
SB
732 if (!core)
733 return 0;
b2476490 734
4dff95dc
SB
735 if (WARN_ON(core->prepare_count == 0))
736 return -ESHUTDOWN;
b2476490 737
4dff95dc
SB
738 if (core->enable_count == 0) {
739 ret = clk_core_enable(core->parent);
b2476490 740
4dff95dc
SB
741 if (ret)
742 return ret;
b2476490 743
f17a0dd1 744 trace_clk_enable_rcuidle(core);
035a61c3 745
4dff95dc
SB
746 if (core->ops->enable)
747 ret = core->ops->enable(core->hw);
035a61c3 748
f17a0dd1 749 trace_clk_enable_complete_rcuidle(core);
4dff95dc
SB
750
751 if (ret) {
752 clk_core_disable(core->parent);
753 return ret;
754 }
755 }
756
757 core->enable_count++;
758 return 0;
035a61c3 759}
b2476490 760
4dff95dc
SB
761/**
762 * clk_enable - ungate a clock
763 * @clk: the clk being ungated
764 *
765 * clk_enable must not sleep, which differentiates it from clk_prepare. In a
766 * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
767 * if the operation will never sleep. One example is a SoC-internal clk which
768 * is controlled via simple register writes. In the complex case a clk ungate
769 * operation may require a fast and a slow part. It is this reason that
770 * clk_enable and clk_prepare are not mutually exclusive. In fact clk_prepare
771 * must be called before clk_enable. Returns 0 on success, -EERROR
772 * otherwise.
773 */
774int clk_enable(struct clk *clk)
5279fc40 775{
4dff95dc
SB
776 unsigned long flags;
777 int ret;
778
779 if (!clk)
5279fc40
BB
780 return 0;
781
4dff95dc
SB
782 flags = clk_enable_lock();
783 ret = clk_core_enable(clk->core);
784 clk_enable_unlock(flags);
5279fc40 785
4dff95dc 786 return ret;
b2476490 787}
4dff95dc 788EXPORT_SYMBOL_GPL(clk_enable);
b2476490 789
0817b62c
BB
790static int clk_core_round_rate_nolock(struct clk_core *core,
791 struct clk_rate_request *req)
3d6ee287 792{
4dff95dc 793 struct clk_core *parent;
0817b62c 794 long rate;
4dff95dc
SB
795
796 lockdep_assert_held(&prepare_lock);
3d6ee287 797
d6968fca 798 if (!core)
4dff95dc 799 return 0;
3d6ee287 800
4dff95dc 801 parent = core->parent;
0817b62c
BB
802 if (parent) {
803 req->best_parent_hw = parent->hw;
804 req->best_parent_rate = parent->rate;
805 } else {
806 req->best_parent_hw = NULL;
807 req->best_parent_rate = 0;
808 }
3d6ee287 809
4dff95dc 810 if (core->ops->determine_rate) {
0817b62c
BB
811 return core->ops->determine_rate(core->hw, req);
812 } else if (core->ops->round_rate) {
813 rate = core->ops->round_rate(core->hw, req->rate,
814 &req->best_parent_rate);
815 if (rate < 0)
816 return rate;
817
818 req->rate = rate;
819 } else if (core->flags & CLK_SET_RATE_PARENT) {
820 return clk_core_round_rate_nolock(parent, req);
821 } else {
822 req->rate = core->rate;
823 }
824
825 return 0;
3d6ee287
UH
826}
827
4dff95dc
SB
828/**
829 * __clk_determine_rate - get the closest rate actually supported by a clock
830 * @hw: determine the rate of this clock
831 * @rate: target rate
832 * @min_rate: returned rate must be greater than this rate
833 * @max_rate: returned rate must be less than this rate
834 *
6e5ab41b 835 * Useful for clk_ops such as .set_rate and .determine_rate.
4dff95dc 836 */
0817b62c 837int __clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
035a61c3 838{
0817b62c
BB
839 if (!hw) {
840 req->rate = 0;
4dff95dc 841 return 0;
0817b62c 842 }
035a61c3 843
0817b62c 844 return clk_core_round_rate_nolock(hw->core, req);
035a61c3 845}
4dff95dc 846EXPORT_SYMBOL_GPL(__clk_determine_rate);
035a61c3 847
1a9c069c
SB
848unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate)
849{
850 int ret;
851 struct clk_rate_request req;
852
853 clk_core_get_boundaries(hw->core, &req.min_rate, &req.max_rate);
854 req.rate = rate;
855
856 ret = clk_core_round_rate_nolock(hw->core, &req);
857 if (ret)
858 return 0;
859
860 return req.rate;
861}
862EXPORT_SYMBOL_GPL(clk_hw_round_rate);
863
4dff95dc
SB
864/**
865 * clk_round_rate - round the given rate for a clk
866 * @clk: the clk for which we are rounding a rate
867 * @rate: the rate which is to be rounded
868 *
869 * Takes in a rate as input and rounds it to a rate that the clk can actually
870 * use which is then returned. If clk doesn't support round_rate operation
871 * then the parent rate is returned.
872 */
873long clk_round_rate(struct clk *clk, unsigned long rate)
035a61c3 874{
fc4a05d4
SB
875 struct clk_rate_request req;
876 int ret;
4dff95dc 877
035a61c3 878 if (!clk)
4dff95dc 879 return 0;
035a61c3 880
4dff95dc 881 clk_prepare_lock();
fc4a05d4
SB
882
883 clk_core_get_boundaries(clk->core, &req.min_rate, &req.max_rate);
884 req.rate = rate;
885
886 ret = clk_core_round_rate_nolock(clk->core, &req);
4dff95dc
SB
887 clk_prepare_unlock();
888
fc4a05d4
SB
889 if (ret)
890 return ret;
891
892 return req.rate;
035a61c3 893}
4dff95dc 894EXPORT_SYMBOL_GPL(clk_round_rate);
b2476490 895
4dff95dc
SB
896/**
897 * __clk_notify - call clk notifier chain
898 * @core: clk that is changing rate
899 * @msg: clk notifier type (see include/linux/clk.h)
900 * @old_rate: old clk rate
901 * @new_rate: new clk rate
902 *
903 * Triggers a notifier call chain on the clk rate-change notification
904 * for 'clk'. Passes a pointer to the struct clk and the previous
905 * and current rates to the notifier callback. Intended to be called by
906 * internal clock code only. Returns NOTIFY_DONE from the last driver
907 * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
908 * a driver returns that.
909 */
910static int __clk_notify(struct clk_core *core, unsigned long msg,
911 unsigned long old_rate, unsigned long new_rate)
b2476490 912{
4dff95dc
SB
913 struct clk_notifier *cn;
914 struct clk_notifier_data cnd;
915 int ret = NOTIFY_DONE;
b2476490 916
4dff95dc
SB
917 cnd.old_rate = old_rate;
918 cnd.new_rate = new_rate;
b2476490 919
4dff95dc
SB
920 list_for_each_entry(cn, &clk_notifier_list, node) {
921 if (cn->clk->core == core) {
922 cnd.clk = cn->clk;
923 ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
924 &cnd);
925 }
b2476490
MT
926 }
927
4dff95dc 928 return ret;
b2476490
MT
929}
930
4dff95dc
SB
931/**
932 * __clk_recalc_accuracies
933 * @core: first clk in the subtree
934 *
935 * Walks the subtree of clks starting with clk and recalculates accuracies as
936 * it goes. Note that if a clk does not implement the .recalc_accuracy
6e5ab41b 937 * callback then it is assumed that the clock will take on the accuracy of its
4dff95dc 938 * parent.
4dff95dc
SB
939 */
940static void __clk_recalc_accuracies(struct clk_core *core)
b2476490 941{
4dff95dc
SB
942 unsigned long parent_accuracy = 0;
943 struct clk_core *child;
b2476490 944
4dff95dc 945 lockdep_assert_held(&prepare_lock);
b2476490 946
4dff95dc
SB
947 if (core->parent)
948 parent_accuracy = core->parent->accuracy;
b2476490 949
4dff95dc
SB
950 if (core->ops->recalc_accuracy)
951 core->accuracy = core->ops->recalc_accuracy(core->hw,
952 parent_accuracy);
953 else
954 core->accuracy = parent_accuracy;
b2476490 955
4dff95dc
SB
956 hlist_for_each_entry(child, &core->children, child_node)
957 __clk_recalc_accuracies(child);
b2476490
MT
958}
959
4dff95dc 960static long clk_core_get_accuracy(struct clk_core *core)
e366fdd7 961{
4dff95dc 962 unsigned long accuracy;
15a02c1f 963
4dff95dc
SB
964 clk_prepare_lock();
965 if (core && (core->flags & CLK_GET_ACCURACY_NOCACHE))
966 __clk_recalc_accuracies(core);
15a02c1f 967
4dff95dc
SB
968 accuracy = __clk_get_accuracy(core);
969 clk_prepare_unlock();
e366fdd7 970
4dff95dc 971 return accuracy;
e366fdd7 972}
15a02c1f 973
4dff95dc
SB
974/**
975 * clk_get_accuracy - return the accuracy of clk
976 * @clk: the clk whose accuracy is being returned
977 *
978 * Simply returns the cached accuracy of the clk, unless
979 * CLK_GET_ACCURACY_NOCACHE flag is set, which means a recalc_rate will be
980 * issued.
981 * If clk is NULL then returns 0.
982 */
983long clk_get_accuracy(struct clk *clk)
035a61c3 984{
4dff95dc
SB
985 if (!clk)
986 return 0;
035a61c3 987
4dff95dc 988 return clk_core_get_accuracy(clk->core);
035a61c3 989}
4dff95dc 990EXPORT_SYMBOL_GPL(clk_get_accuracy);
035a61c3 991
4dff95dc
SB
992static unsigned long clk_recalc(struct clk_core *core,
993 unsigned long parent_rate)
1c8e6004 994{
4dff95dc
SB
995 if (core->ops->recalc_rate)
996 return core->ops->recalc_rate(core->hw, parent_rate);
997 return parent_rate;
1c8e6004
TV
998}
999
4dff95dc
SB
1000/**
1001 * __clk_recalc_rates
1002 * @core: first clk in the subtree
1003 * @msg: notification type (see include/linux/clk.h)
1004 *
1005 * Walks the subtree of clks starting with clk and recalculates rates as it
1006 * goes. Note that if a clk does not implement the .recalc_rate callback then
1007 * it is assumed that the clock will take on the rate of its parent.
1008 *
1009 * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
1010 * if necessary.
15a02c1f 1011 */
4dff95dc 1012static void __clk_recalc_rates(struct clk_core *core, unsigned long msg)
15a02c1f 1013{
4dff95dc
SB
1014 unsigned long old_rate;
1015 unsigned long parent_rate = 0;
1016 struct clk_core *child;
e366fdd7 1017
4dff95dc 1018 lockdep_assert_held(&prepare_lock);
15a02c1f 1019
4dff95dc 1020 old_rate = core->rate;
b2476490 1021
4dff95dc
SB
1022 if (core->parent)
1023 parent_rate = core->parent->rate;
b2476490 1024
4dff95dc 1025 core->rate = clk_recalc(core, parent_rate);
b2476490 1026
4dff95dc
SB
1027 /*
1028 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
1029 * & ABORT_RATE_CHANGE notifiers
1030 */
1031 if (core->notifier_count && msg)
1032 __clk_notify(core, msg, old_rate, core->rate);
b2476490 1033
4dff95dc
SB
1034 hlist_for_each_entry(child, &core->children, child_node)
1035 __clk_recalc_rates(child, msg);
1036}
b2476490 1037
4dff95dc
SB
1038static unsigned long clk_core_get_rate(struct clk_core *core)
1039{
1040 unsigned long rate;
dfc202ea 1041
4dff95dc 1042 clk_prepare_lock();
b2476490 1043
4dff95dc
SB
1044 if (core && (core->flags & CLK_GET_RATE_NOCACHE))
1045 __clk_recalc_rates(core, 0);
1046
1047 rate = clk_core_get_rate_nolock(core);
1048 clk_prepare_unlock();
1049
1050 return rate;
b2476490
MT
1051}
1052
1053/**
4dff95dc
SB
1054 * clk_get_rate - return the rate of clk
1055 * @clk: the clk whose rate is being returned
b2476490 1056 *
4dff95dc
SB
1057 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1058 * is set, which means a recalc_rate will be issued.
1059 * If clk is NULL then returns 0.
b2476490 1060 */
4dff95dc 1061unsigned long clk_get_rate(struct clk *clk)
b2476490 1062{
4dff95dc
SB
1063 if (!clk)
1064 return 0;
63589e92 1065
4dff95dc 1066 return clk_core_get_rate(clk->core);
b2476490 1067}
4dff95dc 1068EXPORT_SYMBOL_GPL(clk_get_rate);
b2476490 1069
4dff95dc
SB
1070static int clk_fetch_parent_index(struct clk_core *core,
1071 struct clk_core *parent)
b2476490 1072{
4dff95dc 1073 int i;
b2476490 1074
508f884a
MY
1075 if (!parent)
1076 return -EINVAL;
1077
470b5e2f
MY
1078 for (i = 0; i < core->num_parents; i++)
1079 if (clk_core_get_parent_by_index(core, i) == parent)
4dff95dc 1080 return i;
b2476490 1081
4dff95dc 1082 return -EINVAL;
b2476490
MT
1083}
1084
e6500344
HS
1085/*
1086 * Update the orphan status of @core and all its children.
1087 */
1088static void clk_core_update_orphan_status(struct clk_core *core, bool is_orphan)
1089{
1090 struct clk_core *child;
1091
1092 core->orphan = is_orphan;
1093
1094 hlist_for_each_entry(child, &core->children, child_node)
1095 clk_core_update_orphan_status(child, is_orphan);
1096}
1097
4dff95dc 1098static void clk_reparent(struct clk_core *core, struct clk_core *new_parent)
b2476490 1099{
e6500344
HS
1100 bool was_orphan = core->orphan;
1101
4dff95dc 1102 hlist_del(&core->child_node);
035a61c3 1103
4dff95dc 1104 if (new_parent) {
e6500344
HS
1105 bool becomes_orphan = new_parent->orphan;
1106
4dff95dc
SB
1107 /* avoid duplicate POST_RATE_CHANGE notifications */
1108 if (new_parent->new_child == core)
1109 new_parent->new_child = NULL;
b2476490 1110
4dff95dc 1111 hlist_add_head(&core->child_node, &new_parent->children);
e6500344
HS
1112
1113 if (was_orphan != becomes_orphan)
1114 clk_core_update_orphan_status(core, becomes_orphan);
4dff95dc
SB
1115 } else {
1116 hlist_add_head(&core->child_node, &clk_orphan_list);
e6500344
HS
1117 if (!was_orphan)
1118 clk_core_update_orphan_status(core, true);
4dff95dc 1119 }
dfc202ea 1120
4dff95dc 1121 core->parent = new_parent;
035a61c3
TV
1122}
1123
4dff95dc
SB
1124static struct clk_core *__clk_set_parent_before(struct clk_core *core,
1125 struct clk_core *parent)
b2476490
MT
1126{
1127 unsigned long flags;
4dff95dc 1128 struct clk_core *old_parent = core->parent;
b2476490 1129
4dff95dc
SB
1130 /*
1131 * Migrate prepare state between parents and prevent race with
1132 * clk_enable().
1133 *
1134 * If the clock is not prepared, then a race with
1135 * clk_enable/disable() is impossible since we already have the
1136 * prepare lock (future calls to clk_enable() need to be preceded by
1137 * a clk_prepare()).
1138 *
1139 * If the clock is prepared, migrate the prepared state to the new
1140 * parent and also protect against a race with clk_enable() by
1141 * forcing the clock and the new parent on. This ensures that all
1142 * future calls to clk_enable() are practically NOPs with respect to
1143 * hardware and software states.
1144 *
1145 * See also: Comment for clk_set_parent() below.
1146 */
1147 if (core->prepare_count) {
1148 clk_core_prepare(parent);
d2a5d46b 1149 flags = clk_enable_lock();
4dff95dc
SB
1150 clk_core_enable(parent);
1151 clk_core_enable(core);
d2a5d46b 1152 clk_enable_unlock(flags);
4dff95dc 1153 }
63589e92 1154
4dff95dc 1155 /* update the clk tree topology */
eab89f69 1156 flags = clk_enable_lock();
4dff95dc 1157 clk_reparent(core, parent);
eab89f69 1158 clk_enable_unlock(flags);
4dff95dc
SB
1159
1160 return old_parent;
b2476490 1161}
b2476490 1162
4dff95dc
SB
1163static void __clk_set_parent_after(struct clk_core *core,
1164 struct clk_core *parent,
1165 struct clk_core *old_parent)
b2476490 1166{
d2a5d46b
DA
1167 unsigned long flags;
1168
4dff95dc
SB
1169 /*
1170 * Finish the migration of prepare state and undo the changes done
1171 * for preventing a race with clk_enable().
1172 */
1173 if (core->prepare_count) {
d2a5d46b 1174 flags = clk_enable_lock();
4dff95dc
SB
1175 clk_core_disable(core);
1176 clk_core_disable(old_parent);
d2a5d46b 1177 clk_enable_unlock(flags);
4dff95dc
SB
1178 clk_core_unprepare(old_parent);
1179 }
1180}
b2476490 1181
4dff95dc
SB
1182static int __clk_set_parent(struct clk_core *core, struct clk_core *parent,
1183 u8 p_index)
1184{
1185 unsigned long flags;
1186 int ret = 0;
1187 struct clk_core *old_parent;
b2476490 1188
4dff95dc 1189 old_parent = __clk_set_parent_before(core, parent);
b2476490 1190
4dff95dc 1191 trace_clk_set_parent(core, parent);
b2476490 1192
4dff95dc
SB
1193 /* change clock input source */
1194 if (parent && core->ops->set_parent)
1195 ret = core->ops->set_parent(core->hw, p_index);
dfc202ea 1196
4dff95dc 1197 trace_clk_set_parent_complete(core, parent);
dfc202ea 1198
4dff95dc
SB
1199 if (ret) {
1200 flags = clk_enable_lock();
1201 clk_reparent(core, old_parent);
1202 clk_enable_unlock(flags);
c660b2eb 1203 __clk_set_parent_after(core, old_parent, parent);
dfc202ea 1204
4dff95dc 1205 return ret;
b2476490
MT
1206 }
1207
4dff95dc
SB
1208 __clk_set_parent_after(core, parent, old_parent);
1209
b2476490
MT
1210 return 0;
1211}
1212
1213/**
4dff95dc
SB
1214 * __clk_speculate_rates
1215 * @core: first clk in the subtree
1216 * @parent_rate: the "future" rate of clk's parent
b2476490 1217 *
4dff95dc
SB
1218 * Walks the subtree of clks starting with clk, speculating rates as it
1219 * goes and firing off PRE_RATE_CHANGE notifications as necessary.
1220 *
1221 * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
1222 * pre-rate change notifications and returns early if no clks in the
1223 * subtree have subscribed to the notifications. Note that if a clk does not
1224 * implement the .recalc_rate callback then it is assumed that the clock will
1225 * take on the rate of its parent.
b2476490 1226 */
4dff95dc
SB
1227static int __clk_speculate_rates(struct clk_core *core,
1228 unsigned long parent_rate)
b2476490 1229{
4dff95dc
SB
1230 struct clk_core *child;
1231 unsigned long new_rate;
1232 int ret = NOTIFY_DONE;
b2476490 1233
4dff95dc 1234 lockdep_assert_held(&prepare_lock);
864e160a 1235
4dff95dc
SB
1236 new_rate = clk_recalc(core, parent_rate);
1237
1238 /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */
1239 if (core->notifier_count)
1240 ret = __clk_notify(core, PRE_RATE_CHANGE, core->rate, new_rate);
1241
1242 if (ret & NOTIFY_STOP_MASK) {
1243 pr_debug("%s: clk notifier callback for clock %s aborted with error %d\n",
1244 __func__, core->name, ret);
1245 goto out;
1246 }
1247
1248 hlist_for_each_entry(child, &core->children, child_node) {
1249 ret = __clk_speculate_rates(child, new_rate);
1250 if (ret & NOTIFY_STOP_MASK)
1251 break;
1252 }
b2476490 1253
4dff95dc 1254out:
b2476490
MT
1255 return ret;
1256}
b2476490 1257
4dff95dc
SB
1258static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate,
1259 struct clk_core *new_parent, u8 p_index)
b2476490 1260{
4dff95dc 1261 struct clk_core *child;
b2476490 1262
4dff95dc
SB
1263 core->new_rate = new_rate;
1264 core->new_parent = new_parent;
1265 core->new_parent_index = p_index;
1266 /* include clk in new parent's PRE_RATE_CHANGE notifications */
1267 core->new_child = NULL;
1268 if (new_parent && new_parent != core->parent)
1269 new_parent->new_child = core;
496eadf8 1270
4dff95dc
SB
1271 hlist_for_each_entry(child, &core->children, child_node) {
1272 child->new_rate = clk_recalc(child, new_rate);
1273 clk_calc_subtree(child, child->new_rate, NULL, 0);
1274 }
1275}
b2476490 1276
4dff95dc
SB
1277/*
1278 * calculate the new rates returning the topmost clock that has to be
1279 * changed.
1280 */
1281static struct clk_core *clk_calc_new_rates(struct clk_core *core,
1282 unsigned long rate)
1283{
1284 struct clk_core *top = core;
1285 struct clk_core *old_parent, *parent;
4dff95dc
SB
1286 unsigned long best_parent_rate = 0;
1287 unsigned long new_rate;
1288 unsigned long min_rate;
1289 unsigned long max_rate;
1290 int p_index = 0;
1291 long ret;
1292
1293 /* sanity */
1294 if (IS_ERR_OR_NULL(core))
1295 return NULL;
1296
1297 /* save parent rate, if it exists */
1298 parent = old_parent = core->parent;
71472c0c 1299 if (parent)
4dff95dc 1300 best_parent_rate = parent->rate;
71472c0c 1301
4dff95dc
SB
1302 clk_core_get_boundaries(core, &min_rate, &max_rate);
1303
1304 /* find the closest rate and parent clk/rate */
d6968fca 1305 if (core->ops->determine_rate) {
0817b62c
BB
1306 struct clk_rate_request req;
1307
1308 req.rate = rate;
1309 req.min_rate = min_rate;
1310 req.max_rate = max_rate;
1311 if (parent) {
1312 req.best_parent_hw = parent->hw;
1313 req.best_parent_rate = parent->rate;
1314 } else {
1315 req.best_parent_hw = NULL;
1316 req.best_parent_rate = 0;
1317 }
1318
1319 ret = core->ops->determine_rate(core->hw, &req);
4dff95dc
SB
1320 if (ret < 0)
1321 return NULL;
1c8e6004 1322
0817b62c
BB
1323 best_parent_rate = req.best_parent_rate;
1324 new_rate = req.rate;
1325 parent = req.best_parent_hw ? req.best_parent_hw->core : NULL;
4dff95dc
SB
1326 } else if (core->ops->round_rate) {
1327 ret = core->ops->round_rate(core->hw, rate,
0817b62c 1328 &best_parent_rate);
4dff95dc
SB
1329 if (ret < 0)
1330 return NULL;
035a61c3 1331
4dff95dc
SB
1332 new_rate = ret;
1333 if (new_rate < min_rate || new_rate > max_rate)
1334 return NULL;
1335 } else if (!parent || !(core->flags & CLK_SET_RATE_PARENT)) {
1336 /* pass-through clock without adjustable parent */
1337 core->new_rate = core->rate;
1338 return NULL;
1339 } else {
1340 /* pass-through clock with adjustable parent */
1341 top = clk_calc_new_rates(parent, rate);
1342 new_rate = parent->new_rate;
1343 goto out;
1344 }
1c8e6004 1345
4dff95dc
SB
1346 /* some clocks must be gated to change parent */
1347 if (parent != old_parent &&
1348 (core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
1349 pr_debug("%s: %s not gated but wants to reparent\n",
1350 __func__, core->name);
1351 return NULL;
1352 }
b2476490 1353
4dff95dc
SB
1354 /* try finding the new parent index */
1355 if (parent && core->num_parents > 1) {
1356 p_index = clk_fetch_parent_index(core, parent);
1357 if (p_index < 0) {
1358 pr_debug("%s: clk %s can not be parent of clk %s\n",
1359 __func__, parent->name, core->name);
1360 return NULL;
1361 }
1362 }
b2476490 1363
4dff95dc
SB
1364 if ((core->flags & CLK_SET_RATE_PARENT) && parent &&
1365 best_parent_rate != parent->rate)
1366 top = clk_calc_new_rates(parent, best_parent_rate);
035a61c3 1367
4dff95dc
SB
1368out:
1369 clk_calc_subtree(core, new_rate, parent, p_index);
b2476490 1370
4dff95dc 1371 return top;
b2476490 1372}
b2476490 1373
4dff95dc
SB
1374/*
1375 * Notify about rate changes in a subtree. Always walk down the whole tree
1376 * so that in case of an error we can walk down the whole tree again and
1377 * abort the change.
b2476490 1378 */
4dff95dc
SB
1379static struct clk_core *clk_propagate_rate_change(struct clk_core *core,
1380 unsigned long event)
b2476490 1381{
4dff95dc 1382 struct clk_core *child, *tmp_clk, *fail_clk = NULL;
b2476490
MT
1383 int ret = NOTIFY_DONE;
1384
4dff95dc
SB
1385 if (core->rate == core->new_rate)
1386 return NULL;
b2476490 1387
4dff95dc
SB
1388 if (core->notifier_count) {
1389 ret = __clk_notify(core, event, core->rate, core->new_rate);
1390 if (ret & NOTIFY_STOP_MASK)
1391 fail_clk = core;
b2476490
MT
1392 }
1393
4dff95dc
SB
1394 hlist_for_each_entry(child, &core->children, child_node) {
1395 /* Skip children who will be reparented to another clock */
1396 if (child->new_parent && child->new_parent != core)
1397 continue;
1398 tmp_clk = clk_propagate_rate_change(child, event);
1399 if (tmp_clk)
1400 fail_clk = tmp_clk;
1401 }
5279fc40 1402
4dff95dc
SB
1403 /* handle the new child who might not be in core->children yet */
1404 if (core->new_child) {
1405 tmp_clk = clk_propagate_rate_change(core->new_child, event);
1406 if (tmp_clk)
1407 fail_clk = tmp_clk;
1408 }
5279fc40 1409
4dff95dc 1410 return fail_clk;
5279fc40
BB
1411}
1412
4dff95dc
SB
1413/*
1414 * walk down a subtree and set the new rates notifying the rate
1415 * change on the way
1416 */
1417static void clk_change_rate(struct clk_core *core)
035a61c3 1418{
4dff95dc
SB
1419 struct clk_core *child;
1420 struct hlist_node *tmp;
1421 unsigned long old_rate;
1422 unsigned long best_parent_rate = 0;
1423 bool skip_set_rate = false;
1424 struct clk_core *old_parent;
035a61c3 1425
4dff95dc 1426 old_rate = core->rate;
035a61c3 1427
4dff95dc
SB
1428 if (core->new_parent)
1429 best_parent_rate = core->new_parent->rate;
1430 else if (core->parent)
1431 best_parent_rate = core->parent->rate;
035a61c3 1432
2eb8c710
HS
1433 if (core->flags & CLK_SET_RATE_UNGATE) {
1434 unsigned long flags;
1435
1436 clk_core_prepare(core);
1437 flags = clk_enable_lock();
1438 clk_core_enable(core);
1439 clk_enable_unlock(flags);
1440 }
1441
4dff95dc
SB
1442 if (core->new_parent && core->new_parent != core->parent) {
1443 old_parent = __clk_set_parent_before(core, core->new_parent);
1444 trace_clk_set_parent(core, core->new_parent);
5279fc40 1445
4dff95dc
SB
1446 if (core->ops->set_rate_and_parent) {
1447 skip_set_rate = true;
1448 core->ops->set_rate_and_parent(core->hw, core->new_rate,
1449 best_parent_rate,
1450 core->new_parent_index);
1451 } else if (core->ops->set_parent) {
1452 core->ops->set_parent(core->hw, core->new_parent_index);
1453 }
5279fc40 1454
4dff95dc
SB
1455 trace_clk_set_parent_complete(core, core->new_parent);
1456 __clk_set_parent_after(core, core->new_parent, old_parent);
1457 }
8f2c2db1 1458
4dff95dc 1459 trace_clk_set_rate(core, core->new_rate);
b2476490 1460
4dff95dc
SB
1461 if (!skip_set_rate && core->ops->set_rate)
1462 core->ops->set_rate(core->hw, core->new_rate, best_parent_rate);
496eadf8 1463
4dff95dc 1464 trace_clk_set_rate_complete(core, core->new_rate);
b2476490 1465
4dff95dc 1466 core->rate = clk_recalc(core, best_parent_rate);
b2476490 1467
2eb8c710
HS
1468 if (core->flags & CLK_SET_RATE_UNGATE) {
1469 unsigned long flags;
1470
1471 flags = clk_enable_lock();
1472 clk_core_disable(core);
1473 clk_enable_unlock(flags);
1474 clk_core_unprepare(core);
1475 }
1476
4dff95dc
SB
1477 if (core->notifier_count && old_rate != core->rate)
1478 __clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate);
b2476490 1479
85e88fab
MT
1480 if (core->flags & CLK_RECALC_NEW_RATES)
1481 (void)clk_calc_new_rates(core, core->new_rate);
d8d91987 1482
b2476490 1483 /*
4dff95dc
SB
1484 * Use safe iteration, as change_rate can actually swap parents
1485 * for certain clock types.
b2476490 1486 */
4dff95dc
SB
1487 hlist_for_each_entry_safe(child, tmp, &core->children, child_node) {
1488 /* Skip children who will be reparented to another clock */
1489 if (child->new_parent && child->new_parent != core)
1490 continue;
1491 clk_change_rate(child);
1492 }
b2476490 1493
4dff95dc
SB
1494 /* handle the new child who might not be in core->children yet */
1495 if (core->new_child)
1496 clk_change_rate(core->new_child);
b2476490
MT
1497}
1498
4dff95dc
SB
1499static int clk_core_set_rate_nolock(struct clk_core *core,
1500 unsigned long req_rate)
a093bde2 1501{
4dff95dc
SB
1502 struct clk_core *top, *fail_clk;
1503 unsigned long rate = req_rate;
a093bde2 1504
4dff95dc
SB
1505 if (!core)
1506 return 0;
a093bde2 1507
4dff95dc
SB
1508 /* bail early if nothing to do */
1509 if (rate == clk_core_get_rate_nolock(core))
1510 return 0;
a093bde2 1511
4dff95dc
SB
1512 if ((core->flags & CLK_SET_RATE_GATE) && core->prepare_count)
1513 return -EBUSY;
a093bde2 1514
4dff95dc
SB
1515 /* calculate new rates and get the topmost changed clock */
1516 top = clk_calc_new_rates(core, rate);
1517 if (!top)
1518 return -EINVAL;
1519
1520 /* notify that we are about to change rates */
1521 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
1522 if (fail_clk) {
1523 pr_debug("%s: failed to set %s rate\n", __func__,
1524 fail_clk->name);
1525 clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
1526 return -EBUSY;
1527 }
1528
1529 /* change the rates */
1530 clk_change_rate(top);
1531
1532 core->req_rate = req_rate;
1533
06b37e4a 1534 return 0;
a093bde2 1535}
035a61c3
TV
1536
1537/**
4dff95dc
SB
1538 * clk_set_rate - specify a new rate for clk
1539 * @clk: the clk whose rate is being changed
1540 * @rate: the new rate for clk
035a61c3 1541 *
4dff95dc
SB
1542 * In the simplest case clk_set_rate will only adjust the rate of clk.
1543 *
1544 * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to
1545 * propagate up to clk's parent; whether or not this happens depends on the
1546 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
1547 * after calling .round_rate then upstream parent propagation is ignored. If
1548 * *parent_rate comes back with a new rate for clk's parent then we propagate
1549 * up to clk's parent and set its rate. Upward propagation will continue
1550 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
1551 * .round_rate stops requesting changes to clk's parent_rate.
1552 *
1553 * Rate changes are accomplished via tree traversal that also recalculates the
1554 * rates for the clocks and fires off POST_RATE_CHANGE notifiers.
1555 *
1556 * Returns 0 on success, -EERROR otherwise.
035a61c3 1557 */
4dff95dc 1558int clk_set_rate(struct clk *clk, unsigned long rate)
035a61c3 1559{
4dff95dc
SB
1560 int ret;
1561
035a61c3
TV
1562 if (!clk)
1563 return 0;
1564
4dff95dc
SB
1565 /* prevent racing with updates to the clock topology */
1566 clk_prepare_lock();
da0f0b2c 1567
4dff95dc 1568 ret = clk_core_set_rate_nolock(clk->core, rate);
da0f0b2c 1569
4dff95dc 1570 clk_prepare_unlock();
4935b22c 1571
4dff95dc 1572 return ret;
4935b22c 1573}
4dff95dc 1574EXPORT_SYMBOL_GPL(clk_set_rate);
4935b22c 1575
4dff95dc
SB
1576/**
1577 * clk_set_rate_range - set a rate range for a clock source
1578 * @clk: clock source
1579 * @min: desired minimum clock rate in Hz, inclusive
1580 * @max: desired maximum clock rate in Hz, inclusive
1581 *
1582 * Returns success (0) or negative errno.
1583 */
1584int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
4935b22c 1585{
4dff95dc 1586 int ret = 0;
4935b22c 1587
4dff95dc
SB
1588 if (!clk)
1589 return 0;
903efc55 1590
4dff95dc
SB
1591 if (min > max) {
1592 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n",
1593 __func__, clk->core->name, clk->dev_id, clk->con_id,
1594 min, max);
1595 return -EINVAL;
903efc55 1596 }
4935b22c 1597
4dff95dc 1598 clk_prepare_lock();
4935b22c 1599
4dff95dc
SB
1600 if (min != clk->min_rate || max != clk->max_rate) {
1601 clk->min_rate = min;
1602 clk->max_rate = max;
1603 ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
4935b22c
JH
1604 }
1605
4dff95dc 1606 clk_prepare_unlock();
4935b22c 1607
4dff95dc 1608 return ret;
3fa2252b 1609}
4dff95dc 1610EXPORT_SYMBOL_GPL(clk_set_rate_range);
3fa2252b 1611
4dff95dc
SB
1612/**
1613 * clk_set_min_rate - set a minimum clock rate for a clock source
1614 * @clk: clock source
1615 * @rate: desired minimum clock rate in Hz, inclusive
1616 *
1617 * Returns success (0) or negative errno.
1618 */
1619int clk_set_min_rate(struct clk *clk, unsigned long rate)
3fa2252b 1620{
4dff95dc
SB
1621 if (!clk)
1622 return 0;
1623
1624 return clk_set_rate_range(clk, rate, clk->max_rate);
3fa2252b 1625}
4dff95dc 1626EXPORT_SYMBOL_GPL(clk_set_min_rate);
3fa2252b 1627
4dff95dc
SB
1628/**
1629 * clk_set_max_rate - set a maximum clock rate for a clock source
1630 * @clk: clock source
1631 * @rate: desired maximum clock rate in Hz, inclusive
1632 *
1633 * Returns success (0) or negative errno.
1634 */
1635int clk_set_max_rate(struct clk *clk, unsigned long rate)
3fa2252b 1636{
4dff95dc
SB
1637 if (!clk)
1638 return 0;
4935b22c 1639
4dff95dc 1640 return clk_set_rate_range(clk, clk->min_rate, rate);
4935b22c 1641}
4dff95dc 1642EXPORT_SYMBOL_GPL(clk_set_max_rate);
4935b22c 1643
b2476490 1644/**
4dff95dc
SB
1645 * clk_get_parent - return the parent of a clk
1646 * @clk: the clk whose parent gets returned
b2476490 1647 *
4dff95dc 1648 * Simply returns clk->parent. Returns NULL if clk is NULL.
b2476490 1649 */
4dff95dc 1650struct clk *clk_get_parent(struct clk *clk)
b2476490 1651{
4dff95dc 1652 struct clk *parent;
b2476490 1653
fc4a05d4
SB
1654 if (!clk)
1655 return NULL;
1656
4dff95dc 1657 clk_prepare_lock();
fc4a05d4
SB
1658 /* TODO: Create a per-user clk and change callers to call clk_put */
1659 parent = !clk->core->parent ? NULL : clk->core->parent->hw->clk;
4dff95dc 1660 clk_prepare_unlock();
496eadf8 1661
4dff95dc
SB
1662 return parent;
1663}
1664EXPORT_SYMBOL_GPL(clk_get_parent);
b2476490 1665
4dff95dc
SB
1666static struct clk_core *__clk_init_parent(struct clk_core *core)
1667{
5146e0b0 1668 u8 index = 0;
4dff95dc 1669
2430a94d 1670 if (core->num_parents > 1 && core->ops->get_parent)
5146e0b0 1671 index = core->ops->get_parent(core->hw);
b2476490 1672
5146e0b0 1673 return clk_core_get_parent_by_index(core, index);
b2476490
MT
1674}
1675
4dff95dc
SB
1676static void clk_core_reparent(struct clk_core *core,
1677 struct clk_core *new_parent)
b2476490 1678{
4dff95dc
SB
1679 clk_reparent(core, new_parent);
1680 __clk_recalc_accuracies(core);
1681 __clk_recalc_rates(core, POST_RATE_CHANGE);
b2476490
MT
1682}
1683
42c86547
TV
1684void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent)
1685{
1686 if (!hw)
1687 return;
1688
1689 clk_core_reparent(hw->core, !new_parent ? NULL : new_parent->core);
1690}
1691
4dff95dc
SB
1692/**
1693 * clk_has_parent - check if a clock is a possible parent for another
1694 * @clk: clock source
1695 * @parent: parent clock source
1696 *
1697 * This function can be used in drivers that need to check that a clock can be
1698 * the parent of another without actually changing the parent.
1699 *
1700 * Returns true if @parent is a possible parent for @clk, false otherwise.
b2476490 1701 */
4dff95dc 1702bool clk_has_parent(struct clk *clk, struct clk *parent)
b2476490 1703{
4dff95dc
SB
1704 struct clk_core *core, *parent_core;
1705 unsigned int i;
b2476490 1706
4dff95dc
SB
1707 /* NULL clocks should be nops, so return success if either is NULL. */
1708 if (!clk || !parent)
1709 return true;
7452b219 1710
4dff95dc
SB
1711 core = clk->core;
1712 parent_core = parent->core;
71472c0c 1713
4dff95dc
SB
1714 /* Optimize for the case where the parent is already the parent. */
1715 if (core->parent == parent_core)
1716 return true;
1c8e6004 1717
4dff95dc
SB
1718 for (i = 0; i < core->num_parents; i++)
1719 if (strcmp(core->parent_names[i], parent_core->name) == 0)
1720 return true;
03bc10ab 1721
4dff95dc
SB
1722 return false;
1723}
1724EXPORT_SYMBOL_GPL(clk_has_parent);
03bc10ab 1725
4dff95dc
SB
1726static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
1727{
1728 int ret = 0;
1729 int p_index = 0;
1730 unsigned long p_rate = 0;
1731
1732 if (!core)
1733 return 0;
1734
1735 /* prevent racing with updates to the clock topology */
1736 clk_prepare_lock();
1737
1738 if (core->parent == parent)
1739 goto out;
1740
1741 /* verify ops for for multi-parent clks */
1742 if ((core->num_parents > 1) && (!core->ops->set_parent)) {
1743 ret = -ENOSYS;
63f5c3b2 1744 goto out;
7452b219
MT
1745 }
1746
4dff95dc
SB
1747 /* check that we are allowed to re-parent if the clock is in use */
1748 if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
1749 ret = -EBUSY;
1750 goto out;
b2476490
MT
1751 }
1752
71472c0c 1753 /* try finding the new parent index */
4dff95dc 1754 if (parent) {
d6968fca 1755 p_index = clk_fetch_parent_index(core, parent);
f1c8b2ed 1756 if (p_index < 0) {
71472c0c 1757 pr_debug("%s: clk %s can not be parent of clk %s\n",
4dff95dc
SB
1758 __func__, parent->name, core->name);
1759 ret = p_index;
1760 goto out;
71472c0c 1761 }
e8f0e68e 1762 p_rate = parent->rate;
b2476490
MT
1763 }
1764
4dff95dc
SB
1765 /* propagate PRE_RATE_CHANGE notifications */
1766 ret = __clk_speculate_rates(core, p_rate);
b2476490 1767
4dff95dc
SB
1768 /* abort if a driver objects */
1769 if (ret & NOTIFY_STOP_MASK)
1770 goto out;
b2476490 1771
4dff95dc
SB
1772 /* do the re-parent */
1773 ret = __clk_set_parent(core, parent, p_index);
b2476490 1774
4dff95dc
SB
1775 /* propagate rate an accuracy recalculation accordingly */
1776 if (ret) {
1777 __clk_recalc_rates(core, ABORT_RATE_CHANGE);
1778 } else {
1779 __clk_recalc_rates(core, POST_RATE_CHANGE);
1780 __clk_recalc_accuracies(core);
b2476490
MT
1781 }
1782
4dff95dc
SB
1783out:
1784 clk_prepare_unlock();
71472c0c 1785
4dff95dc
SB
1786 return ret;
1787}
b2476490 1788
4dff95dc
SB
1789/**
1790 * clk_set_parent - switch the parent of a mux clk
1791 * @clk: the mux clk whose input we are switching
1792 * @parent: the new input to clk
1793 *
1794 * Re-parent clk to use parent as its new input source. If clk is in
1795 * prepared state, the clk will get enabled for the duration of this call. If
1796 * that's not acceptable for a specific clk (Eg: the consumer can't handle
1797 * that, the reparenting is glitchy in hardware, etc), use the
1798 * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
1799 *
1800 * After successfully changing clk's parent clk_set_parent will update the
1801 * clk topology, sysfs topology and propagate rate recalculation via
1802 * __clk_recalc_rates.
1803 *
1804 * Returns 0 on success, -EERROR otherwise.
1805 */
1806int clk_set_parent(struct clk *clk, struct clk *parent)
1807{
1808 if (!clk)
1809 return 0;
1810
1811 return clk_core_set_parent(clk->core, parent ? parent->core : NULL);
b2476490 1812}
4dff95dc 1813EXPORT_SYMBOL_GPL(clk_set_parent);
b2476490 1814
4dff95dc
SB
1815/**
1816 * clk_set_phase - adjust the phase shift of a clock signal
1817 * @clk: clock signal source
1818 * @degrees: number of degrees the signal is shifted
1819 *
1820 * Shifts the phase of a clock signal by the specified
1821 * degrees. Returns 0 on success, -EERROR otherwise.
1822 *
1823 * This function makes no distinction about the input or reference
1824 * signal that we adjust the clock signal phase against. For example
1825 * phase locked-loop clock signal generators we may shift phase with
1826 * respect to feedback clock signal input, but for other cases the
1827 * clock phase may be shifted with respect to some other, unspecified
1828 * signal.
1829 *
1830 * Additionally the concept of phase shift does not propagate through
1831 * the clock tree hierarchy, which sets it apart from clock rates and
1832 * clock accuracy. A parent clock phase attribute does not have an
1833 * impact on the phase attribute of a child clock.
b2476490 1834 */
4dff95dc 1835int clk_set_phase(struct clk *clk, int degrees)
b2476490 1836{
4dff95dc 1837 int ret = -EINVAL;
b2476490 1838
4dff95dc
SB
1839 if (!clk)
1840 return 0;
b2476490 1841
4dff95dc
SB
1842 /* sanity check degrees */
1843 degrees %= 360;
1844 if (degrees < 0)
1845 degrees += 360;
bf47b4fd 1846
4dff95dc 1847 clk_prepare_lock();
3fa2252b 1848
023bd716
SL
1849 /* bail early if nothing to do */
1850 if (degrees == clk->core->phase)
1851 goto out;
1852
4dff95dc 1853 trace_clk_set_phase(clk->core, degrees);
3fa2252b 1854
4dff95dc
SB
1855 if (clk->core->ops->set_phase)
1856 ret = clk->core->ops->set_phase(clk->core->hw, degrees);
3fa2252b 1857
4dff95dc 1858 trace_clk_set_phase_complete(clk->core, degrees);
dfc202ea 1859
4dff95dc
SB
1860 if (!ret)
1861 clk->core->phase = degrees;
b2476490 1862
023bd716 1863out:
4dff95dc 1864 clk_prepare_unlock();
dfc202ea 1865
4dff95dc
SB
1866 return ret;
1867}
1868EXPORT_SYMBOL_GPL(clk_set_phase);
b2476490 1869
4dff95dc
SB
1870static int clk_core_get_phase(struct clk_core *core)
1871{
1872 int ret;
b2476490 1873
4dff95dc
SB
1874 clk_prepare_lock();
1875 ret = core->phase;
1876 clk_prepare_unlock();
71472c0c 1877
4dff95dc 1878 return ret;
b2476490
MT
1879}
1880
4dff95dc
SB
1881/**
1882 * clk_get_phase - return the phase shift of a clock signal
1883 * @clk: clock signal source
1884 *
1885 * Returns the phase shift of a clock node in degrees, otherwise returns
1886 * -EERROR.
1887 */
1888int clk_get_phase(struct clk *clk)
1c8e6004 1889{
4dff95dc 1890 if (!clk)
1c8e6004
TV
1891 return 0;
1892
4dff95dc
SB
1893 return clk_core_get_phase(clk->core);
1894}
1895EXPORT_SYMBOL_GPL(clk_get_phase);
1c8e6004 1896
4dff95dc
SB
1897/**
1898 * clk_is_match - check if two clk's point to the same hardware clock
1899 * @p: clk compared against q
1900 * @q: clk compared against p
1901 *
1902 * Returns true if the two struct clk pointers both point to the same hardware
1903 * clock node. Put differently, returns true if struct clk *p and struct clk *q
1904 * share the same struct clk_core object.
1905 *
1906 * Returns false otherwise. Note that two NULL clks are treated as matching.
1907 */
1908bool clk_is_match(const struct clk *p, const struct clk *q)
1909{
1910 /* trivial case: identical struct clk's or both NULL */
1911 if (p == q)
1912 return true;
1c8e6004 1913
3fe003f9 1914 /* true if clk->core pointers match. Avoid dereferencing garbage */
4dff95dc
SB
1915 if (!IS_ERR_OR_NULL(p) && !IS_ERR_OR_NULL(q))
1916 if (p->core == q->core)
1917 return true;
1c8e6004 1918
4dff95dc
SB
1919 return false;
1920}
1921EXPORT_SYMBOL_GPL(clk_is_match);
1c8e6004 1922
4dff95dc 1923/*** debugfs support ***/
1c8e6004 1924
4dff95dc
SB
1925#ifdef CONFIG_DEBUG_FS
1926#include <linux/debugfs.h>
1c8e6004 1927
4dff95dc
SB
1928static struct dentry *rootdir;
1929static int inited = 0;
1930static DEFINE_MUTEX(clk_debug_lock);
1931static HLIST_HEAD(clk_debug_list);
1c8e6004 1932
4dff95dc
SB
1933static struct hlist_head *all_lists[] = {
1934 &clk_root_list,
1935 &clk_orphan_list,
1936 NULL,
1937};
1938
1939static struct hlist_head *orphan_list[] = {
1940 &clk_orphan_list,
1941 NULL,
1942};
1943
1944static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
1945 int level)
b2476490 1946{
4dff95dc
SB
1947 if (!c)
1948 return;
b2476490 1949
4dff95dc
SB
1950 seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n",
1951 level * 3 + 1, "",
1952 30 - level * 3, c->name,
1953 c->enable_count, c->prepare_count, clk_core_get_rate(c),
1954 clk_core_get_accuracy(c), clk_core_get_phase(c));
1955}
89ac8d7a 1956
4dff95dc
SB
1957static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
1958 int level)
1959{
1960 struct clk_core *child;
b2476490 1961
4dff95dc
SB
1962 if (!c)
1963 return;
b2476490 1964
4dff95dc 1965 clk_summary_show_one(s, c, level);
0e1c0301 1966
4dff95dc
SB
1967 hlist_for_each_entry(child, &c->children, child_node)
1968 clk_summary_show_subtree(s, child, level + 1);
1c8e6004 1969}
b2476490 1970
4dff95dc 1971static int clk_summary_show(struct seq_file *s, void *data)
1c8e6004 1972{
4dff95dc
SB
1973 struct clk_core *c;
1974 struct hlist_head **lists = (struct hlist_head **)s->private;
1c8e6004 1975
4dff95dc
SB
1976 seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n");
1977 seq_puts(s, "----------------------------------------------------------------------------------------\n");
b2476490 1978
1c8e6004
TV
1979 clk_prepare_lock();
1980
4dff95dc
SB
1981 for (; *lists; lists++)
1982 hlist_for_each_entry(c, *lists, child_node)
1983 clk_summary_show_subtree(s, c, 0);
b2476490 1984
eab89f69 1985 clk_prepare_unlock();
b2476490 1986
4dff95dc 1987 return 0;
b2476490 1988}
1c8e6004 1989
1c8e6004 1990
4dff95dc 1991static int clk_summary_open(struct inode *inode, struct file *file)
1c8e6004 1992{
4dff95dc 1993 return single_open(file, clk_summary_show, inode->i_private);
1c8e6004 1994}
b2476490 1995
4dff95dc
SB
1996static const struct file_operations clk_summary_fops = {
1997 .open = clk_summary_open,
1998 .read = seq_read,
1999 .llseek = seq_lseek,
2000 .release = single_release,
2001};
b2476490 2002
4dff95dc
SB
2003static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
2004{
2005 if (!c)
2006 return;
b2476490 2007
7cb81136 2008 /* This should be JSON format, i.e. elements separated with a comma */
4dff95dc
SB
2009 seq_printf(s, "\"%s\": { ", c->name);
2010 seq_printf(s, "\"enable_count\": %d,", c->enable_count);
2011 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
7cb81136
SW
2012 seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
2013 seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
4dff95dc 2014 seq_printf(s, "\"phase\": %d", clk_core_get_phase(c));
b2476490 2015}
b2476490 2016
4dff95dc 2017static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
b2476490 2018{
4dff95dc 2019 struct clk_core *child;
b2476490 2020
4dff95dc
SB
2021 if (!c)
2022 return;
b2476490 2023
4dff95dc 2024 clk_dump_one(s, c, level);
b2476490 2025
4dff95dc
SB
2026 hlist_for_each_entry(child, &c->children, child_node) {
2027 seq_printf(s, ",");
2028 clk_dump_subtree(s, child, level + 1);
b2476490
MT
2029 }
2030
4dff95dc 2031 seq_printf(s, "}");
b2476490
MT
2032}
2033
4dff95dc 2034static int clk_dump(struct seq_file *s, void *data)
4e88f3de 2035{
4dff95dc
SB
2036 struct clk_core *c;
2037 bool first_node = true;
2038 struct hlist_head **lists = (struct hlist_head **)s->private;
4e88f3de 2039
4dff95dc 2040 seq_printf(s, "{");
4e88f3de 2041
4dff95dc 2042 clk_prepare_lock();
035a61c3 2043
4dff95dc
SB
2044 for (; *lists; lists++) {
2045 hlist_for_each_entry(c, *lists, child_node) {
2046 if (!first_node)
2047 seq_puts(s, ",");
2048 first_node = false;
2049 clk_dump_subtree(s, c, 0);
2050 }
2051 }
4e88f3de 2052
4dff95dc 2053 clk_prepare_unlock();
4e88f3de 2054
70e9f4dd 2055 seq_puts(s, "}\n");
4dff95dc 2056 return 0;
4e88f3de 2057}
4e88f3de 2058
4dff95dc
SB
2059
2060static int clk_dump_open(struct inode *inode, struct file *file)
b2476490 2061{
4dff95dc
SB
2062 return single_open(file, clk_dump, inode->i_private);
2063}
b2476490 2064
4dff95dc
SB
2065static const struct file_operations clk_dump_fops = {
2066 .open = clk_dump_open,
2067 .read = seq_read,
2068 .llseek = seq_lseek,
2069 .release = single_release,
2070};
89ac8d7a 2071
4dff95dc
SB
2072static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
2073{
2074 struct dentry *d;
2075 int ret = -ENOMEM;
b2476490 2076
4dff95dc
SB
2077 if (!core || !pdentry) {
2078 ret = -EINVAL;
b2476490 2079 goto out;
4dff95dc 2080 }
b2476490 2081
4dff95dc
SB
2082 d = debugfs_create_dir(core->name, pdentry);
2083 if (!d)
b61c43c0 2084 goto out;
b61c43c0 2085
4dff95dc
SB
2086 core->dentry = d;
2087
2088 d = debugfs_create_u32("clk_rate", S_IRUGO, core->dentry,
2089 (u32 *)&core->rate);
2090 if (!d)
2091 goto err_out;
2092
2093 d = debugfs_create_u32("clk_accuracy", S_IRUGO, core->dentry,
2094 (u32 *)&core->accuracy);
2095 if (!d)
2096 goto err_out;
2097
2098 d = debugfs_create_u32("clk_phase", S_IRUGO, core->dentry,
2099 (u32 *)&core->phase);
2100 if (!d)
2101 goto err_out;
031dcc9b 2102
4dff95dc
SB
2103 d = debugfs_create_x32("clk_flags", S_IRUGO, core->dentry,
2104 (u32 *)&core->flags);
2105 if (!d)
2106 goto err_out;
031dcc9b 2107
4dff95dc
SB
2108 d = debugfs_create_u32("clk_prepare_count", S_IRUGO, core->dentry,
2109 (u32 *)&core->prepare_count);
2110 if (!d)
2111 goto err_out;
b2476490 2112
4dff95dc
SB
2113 d = debugfs_create_u32("clk_enable_count", S_IRUGO, core->dentry,
2114 (u32 *)&core->enable_count);
2115 if (!d)
2116 goto err_out;
b2476490 2117
4dff95dc
SB
2118 d = debugfs_create_u32("clk_notifier_count", S_IRUGO, core->dentry,
2119 (u32 *)&core->notifier_count);
2120 if (!d)
2121 goto err_out;
b2476490 2122
4dff95dc
SB
2123 if (core->ops->debug_init) {
2124 ret = core->ops->debug_init(core->hw, core->dentry);
2125 if (ret)
2126 goto err_out;
5279fc40 2127 }
b2476490 2128
4dff95dc
SB
2129 ret = 0;
2130 goto out;
b2476490 2131
4dff95dc
SB
2132err_out:
2133 debugfs_remove_recursive(core->dentry);
2134 core->dentry = NULL;
2135out:
b2476490
MT
2136 return ret;
2137}
035a61c3
TV
2138
2139/**
6e5ab41b
SB
2140 * clk_debug_register - add a clk node to the debugfs clk directory
2141 * @core: the clk being added to the debugfs clk directory
035a61c3 2142 *
6e5ab41b
SB
2143 * Dynamically adds a clk to the debugfs clk directory if debugfs has been
2144 * initialized. Otherwise it bails out early since the debugfs clk directory
4dff95dc 2145 * will be created lazily by clk_debug_init as part of a late_initcall.
035a61c3 2146 */
4dff95dc 2147static int clk_debug_register(struct clk_core *core)
035a61c3 2148{
4dff95dc 2149 int ret = 0;
035a61c3 2150
4dff95dc
SB
2151 mutex_lock(&clk_debug_lock);
2152 hlist_add_head(&core->debug_node, &clk_debug_list);
2153
2154 if (!inited)
2155 goto unlock;
2156
2157 ret = clk_debug_create_one(core, rootdir);
2158unlock:
2159 mutex_unlock(&clk_debug_lock);
2160
2161 return ret;
035a61c3 2162}
b2476490 2163
4dff95dc 2164 /**
6e5ab41b
SB
2165 * clk_debug_unregister - remove a clk node from the debugfs clk directory
2166 * @core: the clk being removed from the debugfs clk directory
e59c5371 2167 *
6e5ab41b
SB
2168 * Dynamically removes a clk and all its child nodes from the
2169 * debugfs clk directory if clk->dentry points to debugfs created by
706d5c73 2170 * clk_debug_register in __clk_core_init.
e59c5371 2171 */
4dff95dc 2172static void clk_debug_unregister(struct clk_core *core)
e59c5371 2173{
4dff95dc
SB
2174 mutex_lock(&clk_debug_lock);
2175 hlist_del_init(&core->debug_node);
2176 debugfs_remove_recursive(core->dentry);
2177 core->dentry = NULL;
2178 mutex_unlock(&clk_debug_lock);
2179}
e59c5371 2180
4dff95dc
SB
2181struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
2182 void *data, const struct file_operations *fops)
2183{
2184 struct dentry *d = NULL;
e59c5371 2185
4dff95dc
SB
2186 if (hw->core->dentry)
2187 d = debugfs_create_file(name, mode, hw->core->dentry, data,
2188 fops);
e59c5371 2189
4dff95dc
SB
2190 return d;
2191}
2192EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
e59c5371 2193
4dff95dc 2194/**
6e5ab41b 2195 * clk_debug_init - lazily populate the debugfs clk directory
4dff95dc 2196 *
6e5ab41b
SB
2197 * clks are often initialized very early during boot before memory can be
2198 * dynamically allocated and well before debugfs is setup. This function
2199 * populates the debugfs clk directory once at boot-time when we know that
2200 * debugfs is setup. It should only be called once at boot-time, all other clks
2201 * added dynamically will be done so with clk_debug_register.
4dff95dc
SB
2202 */
2203static int __init clk_debug_init(void)
2204{
2205 struct clk_core *core;
2206 struct dentry *d;
dfc202ea 2207
4dff95dc 2208 rootdir = debugfs_create_dir("clk", NULL);
e59c5371 2209
4dff95dc
SB
2210 if (!rootdir)
2211 return -ENOMEM;
dfc202ea 2212
4dff95dc
SB
2213 d = debugfs_create_file("clk_summary", S_IRUGO, rootdir, &all_lists,
2214 &clk_summary_fops);
2215 if (!d)
2216 return -ENOMEM;
e59c5371 2217
4dff95dc
SB
2218 d = debugfs_create_file("clk_dump", S_IRUGO, rootdir, &all_lists,
2219 &clk_dump_fops);
2220 if (!d)
2221 return -ENOMEM;
e59c5371 2222
4dff95dc
SB
2223 d = debugfs_create_file("clk_orphan_summary", S_IRUGO, rootdir,
2224 &orphan_list, &clk_summary_fops);
2225 if (!d)
2226 return -ENOMEM;
e59c5371 2227
4dff95dc
SB
2228 d = debugfs_create_file("clk_orphan_dump", S_IRUGO, rootdir,
2229 &orphan_list, &clk_dump_fops);
2230 if (!d)
2231 return -ENOMEM;
e59c5371 2232
4dff95dc
SB
2233 mutex_lock(&clk_debug_lock);
2234 hlist_for_each_entry(core, &clk_debug_list, debug_node)
2235 clk_debug_create_one(core, rootdir);
e59c5371 2236
4dff95dc
SB
2237 inited = 1;
2238 mutex_unlock(&clk_debug_lock);
e59c5371 2239
4dff95dc
SB
2240 return 0;
2241}
2242late_initcall(clk_debug_init);
2243#else
2244static inline int clk_debug_register(struct clk_core *core) { return 0; }
2245static inline void clk_debug_reparent(struct clk_core *core,
2246 struct clk_core *new_parent)
035a61c3 2247{
035a61c3 2248}
4dff95dc 2249static inline void clk_debug_unregister(struct clk_core *core)
3d3801ef 2250{
3d3801ef 2251}
4dff95dc 2252#endif
3d3801ef 2253
b2476490 2254/**
be45ebf2 2255 * __clk_core_init - initialize the data structures in a struct clk_core
d35c80c2 2256 * @core: clk_core being initialized
b2476490 2257 *
035a61c3 2258 * Initializes the lists in struct clk_core, queries the hardware for the
b2476490 2259 * parent and rate and sets them both.
b2476490 2260 */
be45ebf2 2261static int __clk_core_init(struct clk_core *core)
b2476490 2262{
d1302a36 2263 int i, ret = 0;
035a61c3 2264 struct clk_core *orphan;
b67bfe0d 2265 struct hlist_node *tmp2;
1c8e6004 2266 unsigned long rate;
b2476490 2267
d35c80c2 2268 if (!core)
d1302a36 2269 return -EINVAL;
b2476490 2270
eab89f69 2271 clk_prepare_lock();
b2476490
MT
2272
2273 /* check to see if a clock with this name is already registered */
d6968fca 2274 if (clk_core_lookup(core->name)) {
d1302a36 2275 pr_debug("%s: clk %s already initialized\n",
d6968fca 2276 __func__, core->name);
d1302a36 2277 ret = -EEXIST;
b2476490 2278 goto out;
d1302a36 2279 }
b2476490 2280
d4d7e3dd 2281 /* check that clk_ops are sane. See Documentation/clk.txt */
d6968fca
SB
2282 if (core->ops->set_rate &&
2283 !((core->ops->round_rate || core->ops->determine_rate) &&
2284 core->ops->recalc_rate)) {
c44fccb5
MY
2285 pr_err("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
2286 __func__, core->name);
d1302a36 2287 ret = -EINVAL;
d4d7e3dd
MT
2288 goto out;
2289 }
2290
d6968fca 2291 if (core->ops->set_parent && !core->ops->get_parent) {
c44fccb5
MY
2292 pr_err("%s: %s must implement .get_parent & .set_parent\n",
2293 __func__, core->name);
d1302a36 2294 ret = -EINVAL;
d4d7e3dd
MT
2295 goto out;
2296 }
2297
3c8e77dd
MY
2298 if (core->num_parents > 1 && !core->ops->get_parent) {
2299 pr_err("%s: %s must implement .get_parent as it has multi parents\n",
2300 __func__, core->name);
2301 ret = -EINVAL;
2302 goto out;
2303 }
2304
d6968fca
SB
2305 if (core->ops->set_rate_and_parent &&
2306 !(core->ops->set_parent && core->ops->set_rate)) {
c44fccb5 2307 pr_err("%s: %s must implement .set_parent & .set_rate\n",
d6968fca 2308 __func__, core->name);
3fa2252b
SB
2309 ret = -EINVAL;
2310 goto out;
2311 }
2312
b2476490 2313 /* throw a WARN if any entries in parent_names are NULL */
d6968fca
SB
2314 for (i = 0; i < core->num_parents; i++)
2315 WARN(!core->parent_names[i],
b2476490 2316 "%s: invalid NULL in %s's .parent_names\n",
d6968fca 2317 __func__, core->name);
b2476490 2318
d6968fca 2319 core->parent = __clk_init_parent(core);
b2476490
MT
2320
2321 /*
706d5c73
SB
2322 * Populate core->parent if parent has already been clk_core_init'd. If
2323 * parent has not yet been clk_core_init'd then place clk in the orphan
47b0eeb3 2324 * list. If clk doesn't have any parents then place it in the root
b2476490
MT
2325 * clk list.
2326 *
2327 * Every time a new clk is clk_init'd then we walk the list of orphan
2328 * clocks and re-parent any that are children of the clock currently
2329 * being clk_init'd.
2330 */
e6500344 2331 if (core->parent) {
d6968fca
SB
2332 hlist_add_head(&core->child_node,
2333 &core->parent->children);
e6500344 2334 core->orphan = core->parent->orphan;
47b0eeb3 2335 } else if (!core->num_parents) {
d6968fca 2336 hlist_add_head(&core->child_node, &clk_root_list);
e6500344
HS
2337 core->orphan = false;
2338 } else {
d6968fca 2339 hlist_add_head(&core->child_node, &clk_orphan_list);
e6500344
HS
2340 core->orphan = true;
2341 }
b2476490 2342
5279fc40
BB
2343 /*
2344 * Set clk's accuracy. The preferred method is to use
2345 * .recalc_accuracy. For simple clocks and lazy developers the default
2346 * fallback is to use the parent's accuracy. If a clock doesn't have a
2347 * parent (or is orphaned) then accuracy is set to zero (perfect
2348 * clock).
2349 */
d6968fca
SB
2350 if (core->ops->recalc_accuracy)
2351 core->accuracy = core->ops->recalc_accuracy(core->hw,
2352 __clk_get_accuracy(core->parent));
2353 else if (core->parent)
2354 core->accuracy = core->parent->accuracy;
5279fc40 2355 else
d6968fca 2356 core->accuracy = 0;
5279fc40 2357
9824cf73
MR
2358 /*
2359 * Set clk's phase.
2360 * Since a phase is by definition relative to its parent, just
2361 * query the current clock phase, or just assume it's in phase.
2362 */
d6968fca
SB
2363 if (core->ops->get_phase)
2364 core->phase = core->ops->get_phase(core->hw);
9824cf73 2365 else
d6968fca 2366 core->phase = 0;
9824cf73 2367
b2476490
MT
2368 /*
2369 * Set clk's rate. The preferred method is to use .recalc_rate. For
2370 * simple clocks and lazy developers the default fallback is to use the
2371 * parent's rate. If a clock doesn't have a parent (or is orphaned)
2372 * then rate is set to zero.
2373 */
d6968fca
SB
2374 if (core->ops->recalc_rate)
2375 rate = core->ops->recalc_rate(core->hw,
2376 clk_core_get_rate_nolock(core->parent));
2377 else if (core->parent)
2378 rate = core->parent->rate;
b2476490 2379 else
1c8e6004 2380 rate = 0;
d6968fca 2381 core->rate = core->req_rate = rate;
b2476490
MT
2382
2383 /*
0e8f6e49
MY
2384 * walk the list of orphan clocks and reparent any that newly finds a
2385 * parent.
b2476490 2386 */
b67bfe0d 2387 hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
0e8f6e49 2388 struct clk_core *parent = __clk_init_parent(orphan);
1f61e5f1 2389
0e8f6e49
MY
2390 if (parent)
2391 clk_core_reparent(orphan, parent);
2392 }
b2476490
MT
2393
2394 /*
2395 * optional platform-specific magic
2396 *
2397 * The .init callback is not used by any of the basic clock types, but
2398 * exists for weird hardware that must perform initialization magic.
2399 * Please consider other ways of solving initialization problems before
24ee1a08 2400 * using this callback, as its use is discouraged.
b2476490 2401 */
d6968fca
SB
2402 if (core->ops->init)
2403 core->ops->init(core->hw);
b2476490 2404
32b9b109 2405 if (core->flags & CLK_IS_CRITICAL) {
ef56b79b
MR
2406 unsigned long flags;
2407
32b9b109 2408 clk_core_prepare(core);
ef56b79b
MR
2409
2410 flags = clk_enable_lock();
32b9b109 2411 clk_core_enable(core);
ef56b79b 2412 clk_enable_unlock(flags);
32b9b109
LJ
2413 }
2414
d6968fca 2415 kref_init(&core->ref);
b2476490 2416out:
eab89f69 2417 clk_prepare_unlock();
b2476490 2418
89f7e9de 2419 if (!ret)
d6968fca 2420 clk_debug_register(core);
89f7e9de 2421
d1302a36 2422 return ret;
b2476490
MT
2423}
2424
035a61c3
TV
2425struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
2426 const char *con_id)
0197b3ea 2427{
0197b3ea
SK
2428 struct clk *clk;
2429
035a61c3 2430 /* This is to allow this function to be chained to others */
c1de1357 2431 if (IS_ERR_OR_NULL(hw))
035a61c3 2432 return (struct clk *) hw;
0197b3ea 2433
035a61c3
TV
2434 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
2435 if (!clk)
2436 return ERR_PTR(-ENOMEM);
2437
2438 clk->core = hw->core;
2439 clk->dev_id = dev_id;
2440 clk->con_id = con_id;
1c8e6004
TV
2441 clk->max_rate = ULONG_MAX;
2442
2443 clk_prepare_lock();
50595f8b 2444 hlist_add_head(&clk->clks_node, &hw->core->clks);
1c8e6004 2445 clk_prepare_unlock();
0197b3ea
SK
2446
2447 return clk;
2448}
035a61c3 2449
73e0e496 2450void __clk_free_clk(struct clk *clk)
1c8e6004
TV
2451{
2452 clk_prepare_lock();
50595f8b 2453 hlist_del(&clk->clks_node);
1c8e6004
TV
2454 clk_prepare_unlock();
2455
2456 kfree(clk);
2457}
0197b3ea 2458
293ba3b4
SB
2459/**
2460 * clk_register - allocate a new clock, register it and return an opaque cookie
2461 * @dev: device that is registering this clock
2462 * @hw: link to hardware-specific clock data
2463 *
2464 * clk_register is the primary interface for populating the clock tree with new
2465 * clock nodes. It returns a pointer to the newly allocated struct clk which
a59a5163 2466 * cannot be dereferenced by driver code but may be used in conjunction with the
293ba3b4
SB
2467 * rest of the clock API. In the event of an error clk_register will return an
2468 * error code; drivers must test for an error code after calling clk_register.
2469 */
2470struct clk *clk_register(struct device *dev, struct clk_hw *hw)
b2476490 2471{
d1302a36 2472 int i, ret;
d6968fca 2473 struct clk_core *core;
293ba3b4 2474
d6968fca
SB
2475 core = kzalloc(sizeof(*core), GFP_KERNEL);
2476 if (!core) {
293ba3b4
SB
2477 ret = -ENOMEM;
2478 goto fail_out;
2479 }
b2476490 2480
d6968fca
SB
2481 core->name = kstrdup_const(hw->init->name, GFP_KERNEL);
2482 if (!core->name) {
0197b3ea
SK
2483 ret = -ENOMEM;
2484 goto fail_name;
2485 }
d6968fca 2486 core->ops = hw->init->ops;
ac2df527 2487 if (dev && dev->driver)
d6968fca
SB
2488 core->owner = dev->driver->owner;
2489 core->hw = hw;
2490 core->flags = hw->init->flags;
2491 core->num_parents = hw->init->num_parents;
9783c0d9
SB
2492 core->min_rate = 0;
2493 core->max_rate = ULONG_MAX;
d6968fca 2494 hw->core = core;
b2476490 2495
d1302a36 2496 /* allocate local copy in case parent_names is __initdata */
d6968fca 2497 core->parent_names = kcalloc(core->num_parents, sizeof(char *),
96a7ed90 2498 GFP_KERNEL);
d1302a36 2499
d6968fca 2500 if (!core->parent_names) {
d1302a36
MT
2501 ret = -ENOMEM;
2502 goto fail_parent_names;
2503 }
2504
2505
2506 /* copy each string name in case parent_names is __initdata */
d6968fca
SB
2507 for (i = 0; i < core->num_parents; i++) {
2508 core->parent_names[i] = kstrdup_const(hw->init->parent_names[i],
0197b3ea 2509 GFP_KERNEL);
d6968fca 2510 if (!core->parent_names[i]) {
d1302a36
MT
2511 ret = -ENOMEM;
2512 goto fail_parent_names_copy;
2513 }
2514 }
2515
176d1169
MY
2516 /* avoid unnecessary string look-ups of clk_core's possible parents. */
2517 core->parents = kcalloc(core->num_parents, sizeof(*core->parents),
2518 GFP_KERNEL);
2519 if (!core->parents) {
2520 ret = -ENOMEM;
2521 goto fail_parents;
2522 };
2523
d6968fca 2524 INIT_HLIST_HEAD(&core->clks);
1c8e6004 2525
035a61c3
TV
2526 hw->clk = __clk_create_clk(hw, NULL, NULL);
2527 if (IS_ERR(hw->clk)) {
035a61c3 2528 ret = PTR_ERR(hw->clk);
176d1169 2529 goto fail_parents;
035a61c3
TV
2530 }
2531
be45ebf2 2532 ret = __clk_core_init(core);
d1302a36 2533 if (!ret)
035a61c3 2534 return hw->clk;
b2476490 2535
1c8e6004 2536 __clk_free_clk(hw->clk);
035a61c3 2537 hw->clk = NULL;
b2476490 2538
176d1169
MY
2539fail_parents:
2540 kfree(core->parents);
d1302a36
MT
2541fail_parent_names_copy:
2542 while (--i >= 0)
d6968fca
SB
2543 kfree_const(core->parent_names[i]);
2544 kfree(core->parent_names);
d1302a36 2545fail_parent_names:
d6968fca 2546 kfree_const(core->name);
0197b3ea 2547fail_name:
d6968fca 2548 kfree(core);
d1302a36
MT
2549fail_out:
2550 return ERR_PTR(ret);
b2476490
MT
2551}
2552EXPORT_SYMBOL_GPL(clk_register);
2553
4143804c
SB
2554/**
2555 * clk_hw_register - register a clk_hw and return an error code
2556 * @dev: device that is registering this clock
2557 * @hw: link to hardware-specific clock data
2558 *
2559 * clk_hw_register is the primary interface for populating the clock tree with
2560 * new clock nodes. It returns an integer equal to zero indicating success or
2561 * less than zero indicating failure. Drivers must test for an error code after
2562 * calling clk_hw_register().
2563 */
2564int clk_hw_register(struct device *dev, struct clk_hw *hw)
2565{
2566 return PTR_ERR_OR_ZERO(clk_register(dev, hw));
2567}
2568EXPORT_SYMBOL_GPL(clk_hw_register);
2569
6e5ab41b 2570/* Free memory allocated for a clock. */
fcb0ee6a
SN
2571static void __clk_release(struct kref *ref)
2572{
d6968fca
SB
2573 struct clk_core *core = container_of(ref, struct clk_core, ref);
2574 int i = core->num_parents;
fcb0ee6a 2575
496eadf8
KK
2576 lockdep_assert_held(&prepare_lock);
2577
d6968fca 2578 kfree(core->parents);
fcb0ee6a 2579 while (--i >= 0)
d6968fca 2580 kfree_const(core->parent_names[i]);
fcb0ee6a 2581
d6968fca
SB
2582 kfree(core->parent_names);
2583 kfree_const(core->name);
2584 kfree(core);
fcb0ee6a
SN
2585}
2586
2587/*
2588 * Empty clk_ops for unregistered clocks. These are used temporarily
2589 * after clk_unregister() was called on a clock and until last clock
2590 * consumer calls clk_put() and the struct clk object is freed.
2591 */
2592static int clk_nodrv_prepare_enable(struct clk_hw *hw)
2593{
2594 return -ENXIO;
2595}
2596
2597static void clk_nodrv_disable_unprepare(struct clk_hw *hw)
2598{
2599 WARN_ON_ONCE(1);
2600}
2601
2602static int clk_nodrv_set_rate(struct clk_hw *hw, unsigned long rate,
2603 unsigned long parent_rate)
2604{
2605 return -ENXIO;
2606}
2607
2608static int clk_nodrv_set_parent(struct clk_hw *hw, u8 index)
2609{
2610 return -ENXIO;
2611}
2612
2613static const struct clk_ops clk_nodrv_ops = {
2614 .enable = clk_nodrv_prepare_enable,
2615 .disable = clk_nodrv_disable_unprepare,
2616 .prepare = clk_nodrv_prepare_enable,
2617 .unprepare = clk_nodrv_disable_unprepare,
2618 .set_rate = clk_nodrv_set_rate,
2619 .set_parent = clk_nodrv_set_parent,
2620};
2621
1df5c939
MB
2622/**
2623 * clk_unregister - unregister a currently registered clock
2624 * @clk: clock to unregister
1df5c939 2625 */
fcb0ee6a
SN
2626void clk_unregister(struct clk *clk)
2627{
2628 unsigned long flags;
2629
6314b679
SB
2630 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
2631 return;
2632
035a61c3 2633 clk_debug_unregister(clk->core);
fcb0ee6a
SN
2634
2635 clk_prepare_lock();
2636
035a61c3
TV
2637 if (clk->core->ops == &clk_nodrv_ops) {
2638 pr_err("%s: unregistered clock: %s\n", __func__,
2639 clk->core->name);
4106a3d9 2640 goto unlock;
fcb0ee6a
SN
2641 }
2642 /*
2643 * Assign empty clock ops for consumers that might still hold
2644 * a reference to this clock.
2645 */
2646 flags = clk_enable_lock();
035a61c3 2647 clk->core->ops = &clk_nodrv_ops;
fcb0ee6a
SN
2648 clk_enable_unlock(flags);
2649
035a61c3
TV
2650 if (!hlist_empty(&clk->core->children)) {
2651 struct clk_core *child;
874f224c 2652 struct hlist_node *t;
fcb0ee6a
SN
2653
2654 /* Reparent all children to the orphan list. */
035a61c3
TV
2655 hlist_for_each_entry_safe(child, t, &clk->core->children,
2656 child_node)
2657 clk_core_set_parent(child, NULL);
fcb0ee6a
SN
2658 }
2659
035a61c3 2660 hlist_del_init(&clk->core->child_node);
fcb0ee6a 2661
035a61c3 2662 if (clk->core->prepare_count)
fcb0ee6a 2663 pr_warn("%s: unregistering prepared clock: %s\n",
035a61c3
TV
2664 __func__, clk->core->name);
2665 kref_put(&clk->core->ref, __clk_release);
4106a3d9 2666unlock:
fcb0ee6a
SN
2667 clk_prepare_unlock();
2668}
1df5c939
MB
2669EXPORT_SYMBOL_GPL(clk_unregister);
2670
4143804c
SB
2671/**
2672 * clk_hw_unregister - unregister a currently registered clk_hw
2673 * @hw: hardware-specific clock data to unregister
2674 */
2675void clk_hw_unregister(struct clk_hw *hw)
2676{
2677 clk_unregister(hw->clk);
2678}
2679EXPORT_SYMBOL_GPL(clk_hw_unregister);
2680
46c8773a
SB
2681static void devm_clk_release(struct device *dev, void *res)
2682{
293ba3b4 2683 clk_unregister(*(struct clk **)res);
46c8773a
SB
2684}
2685
4143804c
SB
2686static void devm_clk_hw_release(struct device *dev, void *res)
2687{
2688 clk_hw_unregister(*(struct clk_hw **)res);
2689}
2690
46c8773a
SB
2691/**
2692 * devm_clk_register - resource managed clk_register()
2693 * @dev: device that is registering this clock
2694 * @hw: link to hardware-specific clock data
2695 *
2696 * Managed clk_register(). Clocks returned from this function are
2697 * automatically clk_unregister()ed on driver detach. See clk_register() for
2698 * more information.
2699 */
2700struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw)
2701{
2702 struct clk *clk;
293ba3b4 2703 struct clk **clkp;
46c8773a 2704
293ba3b4
SB
2705 clkp = devres_alloc(devm_clk_release, sizeof(*clkp), GFP_KERNEL);
2706 if (!clkp)
46c8773a
SB
2707 return ERR_PTR(-ENOMEM);
2708
293ba3b4
SB
2709 clk = clk_register(dev, hw);
2710 if (!IS_ERR(clk)) {
2711 *clkp = clk;
2712 devres_add(dev, clkp);
46c8773a 2713 } else {
293ba3b4 2714 devres_free(clkp);
46c8773a
SB
2715 }
2716
2717 return clk;
2718}
2719EXPORT_SYMBOL_GPL(devm_clk_register);
2720
4143804c
SB
2721/**
2722 * devm_clk_hw_register - resource managed clk_hw_register()
2723 * @dev: device that is registering this clock
2724 * @hw: link to hardware-specific clock data
2725 *
c47265ad 2726 * Managed clk_hw_register(). Clocks registered by this function are
4143804c
SB
2727 * automatically clk_hw_unregister()ed on driver detach. See clk_hw_register()
2728 * for more information.
2729 */
2730int devm_clk_hw_register(struct device *dev, struct clk_hw *hw)
2731{
2732 struct clk_hw **hwp;
2733 int ret;
2734
2735 hwp = devres_alloc(devm_clk_hw_release, sizeof(*hwp), GFP_KERNEL);
2736 if (!hwp)
2737 return -ENOMEM;
2738
2739 ret = clk_hw_register(dev, hw);
2740 if (!ret) {
2741 *hwp = hw;
2742 devres_add(dev, hwp);
2743 } else {
2744 devres_free(hwp);
2745 }
2746
2747 return ret;
2748}
2749EXPORT_SYMBOL_GPL(devm_clk_hw_register);
2750
46c8773a
SB
2751static int devm_clk_match(struct device *dev, void *res, void *data)
2752{
2753 struct clk *c = res;
2754 if (WARN_ON(!c))
2755 return 0;
2756 return c == data;
2757}
2758
4143804c
SB
2759static int devm_clk_hw_match(struct device *dev, void *res, void *data)
2760{
2761 struct clk_hw *hw = res;
2762
2763 if (WARN_ON(!hw))
2764 return 0;
2765 return hw == data;
2766}
2767
46c8773a
SB
2768/**
2769 * devm_clk_unregister - resource managed clk_unregister()
2770 * @clk: clock to unregister
2771 *
2772 * Deallocate a clock allocated with devm_clk_register(). Normally
2773 * this function will not need to be called and the resource management
2774 * code will ensure that the resource is freed.
2775 */
2776void devm_clk_unregister(struct device *dev, struct clk *clk)
2777{
2778 WARN_ON(devres_release(dev, devm_clk_release, devm_clk_match, clk));
2779}
2780EXPORT_SYMBOL_GPL(devm_clk_unregister);
2781
4143804c
SB
2782/**
2783 * devm_clk_hw_unregister - resource managed clk_hw_unregister()
2784 * @dev: device that is unregistering the hardware-specific clock data
2785 * @hw: link to hardware-specific clock data
2786 *
2787 * Unregister a clk_hw registered with devm_clk_hw_register(). Normally
2788 * this function will not need to be called and the resource management
2789 * code will ensure that the resource is freed.
2790 */
2791void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw)
2792{
2793 WARN_ON(devres_release(dev, devm_clk_hw_release, devm_clk_hw_match,
2794 hw));
2795}
2796EXPORT_SYMBOL_GPL(devm_clk_hw_unregister);
2797
ac2df527
SN
2798/*
2799 * clkdev helpers
2800 */
2801int __clk_get(struct clk *clk)
2802{
035a61c3
TV
2803 struct clk_core *core = !clk ? NULL : clk->core;
2804
2805 if (core) {
2806 if (!try_module_get(core->owner))
00efcb1c 2807 return 0;
ac2df527 2808
035a61c3 2809 kref_get(&core->ref);
00efcb1c 2810 }
ac2df527
SN
2811 return 1;
2812}
2813
2814void __clk_put(struct clk *clk)
2815{
10cdfe54
TV
2816 struct module *owner;
2817
00efcb1c 2818 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
ac2df527
SN
2819 return;
2820
fcb0ee6a 2821 clk_prepare_lock();
1c8e6004 2822
50595f8b 2823 hlist_del(&clk->clks_node);
ec02ace8
TV
2824 if (clk->min_rate > clk->core->req_rate ||
2825 clk->max_rate < clk->core->req_rate)
2826 clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
2827
1c8e6004
TV
2828 owner = clk->core->owner;
2829 kref_put(&clk->core->ref, __clk_release);
2830
fcb0ee6a
SN
2831 clk_prepare_unlock();
2832
10cdfe54 2833 module_put(owner);
035a61c3 2834
035a61c3 2835 kfree(clk);
ac2df527
SN
2836}
2837
b2476490
MT
2838/*** clk rate change notifiers ***/
2839
2840/**
2841 * clk_notifier_register - add a clk rate change notifier
2842 * @clk: struct clk * to watch
2843 * @nb: struct notifier_block * with callback info
2844 *
2845 * Request notification when clk's rate changes. This uses an SRCU
2846 * notifier because we want it to block and notifier unregistrations are
2847 * uncommon. The callbacks associated with the notifier must not
2848 * re-enter into the clk framework by calling any top-level clk APIs;
2849 * this will cause a nested prepare_lock mutex.
2850 *
198bb594
MY
2851 * In all notification cases (pre, post and abort rate change) the original
2852 * clock rate is passed to the callback via struct clk_notifier_data.old_rate
2853 * and the new frequency is passed via struct clk_notifier_data.new_rate.
b2476490 2854 *
b2476490
MT
2855 * clk_notifier_register() must be called from non-atomic context.
2856 * Returns -EINVAL if called with null arguments, -ENOMEM upon
2857 * allocation failure; otherwise, passes along the return value of
2858 * srcu_notifier_chain_register().
2859 */
2860int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
2861{
2862 struct clk_notifier *cn;
2863 int ret = -ENOMEM;
2864
2865 if (!clk || !nb)
2866 return -EINVAL;
2867
eab89f69 2868 clk_prepare_lock();
b2476490
MT
2869
2870 /* search the list of notifiers for this clk */
2871 list_for_each_entry(cn, &clk_notifier_list, node)
2872 if (cn->clk == clk)
2873 break;
2874
2875 /* if clk wasn't in the notifier list, allocate new clk_notifier */
2876 if (cn->clk != clk) {
2877 cn = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
2878 if (!cn)
2879 goto out;
2880
2881 cn->clk = clk;
2882 srcu_init_notifier_head(&cn->notifier_head);
2883
2884 list_add(&cn->node, &clk_notifier_list);
2885 }
2886
2887 ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
2888
035a61c3 2889 clk->core->notifier_count++;
b2476490
MT
2890
2891out:
eab89f69 2892 clk_prepare_unlock();
b2476490
MT
2893
2894 return ret;
2895}
2896EXPORT_SYMBOL_GPL(clk_notifier_register);
2897
2898/**
2899 * clk_notifier_unregister - remove a clk rate change notifier
2900 * @clk: struct clk *
2901 * @nb: struct notifier_block * with callback info
2902 *
2903 * Request no further notification for changes to 'clk' and frees memory
2904 * allocated in clk_notifier_register.
2905 *
2906 * Returns -EINVAL if called with null arguments; otherwise, passes
2907 * along the return value of srcu_notifier_chain_unregister().
2908 */
2909int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
2910{
2911 struct clk_notifier *cn = NULL;
2912 int ret = -EINVAL;
2913
2914 if (!clk || !nb)
2915 return -EINVAL;
2916
eab89f69 2917 clk_prepare_lock();
b2476490
MT
2918
2919 list_for_each_entry(cn, &clk_notifier_list, node)
2920 if (cn->clk == clk)
2921 break;
2922
2923 if (cn->clk == clk) {
2924 ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
2925
035a61c3 2926 clk->core->notifier_count--;
b2476490
MT
2927
2928 /* XXX the notifier code should handle this better */
2929 if (!cn->notifier_head.head) {
2930 srcu_cleanup_notifier_head(&cn->notifier_head);
72b5322f 2931 list_del(&cn->node);
b2476490
MT
2932 kfree(cn);
2933 }
2934
2935 } else {
2936 ret = -ENOENT;
2937 }
2938
eab89f69 2939 clk_prepare_unlock();
b2476490
MT
2940
2941 return ret;
2942}
2943EXPORT_SYMBOL_GPL(clk_notifier_unregister);
766e6a4e
GL
2944
2945#ifdef CONFIG_OF
2946/**
2947 * struct of_clk_provider - Clock provider registration structure
2948 * @link: Entry in global list of clock providers
2949 * @node: Pointer to device tree node of clock provider
2950 * @get: Get clock callback. Returns NULL or a struct clk for the
2951 * given clock specifier
2952 * @data: context pointer to be passed into @get callback
2953 */
2954struct of_clk_provider {
2955 struct list_head link;
2956
2957 struct device_node *node;
2958 struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
0861e5b8 2959 struct clk_hw *(*get_hw)(struct of_phandle_args *clkspec, void *data);
766e6a4e
GL
2960 void *data;
2961};
2962
f2f6c255
PG
2963static const struct of_device_id __clk_of_table_sentinel
2964 __used __section(__clk_of_table_end);
2965
766e6a4e 2966static LIST_HEAD(of_clk_providers);
d6782c26
SN
2967static DEFINE_MUTEX(of_clk_mutex);
2968
766e6a4e
GL
2969struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
2970 void *data)
2971{
2972 return data;
2973}
2974EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
2975
0861e5b8
SB
2976struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
2977{
2978 return data;
2979}
2980EXPORT_SYMBOL_GPL(of_clk_hw_simple_get);
2981
494bfec9
SG
2982struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
2983{
2984 struct clk_onecell_data *clk_data = data;
2985 unsigned int idx = clkspec->args[0];
2986
2987 if (idx >= clk_data->clk_num) {
7e96353c 2988 pr_err("%s: invalid clock index %u\n", __func__, idx);
494bfec9
SG
2989 return ERR_PTR(-EINVAL);
2990 }
2991
2992 return clk_data->clks[idx];
2993}
2994EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
2995
0861e5b8
SB
2996struct clk_hw *
2997of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
2998{
2999 struct clk_hw_onecell_data *hw_data = data;
3000 unsigned int idx = clkspec->args[0];
3001
3002 if (idx >= hw_data->num) {
3003 pr_err("%s: invalid index %u\n", __func__, idx);
3004 return ERR_PTR(-EINVAL);
3005 }
3006
3007 return hw_data->hws[idx];
3008}
3009EXPORT_SYMBOL_GPL(of_clk_hw_onecell_get);
3010
766e6a4e
GL
3011/**
3012 * of_clk_add_provider() - Register a clock provider for a node
3013 * @np: Device node pointer associated with clock provider
3014 * @clk_src_get: callback for decoding clock
3015 * @data: context pointer for @clk_src_get callback.
3016 */
3017int of_clk_add_provider(struct device_node *np,
3018 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
3019 void *data),
3020 void *data)
3021{
3022 struct of_clk_provider *cp;
86be408b 3023 int ret;
766e6a4e
GL
3024
3025 cp = kzalloc(sizeof(struct of_clk_provider), GFP_KERNEL);
3026 if (!cp)
3027 return -ENOMEM;
3028
3029 cp->node = of_node_get(np);
3030 cp->data = data;
3031 cp->get = clk_src_get;
3032
d6782c26 3033 mutex_lock(&of_clk_mutex);
766e6a4e 3034 list_add(&cp->link, &of_clk_providers);
d6782c26 3035 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
3036 pr_debug("Added clock from %s\n", np->full_name);
3037
86be408b
SN
3038 ret = of_clk_set_defaults(np, true);
3039 if (ret < 0)
3040 of_clk_del_provider(np);
3041
3042 return ret;
766e6a4e
GL
3043}
3044EXPORT_SYMBOL_GPL(of_clk_add_provider);
3045
0861e5b8
SB
3046/**
3047 * of_clk_add_hw_provider() - Register a clock provider for a node
3048 * @np: Device node pointer associated with clock provider
3049 * @get: callback for decoding clk_hw
3050 * @data: context pointer for @get callback.
3051 */
3052int of_clk_add_hw_provider(struct device_node *np,
3053 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
3054 void *data),
3055 void *data)
3056{
3057 struct of_clk_provider *cp;
3058 int ret;
3059
3060 cp = kzalloc(sizeof(*cp), GFP_KERNEL);
3061 if (!cp)
3062 return -ENOMEM;
3063
3064 cp->node = of_node_get(np);
3065 cp->data = data;
3066 cp->get_hw = get;
3067
3068 mutex_lock(&of_clk_mutex);
3069 list_add(&cp->link, &of_clk_providers);
3070 mutex_unlock(&of_clk_mutex);
3071 pr_debug("Added clk_hw provider from %s\n", np->full_name);
3072
3073 ret = of_clk_set_defaults(np, true);
3074 if (ret < 0)
3075 of_clk_del_provider(np);
3076
3077 return ret;
3078}
3079EXPORT_SYMBOL_GPL(of_clk_add_hw_provider);
3080
766e6a4e
GL
3081/**
3082 * of_clk_del_provider() - Remove a previously registered clock provider
3083 * @np: Device node pointer associated with clock provider
3084 */
3085void of_clk_del_provider(struct device_node *np)
3086{
3087 struct of_clk_provider *cp;
3088
d6782c26 3089 mutex_lock(&of_clk_mutex);
766e6a4e
GL
3090 list_for_each_entry(cp, &of_clk_providers, link) {
3091 if (cp->node == np) {
3092 list_del(&cp->link);
3093 of_node_put(cp->node);
3094 kfree(cp);
3095 break;
3096 }
3097 }
d6782c26 3098 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
3099}
3100EXPORT_SYMBOL_GPL(of_clk_del_provider);
3101
0861e5b8
SB
3102static struct clk_hw *
3103__of_clk_get_hw_from_provider(struct of_clk_provider *provider,
3104 struct of_phandle_args *clkspec)
3105{
3106 struct clk *clk;
3107 struct clk_hw *hw = ERR_PTR(-EPROBE_DEFER);
3108
3109 if (provider->get_hw) {
3110 hw = provider->get_hw(clkspec, provider->data);
3111 } else if (provider->get) {
3112 clk = provider->get(clkspec, provider->data);
3113 if (!IS_ERR(clk))
3114 hw = __clk_get_hw(clk);
3115 else
3116 hw = ERR_CAST(clk);
3117 }
3118
3119 return hw;
3120}
3121
73e0e496
SB
3122struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
3123 const char *dev_id, const char *con_id)
766e6a4e
GL
3124{
3125 struct of_clk_provider *provider;
a34cd466 3126 struct clk *clk = ERR_PTR(-EPROBE_DEFER);
0861e5b8 3127 struct clk_hw *hw = ERR_PTR(-EPROBE_DEFER);
766e6a4e 3128
306c342f
SB
3129 if (!clkspec)
3130 return ERR_PTR(-EINVAL);
3131
766e6a4e 3132 /* Check if we have such a provider in our array */
306c342f 3133 mutex_lock(&of_clk_mutex);
766e6a4e
GL
3134 list_for_each_entry(provider, &of_clk_providers, link) {
3135 if (provider->node == clkspec->np)
0861e5b8
SB
3136 hw = __of_clk_get_hw_from_provider(provider, clkspec);
3137 if (!IS_ERR(hw)) {
3138 clk = __clk_create_clk(hw, dev_id, con_id);
73e0e496
SB
3139
3140 if (!IS_ERR(clk) && !__clk_get(clk)) {
3141 __clk_free_clk(clk);
3142 clk = ERR_PTR(-ENOENT);
3143 }
3144
766e6a4e 3145 break;
73e0e496 3146 }
766e6a4e 3147 }
306c342f 3148 mutex_unlock(&of_clk_mutex);
d6782c26
SN
3149
3150 return clk;
3151}
3152
306c342f
SB
3153/**
3154 * of_clk_get_from_provider() - Lookup a clock from a clock provider
3155 * @clkspec: pointer to a clock specifier data structure
3156 *
3157 * This function looks up a struct clk from the registered list of clock
3158 * providers, an input is a clock specifier data structure as returned
3159 * from the of_parse_phandle_with_args() function call.
3160 */
d6782c26
SN
3161struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
3162{
306c342f 3163 return __of_clk_get_from_provider(clkspec, NULL, __func__);
766e6a4e 3164}
fb4dd222 3165EXPORT_SYMBOL_GPL(of_clk_get_from_provider);
766e6a4e 3166
929e7f3b
SB
3167/**
3168 * of_clk_get_parent_count() - Count the number of clocks a device node has
3169 * @np: device node to count
3170 *
3171 * Returns: The number of clocks that are possible parents of this node
3172 */
3173unsigned int of_clk_get_parent_count(struct device_node *np)
f6102742 3174{
929e7f3b
SB
3175 int count;
3176
3177 count = of_count_phandle_with_args(np, "clocks", "#clock-cells");
3178 if (count < 0)
3179 return 0;
3180
3181 return count;
f6102742
MT
3182}
3183EXPORT_SYMBOL_GPL(of_clk_get_parent_count);
3184
766e6a4e
GL
3185const char *of_clk_get_parent_name(struct device_node *np, int index)
3186{
3187 struct of_phandle_args clkspec;
7a0fc1a3 3188 struct property *prop;
766e6a4e 3189 const char *clk_name;
7a0fc1a3
BD
3190 const __be32 *vp;
3191 u32 pv;
766e6a4e 3192 int rc;
7a0fc1a3 3193 int count;
0a4807c2 3194 struct clk *clk;
766e6a4e 3195
766e6a4e
GL
3196 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
3197 &clkspec);
3198 if (rc)
3199 return NULL;
3200
7a0fc1a3
BD
3201 index = clkspec.args_count ? clkspec.args[0] : 0;
3202 count = 0;
3203
3204 /* if there is an indices property, use it to transfer the index
3205 * specified into an array offset for the clock-output-names property.
3206 */
3207 of_property_for_each_u32(clkspec.np, "clock-indices", prop, vp, pv) {
3208 if (index == pv) {
3209 index = count;
3210 break;
3211 }
3212 count++;
3213 }
8da411cc
MY
3214 /* We went off the end of 'clock-indices' without finding it */
3215 if (prop && !vp)
3216 return NULL;
7a0fc1a3 3217
766e6a4e 3218 if (of_property_read_string_index(clkspec.np, "clock-output-names",
7a0fc1a3 3219 index,
0a4807c2
SB
3220 &clk_name) < 0) {
3221 /*
3222 * Best effort to get the name if the clock has been
3223 * registered with the framework. If the clock isn't
3224 * registered, we return the node name as the name of
3225 * the clock as long as #clock-cells = 0.
3226 */
3227 clk = of_clk_get_from_provider(&clkspec);
3228 if (IS_ERR(clk)) {
3229 if (clkspec.args_count == 0)
3230 clk_name = clkspec.np->name;
3231 else
3232 clk_name = NULL;
3233 } else {
3234 clk_name = __clk_get_name(clk);
3235 clk_put(clk);
3236 }
3237 }
3238
766e6a4e
GL
3239
3240 of_node_put(clkspec.np);
3241 return clk_name;
3242}
3243EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
3244
2e61dfb3
DN
3245/**
3246 * of_clk_parent_fill() - Fill @parents with names of @np's parents and return
3247 * number of parents
3248 * @np: Device node pointer associated with clock provider
3249 * @parents: pointer to char array that hold the parents' names
3250 * @size: size of the @parents array
3251 *
3252 * Return: number of parents for the clock node.
3253 */
3254int of_clk_parent_fill(struct device_node *np, const char **parents,
3255 unsigned int size)
3256{
3257 unsigned int i = 0;
3258
3259 while (i < size && (parents[i] = of_clk_get_parent_name(np, i)) != NULL)
3260 i++;
3261
3262 return i;
3263}
3264EXPORT_SYMBOL_GPL(of_clk_parent_fill);
3265
1771b10d
GC
3266struct clock_provider {
3267 of_clk_init_cb_t clk_init_cb;
3268 struct device_node *np;
3269 struct list_head node;
3270};
3271
1771b10d
GC
3272/*
3273 * This function looks for a parent clock. If there is one, then it
3274 * checks that the provider for this parent clock was initialized, in
3275 * this case the parent clock will be ready.
3276 */
3277static int parent_ready(struct device_node *np)
3278{
3279 int i = 0;
3280
3281 while (true) {
3282 struct clk *clk = of_clk_get(np, i);
3283
3284 /* this parent is ready we can check the next one */
3285 if (!IS_ERR(clk)) {
3286 clk_put(clk);
3287 i++;
3288 continue;
3289 }
3290
3291 /* at least one parent is not ready, we exit now */
3292 if (PTR_ERR(clk) == -EPROBE_DEFER)
3293 return 0;
3294
3295 /*
3296 * Here we make assumption that the device tree is
3297 * written correctly. So an error means that there is
3298 * no more parent. As we didn't exit yet, then the
3299 * previous parent are ready. If there is no clock
3300 * parent, no need to wait for them, then we can
3301 * consider their absence as being ready
3302 */
3303 return 1;
3304 }
3305}
3306
d56f8994
LJ
3307/**
3308 * of_clk_detect_critical() - set CLK_IS_CRITICAL flag from Device Tree
3309 * @np: Device node pointer associated with clock provider
3310 * @index: clock index
3311 * @flags: pointer to clk_core->flags
3312 *
3313 * Detects if the clock-critical property exists and, if so, sets the
3314 * corresponding CLK_IS_CRITICAL flag.
3315 *
3316 * Do not use this function. It exists only for legacy Device Tree
3317 * bindings, such as the one-clock-per-node style that are outdated.
3318 * Those bindings typically put all clock data into .dts and the Linux
3319 * driver has no clock data, thus making it impossible to set this flag
3320 * correctly from the driver. Only those drivers may call
3321 * of_clk_detect_critical from their setup functions.
3322 *
3323 * Return: error code or zero on success
3324 */
3325int of_clk_detect_critical(struct device_node *np,
3326 int index, unsigned long *flags)
3327{
3328 struct property *prop;
3329 const __be32 *cur;
3330 uint32_t idx;
3331
3332 if (!np || !flags)
3333 return -EINVAL;
3334
3335 of_property_for_each_u32(np, "clock-critical", prop, cur, idx)
3336 if (index == idx)
3337 *flags |= CLK_IS_CRITICAL;
3338
3339 return 0;
3340}
3341
766e6a4e
GL
3342/**
3343 * of_clk_init() - Scan and init clock providers from the DT
3344 * @matches: array of compatible values and init functions for providers.
3345 *
1771b10d 3346 * This function scans the device tree for matching clock providers
e5ca8fb4 3347 * and calls their initialization functions. It also does it by trying
1771b10d 3348 * to follow the dependencies.
766e6a4e
GL
3349 */
3350void __init of_clk_init(const struct of_device_id *matches)
3351{
7f7ed584 3352 const struct of_device_id *match;
766e6a4e 3353 struct device_node *np;
1771b10d
GC
3354 struct clock_provider *clk_provider, *next;
3355 bool is_init_done;
3356 bool force = false;
2573a02a 3357 LIST_HEAD(clk_provider_list);
766e6a4e 3358
f2f6c255 3359 if (!matches)
819b4861 3360 matches = &__clk_of_table;
f2f6c255 3361
1771b10d 3362 /* First prepare the list of the clocks providers */
7f7ed584 3363 for_each_matching_node_and_match(np, matches, &match) {
2e3b19f1
SB
3364 struct clock_provider *parent;
3365
3e5dd6f6
GU
3366 if (!of_device_is_available(np))
3367 continue;
3368
2e3b19f1
SB
3369 parent = kzalloc(sizeof(*parent), GFP_KERNEL);
3370 if (!parent) {
3371 list_for_each_entry_safe(clk_provider, next,
3372 &clk_provider_list, node) {
3373 list_del(&clk_provider->node);
6bc9d9d6 3374 of_node_put(clk_provider->np);
2e3b19f1
SB
3375 kfree(clk_provider);
3376 }
6bc9d9d6 3377 of_node_put(np);
2e3b19f1
SB
3378 return;
3379 }
1771b10d
GC
3380
3381 parent->clk_init_cb = match->data;
6bc9d9d6 3382 parent->np = of_node_get(np);
3f6d439f 3383 list_add_tail(&parent->node, &clk_provider_list);
1771b10d
GC
3384 }
3385
3386 while (!list_empty(&clk_provider_list)) {
3387 is_init_done = false;
3388 list_for_each_entry_safe(clk_provider, next,
3389 &clk_provider_list, node) {
3390 if (force || parent_ready(clk_provider->np)) {
86be408b 3391
1771b10d 3392 clk_provider->clk_init_cb(clk_provider->np);
86be408b
SN
3393 of_clk_set_defaults(clk_provider->np, true);
3394
1771b10d 3395 list_del(&clk_provider->node);
6bc9d9d6 3396 of_node_put(clk_provider->np);
1771b10d
GC
3397 kfree(clk_provider);
3398 is_init_done = true;
3399 }
3400 }
3401
3402 /*
e5ca8fb4 3403 * We didn't manage to initialize any of the
1771b10d
GC
3404 * remaining providers during the last loop, so now we
3405 * initialize all the remaining ones unconditionally
3406 * in case the clock parent was not mandatory
3407 */
3408 if (!is_init_done)
3409 force = true;
766e6a4e
GL
3410 }
3411}
3412#endif