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CommitLineData
b2476490
MT
1/*
2 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
3 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Standard functionality for the common clock API. See Documentation/clk.txt
10 */
11
b09d6d99 12#include <linux/clk-provider.h>
86be408b 13#include <linux/clk/clk-conf.h>
b2476490
MT
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <linux/spinlock.h>
17#include <linux/err.h>
18#include <linux/list.h>
19#include <linux/slab.h>
766e6a4e 20#include <linux/of.h>
46c8773a 21#include <linux/device.h>
f2f6c255 22#include <linux/init.h>
533ddeb1 23#include <linux/sched.h>
b2476490 24
d6782c26
SN
25#include "clk.h"
26
b2476490
MT
27static DEFINE_SPINLOCK(enable_lock);
28static DEFINE_MUTEX(prepare_lock);
29
533ddeb1
MT
30static struct task_struct *prepare_owner;
31static struct task_struct *enable_owner;
32
33static int prepare_refcnt;
34static int enable_refcnt;
35
b2476490
MT
36static HLIST_HEAD(clk_root_list);
37static HLIST_HEAD(clk_orphan_list);
38static LIST_HEAD(clk_notifier_list);
39
035a61c3
TV
40static long clk_core_get_accuracy(struct clk_core *clk);
41static unsigned long clk_core_get_rate(struct clk_core *clk);
42static int clk_core_get_phase(struct clk_core *clk);
43static bool clk_core_is_prepared(struct clk_core *clk);
44static bool clk_core_is_enabled(struct clk_core *clk);
035a61c3
TV
45static struct clk_core *clk_core_lookup(const char *name);
46
b09d6d99
MT
47/*** private data structures ***/
48
49struct clk_core {
50 const char *name;
51 const struct clk_ops *ops;
52 struct clk_hw *hw;
53 struct module *owner;
54 struct clk_core *parent;
55 const char **parent_names;
56 struct clk_core **parents;
57 u8 num_parents;
58 u8 new_parent_index;
59 unsigned long rate;
1c8e6004 60 unsigned long req_rate;
b09d6d99
MT
61 unsigned long new_rate;
62 struct clk_core *new_parent;
63 struct clk_core *new_child;
64 unsigned long flags;
65 unsigned int enable_count;
66 unsigned int prepare_count;
67 unsigned long accuracy;
68 int phase;
69 struct hlist_head children;
70 struct hlist_node child_node;
71 struct hlist_node debug_node;
1c8e6004 72 struct hlist_head clks;
b09d6d99
MT
73 unsigned int notifier_count;
74#ifdef CONFIG_DEBUG_FS
75 struct dentry *dentry;
76#endif
77 struct kref ref;
78};
79
dfc202ea
SB
80#define CREATE_TRACE_POINTS
81#include <trace/events/clk.h>
82
b09d6d99
MT
83struct clk {
84 struct clk_core *core;
85 const char *dev_id;
86 const char *con_id;
1c8e6004
TV
87 unsigned long min_rate;
88 unsigned long max_rate;
50595f8b 89 struct hlist_node clks_node;
b09d6d99
MT
90};
91
eab89f69
MT
92/*** locking ***/
93static void clk_prepare_lock(void)
94{
533ddeb1
MT
95 if (!mutex_trylock(&prepare_lock)) {
96 if (prepare_owner == current) {
97 prepare_refcnt++;
98 return;
99 }
100 mutex_lock(&prepare_lock);
101 }
102 WARN_ON_ONCE(prepare_owner != NULL);
103 WARN_ON_ONCE(prepare_refcnt != 0);
104 prepare_owner = current;
105 prepare_refcnt = 1;
eab89f69
MT
106}
107
108static void clk_prepare_unlock(void)
109{
533ddeb1
MT
110 WARN_ON_ONCE(prepare_owner != current);
111 WARN_ON_ONCE(prepare_refcnt == 0);
112
113 if (--prepare_refcnt)
114 return;
115 prepare_owner = NULL;
eab89f69
MT
116 mutex_unlock(&prepare_lock);
117}
118
119static unsigned long clk_enable_lock(void)
120{
121 unsigned long flags;
533ddeb1
MT
122
123 if (!spin_trylock_irqsave(&enable_lock, flags)) {
124 if (enable_owner == current) {
125 enable_refcnt++;
126 return flags;
127 }
128 spin_lock_irqsave(&enable_lock, flags);
129 }
130 WARN_ON_ONCE(enable_owner != NULL);
131 WARN_ON_ONCE(enable_refcnt != 0);
132 enable_owner = current;
133 enable_refcnt = 1;
eab89f69
MT
134 return flags;
135}
136
137static void clk_enable_unlock(unsigned long flags)
138{
533ddeb1
MT
139 WARN_ON_ONCE(enable_owner != current);
140 WARN_ON_ONCE(enable_refcnt == 0);
141
142 if (--enable_refcnt)
143 return;
144 enable_owner = NULL;
eab89f69
MT
145 spin_unlock_irqrestore(&enable_lock, flags);
146}
147
b2476490
MT
148/*** debugfs support ***/
149
ea72dc2c 150#ifdef CONFIG_DEBUG_FS
b2476490
MT
151#include <linux/debugfs.h>
152
153static struct dentry *rootdir;
b2476490 154static int inited = 0;
6314b679
SB
155static DEFINE_MUTEX(clk_debug_lock);
156static HLIST_HEAD(clk_debug_list);
b2476490 157
6b44c854
SK
158static struct hlist_head *all_lists[] = {
159 &clk_root_list,
160 &clk_orphan_list,
161 NULL,
162};
163
164static struct hlist_head *orphan_list[] = {
165 &clk_orphan_list,
166 NULL,
167};
168
035a61c3
TV
169static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
170 int level)
1af599df
PG
171{
172 if (!c)
173 return;
174
e59c5371 175 seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n",
1af599df
PG
176 level * 3 + 1, "",
177 30 - level * 3, c->name,
035a61c3
TV
178 c->enable_count, c->prepare_count, clk_core_get_rate(c),
179 clk_core_get_accuracy(c), clk_core_get_phase(c));
1af599df
PG
180}
181
035a61c3 182static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
1af599df
PG
183 int level)
184{
035a61c3 185 struct clk_core *child;
1af599df
PG
186
187 if (!c)
188 return;
189
190 clk_summary_show_one(s, c, level);
191
b67bfe0d 192 hlist_for_each_entry(child, &c->children, child_node)
1af599df
PG
193 clk_summary_show_subtree(s, child, level + 1);
194}
195
196static int clk_summary_show(struct seq_file *s, void *data)
197{
035a61c3 198 struct clk_core *c;
27b8d5f7 199 struct hlist_head **lists = (struct hlist_head **)s->private;
1af599df 200
e59c5371
MT
201 seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n");
202 seq_puts(s, "----------------------------------------------------------------------------------------\n");
1af599df 203
eab89f69 204 clk_prepare_lock();
1af599df 205
27b8d5f7
PDS
206 for (; *lists; lists++)
207 hlist_for_each_entry(c, *lists, child_node)
208 clk_summary_show_subtree(s, c, 0);
1af599df 209
eab89f69 210 clk_prepare_unlock();
1af599df
PG
211
212 return 0;
213}
214
215
216static int clk_summary_open(struct inode *inode, struct file *file)
217{
218 return single_open(file, clk_summary_show, inode->i_private);
219}
220
221static const struct file_operations clk_summary_fops = {
222 .open = clk_summary_open,
223 .read = seq_read,
224 .llseek = seq_lseek,
225 .release = single_release,
226};
227
035a61c3 228static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
bddca894
PG
229{
230 if (!c)
231 return;
232
233 seq_printf(s, "\"%s\": { ", c->name);
234 seq_printf(s, "\"enable_count\": %d,", c->enable_count);
235 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
035a61c3
TV
236 seq_printf(s, "\"rate\": %lu", clk_core_get_rate(c));
237 seq_printf(s, "\"accuracy\": %lu", clk_core_get_accuracy(c));
238 seq_printf(s, "\"phase\": %d", clk_core_get_phase(c));
bddca894
PG
239}
240
035a61c3 241static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
bddca894 242{
035a61c3 243 struct clk_core *child;
bddca894
PG
244
245 if (!c)
246 return;
247
248 clk_dump_one(s, c, level);
249
b67bfe0d 250 hlist_for_each_entry(child, &c->children, child_node) {
bddca894
PG
251 seq_printf(s, ",");
252 clk_dump_subtree(s, child, level + 1);
253 }
254
255 seq_printf(s, "}");
256}
257
258static int clk_dump(struct seq_file *s, void *data)
259{
035a61c3 260 struct clk_core *c;
bddca894 261 bool first_node = true;
27b8d5f7 262 struct hlist_head **lists = (struct hlist_head **)s->private;
bddca894
PG
263
264 seq_printf(s, "{");
265
eab89f69 266 clk_prepare_lock();
bddca894 267
27b8d5f7
PDS
268 for (; *lists; lists++) {
269 hlist_for_each_entry(c, *lists, child_node) {
270 if (!first_node)
271 seq_puts(s, ",");
272 first_node = false;
273 clk_dump_subtree(s, c, 0);
274 }
bddca894
PG
275 }
276
eab89f69 277 clk_prepare_unlock();
bddca894
PG
278
279 seq_printf(s, "}");
280 return 0;
281}
282
283
284static int clk_dump_open(struct inode *inode, struct file *file)
285{
286 return single_open(file, clk_dump, inode->i_private);
287}
288
289static const struct file_operations clk_dump_fops = {
290 .open = clk_dump_open,
291 .read = seq_read,
292 .llseek = seq_lseek,
293 .release = single_release,
294};
295
035a61c3 296static int clk_debug_create_one(struct clk_core *clk, struct dentry *pdentry)
b2476490
MT
297{
298 struct dentry *d;
299 int ret = -ENOMEM;
300
301 if (!clk || !pdentry) {
302 ret = -EINVAL;
303 goto out;
304 }
305
306 d = debugfs_create_dir(clk->name, pdentry);
307 if (!d)
308 goto out;
309
310 clk->dentry = d;
311
312 d = debugfs_create_u32("clk_rate", S_IRUGO, clk->dentry,
313 (u32 *)&clk->rate);
314 if (!d)
315 goto err_out;
316
5279fc40
BB
317 d = debugfs_create_u32("clk_accuracy", S_IRUGO, clk->dentry,
318 (u32 *)&clk->accuracy);
319 if (!d)
320 goto err_out;
321
e59c5371
MT
322 d = debugfs_create_u32("clk_phase", S_IRUGO, clk->dentry,
323 (u32 *)&clk->phase);
324 if (!d)
325 goto err_out;
326
b2476490
MT
327 d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry,
328 (u32 *)&clk->flags);
329 if (!d)
330 goto err_out;
331
332 d = debugfs_create_u32("clk_prepare_count", S_IRUGO, clk->dentry,
333 (u32 *)&clk->prepare_count);
334 if (!d)
335 goto err_out;
336
337 d = debugfs_create_u32("clk_enable_count", S_IRUGO, clk->dentry,
338 (u32 *)&clk->enable_count);
339 if (!d)
340 goto err_out;
341
342 d = debugfs_create_u32("clk_notifier_count", S_IRUGO, clk->dentry,
343 (u32 *)&clk->notifier_count);
344 if (!d)
345 goto err_out;
346
abeab450
CB
347 if (clk->ops->debug_init) {
348 ret = clk->ops->debug_init(clk->hw, clk->dentry);
349 if (ret)
c646cbf1 350 goto err_out;
abeab450 351 }
c646cbf1 352
b2476490
MT
353 ret = 0;
354 goto out;
355
356err_out:
b5f98e65
AE
357 debugfs_remove_recursive(clk->dentry);
358 clk->dentry = NULL;
b2476490
MT
359out:
360 return ret;
361}
362
b2476490
MT
363/**
364 * clk_debug_register - add a clk node to the debugfs clk tree
365 * @clk: the clk being added to the debugfs clk tree
366 *
367 * Dynamically adds a clk to the debugfs clk tree if debugfs has been
368 * initialized. Otherwise it bails out early since the debugfs clk tree
369 * will be created lazily by clk_debug_init as part of a late_initcall.
b2476490 370 */
035a61c3 371static int clk_debug_register(struct clk_core *clk)
b2476490 372{
b2476490
MT
373 int ret = 0;
374
6314b679
SB
375 mutex_lock(&clk_debug_lock);
376 hlist_add_head(&clk->debug_node, &clk_debug_list);
377
b2476490 378 if (!inited)
6314b679 379 goto unlock;
b2476490 380
6314b679
SB
381 ret = clk_debug_create_one(clk, rootdir);
382unlock:
383 mutex_unlock(&clk_debug_lock);
b2476490 384
b2476490
MT
385 return ret;
386}
387
fcb0ee6a
SN
388 /**
389 * clk_debug_unregister - remove a clk node from the debugfs clk tree
390 * @clk: the clk being removed from the debugfs clk tree
391 *
392 * Dynamically removes a clk and all it's children clk nodes from the
393 * debugfs clk tree if clk->dentry points to debugfs created by
394 * clk_debug_register in __clk_init.
fcb0ee6a 395 */
035a61c3 396static void clk_debug_unregister(struct clk_core *clk)
fcb0ee6a 397{
6314b679 398 mutex_lock(&clk_debug_lock);
6314b679 399 hlist_del_init(&clk->debug_node);
fcb0ee6a 400 debugfs_remove_recursive(clk->dentry);
6314b679 401 clk->dentry = NULL;
6314b679 402 mutex_unlock(&clk_debug_lock);
fcb0ee6a
SN
403}
404
61c7cddf 405struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
fb2b3c9f
PDS
406 void *data, const struct file_operations *fops)
407{
408 struct dentry *d = NULL;
409
035a61c3
TV
410 if (hw->core->dentry)
411 d = debugfs_create_file(name, mode, hw->core->dentry, data,
412 fops);
fb2b3c9f
PDS
413
414 return d;
415}
416EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
417
b2476490
MT
418/**
419 * clk_debug_init - lazily create the debugfs clk tree visualization
420 *
421 * clks are often initialized very early during boot before memory can
422 * be dynamically allocated and well before debugfs is setup.
423 * clk_debug_init walks the clk tree hierarchy while holding
424 * prepare_lock and creates the topology as part of a late_initcall,
425 * thus insuring that clks initialized very early will still be
426 * represented in the debugfs clk tree. This function should only be
427 * called once at boot-time, and all other clks added dynamically will
428 * be done so with clk_debug_register.
429 */
430static int __init clk_debug_init(void)
431{
035a61c3 432 struct clk_core *clk;
1af599df 433 struct dentry *d;
b2476490
MT
434
435 rootdir = debugfs_create_dir("clk", NULL);
436
437 if (!rootdir)
438 return -ENOMEM;
439
27b8d5f7 440 d = debugfs_create_file("clk_summary", S_IRUGO, rootdir, &all_lists,
1af599df
PG
441 &clk_summary_fops);
442 if (!d)
443 return -ENOMEM;
444
27b8d5f7 445 d = debugfs_create_file("clk_dump", S_IRUGO, rootdir, &all_lists,
bddca894
PG
446 &clk_dump_fops);
447 if (!d)
448 return -ENOMEM;
449
27b8d5f7
PDS
450 d = debugfs_create_file("clk_orphan_summary", S_IRUGO, rootdir,
451 &orphan_list, &clk_summary_fops);
452 if (!d)
453 return -ENOMEM;
b2476490 454
27b8d5f7
PDS
455 d = debugfs_create_file("clk_orphan_dump", S_IRUGO, rootdir,
456 &orphan_list, &clk_dump_fops);
457 if (!d)
b2476490
MT
458 return -ENOMEM;
459
6314b679
SB
460 mutex_lock(&clk_debug_lock);
461 hlist_for_each_entry(clk, &clk_debug_list, debug_node)
462 clk_debug_create_one(clk, rootdir);
b2476490
MT
463
464 inited = 1;
6314b679 465 mutex_unlock(&clk_debug_lock);
b2476490
MT
466
467 return 0;
468}
469late_initcall(clk_debug_init);
470#else
035a61c3
TV
471static inline int clk_debug_register(struct clk_core *clk) { return 0; }
472static inline void clk_debug_reparent(struct clk_core *clk,
473 struct clk_core *new_parent)
b33d212f
UH
474{
475}
035a61c3 476static inline void clk_debug_unregister(struct clk_core *clk)
fcb0ee6a
SN
477{
478}
70d347e6 479#endif
b2476490 480
1c155b3d 481/* caller must hold prepare_lock */
035a61c3 482static void clk_unprepare_unused_subtree(struct clk_core *clk)
1c155b3d 483{
035a61c3 484 struct clk_core *child;
1c155b3d 485
496eadf8
KK
486 lockdep_assert_held(&prepare_lock);
487
1c155b3d
UH
488 hlist_for_each_entry(child, &clk->children, child_node)
489 clk_unprepare_unused_subtree(child);
490
491 if (clk->prepare_count)
492 return;
493
494 if (clk->flags & CLK_IGNORE_UNUSED)
495 return;
496
035a61c3 497 if (clk_core_is_prepared(clk)) {
dfc202ea 498 trace_clk_unprepare(clk);
3cc8247f
UH
499 if (clk->ops->unprepare_unused)
500 clk->ops->unprepare_unused(clk->hw);
501 else if (clk->ops->unprepare)
1c155b3d 502 clk->ops->unprepare(clk->hw);
dfc202ea 503 trace_clk_unprepare_complete(clk);
3cc8247f 504 }
1c155b3d
UH
505}
506
b2476490 507/* caller must hold prepare_lock */
035a61c3 508static void clk_disable_unused_subtree(struct clk_core *clk)
b2476490 509{
035a61c3 510 struct clk_core *child;
b2476490
MT
511 unsigned long flags;
512
496eadf8
KK
513 lockdep_assert_held(&prepare_lock);
514
b67bfe0d 515 hlist_for_each_entry(child, &clk->children, child_node)
b2476490
MT
516 clk_disable_unused_subtree(child);
517
eab89f69 518 flags = clk_enable_lock();
b2476490
MT
519
520 if (clk->enable_count)
521 goto unlock_out;
522
523 if (clk->flags & CLK_IGNORE_UNUSED)
524 goto unlock_out;
525
7c045a55
MT
526 /*
527 * some gate clocks have special needs during the disable-unused
528 * sequence. call .disable_unused if available, otherwise fall
529 * back to .disable
530 */
035a61c3 531 if (clk_core_is_enabled(clk)) {
dfc202ea 532 trace_clk_disable(clk);
7c045a55
MT
533 if (clk->ops->disable_unused)
534 clk->ops->disable_unused(clk->hw);
535 else if (clk->ops->disable)
536 clk->ops->disable(clk->hw);
dfc202ea 537 trace_clk_disable_complete(clk);
7c045a55 538 }
b2476490
MT
539
540unlock_out:
eab89f69 541 clk_enable_unlock(flags);
b2476490
MT
542}
543
1e435256
OJ
544static bool clk_ignore_unused;
545static int __init clk_ignore_unused_setup(char *__unused)
546{
547 clk_ignore_unused = true;
548 return 1;
549}
550__setup("clk_ignore_unused", clk_ignore_unused_setup);
551
b2476490
MT
552static int clk_disable_unused(void)
553{
035a61c3 554 struct clk_core *clk;
b2476490 555
1e435256
OJ
556 if (clk_ignore_unused) {
557 pr_warn("clk: Not disabling unused clocks\n");
558 return 0;
559 }
560
eab89f69 561 clk_prepare_lock();
b2476490 562
b67bfe0d 563 hlist_for_each_entry(clk, &clk_root_list, child_node)
b2476490
MT
564 clk_disable_unused_subtree(clk);
565
b67bfe0d 566 hlist_for_each_entry(clk, &clk_orphan_list, child_node)
b2476490
MT
567 clk_disable_unused_subtree(clk);
568
1c155b3d
UH
569 hlist_for_each_entry(clk, &clk_root_list, child_node)
570 clk_unprepare_unused_subtree(clk);
571
572 hlist_for_each_entry(clk, &clk_orphan_list, child_node)
573 clk_unprepare_unused_subtree(clk);
574
eab89f69 575 clk_prepare_unlock();
b2476490
MT
576
577 return 0;
578}
d41d5805 579late_initcall_sync(clk_disable_unused);
b2476490
MT
580
581/*** helper functions ***/
582
65800b2c 583const char *__clk_get_name(struct clk *clk)
b2476490 584{
035a61c3 585 return !clk ? NULL : clk->core->name;
b2476490 586}
4895084c 587EXPORT_SYMBOL_GPL(__clk_get_name);
b2476490 588
65800b2c 589struct clk_hw *__clk_get_hw(struct clk *clk)
b2476490 590{
035a61c3 591 return !clk ? NULL : clk->core->hw;
b2476490 592}
0b7f04b8 593EXPORT_SYMBOL_GPL(__clk_get_hw);
b2476490 594
65800b2c 595u8 __clk_get_num_parents(struct clk *clk)
b2476490 596{
035a61c3 597 return !clk ? 0 : clk->core->num_parents;
b2476490 598}
0b7f04b8 599EXPORT_SYMBOL_GPL(__clk_get_num_parents);
b2476490 600
65800b2c 601struct clk *__clk_get_parent(struct clk *clk)
b2476490 602{
035a61c3
TV
603 if (!clk)
604 return NULL;
605
606 /* TODO: Create a per-user clk and change callers to call clk_put */
607 return !clk->core->parent ? NULL : clk->core->parent->hw->clk;
b2476490 608}
0b7f04b8 609EXPORT_SYMBOL_GPL(__clk_get_parent);
b2476490 610
035a61c3
TV
611static struct clk_core *clk_core_get_parent_by_index(struct clk_core *clk,
612 u8 index)
7ef3dcc8
JH
613{
614 if (!clk || index >= clk->num_parents)
615 return NULL;
616 else if (!clk->parents)
035a61c3 617 return clk_core_lookup(clk->parent_names[index]);
7ef3dcc8
JH
618 else if (!clk->parents[index])
619 return clk->parents[index] =
035a61c3 620 clk_core_lookup(clk->parent_names[index]);
7ef3dcc8
JH
621 else
622 return clk->parents[index];
623}
035a61c3
TV
624
625struct clk *clk_get_parent_by_index(struct clk *clk, u8 index)
626{
627 struct clk_core *parent;
628
629 if (!clk)
630 return NULL;
631
632 parent = clk_core_get_parent_by_index(clk->core, index);
633
634 return !parent ? NULL : parent->hw->clk;
635}
0b7f04b8 636EXPORT_SYMBOL_GPL(clk_get_parent_by_index);
7ef3dcc8 637
65800b2c 638unsigned int __clk_get_enable_count(struct clk *clk)
b2476490 639{
035a61c3 640 return !clk ? 0 : clk->core->enable_count;
b2476490
MT
641}
642
035a61c3 643static unsigned long clk_core_get_rate_nolock(struct clk_core *clk)
b2476490
MT
644{
645 unsigned long ret;
646
647 if (!clk) {
34e44fe8 648 ret = 0;
b2476490
MT
649 goto out;
650 }
651
652 ret = clk->rate;
653
654 if (clk->flags & CLK_IS_ROOT)
655 goto out;
656
657 if (!clk->parent)
34e44fe8 658 ret = 0;
b2476490
MT
659
660out:
661 return ret;
662}
035a61c3
TV
663
664unsigned long __clk_get_rate(struct clk *clk)
665{
666 if (!clk)
667 return 0;
668
669 return clk_core_get_rate_nolock(clk->core);
670}
0b7f04b8 671EXPORT_SYMBOL_GPL(__clk_get_rate);
b2476490 672
035a61c3 673static unsigned long __clk_get_accuracy(struct clk_core *clk)
5279fc40
BB
674{
675 if (!clk)
676 return 0;
677
678 return clk->accuracy;
679}
680
65800b2c 681unsigned long __clk_get_flags(struct clk *clk)
b2476490 682{
035a61c3 683 return !clk ? 0 : clk->core->flags;
b2476490 684}
b05c6836 685EXPORT_SYMBOL_GPL(__clk_get_flags);
b2476490 686
035a61c3 687static bool clk_core_is_prepared(struct clk_core *clk)
3d6ee287
UH
688{
689 int ret;
690
691 if (!clk)
692 return false;
693
694 /*
695 * .is_prepared is optional for clocks that can prepare
696 * fall back to software usage counter if it is missing
697 */
698 if (!clk->ops->is_prepared) {
699 ret = clk->prepare_count ? 1 : 0;
700 goto out;
701 }
702
703 ret = clk->ops->is_prepared(clk->hw);
704out:
705 return !!ret;
706}
707
035a61c3
TV
708bool __clk_is_prepared(struct clk *clk)
709{
710 if (!clk)
711 return false;
712
713 return clk_core_is_prepared(clk->core);
714}
715
716static bool clk_core_is_enabled(struct clk_core *clk)
b2476490
MT
717{
718 int ret;
719
720 if (!clk)
2ac6b1f5 721 return false;
b2476490
MT
722
723 /*
724 * .is_enabled is only mandatory for clocks that gate
725 * fall back to software usage counter if .is_enabled is missing
726 */
727 if (!clk->ops->is_enabled) {
728 ret = clk->enable_count ? 1 : 0;
729 goto out;
730 }
731
732 ret = clk->ops->is_enabled(clk->hw);
733out:
2ac6b1f5 734 return !!ret;
b2476490 735}
035a61c3
TV
736
737bool __clk_is_enabled(struct clk *clk)
738{
739 if (!clk)
740 return false;
741
742 return clk_core_is_enabled(clk->core);
743}
0b7f04b8 744EXPORT_SYMBOL_GPL(__clk_is_enabled);
b2476490 745
035a61c3
TV
746static struct clk_core *__clk_lookup_subtree(const char *name,
747 struct clk_core *clk)
b2476490 748{
035a61c3
TV
749 struct clk_core *child;
750 struct clk_core *ret;
b2476490
MT
751
752 if (!strcmp(clk->name, name))
753 return clk;
754
b67bfe0d 755 hlist_for_each_entry(child, &clk->children, child_node) {
b2476490
MT
756 ret = __clk_lookup_subtree(name, child);
757 if (ret)
758 return ret;
759 }
760
761 return NULL;
762}
763
035a61c3 764static struct clk_core *clk_core_lookup(const char *name)
b2476490 765{
035a61c3
TV
766 struct clk_core *root_clk;
767 struct clk_core *ret;
b2476490
MT
768
769 if (!name)
770 return NULL;
771
772 /* search the 'proper' clk tree first */
b67bfe0d 773 hlist_for_each_entry(root_clk, &clk_root_list, child_node) {
b2476490
MT
774 ret = __clk_lookup_subtree(name, root_clk);
775 if (ret)
776 return ret;
777 }
778
779 /* if not found, then search the orphan tree */
b67bfe0d 780 hlist_for_each_entry(root_clk, &clk_orphan_list, child_node) {
b2476490
MT
781 ret = __clk_lookup_subtree(name, root_clk);
782 if (ret)
783 return ret;
784 }
785
786 return NULL;
787}
788
15a02c1f
SB
789static bool mux_is_better_rate(unsigned long rate, unsigned long now,
790 unsigned long best, unsigned long flags)
e366fdd7 791{
15a02c1f
SB
792 if (flags & CLK_MUX_ROUND_CLOSEST)
793 return abs(now - rate) < abs(best - rate);
794
795 return now <= rate && now > best;
796}
797
798static long
799clk_mux_determine_rate_flags(struct clk_hw *hw, unsigned long rate,
1c8e6004
TV
800 unsigned long min_rate,
801 unsigned long max_rate,
15a02c1f
SB
802 unsigned long *best_parent_rate,
803 struct clk_hw **best_parent_p,
804 unsigned long flags)
e366fdd7 805{
035a61c3 806 struct clk_core *core = hw->core, *parent, *best_parent = NULL;
e366fdd7
JH
807 int i, num_parents;
808 unsigned long parent_rate, best = 0;
809
810 /* if NO_REPARENT flag set, pass through to current parent */
035a61c3
TV
811 if (core->flags & CLK_SET_RATE_NO_REPARENT) {
812 parent = core->parent;
813 if (core->flags & CLK_SET_RATE_PARENT)
9e0ad7d2
JMC
814 best = __clk_determine_rate(parent ? parent->hw : NULL,
815 rate, min_rate, max_rate);
e366fdd7 816 else if (parent)
035a61c3 817 best = clk_core_get_rate_nolock(parent);
e366fdd7 818 else
035a61c3 819 best = clk_core_get_rate_nolock(core);
e366fdd7
JH
820 goto out;
821 }
822
823 /* find the parent that can provide the fastest rate <= rate */
035a61c3 824 num_parents = core->num_parents;
e366fdd7 825 for (i = 0; i < num_parents; i++) {
035a61c3 826 parent = clk_core_get_parent_by_index(core, i);
e366fdd7
JH
827 if (!parent)
828 continue;
035a61c3 829 if (core->flags & CLK_SET_RATE_PARENT)
1c8e6004
TV
830 parent_rate = __clk_determine_rate(parent->hw, rate,
831 min_rate,
832 max_rate);
e366fdd7 833 else
035a61c3 834 parent_rate = clk_core_get_rate_nolock(parent);
15a02c1f 835 if (mux_is_better_rate(rate, parent_rate, best, flags)) {
e366fdd7
JH
836 best_parent = parent;
837 best = parent_rate;
838 }
839 }
840
841out:
842 if (best_parent)
646cafc6 843 *best_parent_p = best_parent->hw;
e366fdd7
JH
844 *best_parent_rate = best;
845
846 return best;
847}
15a02c1f 848
035a61c3
TV
849struct clk *__clk_lookup(const char *name)
850{
851 struct clk_core *core = clk_core_lookup(name);
852
853 return !core ? NULL : core->hw->clk;
854}
855
1c8e6004
TV
856static void clk_core_get_boundaries(struct clk_core *clk,
857 unsigned long *min_rate,
858 unsigned long *max_rate)
859{
860 struct clk *clk_user;
861
862 *min_rate = 0;
863 *max_rate = ULONG_MAX;
864
50595f8b 865 hlist_for_each_entry(clk_user, &clk->clks, clks_node)
1c8e6004
TV
866 *min_rate = max(*min_rate, clk_user->min_rate);
867
50595f8b 868 hlist_for_each_entry(clk_user, &clk->clks, clks_node)
1c8e6004
TV
869 *max_rate = min(*max_rate, clk_user->max_rate);
870}
871
15a02c1f
SB
872/*
873 * Helper for finding best parent to provide a given frequency. This can be used
874 * directly as a determine_rate callback (e.g. for a mux), or from a more
875 * complex clock that may combine a mux with other operations.
876 */
877long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
1c8e6004
TV
878 unsigned long min_rate,
879 unsigned long max_rate,
15a02c1f
SB
880 unsigned long *best_parent_rate,
881 struct clk_hw **best_parent_p)
882{
1c8e6004
TV
883 return clk_mux_determine_rate_flags(hw, rate, min_rate, max_rate,
884 best_parent_rate,
15a02c1f
SB
885 best_parent_p, 0);
886}
0b7f04b8 887EXPORT_SYMBOL_GPL(__clk_mux_determine_rate);
e366fdd7 888
15a02c1f 889long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate,
1c8e6004
TV
890 unsigned long min_rate,
891 unsigned long max_rate,
15a02c1f
SB
892 unsigned long *best_parent_rate,
893 struct clk_hw **best_parent_p)
894{
1c8e6004
TV
895 return clk_mux_determine_rate_flags(hw, rate, min_rate, max_rate,
896 best_parent_rate,
15a02c1f
SB
897 best_parent_p,
898 CLK_MUX_ROUND_CLOSEST);
899}
900EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
901
b2476490
MT
902/*** clk api ***/
903
035a61c3 904static void clk_core_unprepare(struct clk_core *clk)
b2476490
MT
905{
906 if (!clk)
907 return;
908
909 if (WARN_ON(clk->prepare_count == 0))
910 return;
911
912 if (--clk->prepare_count > 0)
913 return;
914
915 WARN_ON(clk->enable_count > 0);
916
dfc202ea
SB
917 trace_clk_unprepare(clk);
918
b2476490
MT
919 if (clk->ops->unprepare)
920 clk->ops->unprepare(clk->hw);
921
dfc202ea 922 trace_clk_unprepare_complete(clk);
035a61c3 923 clk_core_unprepare(clk->parent);
b2476490
MT
924}
925
926/**
927 * clk_unprepare - undo preparation of a clock source
24ee1a08 928 * @clk: the clk being unprepared
b2476490
MT
929 *
930 * clk_unprepare may sleep, which differentiates it from clk_disable. In a
931 * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
932 * if the operation may sleep. One example is a clk which is accessed over
933 * I2c. In the complex case a clk gate operation may require a fast and a slow
934 * part. It is this reason that clk_unprepare and clk_disable are not mutually
935 * exclusive. In fact clk_disable must be called before clk_unprepare.
936 */
937void clk_unprepare(struct clk *clk)
938{
63589e92
SB
939 if (IS_ERR_OR_NULL(clk))
940 return;
941
eab89f69 942 clk_prepare_lock();
035a61c3 943 clk_core_unprepare(clk->core);
eab89f69 944 clk_prepare_unlock();
b2476490
MT
945}
946EXPORT_SYMBOL_GPL(clk_unprepare);
947
035a61c3 948static int clk_core_prepare(struct clk_core *clk)
b2476490
MT
949{
950 int ret = 0;
951
952 if (!clk)
953 return 0;
954
955 if (clk->prepare_count == 0) {
035a61c3 956 ret = clk_core_prepare(clk->parent);
b2476490
MT
957 if (ret)
958 return ret;
959
dfc202ea
SB
960 trace_clk_prepare(clk);
961
962 if (clk->ops->prepare)
b2476490 963 ret = clk->ops->prepare(clk->hw);
dfc202ea
SB
964
965 trace_clk_prepare_complete(clk);
966
967 if (ret) {
968 clk_core_unprepare(clk->parent);
969 return ret;
b2476490
MT
970 }
971 }
972
973 clk->prepare_count++;
974
975 return 0;
976}
977
978/**
979 * clk_prepare - prepare a clock source
980 * @clk: the clk being prepared
981 *
982 * clk_prepare may sleep, which differentiates it from clk_enable. In a simple
983 * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
984 * operation may sleep. One example is a clk which is accessed over I2c. In
985 * the complex case a clk ungate operation may require a fast and a slow part.
986 * It is this reason that clk_prepare and clk_enable are not mutually
987 * exclusive. In fact clk_prepare must be called before clk_enable.
988 * Returns 0 on success, -EERROR otherwise.
989 */
990int clk_prepare(struct clk *clk)
991{
992 int ret;
993
035a61c3
TV
994 if (!clk)
995 return 0;
996
eab89f69 997 clk_prepare_lock();
035a61c3 998 ret = clk_core_prepare(clk->core);
eab89f69 999 clk_prepare_unlock();
b2476490
MT
1000
1001 return ret;
1002}
1003EXPORT_SYMBOL_GPL(clk_prepare);
1004
035a61c3 1005static void clk_core_disable(struct clk_core *clk)
b2476490
MT
1006{
1007 if (!clk)
1008 return;
1009
1010 if (WARN_ON(clk->enable_count == 0))
1011 return;
1012
1013 if (--clk->enable_count > 0)
1014 return;
1015
dfc202ea
SB
1016 trace_clk_disable(clk);
1017
b2476490
MT
1018 if (clk->ops->disable)
1019 clk->ops->disable(clk->hw);
1020
dfc202ea
SB
1021 trace_clk_disable_complete(clk);
1022
035a61c3
TV
1023 clk_core_disable(clk->parent);
1024}
1025
1026static void __clk_disable(struct clk *clk)
1027{
1028 if (!clk)
1029 return;
1030
1031 clk_core_disable(clk->core);
b2476490
MT
1032}
1033
1034/**
1035 * clk_disable - gate a clock
1036 * @clk: the clk being gated
1037 *
1038 * clk_disable must not sleep, which differentiates it from clk_unprepare. In
1039 * a simple case, clk_disable can be used instead of clk_unprepare to gate a
1040 * clk if the operation is fast and will never sleep. One example is a
1041 * SoC-internal clk which is controlled via simple register writes. In the
1042 * complex case a clk gate operation may require a fast and a slow part. It is
1043 * this reason that clk_unprepare and clk_disable are not mutually exclusive.
1044 * In fact clk_disable must be called before clk_unprepare.
1045 */
1046void clk_disable(struct clk *clk)
1047{
1048 unsigned long flags;
1049
63589e92
SB
1050 if (IS_ERR_OR_NULL(clk))
1051 return;
1052
eab89f69 1053 flags = clk_enable_lock();
b2476490 1054 __clk_disable(clk);
eab89f69 1055 clk_enable_unlock(flags);
b2476490
MT
1056}
1057EXPORT_SYMBOL_GPL(clk_disable);
1058
035a61c3 1059static int clk_core_enable(struct clk_core *clk)
b2476490
MT
1060{
1061 int ret = 0;
1062
1063 if (!clk)
1064 return 0;
1065
1066 if (WARN_ON(clk->prepare_count == 0))
1067 return -ESHUTDOWN;
1068
1069 if (clk->enable_count == 0) {
035a61c3 1070 ret = clk_core_enable(clk->parent);
b2476490
MT
1071
1072 if (ret)
1073 return ret;
1074
dfc202ea
SB
1075 trace_clk_enable(clk);
1076
1077 if (clk->ops->enable)
b2476490 1078 ret = clk->ops->enable(clk->hw);
dfc202ea
SB
1079
1080 trace_clk_enable_complete(clk);
1081
1082 if (ret) {
1083 clk_core_disable(clk->parent);
1084 return ret;
b2476490
MT
1085 }
1086 }
1087
1088 clk->enable_count++;
1089 return 0;
1090}
1091
035a61c3
TV
1092static int __clk_enable(struct clk *clk)
1093{
1094 if (!clk)
1095 return 0;
1096
1097 return clk_core_enable(clk->core);
1098}
1099
b2476490
MT
1100/**
1101 * clk_enable - ungate a clock
1102 * @clk: the clk being ungated
1103 *
1104 * clk_enable must not sleep, which differentiates it from clk_prepare. In a
1105 * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
1106 * if the operation will never sleep. One example is a SoC-internal clk which
1107 * is controlled via simple register writes. In the complex case a clk ungate
1108 * operation may require a fast and a slow part. It is this reason that
1109 * clk_enable and clk_prepare are not mutually exclusive. In fact clk_prepare
1110 * must be called before clk_enable. Returns 0 on success, -EERROR
1111 * otherwise.
1112 */
1113int clk_enable(struct clk *clk)
1114{
1115 unsigned long flags;
1116 int ret;
1117
eab89f69 1118 flags = clk_enable_lock();
b2476490 1119 ret = __clk_enable(clk);
eab89f69 1120 clk_enable_unlock(flags);
b2476490
MT
1121
1122 return ret;
1123}
1124EXPORT_SYMBOL_GPL(clk_enable);
1125
035a61c3 1126static unsigned long clk_core_round_rate_nolock(struct clk_core *clk,
1c8e6004
TV
1127 unsigned long rate,
1128 unsigned long min_rate,
1129 unsigned long max_rate)
b2476490 1130{
81536e07 1131 unsigned long parent_rate = 0;
035a61c3 1132 struct clk_core *parent;
646cafc6 1133 struct clk_hw *parent_hw;
b2476490 1134
496eadf8
KK
1135 lockdep_assert_held(&prepare_lock);
1136
b2476490 1137 if (!clk)
2ac6b1f5 1138 return 0;
b2476490 1139
71472c0c
JH
1140 parent = clk->parent;
1141 if (parent)
1142 parent_rate = parent->rate;
1143
646cafc6
TV
1144 if (clk->ops->determine_rate) {
1145 parent_hw = parent ? parent->hw : NULL;
1c8e6004
TV
1146 return clk->ops->determine_rate(clk->hw, rate,
1147 min_rate, max_rate,
1148 &parent_rate, &parent_hw);
646cafc6 1149 } else if (clk->ops->round_rate)
71472c0c
JH
1150 return clk->ops->round_rate(clk->hw, rate, &parent_rate);
1151 else if (clk->flags & CLK_SET_RATE_PARENT)
1c8e6004
TV
1152 return clk_core_round_rate_nolock(clk->parent, rate, min_rate,
1153 max_rate);
71472c0c
JH
1154 else
1155 return clk->rate;
b2476490 1156}
035a61c3 1157
1c8e6004
TV
1158/**
1159 * __clk_determine_rate - get the closest rate actually supported by a clock
1160 * @hw: determine the rate of this clock
1161 * @rate: target rate
1162 * @min_rate: returned rate must be greater than this rate
1163 * @max_rate: returned rate must be less than this rate
1164 *
1165 * Caller must hold prepare_lock. Useful for clk_ops such as .set_rate and
1166 * .determine_rate.
1167 */
1168unsigned long __clk_determine_rate(struct clk_hw *hw,
1169 unsigned long rate,
1170 unsigned long min_rate,
1171 unsigned long max_rate)
1172{
1173 if (!hw)
1174 return 0;
1175
1176 return clk_core_round_rate_nolock(hw->core, rate, min_rate, max_rate);
1177}
1178EXPORT_SYMBOL_GPL(__clk_determine_rate);
1179
035a61c3
TV
1180/**
1181 * __clk_round_rate - round the given rate for a clk
1182 * @clk: round the rate of this clock
1183 * @rate: the rate which is to be rounded
1184 *
1185 * Caller must hold prepare_lock. Useful for clk_ops such as .set_rate
1186 */
1187unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
1188{
1c8e6004
TV
1189 unsigned long min_rate;
1190 unsigned long max_rate;
1191
035a61c3
TV
1192 if (!clk)
1193 return 0;
1194
1c8e6004
TV
1195 clk_core_get_boundaries(clk->core, &min_rate, &max_rate);
1196
1197 return clk_core_round_rate_nolock(clk->core, rate, min_rate, max_rate);
035a61c3 1198}
1cdf8ee2 1199EXPORT_SYMBOL_GPL(__clk_round_rate);
b2476490
MT
1200
1201/**
1202 * clk_round_rate - round the given rate for a clk
1203 * @clk: the clk for which we are rounding a rate
1204 * @rate: the rate which is to be rounded
1205 *
1206 * Takes in a rate as input and rounds it to a rate that the clk can actually
1207 * use which is then returned. If clk doesn't support round_rate operation
1208 * then the parent rate is returned.
1209 */
1210long clk_round_rate(struct clk *clk, unsigned long rate)
1211{
1212 unsigned long ret;
1213
035a61c3
TV
1214 if (!clk)
1215 return 0;
1216
eab89f69 1217 clk_prepare_lock();
b2476490 1218 ret = __clk_round_rate(clk, rate);
eab89f69 1219 clk_prepare_unlock();
b2476490
MT
1220
1221 return ret;
1222}
1223EXPORT_SYMBOL_GPL(clk_round_rate);
1224
1225/**
1226 * __clk_notify - call clk notifier chain
1227 * @clk: struct clk * that is changing rate
1228 * @msg: clk notifier type (see include/linux/clk.h)
1229 * @old_rate: old clk rate
1230 * @new_rate: new clk rate
1231 *
1232 * Triggers a notifier call chain on the clk rate-change notification
1233 * for 'clk'. Passes a pointer to the struct clk and the previous
1234 * and current rates to the notifier callback. Intended to be called by
1235 * internal clock code only. Returns NOTIFY_DONE from the last driver
1236 * called if all went well, or NOTIFY_STOP or NOTIFY_BAD immediately if
1237 * a driver returns that.
1238 */
035a61c3 1239static int __clk_notify(struct clk_core *clk, unsigned long msg,
b2476490
MT
1240 unsigned long old_rate, unsigned long new_rate)
1241{
1242 struct clk_notifier *cn;
1243 struct clk_notifier_data cnd;
1244 int ret = NOTIFY_DONE;
1245
b2476490
MT
1246 cnd.old_rate = old_rate;
1247 cnd.new_rate = new_rate;
1248
1249 list_for_each_entry(cn, &clk_notifier_list, node) {
035a61c3
TV
1250 if (cn->clk->core == clk) {
1251 cnd.clk = cn->clk;
b2476490
MT
1252 ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
1253 &cnd);
b2476490
MT
1254 }
1255 }
1256
1257 return ret;
1258}
1259
5279fc40
BB
1260/**
1261 * __clk_recalc_accuracies
1262 * @clk: first clk in the subtree
1263 *
1264 * Walks the subtree of clks starting with clk and recalculates accuracies as
1265 * it goes. Note that if a clk does not implement the .recalc_accuracy
1266 * callback then it is assumed that the clock will take on the accuracy of it's
1267 * parent.
1268 *
1269 * Caller must hold prepare_lock.
1270 */
035a61c3 1271static void __clk_recalc_accuracies(struct clk_core *clk)
5279fc40
BB
1272{
1273 unsigned long parent_accuracy = 0;
035a61c3 1274 struct clk_core *child;
5279fc40 1275
496eadf8
KK
1276 lockdep_assert_held(&prepare_lock);
1277
5279fc40
BB
1278 if (clk->parent)
1279 parent_accuracy = clk->parent->accuracy;
1280
1281 if (clk->ops->recalc_accuracy)
1282 clk->accuracy = clk->ops->recalc_accuracy(clk->hw,
1283 parent_accuracy);
1284 else
1285 clk->accuracy = parent_accuracy;
1286
1287 hlist_for_each_entry(child, &clk->children, child_node)
1288 __clk_recalc_accuracies(child);
1289}
1290
035a61c3
TV
1291static long clk_core_get_accuracy(struct clk_core *clk)
1292{
1293 unsigned long accuracy;
1294
1295 clk_prepare_lock();
1296 if (clk && (clk->flags & CLK_GET_ACCURACY_NOCACHE))
1297 __clk_recalc_accuracies(clk);
1298
1299 accuracy = __clk_get_accuracy(clk);
1300 clk_prepare_unlock();
1301
1302 return accuracy;
1303}
1304
5279fc40
BB
1305/**
1306 * clk_get_accuracy - return the accuracy of clk
1307 * @clk: the clk whose accuracy is being returned
1308 *
1309 * Simply returns the cached accuracy of the clk, unless
1310 * CLK_GET_ACCURACY_NOCACHE flag is set, which means a recalc_rate will be
1311 * issued.
1312 * If clk is NULL then returns 0.
1313 */
1314long clk_get_accuracy(struct clk *clk)
1315{
035a61c3
TV
1316 if (!clk)
1317 return 0;
5279fc40 1318
035a61c3 1319 return clk_core_get_accuracy(clk->core);
5279fc40
BB
1320}
1321EXPORT_SYMBOL_GPL(clk_get_accuracy);
1322
035a61c3
TV
1323static unsigned long clk_recalc(struct clk_core *clk,
1324 unsigned long parent_rate)
8f2c2db1
SB
1325{
1326 if (clk->ops->recalc_rate)
1327 return clk->ops->recalc_rate(clk->hw, parent_rate);
1328 return parent_rate;
1329}
1330
b2476490
MT
1331/**
1332 * __clk_recalc_rates
1333 * @clk: first clk in the subtree
1334 * @msg: notification type (see include/linux/clk.h)
1335 *
1336 * Walks the subtree of clks starting with clk and recalculates rates as it
1337 * goes. Note that if a clk does not implement the .recalc_rate callback then
24ee1a08 1338 * it is assumed that the clock will take on the rate of its parent.
b2476490
MT
1339 *
1340 * clk_recalc_rates also propagates the POST_RATE_CHANGE notification,
1341 * if necessary.
1342 *
1343 * Caller must hold prepare_lock.
1344 */
035a61c3 1345static void __clk_recalc_rates(struct clk_core *clk, unsigned long msg)
b2476490
MT
1346{
1347 unsigned long old_rate;
1348 unsigned long parent_rate = 0;
035a61c3 1349 struct clk_core *child;
b2476490 1350
496eadf8
KK
1351 lockdep_assert_held(&prepare_lock);
1352
b2476490
MT
1353 old_rate = clk->rate;
1354
1355 if (clk->parent)
1356 parent_rate = clk->parent->rate;
1357
8f2c2db1 1358 clk->rate = clk_recalc(clk, parent_rate);
b2476490
MT
1359
1360 /*
1361 * ignore NOTIFY_STOP and NOTIFY_BAD return values for POST_RATE_CHANGE
1362 * & ABORT_RATE_CHANGE notifiers
1363 */
1364 if (clk->notifier_count && msg)
1365 __clk_notify(clk, msg, old_rate, clk->rate);
1366
b67bfe0d 1367 hlist_for_each_entry(child, &clk->children, child_node)
b2476490
MT
1368 __clk_recalc_rates(child, msg);
1369}
1370
035a61c3 1371static unsigned long clk_core_get_rate(struct clk_core *clk)
a093bde2
UH
1372{
1373 unsigned long rate;
1374
eab89f69 1375 clk_prepare_lock();
a093bde2
UH
1376
1377 if (clk && (clk->flags & CLK_GET_RATE_NOCACHE))
1378 __clk_recalc_rates(clk, 0);
1379
035a61c3 1380 rate = clk_core_get_rate_nolock(clk);
eab89f69 1381 clk_prepare_unlock();
a093bde2
UH
1382
1383 return rate;
1384}
035a61c3
TV
1385
1386/**
1387 * clk_get_rate - return the rate of clk
1388 * @clk: the clk whose rate is being returned
1389 *
1390 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1391 * is set, which means a recalc_rate will be issued.
1392 * If clk is NULL then returns 0.
1393 */
1394unsigned long clk_get_rate(struct clk *clk)
1395{
1396 if (!clk)
1397 return 0;
1398
1399 return clk_core_get_rate(clk->core);
1400}
a093bde2
UH
1401EXPORT_SYMBOL_GPL(clk_get_rate);
1402
035a61c3
TV
1403static int clk_fetch_parent_index(struct clk_core *clk,
1404 struct clk_core *parent)
4935b22c 1405{
f1c8b2ed 1406 int i;
4935b22c 1407
f1c8b2ed 1408 if (!clk->parents) {
96a7ed90
TF
1409 clk->parents = kcalloc(clk->num_parents,
1410 sizeof(struct clk *), GFP_KERNEL);
f1c8b2ed
TF
1411 if (!clk->parents)
1412 return -ENOMEM;
1413 }
4935b22c
JH
1414
1415 /*
1416 * find index of new parent clock using cached parent ptrs,
1417 * or if not yet cached, use string name comparison and cache
035a61c3 1418 * them now to avoid future calls to clk_core_lookup.
4935b22c
JH
1419 */
1420 for (i = 0; i < clk->num_parents; i++) {
da0f0b2c 1421 if (clk->parents[i] == parent)
f1c8b2ed 1422 return i;
da0f0b2c
TF
1423
1424 if (clk->parents[i])
1425 continue;
1426
1427 if (!strcmp(clk->parent_names[i], parent->name)) {
035a61c3 1428 clk->parents[i] = clk_core_lookup(parent->name);
f1c8b2ed 1429 return i;
4935b22c
JH
1430 }
1431 }
1432
f1c8b2ed 1433 return -EINVAL;
4935b22c
JH
1434}
1435
035a61c3 1436static void clk_reparent(struct clk_core *clk, struct clk_core *new_parent)
4935b22c
JH
1437{
1438 hlist_del(&clk->child_node);
1439
903efc55
JH
1440 if (new_parent) {
1441 /* avoid duplicate POST_RATE_CHANGE notifications */
1442 if (new_parent->new_child == clk)
1443 new_parent->new_child = NULL;
1444
4935b22c 1445 hlist_add_head(&clk->child_node, &new_parent->children);
903efc55 1446 } else {
4935b22c 1447 hlist_add_head(&clk->child_node, &clk_orphan_list);
903efc55 1448 }
4935b22c
JH
1449
1450 clk->parent = new_parent;
1451}
1452
035a61c3
TV
1453static struct clk_core *__clk_set_parent_before(struct clk_core *clk,
1454 struct clk_core *parent)
4935b22c
JH
1455{
1456 unsigned long flags;
035a61c3 1457 struct clk_core *old_parent = clk->parent;
4935b22c
JH
1458
1459 /*
1460 * Migrate prepare state between parents and prevent race with
1461 * clk_enable().
1462 *
1463 * If the clock is not prepared, then a race with
1464 * clk_enable/disable() is impossible since we already have the
1465 * prepare lock (future calls to clk_enable() need to be preceded by
1466 * a clk_prepare()).
1467 *
1468 * If the clock is prepared, migrate the prepared state to the new
1469 * parent and also protect against a race with clk_enable() by
1470 * forcing the clock and the new parent on. This ensures that all
1471 * future calls to clk_enable() are practically NOPs with respect to
1472 * hardware and software states.
1473 *
1474 * See also: Comment for clk_set_parent() below.
1475 */
1476 if (clk->prepare_count) {
035a61c3 1477 clk_core_prepare(parent);
d2a5d46b 1478 flags = clk_enable_lock();
035a61c3
TV
1479 clk_core_enable(parent);
1480 clk_core_enable(clk);
d2a5d46b 1481 clk_enable_unlock(flags);
4935b22c
JH
1482 }
1483
1484 /* update the clk tree topology */
1485 flags = clk_enable_lock();
1486 clk_reparent(clk, parent);
1487 clk_enable_unlock(flags);
1488
3fa2252b
SB
1489 return old_parent;
1490}
1491
035a61c3
TV
1492static void __clk_set_parent_after(struct clk_core *core,
1493 struct clk_core *parent,
1494 struct clk_core *old_parent)
3fa2252b 1495{
d2a5d46b
DA
1496 unsigned long flags;
1497
3fa2252b
SB
1498 /*
1499 * Finish the migration of prepare state and undo the changes done
1500 * for preventing a race with clk_enable().
1501 */
035a61c3 1502 if (core->prepare_count) {
d2a5d46b 1503 flags = clk_enable_lock();
035a61c3
TV
1504 clk_core_disable(core);
1505 clk_core_disable(old_parent);
d2a5d46b 1506 clk_enable_unlock(flags);
035a61c3 1507 clk_core_unprepare(old_parent);
3fa2252b 1508 }
3fa2252b
SB
1509}
1510
035a61c3
TV
1511static int __clk_set_parent(struct clk_core *clk, struct clk_core *parent,
1512 u8 p_index)
3fa2252b
SB
1513{
1514 unsigned long flags;
1515 int ret = 0;
035a61c3 1516 struct clk_core *old_parent;
3fa2252b
SB
1517
1518 old_parent = __clk_set_parent_before(clk, parent);
1519
dfc202ea
SB
1520 trace_clk_set_parent(clk, parent);
1521
4935b22c
JH
1522 /* change clock input source */
1523 if (parent && clk->ops->set_parent)
1524 ret = clk->ops->set_parent(clk->hw, p_index);
1525
dfc202ea
SB
1526 trace_clk_set_parent_complete(clk, parent);
1527
4935b22c
JH
1528 if (ret) {
1529 flags = clk_enable_lock();
1530 clk_reparent(clk, old_parent);
1531 clk_enable_unlock(flags);
1532
1533 if (clk->prepare_count) {
d2a5d46b 1534 flags = clk_enable_lock();
035a61c3
TV
1535 clk_core_disable(clk);
1536 clk_core_disable(parent);
d2a5d46b 1537 clk_enable_unlock(flags);
035a61c3 1538 clk_core_unprepare(parent);
4935b22c
JH
1539 }
1540 return ret;
1541 }
1542
3fa2252b 1543 __clk_set_parent_after(clk, parent, old_parent);
4935b22c 1544
4935b22c
JH
1545 return 0;
1546}
1547
b2476490
MT
1548/**
1549 * __clk_speculate_rates
1550 * @clk: first clk in the subtree
1551 * @parent_rate: the "future" rate of clk's parent
1552 *
1553 * Walks the subtree of clks starting with clk, speculating rates as it
1554 * goes and firing off PRE_RATE_CHANGE notifications as necessary.
1555 *
1556 * Unlike clk_recalc_rates, clk_speculate_rates exists only for sending
1557 * pre-rate change notifications and returns early if no clks in the
1558 * subtree have subscribed to the notifications. Note that if a clk does not
1559 * implement the .recalc_rate callback then it is assumed that the clock will
24ee1a08 1560 * take on the rate of its parent.
b2476490
MT
1561 *
1562 * Caller must hold prepare_lock.
1563 */
035a61c3
TV
1564static int __clk_speculate_rates(struct clk_core *clk,
1565 unsigned long parent_rate)
b2476490 1566{
035a61c3 1567 struct clk_core *child;
b2476490
MT
1568 unsigned long new_rate;
1569 int ret = NOTIFY_DONE;
1570
496eadf8
KK
1571 lockdep_assert_held(&prepare_lock);
1572
8f2c2db1 1573 new_rate = clk_recalc(clk, parent_rate);
b2476490 1574
fb72a059 1575 /* abort rate change if a driver returns NOTIFY_BAD or NOTIFY_STOP */
b2476490
MT
1576 if (clk->notifier_count)
1577 ret = __clk_notify(clk, PRE_RATE_CHANGE, clk->rate, new_rate);
1578
86bcfa2e
MT
1579 if (ret & NOTIFY_STOP_MASK) {
1580 pr_debug("%s: clk notifier callback for clock %s aborted with error %d\n",
1581 __func__, clk->name, ret);
b2476490 1582 goto out;
86bcfa2e 1583 }
b2476490 1584
b67bfe0d 1585 hlist_for_each_entry(child, &clk->children, child_node) {
b2476490 1586 ret = __clk_speculate_rates(child, new_rate);
fb72a059 1587 if (ret & NOTIFY_STOP_MASK)
b2476490
MT
1588 break;
1589 }
1590
1591out:
1592 return ret;
1593}
1594
035a61c3
TV
1595static void clk_calc_subtree(struct clk_core *clk, unsigned long new_rate,
1596 struct clk_core *new_parent, u8 p_index)
b2476490 1597{
035a61c3 1598 struct clk_core *child;
b2476490
MT
1599
1600 clk->new_rate = new_rate;
71472c0c
JH
1601 clk->new_parent = new_parent;
1602 clk->new_parent_index = p_index;
1603 /* include clk in new parent's PRE_RATE_CHANGE notifications */
1604 clk->new_child = NULL;
1605 if (new_parent && new_parent != clk->parent)
1606 new_parent->new_child = clk;
b2476490 1607
b67bfe0d 1608 hlist_for_each_entry(child, &clk->children, child_node) {
8f2c2db1 1609 child->new_rate = clk_recalc(child, new_rate);
71472c0c 1610 clk_calc_subtree(child, child->new_rate, NULL, 0);
b2476490
MT
1611 }
1612}
1613
1614/*
1615 * calculate the new rates returning the topmost clock that has to be
1616 * changed.
1617 */
035a61c3
TV
1618static struct clk_core *clk_calc_new_rates(struct clk_core *clk,
1619 unsigned long rate)
b2476490 1620{
035a61c3
TV
1621 struct clk_core *top = clk;
1622 struct clk_core *old_parent, *parent;
646cafc6 1623 struct clk_hw *parent_hw;
81536e07 1624 unsigned long best_parent_rate = 0;
b2476490 1625 unsigned long new_rate;
1c8e6004
TV
1626 unsigned long min_rate;
1627 unsigned long max_rate;
f1c8b2ed 1628 int p_index = 0;
03bc10ab 1629 long ret;
b2476490 1630
7452b219
MT
1631 /* sanity */
1632 if (IS_ERR_OR_NULL(clk))
1633 return NULL;
1634
63f5c3b2 1635 /* save parent rate, if it exists */
71472c0c
JH
1636 parent = old_parent = clk->parent;
1637 if (parent)
1638 best_parent_rate = parent->rate;
1639
1c8e6004
TV
1640 clk_core_get_boundaries(clk, &min_rate, &max_rate);
1641
71472c0c
JH
1642 /* find the closest rate and parent clk/rate */
1643 if (clk->ops->determine_rate) {
646cafc6 1644 parent_hw = parent ? parent->hw : NULL;
03bc10ab
BB
1645 ret = clk->ops->determine_rate(clk->hw, rate,
1646 min_rate,
1647 max_rate,
1648 &best_parent_rate,
1649 &parent_hw);
1650 if (ret < 0)
1651 return NULL;
1652
1653 new_rate = ret;
035a61c3 1654 parent = parent_hw ? parent_hw->core : NULL;
71472c0c 1655 } else if (clk->ops->round_rate) {
03bc10ab
BB
1656 ret = clk->ops->round_rate(clk->hw, rate,
1657 &best_parent_rate);
1658 if (ret < 0)
1659 return NULL;
1660
1661 new_rate = ret;
1c8e6004
TV
1662 if (new_rate < min_rate || new_rate > max_rate)
1663 return NULL;
71472c0c
JH
1664 } else if (!parent || !(clk->flags & CLK_SET_RATE_PARENT)) {
1665 /* pass-through clock without adjustable parent */
1666 clk->new_rate = clk->rate;
1667 return NULL;
1668 } else {
1669 /* pass-through clock with adjustable parent */
1670 top = clk_calc_new_rates(parent, rate);
1671 new_rate = parent->new_rate;
63f5c3b2 1672 goto out;
7452b219
MT
1673 }
1674
71472c0c
JH
1675 /* some clocks must be gated to change parent */
1676 if (parent != old_parent &&
1677 (clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count) {
1678 pr_debug("%s: %s not gated but wants to reparent\n",
1679 __func__, clk->name);
b2476490
MT
1680 return NULL;
1681 }
1682
71472c0c 1683 /* try finding the new parent index */
4526e7b8 1684 if (parent && clk->num_parents > 1) {
71472c0c 1685 p_index = clk_fetch_parent_index(clk, parent);
f1c8b2ed 1686 if (p_index < 0) {
71472c0c
JH
1687 pr_debug("%s: clk %s can not be parent of clk %s\n",
1688 __func__, parent->name, clk->name);
1689 return NULL;
1690 }
b2476490
MT
1691 }
1692
71472c0c
JH
1693 if ((clk->flags & CLK_SET_RATE_PARENT) && parent &&
1694 best_parent_rate != parent->rate)
1695 top = clk_calc_new_rates(parent, best_parent_rate);
b2476490
MT
1696
1697out:
71472c0c 1698 clk_calc_subtree(clk, new_rate, parent, p_index);
b2476490
MT
1699
1700 return top;
1701}
1702
1703/*
1704 * Notify about rate changes in a subtree. Always walk down the whole tree
1705 * so that in case of an error we can walk down the whole tree again and
1706 * abort the change.
1707 */
035a61c3
TV
1708static struct clk_core *clk_propagate_rate_change(struct clk_core *clk,
1709 unsigned long event)
b2476490 1710{
035a61c3 1711 struct clk_core *child, *tmp_clk, *fail_clk = NULL;
b2476490
MT
1712 int ret = NOTIFY_DONE;
1713
1714 if (clk->rate == clk->new_rate)
5fda6858 1715 return NULL;
b2476490
MT
1716
1717 if (clk->notifier_count) {
1718 ret = __clk_notify(clk, event, clk->rate, clk->new_rate);
fb72a059 1719 if (ret & NOTIFY_STOP_MASK)
b2476490
MT
1720 fail_clk = clk;
1721 }
1722
b67bfe0d 1723 hlist_for_each_entry(child, &clk->children, child_node) {
71472c0c
JH
1724 /* Skip children who will be reparented to another clock */
1725 if (child->new_parent && child->new_parent != clk)
1726 continue;
1727 tmp_clk = clk_propagate_rate_change(child, event);
1728 if (tmp_clk)
1729 fail_clk = tmp_clk;
1730 }
1731
1732 /* handle the new child who might not be in clk->children yet */
1733 if (clk->new_child) {
1734 tmp_clk = clk_propagate_rate_change(clk->new_child, event);
1735 if (tmp_clk)
1736 fail_clk = tmp_clk;
b2476490
MT
1737 }
1738
1739 return fail_clk;
1740}
1741
1742/*
1743 * walk down a subtree and set the new rates notifying the rate
1744 * change on the way
1745 */
035a61c3 1746static void clk_change_rate(struct clk_core *clk)
b2476490 1747{
035a61c3 1748 struct clk_core *child;
067bb174 1749 struct hlist_node *tmp;
b2476490 1750 unsigned long old_rate;
bf47b4fd 1751 unsigned long best_parent_rate = 0;
3fa2252b 1752 bool skip_set_rate = false;
035a61c3 1753 struct clk_core *old_parent;
b2476490
MT
1754
1755 old_rate = clk->rate;
1756
3fa2252b
SB
1757 if (clk->new_parent)
1758 best_parent_rate = clk->new_parent->rate;
1759 else if (clk->parent)
bf47b4fd
PM
1760 best_parent_rate = clk->parent->rate;
1761
3fa2252b
SB
1762 if (clk->new_parent && clk->new_parent != clk->parent) {
1763 old_parent = __clk_set_parent_before(clk, clk->new_parent);
dfc202ea 1764 trace_clk_set_parent(clk, clk->new_parent);
3fa2252b
SB
1765
1766 if (clk->ops->set_rate_and_parent) {
1767 skip_set_rate = true;
1768 clk->ops->set_rate_and_parent(clk->hw, clk->new_rate,
1769 best_parent_rate,
1770 clk->new_parent_index);
1771 } else if (clk->ops->set_parent) {
1772 clk->ops->set_parent(clk->hw, clk->new_parent_index);
1773 }
1774
dfc202ea 1775 trace_clk_set_parent_complete(clk, clk->new_parent);
3fa2252b
SB
1776 __clk_set_parent_after(clk, clk->new_parent, old_parent);
1777 }
1778
dfc202ea
SB
1779 trace_clk_set_rate(clk, clk->new_rate);
1780
3fa2252b 1781 if (!skip_set_rate && clk->ops->set_rate)
bf47b4fd 1782 clk->ops->set_rate(clk->hw, clk->new_rate, best_parent_rate);
b2476490 1783
dfc202ea
SB
1784 trace_clk_set_rate_complete(clk, clk->new_rate);
1785
8f2c2db1 1786 clk->rate = clk_recalc(clk, best_parent_rate);
b2476490
MT
1787
1788 if (clk->notifier_count && old_rate != clk->rate)
1789 __clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate);
1790
067bb174
TK
1791 /*
1792 * Use safe iteration, as change_rate can actually swap parents
1793 * for certain clock types.
1794 */
1795 hlist_for_each_entry_safe(child, tmp, &clk->children, child_node) {
71472c0c
JH
1796 /* Skip children who will be reparented to another clock */
1797 if (child->new_parent && child->new_parent != clk)
1798 continue;
b2476490 1799 clk_change_rate(child);
71472c0c
JH
1800 }
1801
1802 /* handle the new child who might not be in clk->children yet */
1803 if (clk->new_child)
1804 clk_change_rate(clk->new_child);
b2476490
MT
1805}
1806
1c8e6004
TV
1807static int clk_core_set_rate_nolock(struct clk_core *clk,
1808 unsigned long req_rate)
1809{
1810 struct clk_core *top, *fail_clk;
1811 unsigned long rate = req_rate;
1812 int ret = 0;
1813
1814 if (!clk)
1815 return 0;
1816
1817 /* bail early if nothing to do */
1818 if (rate == clk_core_get_rate_nolock(clk))
1819 return 0;
1820
1821 if ((clk->flags & CLK_SET_RATE_GATE) && clk->prepare_count)
1822 return -EBUSY;
1823
1824 /* calculate new rates and get the topmost changed clock */
1825 top = clk_calc_new_rates(clk, rate);
1826 if (!top)
1827 return -EINVAL;
1828
1829 /* notify that we are about to change rates */
1830 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
1831 if (fail_clk) {
1832 pr_debug("%s: failed to set %s rate\n", __func__,
1833 fail_clk->name);
1834 clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
1835 return -EBUSY;
1836 }
1837
1838 /* change the rates */
1839 clk_change_rate(top);
1840
1841 clk->req_rate = req_rate;
1842
1843 return ret;
1844}
1845
b2476490
MT
1846/**
1847 * clk_set_rate - specify a new rate for clk
1848 * @clk: the clk whose rate is being changed
1849 * @rate: the new rate for clk
1850 *
5654dc94 1851 * In the simplest case clk_set_rate will only adjust the rate of clk.
b2476490 1852 *
5654dc94
MT
1853 * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to
1854 * propagate up to clk's parent; whether or not this happens depends on the
1855 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
1856 * after calling .round_rate then upstream parent propagation is ignored. If
1857 * *parent_rate comes back with a new rate for clk's parent then we propagate
24ee1a08 1858 * up to clk's parent and set its rate. Upward propagation will continue
5654dc94
MT
1859 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
1860 * .round_rate stops requesting changes to clk's parent_rate.
b2476490 1861 *
5654dc94
MT
1862 * Rate changes are accomplished via tree traversal that also recalculates the
1863 * rates for the clocks and fires off POST_RATE_CHANGE notifiers.
b2476490
MT
1864 *
1865 * Returns 0 on success, -EERROR otherwise.
1866 */
1867int clk_set_rate(struct clk *clk, unsigned long rate)
1868{
1c8e6004 1869 int ret;
b2476490 1870
89ac8d7a
MT
1871 if (!clk)
1872 return 0;
1873
b2476490 1874 /* prevent racing with updates to the clock topology */
eab89f69 1875 clk_prepare_lock();
b2476490 1876
1c8e6004 1877 ret = clk_core_set_rate_nolock(clk->core, rate);
b2476490 1878
1c8e6004 1879 clk_prepare_unlock();
0e1c0301 1880
1c8e6004
TV
1881 return ret;
1882}
1883EXPORT_SYMBOL_GPL(clk_set_rate);
b2476490 1884
1c8e6004
TV
1885/**
1886 * clk_set_rate_range - set a rate range for a clock source
1887 * @clk: clock source
1888 * @min: desired minimum clock rate in Hz, inclusive
1889 * @max: desired maximum clock rate in Hz, inclusive
1890 *
1891 * Returns success (0) or negative errno.
1892 */
1893int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
1894{
1895 int ret = 0;
1896
1897 if (!clk)
1898 return 0;
1899
1900 if (min > max) {
1901 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n",
1902 __func__, clk->core->name, clk->dev_id, clk->con_id,
1903 min, max);
1904 return -EINVAL;
b2476490
MT
1905 }
1906
1c8e6004
TV
1907 clk_prepare_lock();
1908
1909 if (min != clk->min_rate || max != clk->max_rate) {
1910 clk->min_rate = min;
1911 clk->max_rate = max;
1912 ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
1913 }
b2476490 1914
eab89f69 1915 clk_prepare_unlock();
b2476490
MT
1916
1917 return ret;
1918}
1c8e6004
TV
1919EXPORT_SYMBOL_GPL(clk_set_rate_range);
1920
1921/**
1922 * clk_set_min_rate - set a minimum clock rate for a clock source
1923 * @clk: clock source
1924 * @rate: desired minimum clock rate in Hz, inclusive
1925 *
1926 * Returns success (0) or negative errno.
1927 */
1928int clk_set_min_rate(struct clk *clk, unsigned long rate)
1929{
1930 if (!clk)
1931 return 0;
1932
1933 return clk_set_rate_range(clk, rate, clk->max_rate);
1934}
1935EXPORT_SYMBOL_GPL(clk_set_min_rate);
1936
1937/**
1938 * clk_set_max_rate - set a maximum clock rate for a clock source
1939 * @clk: clock source
1940 * @rate: desired maximum clock rate in Hz, inclusive
1941 *
1942 * Returns success (0) or negative errno.
1943 */
1944int clk_set_max_rate(struct clk *clk, unsigned long rate)
1945{
1946 if (!clk)
1947 return 0;
1948
1949 return clk_set_rate_range(clk, clk->min_rate, rate);
1950}
1951EXPORT_SYMBOL_GPL(clk_set_max_rate);
b2476490
MT
1952
1953/**
1954 * clk_get_parent - return the parent of a clk
1955 * @clk: the clk whose parent gets returned
1956 *
1957 * Simply returns clk->parent. Returns NULL if clk is NULL.
1958 */
1959struct clk *clk_get_parent(struct clk *clk)
1960{
1961 struct clk *parent;
1962
eab89f69 1963 clk_prepare_lock();
b2476490 1964 parent = __clk_get_parent(clk);
eab89f69 1965 clk_prepare_unlock();
b2476490
MT
1966
1967 return parent;
1968}
1969EXPORT_SYMBOL_GPL(clk_get_parent);
1970
1971/*
1972 * .get_parent is mandatory for clocks with multiple possible parents. It is
1973 * optional for single-parent clocks. Always call .get_parent if it is
1974 * available and WARN if it is missing for multi-parent clocks.
1975 *
1976 * For single-parent clocks without .get_parent, first check to see if the
1977 * .parents array exists, and if so use it to avoid an expensive tree
035a61c3 1978 * traversal. If .parents does not exist then walk the tree.
b2476490 1979 */
035a61c3 1980static struct clk_core *__clk_init_parent(struct clk_core *clk)
b2476490 1981{
035a61c3 1982 struct clk_core *ret = NULL;
b2476490
MT
1983 u8 index;
1984
1985 /* handle the trivial cases */
1986
1987 if (!clk->num_parents)
1988 goto out;
1989
1990 if (clk->num_parents == 1) {
1991 if (IS_ERR_OR_NULL(clk->parent))
035a61c3 1992 clk->parent = clk_core_lookup(clk->parent_names[0]);
b2476490
MT
1993 ret = clk->parent;
1994 goto out;
1995 }
1996
1997 if (!clk->ops->get_parent) {
1998 WARN(!clk->ops->get_parent,
1999 "%s: multi-parent clocks must implement .get_parent\n",
2000 __func__);
2001 goto out;
2002 };
2003
2004 /*
2005 * Do our best to cache parent clocks in clk->parents. This prevents
035a61c3
TV
2006 * unnecessary and expensive lookups. We don't set clk->parent here;
2007 * that is done by the calling function.
b2476490
MT
2008 */
2009
2010 index = clk->ops->get_parent(clk->hw);
2011
2012 if (!clk->parents)
2013 clk->parents =
96a7ed90 2014 kcalloc(clk->num_parents, sizeof(struct clk *),
b2476490
MT
2015 GFP_KERNEL);
2016
035a61c3 2017 ret = clk_core_get_parent_by_index(clk, index);
b2476490
MT
2018
2019out:
2020 return ret;
2021}
2022
035a61c3
TV
2023static void clk_core_reparent(struct clk_core *clk,
2024 struct clk_core *new_parent)
b33d212f
UH
2025{
2026 clk_reparent(clk, new_parent);
5279fc40 2027 __clk_recalc_accuracies(clk);
b2476490
MT
2028 __clk_recalc_rates(clk, POST_RATE_CHANGE);
2029}
2030
b2476490 2031/**
4e88f3de
TR
2032 * clk_has_parent - check if a clock is a possible parent for another
2033 * @clk: clock source
2034 * @parent: parent clock source
b2476490 2035 *
4e88f3de
TR
2036 * This function can be used in drivers that need to check that a clock can be
2037 * the parent of another without actually changing the parent.
f8aa0bd5 2038 *
4e88f3de 2039 * Returns true if @parent is a possible parent for @clk, false otherwise.
b2476490 2040 */
4e88f3de
TR
2041bool clk_has_parent(struct clk *clk, struct clk *parent)
2042{
035a61c3 2043 struct clk_core *core, *parent_core;
4e88f3de
TR
2044 unsigned int i;
2045
2046 /* NULL clocks should be nops, so return success if either is NULL. */
2047 if (!clk || !parent)
2048 return true;
2049
035a61c3
TV
2050 core = clk->core;
2051 parent_core = parent->core;
2052
4e88f3de 2053 /* Optimize for the case where the parent is already the parent. */
035a61c3 2054 if (core->parent == parent_core)
4e88f3de
TR
2055 return true;
2056
035a61c3
TV
2057 for (i = 0; i < core->num_parents; i++)
2058 if (strcmp(core->parent_names[i], parent_core->name) == 0)
4e88f3de
TR
2059 return true;
2060
2061 return false;
2062}
2063EXPORT_SYMBOL_GPL(clk_has_parent);
2064
035a61c3 2065static int clk_core_set_parent(struct clk_core *clk, struct clk_core *parent)
b2476490
MT
2066{
2067 int ret = 0;
f1c8b2ed 2068 int p_index = 0;
031dcc9b 2069 unsigned long p_rate = 0;
b2476490 2070
89ac8d7a
MT
2071 if (!clk)
2072 return 0;
2073
b2476490 2074 /* prevent racing with updates to the clock topology */
eab89f69 2075 clk_prepare_lock();
b2476490
MT
2076
2077 if (clk->parent == parent)
2078 goto out;
2079
b61c43c0
SB
2080 /* verify ops for for multi-parent clks */
2081 if ((clk->num_parents > 1) && (!clk->ops->set_parent)) {
2082 ret = -ENOSYS;
2083 goto out;
2084 }
2085
031dcc9b
UH
2086 /* check that we are allowed to re-parent if the clock is in use */
2087 if ((clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count) {
2088 ret = -EBUSY;
2089 goto out;
2090 }
2091
2092 /* try finding the new parent index */
2093 if (parent) {
2094 p_index = clk_fetch_parent_index(clk, parent);
2095 p_rate = parent->rate;
f1c8b2ed 2096 if (p_index < 0) {
031dcc9b
UH
2097 pr_debug("%s: clk %s can not be parent of clk %s\n",
2098 __func__, parent->name, clk->name);
f1c8b2ed 2099 ret = p_index;
031dcc9b
UH
2100 goto out;
2101 }
2102 }
2103
b2476490 2104 /* propagate PRE_RATE_CHANGE notifications */
f3aab5d6 2105 ret = __clk_speculate_rates(clk, p_rate);
b2476490
MT
2106
2107 /* abort if a driver objects */
fb72a059 2108 if (ret & NOTIFY_STOP_MASK)
b2476490
MT
2109 goto out;
2110
031dcc9b
UH
2111 /* do the re-parent */
2112 ret = __clk_set_parent(clk, parent, p_index);
b2476490 2113
5279fc40
BB
2114 /* propagate rate an accuracy recalculation accordingly */
2115 if (ret) {
b2476490 2116 __clk_recalc_rates(clk, ABORT_RATE_CHANGE);
5279fc40 2117 } else {
a68de8e4 2118 __clk_recalc_rates(clk, POST_RATE_CHANGE);
5279fc40
BB
2119 __clk_recalc_accuracies(clk);
2120 }
b2476490
MT
2121
2122out:
eab89f69 2123 clk_prepare_unlock();
b2476490
MT
2124
2125 return ret;
2126}
035a61c3
TV
2127
2128/**
2129 * clk_set_parent - switch the parent of a mux clk
2130 * @clk: the mux clk whose input we are switching
2131 * @parent: the new input to clk
2132 *
2133 * Re-parent clk to use parent as its new input source. If clk is in
2134 * prepared state, the clk will get enabled for the duration of this call. If
2135 * that's not acceptable for a specific clk (Eg: the consumer can't handle
2136 * that, the reparenting is glitchy in hardware, etc), use the
2137 * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
2138 *
2139 * After successfully changing clk's parent clk_set_parent will update the
2140 * clk topology, sysfs topology and propagate rate recalculation via
2141 * __clk_recalc_rates.
2142 *
2143 * Returns 0 on success, -EERROR otherwise.
2144 */
2145int clk_set_parent(struct clk *clk, struct clk *parent)
2146{
2147 if (!clk)
2148 return 0;
2149
2150 return clk_core_set_parent(clk->core, parent ? parent->core : NULL);
2151}
b2476490
MT
2152EXPORT_SYMBOL_GPL(clk_set_parent);
2153
e59c5371
MT
2154/**
2155 * clk_set_phase - adjust the phase shift of a clock signal
2156 * @clk: clock signal source
2157 * @degrees: number of degrees the signal is shifted
2158 *
2159 * Shifts the phase of a clock signal by the specified
2160 * degrees. Returns 0 on success, -EERROR otherwise.
2161 *
2162 * This function makes no distinction about the input or reference
2163 * signal that we adjust the clock signal phase against. For example
2164 * phase locked-loop clock signal generators we may shift phase with
2165 * respect to feedback clock signal input, but for other cases the
2166 * clock phase may be shifted with respect to some other, unspecified
2167 * signal.
2168 *
2169 * Additionally the concept of phase shift does not propagate through
2170 * the clock tree hierarchy, which sets it apart from clock rates and
2171 * clock accuracy. A parent clock phase attribute does not have an
2172 * impact on the phase attribute of a child clock.
2173 */
2174int clk_set_phase(struct clk *clk, int degrees)
2175{
08b95756 2176 int ret = -EINVAL;
e59c5371
MT
2177
2178 if (!clk)
08b95756 2179 return 0;
e59c5371
MT
2180
2181 /* sanity check degrees */
2182 degrees %= 360;
2183 if (degrees < 0)
2184 degrees += 360;
2185
2186 clk_prepare_lock();
2187
dfc202ea
SB
2188 trace_clk_set_phase(clk->core, degrees);
2189
08b95756
SB
2190 if (clk->core->ops->set_phase)
2191 ret = clk->core->ops->set_phase(clk->core->hw, degrees);
e59c5371 2192
dfc202ea
SB
2193 trace_clk_set_phase_complete(clk->core, degrees);
2194
e59c5371 2195 if (!ret)
035a61c3 2196 clk->core->phase = degrees;
e59c5371 2197
e59c5371
MT
2198 clk_prepare_unlock();
2199
e59c5371
MT
2200 return ret;
2201}
9767b04f 2202EXPORT_SYMBOL_GPL(clk_set_phase);
e59c5371 2203
035a61c3 2204static int clk_core_get_phase(struct clk_core *clk)
e59c5371
MT
2205{
2206 int ret = 0;
2207
2208 if (!clk)
2209 goto out;
2210
2211 clk_prepare_lock();
2212 ret = clk->phase;
2213 clk_prepare_unlock();
2214
2215out:
2216 return ret;
2217}
9767b04f 2218EXPORT_SYMBOL_GPL(clk_get_phase);
e59c5371 2219
035a61c3
TV
2220/**
2221 * clk_get_phase - return the phase shift of a clock signal
2222 * @clk: clock signal source
2223 *
2224 * Returns the phase shift of a clock node in degrees, otherwise returns
2225 * -EERROR.
2226 */
2227int clk_get_phase(struct clk *clk)
2228{
2229 if (!clk)
2230 return 0;
2231
2232 return clk_core_get_phase(clk->core);
2233}
e59c5371 2234
3d3801ef
MT
2235/**
2236 * clk_is_match - check if two clk's point to the same hardware clock
2237 * @p: clk compared against q
2238 * @q: clk compared against p
2239 *
2240 * Returns true if the two struct clk pointers both point to the same hardware
2241 * clock node. Put differently, returns true if struct clk *p and struct clk *q
2242 * share the same struct clk_core object.
2243 *
2244 * Returns false otherwise. Note that two NULL clks are treated as matching.
2245 */
2246bool clk_is_match(const struct clk *p, const struct clk *q)
2247{
2248 /* trivial case: identical struct clk's or both NULL */
2249 if (p == q)
2250 return true;
2251
2252 /* true if clk->core pointers match. Avoid derefing garbage */
2253 if (!IS_ERR_OR_NULL(p) && !IS_ERR_OR_NULL(q))
2254 if (p->core == q->core)
2255 return true;
2256
2257 return false;
2258}
2259EXPORT_SYMBOL_GPL(clk_is_match);
2260
b2476490
MT
2261/**
2262 * __clk_init - initialize the data structures in a struct clk
2263 * @dev: device initializing this clk, placeholder for now
2264 * @clk: clk being initialized
2265 *
035a61c3 2266 * Initializes the lists in struct clk_core, queries the hardware for the
b2476490 2267 * parent and rate and sets them both.
b2476490 2268 */
b09d6d99 2269static int __clk_init(struct device *dev, struct clk *clk_user)
b2476490 2270{
d1302a36 2271 int i, ret = 0;
035a61c3 2272 struct clk_core *orphan;
b67bfe0d 2273 struct hlist_node *tmp2;
035a61c3 2274 struct clk_core *clk;
1c8e6004 2275 unsigned long rate;
b2476490 2276
035a61c3 2277 if (!clk_user)
d1302a36 2278 return -EINVAL;
b2476490 2279
035a61c3
TV
2280 clk = clk_user->core;
2281
eab89f69 2282 clk_prepare_lock();
b2476490
MT
2283
2284 /* check to see if a clock with this name is already registered */
035a61c3 2285 if (clk_core_lookup(clk->name)) {
d1302a36
MT
2286 pr_debug("%s: clk %s already initialized\n",
2287 __func__, clk->name);
2288 ret = -EEXIST;
b2476490 2289 goto out;
d1302a36 2290 }
b2476490 2291
d4d7e3dd
MT
2292 /* check that clk_ops are sane. See Documentation/clk.txt */
2293 if (clk->ops->set_rate &&
71472c0c
JH
2294 !((clk->ops->round_rate || clk->ops->determine_rate) &&
2295 clk->ops->recalc_rate)) {
2296 pr_warning("%s: %s must implement .round_rate or .determine_rate in addition to .recalc_rate\n",
d4d7e3dd 2297 __func__, clk->name);
d1302a36 2298 ret = -EINVAL;
d4d7e3dd
MT
2299 goto out;
2300 }
2301
2302 if (clk->ops->set_parent && !clk->ops->get_parent) {
2303 pr_warning("%s: %s must implement .get_parent & .set_parent\n",
2304 __func__, clk->name);
d1302a36 2305 ret = -EINVAL;
d4d7e3dd
MT
2306 goto out;
2307 }
2308
3fa2252b
SB
2309 if (clk->ops->set_rate_and_parent &&
2310 !(clk->ops->set_parent && clk->ops->set_rate)) {
2311 pr_warn("%s: %s must implement .set_parent & .set_rate\n",
2312 __func__, clk->name);
2313 ret = -EINVAL;
2314 goto out;
2315 }
2316
b2476490
MT
2317 /* throw a WARN if any entries in parent_names are NULL */
2318 for (i = 0; i < clk->num_parents; i++)
2319 WARN(!clk->parent_names[i],
2320 "%s: invalid NULL in %s's .parent_names\n",
2321 __func__, clk->name);
2322
2323 /*
2324 * Allocate an array of struct clk *'s to avoid unnecessary string
2325 * look-ups of clk's possible parents. This can fail for clocks passed
2326 * in to clk_init during early boot; thus any access to clk->parents[]
2327 * must always check for a NULL pointer and try to populate it if
2328 * necessary.
2329 *
2330 * If clk->parents is not NULL we skip this entire block. This allows
2331 * for clock drivers to statically initialize clk->parents.
2332 */
9ca1c5a4 2333 if (clk->num_parents > 1 && !clk->parents) {
96a7ed90
TF
2334 clk->parents = kcalloc(clk->num_parents, sizeof(struct clk *),
2335 GFP_KERNEL);
b2476490 2336 /*
035a61c3 2337 * clk_core_lookup returns NULL for parents that have not been
b2476490
MT
2338 * clk_init'd; thus any access to clk->parents[] must check
2339 * for a NULL pointer. We can always perform lazy lookups for
2340 * missing parents later on.
2341 */
2342 if (clk->parents)
2343 for (i = 0; i < clk->num_parents; i++)
2344 clk->parents[i] =
035a61c3 2345 clk_core_lookup(clk->parent_names[i]);
b2476490
MT
2346 }
2347
2348 clk->parent = __clk_init_parent(clk);
2349
2350 /*
2351 * Populate clk->parent if parent has already been __clk_init'd. If
2352 * parent has not yet been __clk_init'd then place clk in the orphan
2353 * list. If clk has set the CLK_IS_ROOT flag then place it in the root
2354 * clk list.
2355 *
2356 * Every time a new clk is clk_init'd then we walk the list of orphan
2357 * clocks and re-parent any that are children of the clock currently
2358 * being clk_init'd.
2359 */
2360 if (clk->parent)
2361 hlist_add_head(&clk->child_node,
2362 &clk->parent->children);
2363 else if (clk->flags & CLK_IS_ROOT)
2364 hlist_add_head(&clk->child_node, &clk_root_list);
2365 else
2366 hlist_add_head(&clk->child_node, &clk_orphan_list);
2367
5279fc40
BB
2368 /*
2369 * Set clk's accuracy. The preferred method is to use
2370 * .recalc_accuracy. For simple clocks and lazy developers the default
2371 * fallback is to use the parent's accuracy. If a clock doesn't have a
2372 * parent (or is orphaned) then accuracy is set to zero (perfect
2373 * clock).
2374 */
2375 if (clk->ops->recalc_accuracy)
2376 clk->accuracy = clk->ops->recalc_accuracy(clk->hw,
2377 __clk_get_accuracy(clk->parent));
2378 else if (clk->parent)
2379 clk->accuracy = clk->parent->accuracy;
2380 else
2381 clk->accuracy = 0;
2382
9824cf73
MR
2383 /*
2384 * Set clk's phase.
2385 * Since a phase is by definition relative to its parent, just
2386 * query the current clock phase, or just assume it's in phase.
2387 */
2388 if (clk->ops->get_phase)
2389 clk->phase = clk->ops->get_phase(clk->hw);
2390 else
2391 clk->phase = 0;
2392
b2476490
MT
2393 /*
2394 * Set clk's rate. The preferred method is to use .recalc_rate. For
2395 * simple clocks and lazy developers the default fallback is to use the
2396 * parent's rate. If a clock doesn't have a parent (or is orphaned)
2397 * then rate is set to zero.
2398 */
2399 if (clk->ops->recalc_rate)
1c8e6004 2400 rate = clk->ops->recalc_rate(clk->hw,
035a61c3 2401 clk_core_get_rate_nolock(clk->parent));
b2476490 2402 else if (clk->parent)
1c8e6004 2403 rate = clk->parent->rate;
b2476490 2404 else
1c8e6004
TV
2405 rate = 0;
2406 clk->rate = clk->req_rate = rate;
b2476490
MT
2407
2408 /*
2409 * walk the list of orphan clocks and reparent any that are children of
2410 * this clock
2411 */
b67bfe0d 2412 hlist_for_each_entry_safe(orphan, tmp2, &clk_orphan_list, child_node) {
12d29886 2413 if (orphan->num_parents && orphan->ops->get_parent) {
1f61e5f1
MF
2414 i = orphan->ops->get_parent(orphan->hw);
2415 if (!strcmp(clk->name, orphan->parent_names[i]))
035a61c3 2416 clk_core_reparent(orphan, clk);
1f61e5f1
MF
2417 continue;
2418 }
2419
b2476490
MT
2420 for (i = 0; i < orphan->num_parents; i++)
2421 if (!strcmp(clk->name, orphan->parent_names[i])) {
035a61c3 2422 clk_core_reparent(orphan, clk);
b2476490
MT
2423 break;
2424 }
1f61e5f1 2425 }
b2476490
MT
2426
2427 /*
2428 * optional platform-specific magic
2429 *
2430 * The .init callback is not used by any of the basic clock types, but
2431 * exists for weird hardware that must perform initialization magic.
2432 * Please consider other ways of solving initialization problems before
24ee1a08 2433 * using this callback, as its use is discouraged.
b2476490
MT
2434 */
2435 if (clk->ops->init)
2436 clk->ops->init(clk->hw);
2437
fcb0ee6a 2438 kref_init(&clk->ref);
b2476490 2439out:
eab89f69 2440 clk_prepare_unlock();
b2476490 2441
89f7e9de
SB
2442 if (!ret)
2443 clk_debug_register(clk);
2444
d1302a36 2445 return ret;
b2476490
MT
2446}
2447
035a61c3
TV
2448struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
2449 const char *con_id)
0197b3ea 2450{
0197b3ea
SK
2451 struct clk *clk;
2452
035a61c3
TV
2453 /* This is to allow this function to be chained to others */
2454 if (!hw || IS_ERR(hw))
2455 return (struct clk *) hw;
0197b3ea 2456
035a61c3
TV
2457 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
2458 if (!clk)
2459 return ERR_PTR(-ENOMEM);
2460
2461 clk->core = hw->core;
2462 clk->dev_id = dev_id;
2463 clk->con_id = con_id;
1c8e6004
TV
2464 clk->max_rate = ULONG_MAX;
2465
2466 clk_prepare_lock();
50595f8b 2467 hlist_add_head(&clk->clks_node, &hw->core->clks);
1c8e6004 2468 clk_prepare_unlock();
0197b3ea
SK
2469
2470 return clk;
2471}
035a61c3 2472
73e0e496 2473void __clk_free_clk(struct clk *clk)
1c8e6004
TV
2474{
2475 clk_prepare_lock();
50595f8b 2476 hlist_del(&clk->clks_node);
1c8e6004
TV
2477 clk_prepare_unlock();
2478
2479 kfree(clk);
2480}
0197b3ea 2481
293ba3b4
SB
2482/**
2483 * clk_register - allocate a new clock, register it and return an opaque cookie
2484 * @dev: device that is registering this clock
2485 * @hw: link to hardware-specific clock data
2486 *
2487 * clk_register is the primary interface for populating the clock tree with new
2488 * clock nodes. It returns a pointer to the newly allocated struct clk which
2489 * cannot be dereferenced by driver code but may be used in conjuction with the
2490 * rest of the clock API. In the event of an error clk_register will return an
2491 * error code; drivers must test for an error code after calling clk_register.
2492 */
2493struct clk *clk_register(struct device *dev, struct clk_hw *hw)
b2476490 2494{
d1302a36 2495 int i, ret;
035a61c3 2496 struct clk_core *clk;
293ba3b4
SB
2497
2498 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
2499 if (!clk) {
2500 pr_err("%s: could not allocate clk\n", __func__);
2501 ret = -ENOMEM;
2502 goto fail_out;
2503 }
b2476490 2504
612936f2 2505 clk->name = kstrdup_const(hw->init->name, GFP_KERNEL);
0197b3ea
SK
2506 if (!clk->name) {
2507 pr_err("%s: could not allocate clk->name\n", __func__);
2508 ret = -ENOMEM;
2509 goto fail_name;
2510 }
2511 clk->ops = hw->init->ops;
ac2df527
SN
2512 if (dev && dev->driver)
2513 clk->owner = dev->driver->owner;
b2476490 2514 clk->hw = hw;
0197b3ea
SK
2515 clk->flags = hw->init->flags;
2516 clk->num_parents = hw->init->num_parents;
035a61c3 2517 hw->core = clk;
b2476490 2518
d1302a36 2519 /* allocate local copy in case parent_names is __initdata */
96a7ed90
TF
2520 clk->parent_names = kcalloc(clk->num_parents, sizeof(char *),
2521 GFP_KERNEL);
d1302a36
MT
2522
2523 if (!clk->parent_names) {
2524 pr_err("%s: could not allocate clk->parent_names\n", __func__);
2525 ret = -ENOMEM;
2526 goto fail_parent_names;
2527 }
2528
2529
2530 /* copy each string name in case parent_names is __initdata */
0197b3ea 2531 for (i = 0; i < clk->num_parents; i++) {
612936f2 2532 clk->parent_names[i] = kstrdup_const(hw->init->parent_names[i],
0197b3ea 2533 GFP_KERNEL);
d1302a36
MT
2534 if (!clk->parent_names[i]) {
2535 pr_err("%s: could not copy parent_names\n", __func__);
2536 ret = -ENOMEM;
2537 goto fail_parent_names_copy;
2538 }
2539 }
2540
1c8e6004
TV
2541 INIT_HLIST_HEAD(&clk->clks);
2542
035a61c3
TV
2543 hw->clk = __clk_create_clk(hw, NULL, NULL);
2544 if (IS_ERR(hw->clk)) {
2545 pr_err("%s: could not allocate per-user clk\n", __func__);
2546 ret = PTR_ERR(hw->clk);
2547 goto fail_parent_names_copy;
2548 }
2549
2550 ret = __clk_init(dev, hw->clk);
d1302a36 2551 if (!ret)
035a61c3 2552 return hw->clk;
b2476490 2553
1c8e6004 2554 __clk_free_clk(hw->clk);
035a61c3 2555 hw->clk = NULL;
b2476490 2556
d1302a36
MT
2557fail_parent_names_copy:
2558 while (--i >= 0)
612936f2 2559 kfree_const(clk->parent_names[i]);
d1302a36
MT
2560 kfree(clk->parent_names);
2561fail_parent_names:
612936f2 2562 kfree_const(clk->name);
0197b3ea 2563fail_name:
d1302a36
MT
2564 kfree(clk);
2565fail_out:
2566 return ERR_PTR(ret);
b2476490
MT
2567}
2568EXPORT_SYMBOL_GPL(clk_register);
2569
fcb0ee6a
SN
2570/*
2571 * Free memory allocated for a clock.
2572 * Caller must hold prepare_lock.
2573 */
2574static void __clk_release(struct kref *ref)
2575{
035a61c3 2576 struct clk_core *clk = container_of(ref, struct clk_core, ref);
fcb0ee6a
SN
2577 int i = clk->num_parents;
2578
496eadf8
KK
2579 lockdep_assert_held(&prepare_lock);
2580
fcb0ee6a
SN
2581 kfree(clk->parents);
2582 while (--i >= 0)
612936f2 2583 kfree_const(clk->parent_names[i]);
fcb0ee6a
SN
2584
2585 kfree(clk->parent_names);
612936f2 2586 kfree_const(clk->name);
fcb0ee6a
SN
2587 kfree(clk);
2588}
2589
2590/*
2591 * Empty clk_ops for unregistered clocks. These are used temporarily
2592 * after clk_unregister() was called on a clock and until last clock
2593 * consumer calls clk_put() and the struct clk object is freed.
2594 */
2595static int clk_nodrv_prepare_enable(struct clk_hw *hw)
2596{
2597 return -ENXIO;
2598}
2599
2600static void clk_nodrv_disable_unprepare(struct clk_hw *hw)
2601{
2602 WARN_ON_ONCE(1);
2603}
2604
2605static int clk_nodrv_set_rate(struct clk_hw *hw, unsigned long rate,
2606 unsigned long parent_rate)
2607{
2608 return -ENXIO;
2609}
2610
2611static int clk_nodrv_set_parent(struct clk_hw *hw, u8 index)
2612{
2613 return -ENXIO;
2614}
2615
2616static const struct clk_ops clk_nodrv_ops = {
2617 .enable = clk_nodrv_prepare_enable,
2618 .disable = clk_nodrv_disable_unprepare,
2619 .prepare = clk_nodrv_prepare_enable,
2620 .unprepare = clk_nodrv_disable_unprepare,
2621 .set_rate = clk_nodrv_set_rate,
2622 .set_parent = clk_nodrv_set_parent,
2623};
2624
1df5c939
MB
2625/**
2626 * clk_unregister - unregister a currently registered clock
2627 * @clk: clock to unregister
1df5c939 2628 */
fcb0ee6a
SN
2629void clk_unregister(struct clk *clk)
2630{
2631 unsigned long flags;
2632
6314b679
SB
2633 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
2634 return;
2635
035a61c3 2636 clk_debug_unregister(clk->core);
fcb0ee6a
SN
2637
2638 clk_prepare_lock();
2639
035a61c3
TV
2640 if (clk->core->ops == &clk_nodrv_ops) {
2641 pr_err("%s: unregistered clock: %s\n", __func__,
2642 clk->core->name);
6314b679 2643 return;
fcb0ee6a
SN
2644 }
2645 /*
2646 * Assign empty clock ops for consumers that might still hold
2647 * a reference to this clock.
2648 */
2649 flags = clk_enable_lock();
035a61c3 2650 clk->core->ops = &clk_nodrv_ops;
fcb0ee6a
SN
2651 clk_enable_unlock(flags);
2652
035a61c3
TV
2653 if (!hlist_empty(&clk->core->children)) {
2654 struct clk_core *child;
874f224c 2655 struct hlist_node *t;
fcb0ee6a
SN
2656
2657 /* Reparent all children to the orphan list. */
035a61c3
TV
2658 hlist_for_each_entry_safe(child, t, &clk->core->children,
2659 child_node)
2660 clk_core_set_parent(child, NULL);
fcb0ee6a
SN
2661 }
2662
035a61c3 2663 hlist_del_init(&clk->core->child_node);
fcb0ee6a 2664
035a61c3 2665 if (clk->core->prepare_count)
fcb0ee6a 2666 pr_warn("%s: unregistering prepared clock: %s\n",
035a61c3
TV
2667 __func__, clk->core->name);
2668 kref_put(&clk->core->ref, __clk_release);
6314b679 2669
fcb0ee6a
SN
2670 clk_prepare_unlock();
2671}
1df5c939
MB
2672EXPORT_SYMBOL_GPL(clk_unregister);
2673
46c8773a
SB
2674static void devm_clk_release(struct device *dev, void *res)
2675{
293ba3b4 2676 clk_unregister(*(struct clk **)res);
46c8773a
SB
2677}
2678
2679/**
2680 * devm_clk_register - resource managed clk_register()
2681 * @dev: device that is registering this clock
2682 * @hw: link to hardware-specific clock data
2683 *
2684 * Managed clk_register(). Clocks returned from this function are
2685 * automatically clk_unregister()ed on driver detach. See clk_register() for
2686 * more information.
2687 */
2688struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw)
2689{
2690 struct clk *clk;
293ba3b4 2691 struct clk **clkp;
46c8773a 2692
293ba3b4
SB
2693 clkp = devres_alloc(devm_clk_release, sizeof(*clkp), GFP_KERNEL);
2694 if (!clkp)
46c8773a
SB
2695 return ERR_PTR(-ENOMEM);
2696
293ba3b4
SB
2697 clk = clk_register(dev, hw);
2698 if (!IS_ERR(clk)) {
2699 *clkp = clk;
2700 devres_add(dev, clkp);
46c8773a 2701 } else {
293ba3b4 2702 devres_free(clkp);
46c8773a
SB
2703 }
2704
2705 return clk;
2706}
2707EXPORT_SYMBOL_GPL(devm_clk_register);
2708
2709static int devm_clk_match(struct device *dev, void *res, void *data)
2710{
2711 struct clk *c = res;
2712 if (WARN_ON(!c))
2713 return 0;
2714 return c == data;
2715}
2716
2717/**
2718 * devm_clk_unregister - resource managed clk_unregister()
2719 * @clk: clock to unregister
2720 *
2721 * Deallocate a clock allocated with devm_clk_register(). Normally
2722 * this function will not need to be called and the resource management
2723 * code will ensure that the resource is freed.
2724 */
2725void devm_clk_unregister(struct device *dev, struct clk *clk)
2726{
2727 WARN_ON(devres_release(dev, devm_clk_release, devm_clk_match, clk));
2728}
2729EXPORT_SYMBOL_GPL(devm_clk_unregister);
2730
ac2df527
SN
2731/*
2732 * clkdev helpers
2733 */
2734int __clk_get(struct clk *clk)
2735{
035a61c3
TV
2736 struct clk_core *core = !clk ? NULL : clk->core;
2737
2738 if (core) {
2739 if (!try_module_get(core->owner))
00efcb1c 2740 return 0;
ac2df527 2741
035a61c3 2742 kref_get(&core->ref);
00efcb1c 2743 }
ac2df527
SN
2744 return 1;
2745}
2746
2747void __clk_put(struct clk *clk)
2748{
10cdfe54
TV
2749 struct module *owner;
2750
00efcb1c 2751 if (!clk || WARN_ON_ONCE(IS_ERR(clk)))
ac2df527
SN
2752 return;
2753
fcb0ee6a 2754 clk_prepare_lock();
1c8e6004 2755
50595f8b 2756 hlist_del(&clk->clks_node);
ec02ace8
TV
2757 if (clk->min_rate > clk->core->req_rate ||
2758 clk->max_rate < clk->core->req_rate)
2759 clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
2760
1c8e6004
TV
2761 owner = clk->core->owner;
2762 kref_put(&clk->core->ref, __clk_release);
2763
fcb0ee6a
SN
2764 clk_prepare_unlock();
2765
10cdfe54 2766 module_put(owner);
035a61c3 2767
035a61c3 2768 kfree(clk);
ac2df527
SN
2769}
2770
b2476490
MT
2771/*** clk rate change notifiers ***/
2772
2773/**
2774 * clk_notifier_register - add a clk rate change notifier
2775 * @clk: struct clk * to watch
2776 * @nb: struct notifier_block * with callback info
2777 *
2778 * Request notification when clk's rate changes. This uses an SRCU
2779 * notifier because we want it to block and notifier unregistrations are
2780 * uncommon. The callbacks associated with the notifier must not
2781 * re-enter into the clk framework by calling any top-level clk APIs;
2782 * this will cause a nested prepare_lock mutex.
2783 *
5324fda7
SB
2784 * In all notification cases cases (pre, post and abort rate change) the
2785 * original clock rate is passed to the callback via struct
2786 * clk_notifier_data.old_rate and the new frequency is passed via struct
b2476490
MT
2787 * clk_notifier_data.new_rate.
2788 *
b2476490
MT
2789 * clk_notifier_register() must be called from non-atomic context.
2790 * Returns -EINVAL if called with null arguments, -ENOMEM upon
2791 * allocation failure; otherwise, passes along the return value of
2792 * srcu_notifier_chain_register().
2793 */
2794int clk_notifier_register(struct clk *clk, struct notifier_block *nb)
2795{
2796 struct clk_notifier *cn;
2797 int ret = -ENOMEM;
2798
2799 if (!clk || !nb)
2800 return -EINVAL;
2801
eab89f69 2802 clk_prepare_lock();
b2476490
MT
2803
2804 /* search the list of notifiers for this clk */
2805 list_for_each_entry(cn, &clk_notifier_list, node)
2806 if (cn->clk == clk)
2807 break;
2808
2809 /* if clk wasn't in the notifier list, allocate new clk_notifier */
2810 if (cn->clk != clk) {
2811 cn = kzalloc(sizeof(struct clk_notifier), GFP_KERNEL);
2812 if (!cn)
2813 goto out;
2814
2815 cn->clk = clk;
2816 srcu_init_notifier_head(&cn->notifier_head);
2817
2818 list_add(&cn->node, &clk_notifier_list);
2819 }
2820
2821 ret = srcu_notifier_chain_register(&cn->notifier_head, nb);
2822
035a61c3 2823 clk->core->notifier_count++;
b2476490
MT
2824
2825out:
eab89f69 2826 clk_prepare_unlock();
b2476490
MT
2827
2828 return ret;
2829}
2830EXPORT_SYMBOL_GPL(clk_notifier_register);
2831
2832/**
2833 * clk_notifier_unregister - remove a clk rate change notifier
2834 * @clk: struct clk *
2835 * @nb: struct notifier_block * with callback info
2836 *
2837 * Request no further notification for changes to 'clk' and frees memory
2838 * allocated in clk_notifier_register.
2839 *
2840 * Returns -EINVAL if called with null arguments; otherwise, passes
2841 * along the return value of srcu_notifier_chain_unregister().
2842 */
2843int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb)
2844{
2845 struct clk_notifier *cn = NULL;
2846 int ret = -EINVAL;
2847
2848 if (!clk || !nb)
2849 return -EINVAL;
2850
eab89f69 2851 clk_prepare_lock();
b2476490
MT
2852
2853 list_for_each_entry(cn, &clk_notifier_list, node)
2854 if (cn->clk == clk)
2855 break;
2856
2857 if (cn->clk == clk) {
2858 ret = srcu_notifier_chain_unregister(&cn->notifier_head, nb);
2859
035a61c3 2860 clk->core->notifier_count--;
b2476490
MT
2861
2862 /* XXX the notifier code should handle this better */
2863 if (!cn->notifier_head.head) {
2864 srcu_cleanup_notifier_head(&cn->notifier_head);
72b5322f 2865 list_del(&cn->node);
b2476490
MT
2866 kfree(cn);
2867 }
2868
2869 } else {
2870 ret = -ENOENT;
2871 }
2872
eab89f69 2873 clk_prepare_unlock();
b2476490
MT
2874
2875 return ret;
2876}
2877EXPORT_SYMBOL_GPL(clk_notifier_unregister);
766e6a4e
GL
2878
2879#ifdef CONFIG_OF
2880/**
2881 * struct of_clk_provider - Clock provider registration structure
2882 * @link: Entry in global list of clock providers
2883 * @node: Pointer to device tree node of clock provider
2884 * @get: Get clock callback. Returns NULL or a struct clk for the
2885 * given clock specifier
2886 * @data: context pointer to be passed into @get callback
2887 */
2888struct of_clk_provider {
2889 struct list_head link;
2890
2891 struct device_node *node;
2892 struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
2893 void *data;
2894};
2895
f2f6c255
PG
2896static const struct of_device_id __clk_of_table_sentinel
2897 __used __section(__clk_of_table_end);
2898
766e6a4e 2899static LIST_HEAD(of_clk_providers);
d6782c26
SN
2900static DEFINE_MUTEX(of_clk_mutex);
2901
766e6a4e
GL
2902struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
2903 void *data)
2904{
2905 return data;
2906}
2907EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
2908
494bfec9
SG
2909struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
2910{
2911 struct clk_onecell_data *clk_data = data;
2912 unsigned int idx = clkspec->args[0];
2913
2914 if (idx >= clk_data->clk_num) {
2915 pr_err("%s: invalid clock index %d\n", __func__, idx);
2916 return ERR_PTR(-EINVAL);
2917 }
2918
2919 return clk_data->clks[idx];
2920}
2921EXPORT_SYMBOL_GPL(of_clk_src_onecell_get);
2922
766e6a4e
GL
2923/**
2924 * of_clk_add_provider() - Register a clock provider for a node
2925 * @np: Device node pointer associated with clock provider
2926 * @clk_src_get: callback for decoding clock
2927 * @data: context pointer for @clk_src_get callback.
2928 */
2929int of_clk_add_provider(struct device_node *np,
2930 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec,
2931 void *data),
2932 void *data)
2933{
2934 struct of_clk_provider *cp;
86be408b 2935 int ret;
766e6a4e
GL
2936
2937 cp = kzalloc(sizeof(struct of_clk_provider), GFP_KERNEL);
2938 if (!cp)
2939 return -ENOMEM;
2940
2941 cp->node = of_node_get(np);
2942 cp->data = data;
2943 cp->get = clk_src_get;
2944
d6782c26 2945 mutex_lock(&of_clk_mutex);
766e6a4e 2946 list_add(&cp->link, &of_clk_providers);
d6782c26 2947 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
2948 pr_debug("Added clock from %s\n", np->full_name);
2949
86be408b
SN
2950 ret = of_clk_set_defaults(np, true);
2951 if (ret < 0)
2952 of_clk_del_provider(np);
2953
2954 return ret;
766e6a4e
GL
2955}
2956EXPORT_SYMBOL_GPL(of_clk_add_provider);
2957
2958/**
2959 * of_clk_del_provider() - Remove a previously registered clock provider
2960 * @np: Device node pointer associated with clock provider
2961 */
2962void of_clk_del_provider(struct device_node *np)
2963{
2964 struct of_clk_provider *cp;
2965
d6782c26 2966 mutex_lock(&of_clk_mutex);
766e6a4e
GL
2967 list_for_each_entry(cp, &of_clk_providers, link) {
2968 if (cp->node == np) {
2969 list_del(&cp->link);
2970 of_node_put(cp->node);
2971 kfree(cp);
2972 break;
2973 }
2974 }
d6782c26 2975 mutex_unlock(&of_clk_mutex);
766e6a4e
GL
2976}
2977EXPORT_SYMBOL_GPL(of_clk_del_provider);
2978
73e0e496
SB
2979struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
2980 const char *dev_id, const char *con_id)
766e6a4e
GL
2981{
2982 struct of_clk_provider *provider;
a34cd466 2983 struct clk *clk = ERR_PTR(-EPROBE_DEFER);
766e6a4e 2984
306c342f
SB
2985 if (!clkspec)
2986 return ERR_PTR(-EINVAL);
2987
766e6a4e 2988 /* Check if we have such a provider in our array */
306c342f 2989 mutex_lock(&of_clk_mutex);
766e6a4e
GL
2990 list_for_each_entry(provider, &of_clk_providers, link) {
2991 if (provider->node == clkspec->np)
2992 clk = provider->get(clkspec, provider->data);
73e0e496
SB
2993 if (!IS_ERR(clk)) {
2994 clk = __clk_create_clk(__clk_get_hw(clk), dev_id,
2995 con_id);
2996
2997 if (!IS_ERR(clk) && !__clk_get(clk)) {
2998 __clk_free_clk(clk);
2999 clk = ERR_PTR(-ENOENT);
3000 }
3001
766e6a4e 3002 break;
73e0e496 3003 }
766e6a4e 3004 }
306c342f 3005 mutex_unlock(&of_clk_mutex);
d6782c26
SN
3006
3007 return clk;
3008}
3009
306c342f
SB
3010/**
3011 * of_clk_get_from_provider() - Lookup a clock from a clock provider
3012 * @clkspec: pointer to a clock specifier data structure
3013 *
3014 * This function looks up a struct clk from the registered list of clock
3015 * providers, an input is a clock specifier data structure as returned
3016 * from the of_parse_phandle_with_args() function call.
3017 */
d6782c26
SN
3018struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
3019{
306c342f 3020 return __of_clk_get_from_provider(clkspec, NULL, __func__);
766e6a4e
GL
3021}
3022
f6102742
MT
3023int of_clk_get_parent_count(struct device_node *np)
3024{
3025 return of_count_phandle_with_args(np, "clocks", "#clock-cells");
3026}
3027EXPORT_SYMBOL_GPL(of_clk_get_parent_count);
3028
766e6a4e
GL
3029const char *of_clk_get_parent_name(struct device_node *np, int index)
3030{
3031 struct of_phandle_args clkspec;
7a0fc1a3 3032 struct property *prop;
766e6a4e 3033 const char *clk_name;
7a0fc1a3
BD
3034 const __be32 *vp;
3035 u32 pv;
766e6a4e 3036 int rc;
7a0fc1a3 3037 int count;
766e6a4e
GL
3038
3039 if (index < 0)
3040 return NULL;
3041
3042 rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
3043 &clkspec);
3044 if (rc)
3045 return NULL;
3046
7a0fc1a3
BD
3047 index = clkspec.args_count ? clkspec.args[0] : 0;
3048 count = 0;
3049
3050 /* if there is an indices property, use it to transfer the index
3051 * specified into an array offset for the clock-output-names property.
3052 */
3053 of_property_for_each_u32(clkspec.np, "clock-indices", prop, vp, pv) {
3054 if (index == pv) {
3055 index = count;
3056 break;
3057 }
3058 count++;
3059 }
3060
766e6a4e 3061 if (of_property_read_string_index(clkspec.np, "clock-output-names",
7a0fc1a3 3062 index,
766e6a4e
GL
3063 &clk_name) < 0)
3064 clk_name = clkspec.np->name;
3065
3066 of_node_put(clkspec.np);
3067 return clk_name;
3068}
3069EXPORT_SYMBOL_GPL(of_clk_get_parent_name);
3070
1771b10d
GC
3071struct clock_provider {
3072 of_clk_init_cb_t clk_init_cb;
3073 struct device_node *np;
3074 struct list_head node;
3075};
3076
3077static LIST_HEAD(clk_provider_list);
3078
3079/*
3080 * This function looks for a parent clock. If there is one, then it
3081 * checks that the provider for this parent clock was initialized, in
3082 * this case the parent clock will be ready.
3083 */
3084static int parent_ready(struct device_node *np)
3085{
3086 int i = 0;
3087
3088 while (true) {
3089 struct clk *clk = of_clk_get(np, i);
3090
3091 /* this parent is ready we can check the next one */
3092 if (!IS_ERR(clk)) {
3093 clk_put(clk);
3094 i++;
3095 continue;
3096 }
3097
3098 /* at least one parent is not ready, we exit now */
3099 if (PTR_ERR(clk) == -EPROBE_DEFER)
3100 return 0;
3101
3102 /*
3103 * Here we make assumption that the device tree is
3104 * written correctly. So an error means that there is
3105 * no more parent. As we didn't exit yet, then the
3106 * previous parent are ready. If there is no clock
3107 * parent, no need to wait for them, then we can
3108 * consider their absence as being ready
3109 */
3110 return 1;
3111 }
3112}
3113
766e6a4e
GL
3114/**
3115 * of_clk_init() - Scan and init clock providers from the DT
3116 * @matches: array of compatible values and init functions for providers.
3117 *
1771b10d 3118 * This function scans the device tree for matching clock providers
e5ca8fb4 3119 * and calls their initialization functions. It also does it by trying
1771b10d 3120 * to follow the dependencies.
766e6a4e
GL
3121 */
3122void __init of_clk_init(const struct of_device_id *matches)
3123{
7f7ed584 3124 const struct of_device_id *match;
766e6a4e 3125 struct device_node *np;
1771b10d
GC
3126 struct clock_provider *clk_provider, *next;
3127 bool is_init_done;
3128 bool force = false;
766e6a4e 3129
f2f6c255 3130 if (!matches)
819b4861 3131 matches = &__clk_of_table;
f2f6c255 3132
1771b10d 3133 /* First prepare the list of the clocks providers */
7f7ed584 3134 for_each_matching_node_and_match(np, matches, &match) {
1771b10d
GC
3135 struct clock_provider *parent =
3136 kzalloc(sizeof(struct clock_provider), GFP_KERNEL);
3137
3138 parent->clk_init_cb = match->data;
3139 parent->np = np;
3f6d439f 3140 list_add_tail(&parent->node, &clk_provider_list);
1771b10d
GC
3141 }
3142
3143 while (!list_empty(&clk_provider_list)) {
3144 is_init_done = false;
3145 list_for_each_entry_safe(clk_provider, next,
3146 &clk_provider_list, node) {
3147 if (force || parent_ready(clk_provider->np)) {
86be408b 3148
1771b10d 3149 clk_provider->clk_init_cb(clk_provider->np);
86be408b
SN
3150 of_clk_set_defaults(clk_provider->np, true);
3151
1771b10d
GC
3152 list_del(&clk_provider->node);
3153 kfree(clk_provider);
3154 is_init_done = true;
3155 }
3156 }
3157
3158 /*
e5ca8fb4 3159 * We didn't manage to initialize any of the
1771b10d
GC
3160 * remaining providers during the last loop, so now we
3161 * initialize all the remaining ones unconditionally
3162 * in case the clock parent was not mandatory
3163 */
3164 if (!is_init_done)
3165 force = true;
766e6a4e
GL
3166 }
3167}
3168#endif