[mirror_ubuntu-bionic-kernel.git] / drivers / clk / hisilicon / clk.h

/*
 * Hisilicon Hi3620 clock gate driver
 *
 * Copyright (c) 2012-2013 Hisilicon Limited.
 * Copyright (c) 2012-2013 Linaro Limited.
 *
 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
 *	   Xin Li <li.xin@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 *
 */

#ifndef	__HISI_CLK_H
#define	__HISI_CLK_H

#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/spinlock.h>

struct hisi_clock_data {
	struct clk_onecell_data	clk_data;
	void __iomem		*base;
};

struct hisi_fixed_rate_clock {
	unsigned int		id;
	char			*name;
	const char		*parent_name;
	unsigned long		flags;
	unsigned long		fixed_rate;
};

struct hisi_fixed_factor_clock {
	unsigned int		id;
	char			*name;
	const char		*parent_name;
	unsigned long		mult;
	unsigned long		div;
	unsigned long		flags;
};

struct hisi_mux_clock {
	unsigned int		id;
	const char		*name;
	const char		**parent_names;
	u8			num_parents;
	unsigned long		flags;
	unsigned long		offset;
	u8			shift;
	u8			width;
	u8			mux_flags;
	u32			*table;
	const char		*alias;
};

struct hisi_divider_clock {
	unsigned int		id;
	const char		*name;
	const char		*parent_name;
	unsigned long		flags;
	unsigned long		offset;
	u8			shift;
	u8			width;
	u8			div_flags;
	struct clk_div_table	*table;
	const char		*alias;
};

struct hisi_gate_clock {
	unsigned int		id;
	const char		*name;
	const char		*parent_name;
	unsigned long		flags;
	unsigned long		offset;
	u8			bit_idx;
	u8			gate_flags;
	const char		*alias;
};

struct clk *hisi_register_clkgate_sep(struct device *, const char *,
				const char *, unsigned long,
				void __iomem *, u8,
				u8, spinlock_t *);

struct hisi_clock_data __init *hisi_clk_init(struct device_node *, int);
void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *,
					int, struct hisi_clock_data *);
void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,
					int, struct hisi_clock_data *);
void __init hisi_clk_register_mux(struct hisi_mux_clock *, int,
				struct hisi_clock_data *);
void __init hisi_clk_register_divider(struct hisi_divider_clock *,
				int, struct hisi_clock_data *);
void __init hisi_clk_register_gate(struct hisi_gate_clock *,
					int, struct hisi_clock_data *);
void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *,
					int, struct hisi_clock_data *);
#endif	/* __HISI_CLK_H */
Commit	Line	Data
0aa0c95f HZ	1	/*
	2	* Hisilicon Hi3620 clock gate driver
	3	*
	4	* Copyright (c) 2012-2013 Hisilicon Limited.
	5	* Copyright (c) 2012-2013 Linaro Limited.
	6	*
	7	* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
	8	* Xin Li <li.xin@linaro.org>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License along
	21	* with this program; if not, write to the Free Software Foundation, Inc.,
	22	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
	23	*
	24	*/
	25
	26	#ifndef __HISI_CLK_H
	27	#define __HISI_CLK_H
	28
	29	#include <linux/clk-provider.h>
	30	#include <linux/io.h>
	31	#include <linux/spinlock.h>
	32
75af25f5 HZ	33	struct hisi_clock_data {
	34	struct clk_onecell_data clk_data;
	35	void __iomem *base;
	36	};
	37
0aa0c95f HZ	38	struct hisi_fixed_rate_clock {
	39	unsigned int id;
	40	char *name;
	41	const char *parent_name;
	42	unsigned long flags;
	43	unsigned long fixed_rate;
	44	};
	45
	46	struct hisi_fixed_factor_clock {
	47	unsigned int id;
	48	char *name;
	49	const char *parent_name;
	50	unsigned long mult;
	51	unsigned long div;
	52	unsigned long flags;
	53	};
	54
	55	struct hisi_mux_clock {
	56	unsigned int id;
	57	const char *name;
	58	const char **parent_names;
	59	u8 num_parents;
	60	unsigned long flags;
	61	unsigned long offset;
	62	u8 shift;
	63	u8 width;
	64	u8 mux_flags;
156342a1	65	u32 *table;
0aa0c95f HZ	66	const char *alias;
	67	};
	68
	69	struct hisi_divider_clock {
	70	unsigned int id;
	71	const char *name;
	72	const char *parent_name;
	73	unsigned long flags;
	74	unsigned long offset;
	75	u8 shift;
	76	u8 width;
	77	u8 div_flags;
	78	struct clk_div_table *table;
	79	const char *alias;
	80	};
	81
	82	struct hisi_gate_clock {
	83	unsigned int id;
	84	const char *name;
	85	const char *parent_name;
	86	unsigned long flags;
	87	unsigned long offset;
	88	u8 bit_idx;
	89	u8 gate_flags;
	90	const char *alias;
	91	};
	92
	93	struct clk hisi_register_clkgate_sep(struct device , const char *,
	94	const char *, unsigned long,
	95	void __iomem *, u8,
	96	u8, spinlock_t *);
	97
75af25f5	98	struct hisi_clock_data __init hisi_clk_init(struct device_node , int);
0aa0c95f	99	void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *,
75af25f5	100	int, struct hisi_clock_data *);
0aa0c95f	101	void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,
75af25f5	102	int, struct hisi_clock_data *);
0aa0c95f	103	void __init hisi_clk_register_mux(struct hisi_mux_clock *, int,
75af25f5	104	struct hisi_clock_data *);
0aa0c95f	105	void __init hisi_clk_register_divider(struct hisi_divider_clock *,
75af25f5	106	int, struct hisi_clock_data *);
8b9dcb6c ZG	107	void __init hisi_clk_register_gate(struct hisi_gate_clock *,
8b9dcb6c ZG	108	int, struct hisi_clock_data *);
0aa0c95f	109	void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *,
75af25f5	110	int, struct hisi_clock_data *);
0aa0c95f	111	#endif /* __HISI_CLK_H */