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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
93421e42 SH |
2 | /* |
3 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
4 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
5 | * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com | |
93421e42 SH |
6 | */ |
7 | ||
93421e42 | 8 | #include <linux/clk-provider.h> |
548694b9 | 9 | #include <linux/clkdev.h> |
62e59c4e | 10 | #include <linux/io.h> |
35bcaf00 AS |
11 | #include <linux/of.h> |
12 | #include <linux/of_address.h> | |
13 | #include <dt-bindings/clock/imx21-clock.h> | |
0931aff7 | 14 | #include <soc/imx/timer.h> |
0c831317 | 15 | #include <asm/irq.h> |
93421e42 | 16 | |
93421e42 | 17 | #include "clk.h" |
0c831317 SG |
18 | |
19 | #define MX21_CCM_BASE_ADDR 0x10027000 | |
20 | #define MX21_GPT1_BASE_ADDR 0x10003000 | |
21 | #define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26) | |
93421e42 | 22 | |
35bcaf00 | 23 | static void __iomem *ccm __initdata; |
93421e42 SH |
24 | |
25 | /* Register offsets */ | |
35bcaf00 AS |
26 | #define CCM_CSCR (ccm + 0x00) |
27 | #define CCM_MPCTL0 (ccm + 0x04) | |
28 | #define CCM_SPCTL0 (ccm + 0x0c) | |
29 | #define CCM_PCDR0 (ccm + 0x18) | |
30 | #define CCM_PCDR1 (ccm + 0x1c) | |
31 | #define CCM_PCCR0 (ccm + 0x20) | |
32 | #define CCM_PCCR1 (ccm + 0x24) | |
93421e42 | 33 | |
65251690 AS |
34 | static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", }; |
35 | static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", }; | |
36 | static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", }; | |
37 | static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", }; | |
93421e42 | 38 | |
35bcaf00 AS |
39 | static struct clk *clk[IMX21_CLK_MAX]; |
40 | static struct clk_onecell_data clk_data; | |
93421e42 | 41 | |
35bcaf00 | 42 | static void __init _mx21_clocks_init(unsigned long lref, unsigned long href) |
93421e42 | 43 | { |
35bcaf00 AS |
44 | BUG_ON(!ccm); |
45 | ||
46 | clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0); | |
47 | clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref); | |
48 | clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href); | |
49 | clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1); | |
50 | clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); | |
51 | ||
52 | clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); | |
53 | clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); | |
54 | clk[IMX21_CLK_FPM_GATE] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2); | |
55 | clk[IMX21_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); | |
56 | clk[IMX21_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks)); | |
57 | clk[IMX21_CLK_IPG] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1); | |
58 | clk[IMX21_CLK_HCLK] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4); | |
59 | clk[IMX21_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks)); | |
60 | clk[IMX21_CLK_SPLL_SEL] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks)); | |
61 | clk[IMX21_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); | |
62 | clk[IMX21_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); | |
63 | clk[IMX21_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3); | |
64 | clk[IMX21_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3); | |
65 | ||
3bec5f81 | 66 | clk[IMX21_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX21, "mpll", "mpll_sel", CCM_MPCTL0); |
35bcaf00 | 67 | |
3bec5f81 | 68 | clk[IMX21_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX21, "spll", "spll_sel", CCM_SPCTL0); |
35bcaf00 AS |
69 | |
70 | clk[IMX21_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4); | |
71 | clk[IMX21_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); | |
72 | clk[IMX21_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6); | |
73 | ||
74 | clk[IMX21_CLK_PER1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6); | |
75 | clk[IMX21_CLK_PER2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6); | |
76 | clk[IMX21_CLK_PER3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6); | |
77 | clk[IMX21_CLK_PER4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6); | |
78 | ||
79 | clk[IMX21_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0); | |
80 | clk[IMX21_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1); | |
81 | clk[IMX21_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2); | |
82 | clk[IMX21_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3); | |
83 | clk[IMX21_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4); | |
84 | clk[IMX21_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5); | |
85 | clk[IMX21_CLK_SSI1_GATE] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6); | |
86 | clk[IMX21_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7); | |
87 | clk[IMX21_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9); | |
88 | clk[IMX21_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10); | |
89 | clk[IMX21_CLK_GPIO_GATE] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11); | |
90 | clk[IMX21_CLK_I2C_GATE] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12); | |
91 | clk[IMX21_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13); | |
92 | clk[IMX21_CLK_USB_GATE] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14); | |
93 | clk[IMX21_CLK_EMMA_GATE] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15); | |
94 | clk[IMX21_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16); | |
95 | clk[IMX21_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17); | |
96 | clk[IMX21_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18); | |
97 | clk[IMX21_CLK_NFC_GATE] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19); | |
98 | clk[IMX21_CLK_SLCDC_HCLK_GATE] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21); | |
99 | clk[IMX21_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22); | |
100 | clk[IMX21_CLK_BMI_GATE] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23); | |
101 | clk[IMX21_CLK_USB_HCLK_GATE] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24); | |
102 | clk[IMX21_CLK_SLCDC_GATE] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25); | |
103 | clk[IMX21_CLK_LCDC_HCLK_GATE] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26); | |
104 | clk[IMX21_CLK_EMMA_HCLK_GATE] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27); | |
105 | clk[IMX21_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28); | |
106 | clk[IMX21_CLK_DMA_HCLK_GATE] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30); | |
107 | clk[IMX21_CLK_CSI_HCLK_GATE] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31); | |
108 | ||
109 | clk[IMX21_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23); | |
110 | clk[IMX21_CLK_WDOG_GATE] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24); | |
111 | clk[IMX21_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25); | |
112 | clk[IMX21_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26); | |
113 | clk[IMX21_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27); | |
114 | clk[IMX21_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28); | |
115 | clk[IMX21_CLK_RTC_GATE] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29); | |
116 | clk[IMX21_CLK_KPP_GATE] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30); | |
117 | clk[IMX21_CLK_OWIRE_GATE] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31); | |
93421e42 | 118 | |
229be9c1 | 119 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
35bcaf00 | 120 | } |
93421e42 | 121 | |
35bcaf00 AS |
122 | int __init mx21_clocks_init(unsigned long lref, unsigned long href) |
123 | { | |
124 | ccm = ioremap(MX21_CCM_BASE_ADDR, SZ_2K); | |
125 | ||
126 | _mx21_clocks_init(lref, href); | |
127 | ||
128 | clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.0"); | |
129 | clk_register_clkdev(clk[IMX21_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); | |
130 | clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.1"); | |
131 | clk_register_clkdev(clk[IMX21_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); | |
132 | clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.2"); | |
133 | clk_register_clkdev(clk[IMX21_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); | |
134 | clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.3"); | |
135 | clk_register_clkdev(clk[IMX21_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); | |
136 | clk_register_clkdev(clk[IMX21_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0"); | |
137 | clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx-gpt.0"); | |
138 | clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.0"); | |
139 | clk_register_clkdev(clk[IMX21_CLK_CSPI1_IPG_GATE], "ipg", "imx21-cspi.0"); | |
140 | clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.1"); | |
141 | clk_register_clkdev(clk[IMX21_CLK_CSPI2_IPG_GATE], "ipg", "imx21-cspi.1"); | |
142 | clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.2"); | |
143 | clk_register_clkdev(clk[IMX21_CLK_CSPI3_IPG_GATE], "ipg", "imx21-cspi.2"); | |
144 | clk_register_clkdev(clk[IMX21_CLK_PER3], "per", "imx21-fb.0"); | |
145 | clk_register_clkdev(clk[IMX21_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); | |
146 | clk_register_clkdev(clk[IMX21_CLK_LCDC_HCLK_GATE], "ahb", "imx21-fb.0"); | |
147 | clk_register_clkdev(clk[IMX21_CLK_USB_GATE], "per", "imx21-hcd.0"); | |
148 | clk_register_clkdev(clk[IMX21_CLK_USB_HCLK_GATE], "ahb", "imx21-hcd.0"); | |
149 | clk_register_clkdev(clk[IMX21_CLK_NFC_GATE], NULL, "imx21-nand.0"); | |
150 | clk_register_clkdev(clk[IMX21_CLK_DMA_HCLK_GATE], "ahb", "imx21-dma"); | |
151 | clk_register_clkdev(clk[IMX21_CLK_DMA_GATE], "ipg", "imx21-dma"); | |
152 | clk_register_clkdev(clk[IMX21_CLK_WDOG_GATE], NULL, "imx2-wdt.0"); | |
153 | clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0"); | |
154 | clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0"); | |
93421e42 | 155 | |
0931aff7 | 156 | mxc_timer_init(MX21_GPT1_BASE_ADDR, MX21_INT_GPT1, GPT_TYPE_IMX21); |
2cfb4518 | 157 | |
93421e42 SH |
158 | return 0; |
159 | } | |
35bcaf00 AS |
160 | |
161 | static void __init mx21_clocks_init_dt(struct device_node *np) | |
162 | { | |
163 | ccm = of_iomap(np, 0); | |
164 | ||
165 | _mx21_clocks_init(32768, 26000000); | |
166 | ||
167 | clk_data.clks = clk; | |
168 | clk_data.clk_num = ARRAY_SIZE(clk); | |
169 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
35bcaf00 AS |
170 | } |
171 | CLK_OF_DECLARE(imx27_ccm, "fsl,imx21-ccm", mx21_clocks_init_dt); |