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95878cbe SH |
1 | /* |
2 | * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version 2 | |
7 | * of the License, or (at your option) any later version. | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/clkdev.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/err.h> | |
d2a37b3d | 23 | #include <linux/of.h> |
0c831317 | 24 | #include <soc/imx/revision.h> |
0931aff7 | 25 | #include <soc/imx/timer.h> |
0c831317 | 26 | #include <asm/irq.h> |
95878cbe | 27 | |
95878cbe | 28 | #include "clk.h" |
0c831317 SG |
29 | |
30 | #define MX31_CCM_BASE_ADDR 0x53f80000 | |
31 | #define MX31_GPT1_BASE_ADDR 0x53f90000 | |
32 | #define MX31_INT_GPT (NR_IRQS_LEGACY + 29) | |
33 | ||
34 | #define MXC_CCM_CCMR 0x00 | |
35 | #define MXC_CCM_PDR0 0x04 | |
36 | #define MXC_CCM_PDR1 0x08 | |
37 | #define MXC_CCM_MPCTL 0x10 | |
38 | #define MXC_CCM_UPCTL 0x14 | |
39 | #define MXC_CCM_SRPCTL 0x18 | |
40 | #define MXC_CCM_CGR0 0x20 | |
41 | #define MXC_CCM_CGR1 0x24 | |
42 | #define MXC_CCM_CGR2 0x28 | |
43 | #define MXC_CCM_PMCR0 0x5c | |
95878cbe SH |
44 | |
45 | static const char *mcu_main_sel[] = { "spll", "mpll", }; | |
46 | static const char *per_sel[] = { "per_div", "ipg", }; | |
47 | static const char *csi_sel[] = { "upll", "spll", }; | |
48 | static const char *fir_sel[] = { "mcu_main", "upll", "spll" }; | |
49 | ||
50 | enum mx31_clks { | |
8a1a9540 FE |
51 | dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, |
52 | per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre, | |
95878cbe SH |
53 | fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate, |
54 | iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate, | |
55 | uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate, | |
56 | mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate, | |
57 | sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate, | |
58 | uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate, | |
59 | gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max | |
60 | }; | |
61 | ||
62 | static struct clk *clk[clk_max]; | |
ef0e4a60 | 63 | static struct clk_onecell_data clk_data; |
95878cbe | 64 | |
5c678cdd LS |
65 | static struct clk ** const uart_clks[] __initconst = { |
66 | &clk[ipg], | |
67 | &clk[uart1_gate], | |
68 | &clk[uart2_gate], | |
69 | &clk[uart3_gate], | |
70 | &clk[uart4_gate], | |
71 | &clk[uart5_gate], | |
72 | NULL | |
73 | }; | |
74 | ||
d9388c84 | 75 | static void __init _mx31_clocks_init(unsigned long fref) |
95878cbe | 76 | { |
5ab96a8d | 77 | void __iomem *base; |
ef0e4a60 | 78 | struct device_node *np; |
95878cbe | 79 | |
5ab96a8d SG |
80 | base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K); |
81 | BUG_ON(!base); | |
82 | ||
8a1a9540 | 83 | clk[dummy] = imx_clk_fixed("dummy", 0); |
95878cbe SH |
84 | clk[ckih] = imx_clk_fixed("ckih", fref); |
85 | clk[ckil] = imx_clk_fixed("ckil", 32768); | |
3bec5f81 SG |
86 | clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); |
87 | clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); | |
88 | clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL); | |
95878cbe SH |
89 | clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel)); |
90 | clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3); | |
91 | clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); | |
92 | clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); | |
93 | clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); | |
94 | clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5); | |
95 | clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel)); | |
96 | clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel)); | |
97 | clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel)); | |
98 | clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9); | |
99 | clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2); | |
100 | clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3); | |
101 | clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3); | |
102 | clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6); | |
103 | clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0); | |
104 | clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2); | |
105 | clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4); | |
106 | clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6); | |
107 | clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8); | |
108 | clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10); | |
109 | clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12); | |
110 | clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14); | |
111 | clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16); | |
112 | clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18); | |
113 | clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20); | |
114 | clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22); | |
115 | clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24); | |
116 | clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26); | |
117 | clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28); | |
118 | clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30); | |
119 | clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0); | |
120 | clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2); | |
121 | clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4); | |
122 | clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6); | |
123 | clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8); | |
124 | clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10); | |
125 | clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12); | |
126 | clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14); | |
127 | clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16); | |
128 | clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18); | |
129 | clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20); | |
130 | clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22); | |
131 | clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24); | |
132 | clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26); | |
133 | clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28); | |
134 | clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30); | |
135 | clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0); | |
136 | clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2); | |
137 | clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4); | |
138 | clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6); | |
139 | clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8); | |
140 | clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); | |
141 | clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12); | |
142 | ||
229be9c1 | 143 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
95878cbe | 144 | |
d9388c84 AS |
145 | clk_set_parent(clk[csi], clk[upll]); |
146 | clk_prepare_enable(clk[emi_gate]); | |
147 | clk_prepare_enable(clk[iim_gate]); | |
148 | mx31_revision(); | |
149 | clk_disable_unprepare(clk[iim_gate]); | |
150 | ||
ef0e4a60 FE |
151 | np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm"); |
152 | ||
153 | if (np) { | |
154 | clk_data.clks = clk; | |
155 | clk_data.clk_num = ARRAY_SIZE(clk); | |
156 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
157 | } | |
d9388c84 AS |
158 | } |
159 | ||
160 | int __init mx31_clocks_init(void) | |
161 | { | |
162 | u32 fref = 26000000; /* default */ | |
163 | ||
164 | _mx31_clocks_init(fref); | |
ef0e4a60 | 165 | |
95878cbe SH |
166 | clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); |
167 | clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); | |
168 | clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0"); | |
169 | clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1"); | |
170 | clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2"); | |
171 | clk_register_clkdev(clk[pwm_gate], "pwm", NULL); | |
172 | clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); | |
00a48fe3 PR |
173 | clk_register_clkdev(clk[ckil], "ref", "imx21-rtc"); |
174 | clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc"); | |
95878cbe SH |
175 | clk_register_clkdev(clk[epit1_gate], "epit", NULL); |
176 | clk_register_clkdev(clk[epit2_gate], "epit", NULL); | |
4d62435f | 177 | clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0"); |
95878cbe SH |
178 | clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); |
179 | clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); | |
8cc7a2b9 | 180 | clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); |
95878cbe SH |
181 | clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0"); |
182 | clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0"); | |
183 | clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); | |
184 | clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1"); | |
185 | clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1"); | |
186 | clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); | |
187 | clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2"); | |
188 | clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2"); | |
189 | clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); | |
61c4b560 PC |
190 | clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27"); |
191 | clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27"); | |
192 | clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); | |
95878cbe SH |
193 | clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); |
194 | /* i.mx31 has the i.mx21 type uart */ | |
195 | clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); | |
196 | clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); | |
197 | clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); | |
198 | clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); | |
199 | clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); | |
200 | clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); | |
201 | clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3"); | |
202 | clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3"); | |
203 | clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4"); | |
204 | clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4"); | |
5bdfba29 SG |
205 | clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); |
206 | clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); | |
207 | clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); | |
95878cbe | 208 | clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0"); |
7f917a8d SG |
209 | clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0"); |
210 | clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1"); | |
95878cbe SH |
211 | clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); |
212 | clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); | |
213 | clk_register_clkdev(clk[firi_gate], "firi", NULL); | |
214 | clk_register_clkdev(clk[ata_gate], NULL, "pata_imx"); | |
215 | clk_register_clkdev(clk[rtic_gate], "rtic", NULL); | |
14ac5b88 | 216 | clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga"); |
95878cbe SH |
217 | clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma"); |
218 | clk_register_clkdev(clk[iim_gate], "iim", NULL); | |
219 | ||
95878cbe | 220 | |
5c678cdd | 221 | imx_register_uart_clocks(uart_clks); |
0931aff7 | 222 | mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31); |
95878cbe SH |
223 | |
224 | return 0; | |
225 | } | |
d2a37b3d | 226 | |
d2a37b3d DGC |
227 | int __init mx31_clocks_init_dt(void) |
228 | { | |
229 | struct device_node *np; | |
230 | u32 fref = 26000000; /* default */ | |
231 | ||
232 | for_each_compatible_node(np, NULL, "fixed-clock") { | |
233 | if (!of_device_is_compatible(np, "fsl,imx-osc26m")) | |
234 | continue; | |
235 | ||
236 | if (!of_property_read_u32(np, "clock-frequency", &fref)) | |
237 | break; | |
238 | } | |
239 | ||
d9388c84 AS |
240 | _mx31_clocks_init(fref); |
241 | ||
242 | return 0; | |
d2a37b3d | 243 | } |