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2acd1b6f | 1 | /* |
e7b82d64 | 2 | * Copyright 2011-2013 Freescale Semiconductor, Inc. |
2acd1b6f SG |
3 | * Copyright 2011 Linaro Ltd. |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/types.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/clkdev.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_address.h> | |
21 | #include <linux/of_irq.h> | |
0c831317 | 22 | #include <soc/imx/revision.h> |
d2d2e54d | 23 | #include <dt-bindings/clock/imx6qdl-clock.h> |
e3372474 | 24 | |
2acd1b6f SG |
25 | #include "clk.h" |
26 | ||
2acd1b6f SG |
27 | static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; |
28 | static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; | |
29 | static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; | |
72cd7447 PZ |
30 | static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; |
31 | static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; | |
2acd1b6f SG |
32 | static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; |
33 | static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; | |
a08b9bc5 | 34 | static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; |
64990a43 | 35 | static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; |
2acd1b6f | 36 | static const char *gpu_axi_sels[] = { "axi", "ahb", }; |
ee360274 | 37 | static const char *pre_axi_sels[] = { "axi", "ahb", }; |
2acd1b6f | 38 | static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; |
ee360274 | 39 | static const char *gpu2d_core_sels_2[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m",}; |
2acd1b6f | 40 | static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; |
de78a23d | 41 | static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; |
2acd1b6f | 42 | static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; |
cc9a3e99 | 43 | static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; |
2df1d026 | 44 | static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; |
2acd1b6f SG |
45 | static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; |
46 | static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; | |
47 | static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; | |
48 | static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; | |
ee360274 BP |
49 | static const char *ipu1_di0_sels_2[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; |
50 | static const char *ipu1_di1_sels_2[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; | |
51 | static const char *ipu2_di0_sels_2[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; | |
52 | static const char *ipu2_di1_sels_2[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; | |
2acd1b6f SG |
53 | static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; |
54 | static const char *pcie_axi_sels[] = { "axi", "ahb", }; | |
64990a43 | 55 | static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; |
2acd1b6f SG |
56 | static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; |
57 | static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; | |
ee360274 | 58 | static const char *enfc_sels_2[] = {"pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", }; |
a1fc1980 SL |
59 | static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; |
60 | static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; | |
2acd1b6f SG |
61 | static const char *vdo_axi_sels[] = { "axi", "ahb", }; |
62 | static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; | |
ee360274 BP |
63 | static const char *uart_sels[] = { "pll3_80m", "osc", }; |
64 | static const char *ipg_per_sels[] = { "ipg", "osc", }; | |
65 | static const char *ecspi_sels[] = { "pll3_60m", "osc", }; | |
66 | static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", }; | |
2df1d026 | 67 | static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", |
2acd1b6f | 68 | "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", |
64990a43 | 69 | "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", }; |
6526bb3c SG |
70 | static const char *cko2_sels[] = { |
71 | "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1", | |
72 | "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi", | |
73 | "usdhc3", "dummy", "arm", "ipu1", | |
74 | "ipu2", "vdo_axi", "osc", "gpu2d_core", | |
75 | "gpu3d_core", "usdhc2", "ssi1", "ssi2", | |
76 | "ssi3", "gpu3d_shader", "vpu_axi", "can_root", | |
7bce3d23 | 77 | "ldb_di0", "ldb_di1", "esai_extal", "eim_slow", |
6526bb3c SG |
78 | "uart_serial", "spdif", "asrc", "hsi_tx", |
79 | }; | |
6cd62235 | 80 | static const char *cko_sels[] = { "cko1", "cko2", }; |
bf221721 SC |
81 | static const char *lvds_sels[] = { |
82 | "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", | |
83 | "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", | |
2e133f61 MT |
84 | "pcie_ref_125m", "sata_ref_100m", "usbphy1", "usbphy2", |
85 | "dummy", "dummy", "dummy", "dummy", "osc", | |
bf221721 | 86 | }; |
b1f156db SG |
87 | static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", }; |
88 | static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; | |
89 | static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", }; | |
90 | static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", }; | |
91 | static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", }; | |
92 | static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", }; | |
93 | static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", }; | |
94 | static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; | |
2acd1b6f | 95 | |
d2d2e54d | 96 | static struct clk *clk[IMX6QDL_CLK_END]; |
0e87e043 | 97 | static struct clk_onecell_data clk_data; |
2acd1b6f | 98 | |
d2d2e54d SG |
99 | static unsigned int const clks_init_on[] __initconst = { |
100 | IMX6QDL_CLK_MMDC_CH0_AXI, | |
101 | IMX6QDL_CLK_ROM, | |
102 | IMX6QDL_CLK_ARM, | |
b0286f20 RZ |
103 | }; |
104 | ||
7a04092c SH |
105 | static struct clk_div_table clk_enet_ref_table[] = { |
106 | { .val = 0, .div = 20, }, | |
107 | { .val = 1, .div = 10, }, | |
108 | { .val = 2, .div = 5, }, | |
109 | { .val = 3, .div = 4, }, | |
ec9de6cd | 110 | { /* sentinel */ } |
7a04092c SH |
111 | }; |
112 | ||
2df1d026 PZ |
113 | static struct clk_div_table post_div_table[] = { |
114 | { .val = 2, .div = 1, }, | |
115 | { .val = 1, .div = 2, }, | |
116 | { .val = 0, .div = 4, }, | |
ec9de6cd | 117 | { /* sentinel */ } |
2df1d026 PZ |
118 | }; |
119 | ||
120 | static struct clk_div_table video_div_table[] = { | |
121 | { .val = 0, .div = 1, }, | |
122 | { .val = 1, .div = 2, }, | |
123 | { .val = 2, .div = 1, }, | |
124 | { .val = 3, .div = 4, }, | |
ec9de6cd | 125 | { /* sentinel */ } |
2df1d026 PZ |
126 | }; |
127 | ||
886cda41 | 128 | static unsigned int share_count_esai; |
aec247d4 | 129 | static unsigned int share_count_asrc; |
bd404b1d SW |
130 | static unsigned int share_count_ssi1; |
131 | static unsigned int share_count_ssi2; | |
132 | static unsigned int share_count_ssi3; | |
721fee59 | 133 | static unsigned int share_count_mipi_core_cfg; |
84a87250 | 134 | static unsigned int share_count_spdif; |
ee360274 BP |
135 | static unsigned int share_count_prg0; |
136 | static unsigned int share_count_prg1; | |
886cda41 | 137 | |
961dfd37 SG |
138 | static inline int clk_on_imx6q(void) |
139 | { | |
140 | return of_machine_is_compatible("fsl,imx6q"); | |
141 | } | |
142 | ||
ee360274 BP |
143 | static inline int clk_on_imx6qp(void) |
144 | { | |
145 | return of_machine_is_compatible("fsl,imx6qp"); | |
146 | } | |
147 | ||
961dfd37 SG |
148 | static inline int clk_on_imx6dl(void) |
149 | { | |
150 | return of_machine_is_compatible("fsl,imx6dl"); | |
151 | } | |
152 | ||
0822f933 LS |
153 | static struct clk ** const uart_clks[] __initconst = { |
154 | &clk[IMX6QDL_CLK_UART_IPG], | |
155 | &clk[IMX6QDL_CLK_UART_SERIAL], | |
156 | NULL | |
157 | }; | |
158 | ||
5d283b08 FE |
159 | static int ldb_di_sel_by_clock_id(int clock_id) |
160 | { | |
161 | switch (clock_id) { | |
162 | case IMX6QDL_CLK_PLL5_VIDEO_DIV: | |
163 | if (clk_on_imx6q() && | |
164 | imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) | |
165 | return -ENOENT; | |
166 | return 0; | |
167 | case IMX6QDL_CLK_PLL2_PFD0_352M: | |
168 | return 1; | |
169 | case IMX6QDL_CLK_PLL2_PFD2_396M: | |
170 | return 2; | |
171 | case IMX6QDL_CLK_MMDC_CH1_AXI: | |
172 | return 3; | |
173 | case IMX6QDL_CLK_PLL3_USB_OTG: | |
174 | return 4; | |
175 | default: | |
176 | return -ENOENT; | |
177 | } | |
178 | } | |
179 | ||
180 | static void of_assigned_ldb_sels(struct device_node *node, | |
181 | unsigned int *ldb_di0_sel, | |
182 | unsigned int *ldb_di1_sel) | |
183 | { | |
184 | struct of_phandle_args clkspec; | |
185 | int index, rc, num_parents; | |
186 | int parent, child, sel; | |
187 | ||
188 | num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", | |
189 | "#clock-cells"); | |
190 | for (index = 0; index < num_parents; index++) { | |
191 | rc = of_parse_phandle_with_args(node, "assigned-clock-parents", | |
192 | "#clock-cells", index, &clkspec); | |
193 | if (rc < 0) { | |
194 | /* skip empty (null) phandles */ | |
195 | if (rc == -ENOENT) | |
196 | continue; | |
197 | else | |
198 | return; | |
199 | } | |
200 | if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) { | |
201 | pr_err("ccm: parent clock %d not in ccm\n", index); | |
202 | return; | |
203 | } | |
204 | parent = clkspec.args[0]; | |
205 | ||
206 | rc = of_parse_phandle_with_args(node, "assigned-clocks", | |
207 | "#clock-cells", index, &clkspec); | |
208 | if (rc < 0) | |
209 | return; | |
210 | if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) { | |
211 | pr_err("ccm: child clock %d not in ccm\n", index); | |
212 | return; | |
213 | } | |
214 | child = clkspec.args[0]; | |
215 | ||
216 | if (child != IMX6QDL_CLK_LDB_DI0_SEL && | |
217 | child != IMX6QDL_CLK_LDB_DI1_SEL) | |
218 | continue; | |
219 | ||
220 | sel = ldb_di_sel_by_clock_id(parent); | |
221 | if (sel < 0) { | |
222 | pr_err("ccm: invalid ldb_di%d parent clock: %d\n", | |
223 | child == IMX6QDL_CLK_LDB_DI1_SEL, parent); | |
224 | continue; | |
225 | } | |
226 | ||
227 | if (child == IMX6QDL_CLK_LDB_DI0_SEL) | |
228 | *ldb_di0_sel = sel; | |
229 | if (child == IMX6QDL_CLK_LDB_DI1_SEL) | |
230 | *ldb_di1_sel = sel; | |
231 | } | |
232 | } | |
233 | ||
f13abeff | 234 | #define CCM_CCDR 0x04 |
5d283b08 FE |
235 | #define CCM_CCSR 0x0c |
236 | #define CCM_CS2CDR 0x2c | |
237 | ||
238 | #define CCDR_MMDC_CH1_MASK BIT(16) | |
239 | #define CCSR_PLL3_SW_CLK_SEL BIT(0) | |
f13abeff | 240 | |
5d283b08 FE |
241 | #define CS2CDR_LDB_DI0_CLK_SEL_SHIFT 9 |
242 | #define CS2CDR_LDB_DI1_CLK_SEL_SHIFT 12 | |
f13abeff PZ |
243 | |
244 | static void __init imx6q_mmdc_ch1_mask_handshake(void __iomem *ccm_base) | |
245 | { | |
246 | unsigned int reg; | |
247 | ||
248 | reg = readl_relaxed(ccm_base + CCM_CCDR); | |
249 | reg |= CCDR_MMDC_CH1_MASK; | |
250 | writel_relaxed(reg, ccm_base + CCM_CCDR); | |
251 | } | |
252 | ||
5d283b08 FE |
253 | /* |
254 | * The only way to disable the MMDC_CH1 clock is to move it to pll3_sw_clk | |
255 | * via periph2_clk2_sel and then to disable pll3_sw_clk by selecting the | |
256 | * bypass clock source, since there is no CG bit for mmdc_ch1. | |
257 | */ | |
258 | static void mmdc_ch1_disable(void __iomem *ccm_base) | |
259 | { | |
260 | unsigned int reg; | |
261 | ||
262 | clk_set_parent(clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL], | |
263 | clk[IMX6QDL_CLK_PLL3_USB_OTG]); | |
264 | ||
265 | /* | |
266 | * Handshake with mmdc_ch1 module must be masked when changing | |
267 | * periph2_clk_sel. | |
268 | */ | |
269 | clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_CLK2]); | |
270 | ||
271 | /* Disable pll3_sw_clk by selecting the bypass clock source */ | |
272 | reg = readl_relaxed(ccm_base + CCM_CCSR); | |
273 | reg |= CCSR_PLL3_SW_CLK_SEL; | |
274 | writel_relaxed(reg, ccm_base + CCM_CCSR); | |
275 | } | |
276 | ||
277 | static void mmdc_ch1_reenable(void __iomem *ccm_base) | |
278 | { | |
279 | unsigned int reg; | |
280 | ||
281 | /* Enable pll3_sw_clk by disabling the bypass */ | |
282 | reg = readl_relaxed(ccm_base + CCM_CCSR); | |
283 | reg &= ~CCSR_PLL3_SW_CLK_SEL; | |
284 | writel_relaxed(reg, ccm_base + CCM_CCSR); | |
285 | ||
286 | clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_PRE]); | |
287 | } | |
288 | ||
289 | /* | |
290 | * We have to follow a strict procedure when changing the LDB clock source, | |
291 | * otherwise we risk introducing a glitch that can lock up the LDB divider. | |
292 | * Things to keep in mind: | |
293 | * | |
294 | * 1. The current and new parent clock inputs to the mux must be disabled. | |
295 | * 2. The default clock input for ldb_di0/1_clk_sel is mmdc_ch1_axi, which | |
296 | * has no CG bit. | |
297 | * 3. pll2_pfd2_396m can not be gated if it is used as memory clock. | |
298 | * 4. In the RTL implementation of the LDB_DI_CLK_SEL muxes the top four | |
299 | * options are in one mux and the PLL3 option along with three unused | |
300 | * inputs is in a second mux. There is a third mux with two inputs used | |
301 | * to decide between the first and second 4-port mux: | |
302 | * | |
303 | * pll5_video_div 0 --|\ | |
304 | * pll2_pfd0_352m 1 --| |_ | |
305 | * pll2_pfd2_396m 2 --| | `-|\ | |
306 | * mmdc_ch1_axi 3 --|/ | | | |
307 | * | |-- | |
308 | * pll3_usb_otg 4 --|\ | | | |
309 | * 5 --| |_,-|/ | |
310 | * 6 --| | | |
311 | * 7 --|/ | |
312 | * | |
313 | * The ldb_di0/1_clk_sel[1:0] bits control both 4-port muxes at the same time. | |
314 | * The ldb_di0/1_clk_sel[2] bit controls the 2-port mux. The code below | |
315 | * switches the parent to the bottom mux first and then manipulates the top | |
316 | * mux to ensure that no glitch will enter the divider. | |
317 | */ | |
318 | static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base) | |
319 | { | |
320 | unsigned int reg; | |
321 | unsigned int sel[2][4]; | |
322 | int i; | |
323 | ||
324 | reg = readl_relaxed(ccm_base + CCM_CS2CDR); | |
325 | sel[0][0] = (reg >> CS2CDR_LDB_DI0_CLK_SEL_SHIFT) & 7; | |
326 | sel[1][0] = (reg >> CS2CDR_LDB_DI1_CLK_SEL_SHIFT) & 7; | |
327 | ||
328 | sel[0][3] = sel[0][2] = sel[0][1] = sel[0][0]; | |
329 | sel[1][3] = sel[1][2] = sel[1][1] = sel[1][0]; | |
330 | ||
331 | of_assigned_ldb_sels(np, &sel[0][3], &sel[1][3]); | |
332 | ||
333 | for (i = 0; i < 2; i++) { | |
334 | /* Warn if a glitch might have been introduced already */ | |
335 | if (sel[i][0] != 3) { | |
336 | pr_warn("ccm: ldb_di%d_sel already changed from reset value: %d\n", | |
337 | i, sel[i][0]); | |
338 | } | |
339 | ||
340 | if (sel[i][0] == sel[i][3]) | |
341 | continue; | |
342 | ||
343 | /* Only switch to or from pll2_pfd2_396m if it is disabled */ | |
344 | if ((sel[i][0] == 2 || sel[i][3] == 2) && | |
345 | (clk_get_parent(clk[IMX6QDL_CLK_PERIPH_PRE]) == | |
346 | clk[IMX6QDL_CLK_PLL2_PFD2_396M])) { | |
347 | pr_err("ccm: ldb_di%d_sel: couldn't disable pll2_pfd2_396m\n", | |
348 | i); | |
349 | sel[i][3] = sel[i][2] = sel[i][1] = sel[i][0]; | |
350 | continue; | |
351 | } | |
352 | ||
353 | /* First switch to the bottom mux */ | |
354 | sel[i][1] = sel[i][0] | 4; | |
355 | ||
356 | /* Then configure the top mux before switching back to it */ | |
357 | sel[i][2] = sel[i][3] | 4; | |
358 | ||
359 | pr_debug("ccm: switching ldb_di%d_sel: %d->%d->%d->%d\n", i, | |
360 | sel[i][0], sel[i][1], sel[i][2], sel[i][3]); | |
361 | } | |
362 | ||
363 | if (sel[0][0] == sel[0][3] && sel[1][0] == sel[1][3]) | |
364 | return; | |
365 | ||
366 | mmdc_ch1_disable(ccm_base); | |
367 | ||
368 | for (i = 1; i < 4; i++) { | |
369 | reg = readl_relaxed(ccm_base + CCM_CS2CDR); | |
370 | reg &= ~((7 << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) | | |
371 | (7 << CS2CDR_LDB_DI1_CLK_SEL_SHIFT)); | |
372 | reg |= ((sel[0][i] << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) | | |
373 | (sel[1][i] << CS2CDR_LDB_DI1_CLK_SEL_SHIFT)); | |
374 | writel_relaxed(reg, ccm_base + CCM_CS2CDR); | |
375 | } | |
376 | ||
377 | mmdc_ch1_reenable(ccm_base); | |
378 | } | |
379 | ||
380 | #define CCM_ANALOG_PLL_VIDEO 0xa0 | |
381 | #define CCM_ANALOG_PFD_480 0xf0 | |
382 | #define CCM_ANALOG_PFD_528 0x100 | |
383 | ||
384 | #define PLL_ENABLE BIT(13) | |
385 | ||
386 | #define PFD0_CLKGATE BIT(7) | |
387 | #define PFD1_CLKGATE BIT(15) | |
388 | #define PFD2_CLKGATE BIT(23) | |
389 | #define PFD3_CLKGATE BIT(31) | |
390 | ||
391 | static void disable_anatop_clocks(void __iomem *anatop_base) | |
392 | { | |
393 | unsigned int reg; | |
394 | ||
395 | /* Make sure PLL2 PFDs 0-2 are gated */ | |
396 | reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528); | |
397 | /* Cannot gate PFD2 if pll2_pfd2_396m is the parent of MMDC clock */ | |
398 | if (clk_get_parent(clk[IMX6QDL_CLK_PERIPH_PRE]) == | |
399 | clk[IMX6QDL_CLK_PLL2_PFD2_396M]) | |
400 | reg |= PFD0_CLKGATE | PFD1_CLKGATE; | |
401 | else | |
402 | reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE; | |
403 | writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528); | |
404 | ||
405 | /* Make sure PLL3 PFDs 0-3 are gated */ | |
406 | reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480); | |
407 | reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE; | |
408 | writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480); | |
409 | ||
410 | /* Make sure PLL5 is disabled */ | |
411 | reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO); | |
412 | reg &= ~PLL_ENABLE; | |
413 | writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO); | |
414 | } | |
415 | ||
53bb71da | 416 | static void __init imx6q_clocks_init(struct device_node *ccm_node) |
2acd1b6f SG |
417 | { |
418 | struct device_node *np; | |
5d283b08 | 419 | void __iomem *anatop_base, *base; |
876292d6 | 420 | int i; |
a94f8ecb | 421 | int ret; |
2acd1b6f | 422 | |
d2d2e54d SG |
423 | clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); |
424 | clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); | |
425 | clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0); | |
426 | clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); | |
b1f156db SG |
427 | /* Clock source from external clock via CLK1/2 PADs */ |
428 | clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); | |
429 | clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0); | |
2acd1b6f SG |
430 | |
431 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); | |
5d283b08 | 432 | anatop_base = base = of_iomap(np, 0); |
2acd1b6f SG |
433 | WARN_ON(!base); |
434 | ||
2df1d026 | 435 | /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ |
961dfd37 | 436 | if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { |
2df1d026 PZ |
437 | post_div_table[1].div = 1; |
438 | post_div_table[2].div = 1; | |
439 | video_div_table[1].div = 1; | |
81ef4479 | 440 | video_div_table[3].div = 1; |
d2a10a17 | 441 | } |
2df1d026 | 442 | |
b1f156db SG |
443 | clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
444 | clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
445 | clk[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
446 | clk[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
447 | clk[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
448 | clk[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
449 | clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
450 | ||
451 | /* type name parent_name base div_mask */ | |
f83d3163 DA |
452 | clk[IMX6QDL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f); |
453 | clk[IMX6QDL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1); | |
454 | clk[IMX6QDL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3); | |
455 | clk[IMX6QDL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f); | |
456 | clk[IMX6QDL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); | |
457 | clk[IMX6QDL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); | |
458 | clk[IMX6QDL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); | |
b1f156db SG |
459 | |
460 | clk[IMX6QDL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); | |
461 | clk[IMX6QDL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); | |
462 | clk[IMX6QDL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); | |
463 | clk[IMX6QDL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); | |
464 | clk[IMX6QDL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); | |
465 | clk[IMX6QDL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); | |
466 | clk[IMX6QDL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); | |
467 | ||
468 | /* Do not bypass PLLs initially */ | |
469 | clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]); | |
470 | clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]); | |
471 | clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]); | |
472 | clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]); | |
473 | clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]); | |
474 | clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]); | |
475 | clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]); | |
476 | ||
477 | clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); | |
478 | clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); | |
479 | clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); | |
480 | clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); | |
481 | clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); | |
482 | clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); | |
69d9a3fe | 483 | clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); |
2acd1b6f | 484 | |
a5120e89 PC |
485 | /* |
486 | * Bit 20 is the reserved and read-only bit, we do this only for: | |
487 | * - Do nothing for usbphy clk_enable/disable | |
488 | * - Keep refcount when do usbphy clk_enable/disable, in that case, | |
489 | * the clk framework may need to enable/disable usbphy's parent | |
490 | */ | |
d2d2e54d SG |
491 | clk[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); |
492 | clk[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); | |
a5120e89 PC |
493 | |
494 | /* | |
495 | * usbphy*_gate needs to be on after system boots up, and software | |
496 | * never needs to control it anymore. | |
497 | */ | |
d2d2e54d SG |
498 | clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); |
499 | clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); | |
7571d283 | 500 | |
d2d2e54d SG |
501 | clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); |
502 | clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); | |
7a04092c | 503 | |
d2d2e54d SG |
504 | clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); |
505 | clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); | |
7a04092c | 506 | |
d2d2e54d | 507 | clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, |
7a04092c SH |
508 | base + 0xe0, 0, 2, 0, clk_enet_ref_table, |
509 | &imx_ccm_lock); | |
510 | ||
d2d2e54d SG |
511 | clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); |
512 | clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); | |
bf221721 SC |
513 | |
514 | /* | |
515 | * lvds1_gate and lvds2_gate are pseudo-gates. Both can be | |
516 | * independently configured as clock inputs or outputs. We treat | |
517 | * the "output_enable" bit as a gate, even though it's really just | |
518 | * enabling clock output. | |
519 | */ | |
b1f156db SG |
520 | clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12)); |
521 | clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13)); | |
522 | ||
523 | clk[IMX6QDL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); | |
524 | clk[IMX6QDL_CLK_LVDS2_IN] = imx_clk_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11)); | |
d2d2e54d SG |
525 | |
526 | /* name parent_name reg idx */ | |
527 | clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); | |
528 | clk[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); | |
529 | clk[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); | |
530 | clk[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); | |
531 | clk[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); | |
532 | clk[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); | |
533 | clk[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); | |
534 | ||
535 | /* name parent_name mult div */ | |
536 | clk[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); | |
537 | clk[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); | |
538 | clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); | |
539 | clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); | |
540 | clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); | |
6f11c69d | 541 | clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); |
8f21d8d4 | 542 | clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20); |
ee360274 | 543 | if (clk_on_imx6dl() || clk_on_imx6qp()) { |
6248c273 AH |
544 | clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); |
545 | clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); | |
546 | } | |
d2d2e54d SG |
547 | |
548 | clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); | |
549 | clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); | |
550 | clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); | |
551 | clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); | |
2df1d026 | 552 | |
53bb71da | 553 | np = ccm_node; |
2acd1b6f SG |
554 | base = of_iomap(np, 0); |
555 | WARN_ON(!base); | |
9e8147bb | 556 | |
d2d2e54d SG |
557 | /* name reg shift width parent_names num_parents */ |
558 | clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); | |
559 | clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); | |
560 | clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); | |
561 | clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); | |
562 | clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); | |
563 | clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); | |
564 | clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); | |
565 | clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
566 | clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
567 | clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
961dfd37 | 568 | if (clk_on_imx6q()) { |
6248c273 AH |
569 | clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); |
570 | clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); | |
571 | } | |
ee360274 BP |
572 | if (clk_on_imx6qp()) { |
573 | clk[IMX6QDL_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); | |
574 | clk[IMX6QDL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); | |
575 | clk[IMX6QDL_CLK_IPG_PER_SEL] = imx_clk_mux("ipg_per_sel", base + 0x1c, 6, 1, ipg_per_sels, ARRAY_SIZE(ipg_per_sels)); | |
576 | clk[IMX6QDL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); | |
577 | clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels_2, ARRAY_SIZE(gpu2d_core_sels_2)); | |
b1d51b44 LS |
578 | } else if (clk_on_imx6dl()) { |
579 | clk[IMX6QDL_CLK_MLB_SEL] = imx_clk_mux("mlb_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); | |
ee360274 BP |
580 | } else { |
581 | clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); | |
582 | } | |
d2d2e54d | 583 | clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); |
b1d51b44 LS |
584 | if (clk_on_imx6dl()) |
585 | clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); | |
586 | else | |
587 | clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); | |
d2d2e54d SG |
588 | clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); |
589 | clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); | |
5d283b08 FE |
590 | |
591 | disable_anatop_clocks(anatop_base); | |
592 | ||
593 | imx6q_mmdc_ch1_mask_handshake(base); | |
594 | ||
f4a0a6c3 LS |
595 | if (clk_on_imx6qp()) { |
596 | clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); | |
597 | clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); | |
598 | } else { | |
599 | /* | |
600 | * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware | |
601 | * bug. Set the muxes to the requested values before registering the | |
602 | * ldb_di_sel clocks. | |
603 | */ | |
604 | init_ldb_clks(np, base); | |
605 | ||
606 | clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); | |
607 | clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); | |
608 | } | |
d2d2e54d SG |
609 | clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); |
610 | clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); | |
611 | clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); | |
612 | clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); | |
d2d2e54d SG |
613 | clk[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); |
614 | clk[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); | |
ee360274 BP |
615 | if (clk_on_imx6qp()) { |
616 | clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels_2, ARRAY_SIZE(ipu1_di0_sels_2), CLK_SET_RATE_PARENT); | |
617 | clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels_2, ARRAY_SIZE(ipu1_di1_sels_2), CLK_SET_RATE_PARENT); | |
618 | clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels_2, ARRAY_SIZE(ipu2_di0_sels_2), CLK_SET_RATE_PARENT); | |
619 | clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels_2, ARRAY_SIZE(ipu2_di1_sels_2), CLK_SET_RATE_PARENT); | |
620 | clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | |
621 | clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | |
622 | clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | |
623 | clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | |
624 | clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | |
625 | clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | |
626 | clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | |
627 | clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels_2, ARRAY_SIZE(enfc_sels_2)); | |
628 | clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels)); | |
629 | clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels)); | |
630 | clk[IMX6QDL_CLK_PRE_AXI] = imx_clk_mux("pre_axi", base + 0x18, 1, 1, pre_axi_sels, ARRAY_SIZE(pre_axi_sels)); | |
631 | } else { | |
632 | clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT); | |
633 | clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT); | |
634 | clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT); | |
635 | clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT); | |
636 | clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | |
637 | clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | |
638 | clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | |
639 | clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
640 | clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
641 | clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
642 | clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
643 | clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); | |
644 | clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup); | |
645 | clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup); | |
646 | } | |
d2d2e54d SG |
647 | clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); |
648 | clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); | |
649 | clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); | |
650 | clk[IMX6QDL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); | |
651 | clk[IMX6QDL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); | |
652 | ||
653 | /* name reg shift width busy: reg, shift parent_names num_parents */ | |
654 | clk[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); | |
655 | clk[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); | |
656 | ||
657 | /* name parent_name reg shift width */ | |
658 | clk[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); | |
659 | clk[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); | |
660 | clk[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); | |
d2d2e54d SG |
661 | clk[IMX6QDL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); |
662 | clk[IMX6QDL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); | |
663 | clk[IMX6QDL_CLK_ASRC_PRED] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); | |
664 | clk[IMX6QDL_CLK_ASRC_PODF] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); | |
665 | clk[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); | |
666 | clk[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); | |
ee360274 BP |
667 | if (clk_on_imx6qp()) { |
668 | clk[IMX6QDL_CLK_IPG_PER] = imx_clk_divider("ipg_per", "ipg_per_sel", base + 0x1c, 0, 6); | |
669 | clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6); | |
670 | clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "can_sel", base + 0x20, 2, 6); | |
671 | clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6); | |
672 | clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0", 2, 7); | |
673 | clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7); | |
674 | } else { | |
675 | clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); | |
7196c52c | 676 | clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); |
ee360274 BP |
677 | clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); |
678 | clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); | |
679 | clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); | |
680 | clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); | |
681 | } | |
b1d51b44 LS |
682 | if (clk_on_imx6dl()) |
683 | clk[IMX6QDL_CLK_MLB_PODF] = imx_clk_divider("mlb_podf", "mlb_sel", base + 0x18, 23, 3); | |
684 | else | |
685 | clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); | |
d2d2e54d | 686 | clk[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); |
b1d51b44 LS |
687 | if (clk_on_imx6dl()) |
688 | clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 29, 3); | |
689 | else | |
690 | clk[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); | |
d2d2e54d SG |
691 | clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); |
692 | clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); | |
d2d2e54d | 693 | clk[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); |
d2d2e54d SG |
694 | clk[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); |
695 | clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); | |
696 | clk[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); | |
697 | clk[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); | |
698 | clk[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); | |
699 | clk[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); | |
700 | clk[IMX6QDL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); | |
701 | clk[IMX6QDL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); | |
702 | clk[IMX6QDL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); | |
703 | clk[IMX6QDL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); | |
704 | clk[IMX6QDL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); | |
705 | clk[IMX6QDL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); | |
d2d2e54d SG |
706 | clk[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); |
707 | clk[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); | |
708 | clk[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); | |
709 | clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); | |
710 | clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); | |
711 | clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); | |
ee360274 BP |
712 | if (clk_on_imx6qp()) { |
713 | clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3); | |
714 | clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3); | |
715 | } else { | |
716 | clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); | |
717 | clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); | |
718 | } | |
d2d2e54d SG |
719 | clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); |
720 | clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); | |
721 | clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); | |
722 | ||
723 | /* name parent_name reg shift width busy: reg, shift */ | |
724 | clk[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); | |
725 | clk[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); | |
ee360274 BP |
726 | if (clk_on_imx6qp()) { |
727 | clk[IMX6QDL_CLK_MMDC_CH1_AXI_CG] = imx_clk_gate("mmdc_ch1_axi_cg", "periph2", base + 0x4, 18); | |
728 | clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "mmdc_ch1_axi_cg", base + 0x14, 3, 3, base + 0x48, 2); | |
729 | } else { | |
730 | clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); | |
731 | } | |
d2d2e54d SG |
732 | clk[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); |
733 | clk[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); | |
734 | ||
735 | /* name parent_name reg shift */ | |
736 | clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); | |
aec247d4 SW |
737 | clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc); |
738 | clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); | |
739 | clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); | |
dd503f66 VM |
740 | clk[IMX6QDL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); |
741 | clk[IMX6QDL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); | |
742 | clk[IMX6QDL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); | |
d2d2e54d SG |
743 | clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); |
744 | clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); | |
745 | clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); | |
746 | clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); | |
747 | clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); | |
748 | clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); | |
749 | clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); | |
750 | clk[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); | |
961dfd37 | 751 | if (clk_on_imx6dl()) |
d2d2e54d | 752 | clk[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8); |
ee3387f9 | 753 | else |
d2d2e54d SG |
754 | clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); |
755 | clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); | |
7bce3d23 | 756 | clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai); |
ade9233f | 757 | clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai); |
7bce3d23 | 758 | clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); |
d2d2e54d SG |
759 | clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); |
760 | clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); | |
b1d51b44 | 761 | clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); |
d2d2e54d SG |
762 | clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); |
763 | clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); | |
974a7115 | 764 | clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "video_27m", base + 0x70, 4); |
d2d2e54d SG |
765 | clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); |
766 | clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); | |
767 | clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); | |
768 | clk[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); | |
769 | clk[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); | |
770 | clk[IMX6QDL_CLK_VDOA] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26); | |
771 | clk[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); | |
772 | clk[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); | |
773 | clk[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); | |
774 | clk[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6); | |
775 | clk[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); | |
ee360274 BP |
776 | if (clk_on_imx6qp()) { |
777 | clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_sel", base + 0x74, 12); | |
778 | clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_sel", base + 0x74, 14); | |
779 | } else { | |
780 | clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); | |
781 | clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); | |
782 | } | |
d2d2e54d | 783 | clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); |
721fee59 | 784 | clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg); |
5ccc248c | 785 | clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg); |
e654df7a | 786 | clk[IMX6QDL_CLK_MIPI_IPG] = imx_clk_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg); |
961dfd37 | 787 | if (clk_on_imx6dl()) |
fbcb4412 DB |
788 | /* |
789 | * The multiplexer and divider of the imx6q clock gpu2d get | |
790 | * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl. | |
791 | */ | |
b1d51b44 | 792 | clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "mlb_podf", base + 0x74, 18); |
fbcb4412 | 793 | else |
d2d2e54d SG |
794 | clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); |
795 | clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); | |
796 | clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); | |
797 | clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); | |
798 | clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); | |
799 | clk[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); | |
800 | clk[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); | |
801 | clk[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); | |
802 | clk[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); | |
803 | clk[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); | |
804 | clk[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22); | |
805 | clk[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); | |
806 | clk[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); | |
807 | clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); | |
808 | clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); | |
809 | clk[IMX6QDL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); | |
da946aea | 810 | clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4); |
d2d2e54d SG |
811 | clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); |
812 | clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); | |
84a87250 SW |
813 | clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif); |
814 | clk[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); | |
bd404b1d SW |
815 | clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); |
816 | clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); | |
817 | clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); | |
818 | clk[IMX6QDL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); | |
819 | clk[IMX6QDL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); | |
820 | clk[IMX6QDL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); | |
d2d2e54d SG |
821 | clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); |
822 | clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); | |
823 | clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); | |
824 | clk[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); | |
825 | clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); | |
826 | clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); | |
827 | clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); | |
a1fc1980 | 828 | clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10); |
d2d2e54d SG |
829 | clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); |
830 | clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); | |
ee360274 BP |
831 | if (clk_on_imx6qp()) { |
832 | clk[IMX6QDL_CLK_PRE0] = imx_clk_gate2("pre0", "pre_axi", base + 0x80, 16); | |
833 | clk[IMX6QDL_CLK_PRE1] = imx_clk_gate2("pre1", "pre_axi", base + 0x80, 18); | |
834 | clk[IMX6QDL_CLK_PRE2] = imx_clk_gate2("pre2", "pre_axi", base + 0x80, 20); | |
835 | clk[IMX6QDL_CLK_PRE3] = imx_clk_gate2("pre3", "pre_axi", base + 0x80, 22); | |
836 | clk[IMX6QDL_CLK_PRG0_AXI] = imx_clk_gate2_shared("prg0_axi", "ipu1_podf", base + 0x80, 24, &share_count_prg0); | |
837 | clk[IMX6QDL_CLK_PRG1_AXI] = imx_clk_gate2_shared("prg1_axi", "ipu2_podf", base + 0x80, 26, &share_count_prg1); | |
838 | clk[IMX6QDL_CLK_PRG0_APB] = imx_clk_gate2_shared("prg0_apb", "ipg", base + 0x80, 24, &share_count_prg0); | |
839 | clk[IMX6QDL_CLK_PRG1_APB] = imx_clk_gate2_shared("prg1_apb", "ipg", base + 0x80, 26, &share_count_prg1); | |
840 | } | |
d2d2e54d SG |
841 | clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); |
842 | clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); | |
2acd1b6f | 843 | |
6f11c69d AH |
844 | /* |
845 | * The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it | |
846 | * to clock gpt_ipg_per to ease the gpt driver code. | |
847 | */ | |
961dfd37 | 848 | if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) |
6f11c69d AH |
849 | clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER]; |
850 | ||
229be9c1 | 851 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
2acd1b6f | 852 | |
0e87e043 SG |
853 | clk_data.clks = clk; |
854 | clk_data.clk_num = ARRAY_SIZE(clk); | |
855 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
856 | ||
d2d2e54d | 857 | clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); |
2acd1b6f | 858 | |
05e062f9 FE |
859 | clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000); |
860 | if (clk_on_imx6dl()) | |
861 | clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]); | |
862 | ||
d2d2e54d SG |
863 | clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); |
864 | clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); | |
865 | clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); | |
866 | clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); | |
867 | clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]); | |
868 | clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]); | |
869 | clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]); | |
870 | clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]); | |
17b9b3b9 | 871 | |
cc7887c3 HS |
872 | /* |
873 | * The gpmi needs 100MHz frequency in the EDO/Sync mode, | |
874 | * We can not get the 100MHz from the pll2_pfd0_352m. | |
875 | * So choose pll2_pfd2_396m as enfc_sel's parent. | |
876 | */ | |
d2d2e54d | 877 | clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); |
cc7887c3 | 878 | |
b0286f20 RZ |
879 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
880 | clk_prepare_enable(clk[clks_init_on[i]]); | |
2acd1b6f | 881 | |
a5120e89 | 882 | if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { |
d2d2e54d SG |
883 | clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]); |
884 | clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); | |
a5120e89 PC |
885 | } |
886 | ||
a94f8ecb SG |
887 | /* |
888 | * Let's initially set up CLKO with OSC24M, since this configuration | |
889 | * is widely used by imx6q board designs to clock audio codec. | |
890 | */ | |
d2d2e54d | 891 | ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]); |
a94f8ecb | 892 | if (!ret) |
d2d2e54d | 893 | ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]); |
a94f8ecb SG |
894 | if (ret) |
895 | pr_warn("failed to set up CLKO: %d\n", ret); | |
896 | ||
4390e622 | 897 | /* Audio-related clocks configuration */ |
d2d2e54d | 898 | clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]); |
4390e622 | 899 | |
74b80313 SC |
900 | /* All existing boards with PCIe use LVDS1 */ |
901 | if (IS_ENABLED(CONFIG_PCI_IMX6)) | |
d2d2e54d | 902 | clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]); |
0822f933 | 903 | |
d8846023 LS |
904 | /* |
905 | * Initialize the GPU clock muxes, so that the maximum specified clock | |
906 | * rates for the respective SoC are not exceeded. | |
907 | */ | |
908 | if (clk_on_imx6dl()) { | |
909 | clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], | |
910 | clk[IMX6QDL_CLK_PLL2_PFD1_594M]); | |
911 | clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], | |
912 | clk[IMX6QDL_CLK_PLL2_PFD1_594M]); | |
913 | } else if (clk_on_imx6q()) { | |
914 | clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], | |
915 | clk[IMX6QDL_CLK_MMDC_CH0_AXI]); | |
916 | clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], | |
917 | clk[IMX6QDL_CLK_PLL2_PFD1_594M]); | |
918 | clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], | |
919 | clk[IMX6QDL_CLK_PLL3_USB_OTG]); | |
920 | } | |
921 | ||
0822f933 | 922 | imx_register_uart_clocks(uart_clks); |
2acd1b6f | 923 | } |
53bb71da | 924 | CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); |