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fcaf2036 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2acd1b6f | 2 | /* |
e7b82d64 | 3 | * Copyright 2011-2013 Freescale Semiconductor, Inc. |
2acd1b6f | 4 | * Copyright 2011 Linaro Ltd. |
2acd1b6f SG |
5 | */ |
6 | ||
7 | #include <linux/init.h> | |
8 | #include <linux/types.h> | |
9 | #include <linux/clk.h> | |
10 | #include <linux/clkdev.h> | |
1df37992 | 11 | #include <linux/clk-provider.h> |
2acd1b6f SG |
12 | #include <linux/err.h> |
13 | #include <linux/io.h> | |
14 | #include <linux/of.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/of_irq.h> | |
0c831317 | 17 | #include <soc/imx/revision.h> |
d2d2e54d | 18 | #include <dt-bindings/clock/imx6qdl-clock.h> |
e3372474 | 19 | |
2acd1b6f SG |
20 | #include "clk.h" |
21 | ||
2acd1b6f SG |
22 | static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; |
23 | static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; | |
24 | static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; | |
72cd7447 PZ |
25 | static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", }; |
26 | static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; | |
2acd1b6f SG |
27 | static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; |
28 | static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; | |
a08b9bc5 | 29 | static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; |
64990a43 | 30 | static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; |
2acd1b6f | 31 | static const char *gpu_axi_sels[] = { "axi", "ahb", }; |
ee360274 | 32 | static const char *pre_axi_sels[] = { "axi", "ahb", }; |
2acd1b6f | 33 | static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; |
ee360274 | 34 | static const char *gpu2d_core_sels_2[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m",}; |
2acd1b6f | 35 | static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; |
de78a23d | 36 | static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; |
2acd1b6f | 37 | static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; |
cc9a3e99 | 38 | static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; |
2df1d026 | 39 | static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; |
2acd1b6f SG |
40 | static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; |
41 | static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; | |
42 | static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; | |
43 | static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; | |
ee360274 BP |
44 | static const char *ipu1_di0_sels_2[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; |
45 | static const char *ipu1_di1_sels_2[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; | |
46 | static const char *ipu2_di0_sels_2[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; | |
47 | static const char *ipu2_di1_sels_2[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", }; | |
2acd1b6f SG |
48 | static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; |
49 | static const char *pcie_axi_sels[] = { "axi", "ahb", }; | |
64990a43 | 50 | static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; |
2acd1b6f SG |
51 | static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; |
52 | static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; | |
ee360274 | 53 | static const char *enfc_sels_2[] = {"pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", }; |
a1fc1980 SL |
54 | static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; |
55 | static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", }; | |
2acd1b6f SG |
56 | static const char *vdo_axi_sels[] = { "axi", "ahb", }; |
57 | static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; | |
ee360274 BP |
58 | static const char *uart_sels[] = { "pll3_80m", "osc", }; |
59 | static const char *ipg_per_sels[] = { "ipg", "osc", }; | |
60 | static const char *ecspi_sels[] = { "pll3_60m", "osc", }; | |
61 | static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", }; | |
2df1d026 | 62 | static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", |
a7047564 | 63 | "video_27m", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", |
64990a43 | 64 | "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", }; |
6526bb3c SG |
65 | static const char *cko2_sels[] = { |
66 | "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1", | |
67 | "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi", | |
68 | "usdhc3", "dummy", "arm", "ipu1", | |
69 | "ipu2", "vdo_axi", "osc", "gpu2d_core", | |
70 | "gpu3d_core", "usdhc2", "ssi1", "ssi2", | |
71 | "ssi3", "gpu3d_shader", "vpu_axi", "can_root", | |
7bce3d23 | 72 | "ldb_di0", "ldb_di1", "esai_extal", "eim_slow", |
6526bb3c SG |
73 | "uart_serial", "spdif", "asrc", "hsi_tx", |
74 | }; | |
6cd62235 | 75 | static const char *cko_sels[] = { "cko1", "cko2", }; |
bf221721 SC |
76 | static const char *lvds_sels[] = { |
77 | "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", | |
78 | "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", | |
2e133f61 MT |
79 | "pcie_ref_125m", "sata_ref_100m", "usbphy1", "usbphy2", |
80 | "dummy", "dummy", "dummy", "dummy", "osc", | |
bf221721 | 81 | }; |
b1f156db SG |
82 | static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", }; |
83 | static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; | |
84 | static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", }; | |
85 | static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", }; | |
86 | static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", }; | |
87 | static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", }; | |
88 | static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", }; | |
89 | static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; | |
2acd1b6f | 90 | |
992b703b AV |
91 | static struct clk_hw **hws; |
92 | static struct clk_hw_onecell_data *clk_hw_data; | |
2acd1b6f | 93 | |
7a04092c SH |
94 | static struct clk_div_table clk_enet_ref_table[] = { |
95 | { .val = 0, .div = 20, }, | |
96 | { .val = 1, .div = 10, }, | |
97 | { .val = 2, .div = 5, }, | |
98 | { .val = 3, .div = 4, }, | |
ec9de6cd | 99 | { /* sentinel */ } |
7a04092c SH |
100 | }; |
101 | ||
2df1d026 PZ |
102 | static struct clk_div_table post_div_table[] = { |
103 | { .val = 2, .div = 1, }, | |
104 | { .val = 1, .div = 2, }, | |
105 | { .val = 0, .div = 4, }, | |
ec9de6cd | 106 | { /* sentinel */ } |
2df1d026 PZ |
107 | }; |
108 | ||
109 | static struct clk_div_table video_div_table[] = { | |
110 | { .val = 0, .div = 1, }, | |
111 | { .val = 1, .div = 2, }, | |
112 | { .val = 2, .div = 1, }, | |
113 | { .val = 3, .div = 4, }, | |
ec9de6cd | 114 | { /* sentinel */ } |
2df1d026 PZ |
115 | }; |
116 | ||
886cda41 | 117 | static unsigned int share_count_esai; |
aec247d4 | 118 | static unsigned int share_count_asrc; |
bd404b1d SW |
119 | static unsigned int share_count_ssi1; |
120 | static unsigned int share_count_ssi2; | |
121 | static unsigned int share_count_ssi3; | |
721fee59 | 122 | static unsigned int share_count_mipi_core_cfg; |
84a87250 | 123 | static unsigned int share_count_spdif; |
ee360274 BP |
124 | static unsigned int share_count_prg0; |
125 | static unsigned int share_count_prg1; | |
886cda41 | 126 | |
961dfd37 SG |
127 | static inline int clk_on_imx6q(void) |
128 | { | |
129 | return of_machine_is_compatible("fsl,imx6q"); | |
130 | } | |
131 | ||
ee360274 BP |
132 | static inline int clk_on_imx6qp(void) |
133 | { | |
134 | return of_machine_is_compatible("fsl,imx6qp"); | |
135 | } | |
136 | ||
961dfd37 SG |
137 | static inline int clk_on_imx6dl(void) |
138 | { | |
139 | return of_machine_is_compatible("fsl,imx6dl"); | |
140 | } | |
141 | ||
992b703b AV |
142 | static const int uart_clk_ids[] __initconst = { |
143 | IMX6QDL_CLK_UART_IPG, | |
144 | IMX6QDL_CLK_UART_SERIAL, | |
0822f933 LS |
145 | }; |
146 | ||
992b703b AV |
147 | static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata; |
148 | ||
5d283b08 FE |
149 | static int ldb_di_sel_by_clock_id(int clock_id) |
150 | { | |
151 | switch (clock_id) { | |
152 | case IMX6QDL_CLK_PLL5_VIDEO_DIV: | |
153 | if (clk_on_imx6q() && | |
154 | imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) | |
155 | return -ENOENT; | |
156 | return 0; | |
157 | case IMX6QDL_CLK_PLL2_PFD0_352M: | |
158 | return 1; | |
159 | case IMX6QDL_CLK_PLL2_PFD2_396M: | |
160 | return 2; | |
161 | case IMX6QDL_CLK_MMDC_CH1_AXI: | |
162 | return 3; | |
163 | case IMX6QDL_CLK_PLL3_USB_OTG: | |
164 | return 4; | |
165 | default: | |
166 | return -ENOENT; | |
167 | } | |
168 | } | |
169 | ||
170 | static void of_assigned_ldb_sels(struct device_node *node, | |
171 | unsigned int *ldb_di0_sel, | |
172 | unsigned int *ldb_di1_sel) | |
173 | { | |
174 | struct of_phandle_args clkspec; | |
175 | int index, rc, num_parents; | |
176 | int parent, child, sel; | |
177 | ||
178 | num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", | |
179 | "#clock-cells"); | |
180 | for (index = 0; index < num_parents; index++) { | |
181 | rc = of_parse_phandle_with_args(node, "assigned-clock-parents", | |
182 | "#clock-cells", index, &clkspec); | |
183 | if (rc < 0) { | |
184 | /* skip empty (null) phandles */ | |
185 | if (rc == -ENOENT) | |
186 | continue; | |
187 | else | |
188 | return; | |
189 | } | |
190 | if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) { | |
191 | pr_err("ccm: parent clock %d not in ccm\n", index); | |
192 | return; | |
193 | } | |
194 | parent = clkspec.args[0]; | |
195 | ||
196 | rc = of_parse_phandle_with_args(node, "assigned-clocks", | |
197 | "#clock-cells", index, &clkspec); | |
198 | if (rc < 0) | |
199 | return; | |
200 | if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) { | |
201 | pr_err("ccm: child clock %d not in ccm\n", index); | |
202 | return; | |
203 | } | |
204 | child = clkspec.args[0]; | |
205 | ||
206 | if (child != IMX6QDL_CLK_LDB_DI0_SEL && | |
207 | child != IMX6QDL_CLK_LDB_DI1_SEL) | |
208 | continue; | |
209 | ||
210 | sel = ldb_di_sel_by_clock_id(parent); | |
211 | if (sel < 0) { | |
212 | pr_err("ccm: invalid ldb_di%d parent clock: %d\n", | |
213 | child == IMX6QDL_CLK_LDB_DI1_SEL, parent); | |
214 | continue; | |
215 | } | |
216 | ||
217 | if (child == IMX6QDL_CLK_LDB_DI0_SEL) | |
218 | *ldb_di0_sel = sel; | |
219 | if (child == IMX6QDL_CLK_LDB_DI1_SEL) | |
220 | *ldb_di1_sel = sel; | |
221 | } | |
222 | } | |
223 | ||
3cc48976 LS |
224 | static bool pll6_bypassed(struct device_node *node) |
225 | { | |
226 | int index, ret, num_clocks; | |
227 | struct of_phandle_args clkspec; | |
228 | ||
229 | num_clocks = of_count_phandle_with_args(node, "assigned-clocks", | |
230 | "#clock-cells"); | |
231 | if (num_clocks < 0) | |
232 | return false; | |
233 | ||
234 | for (index = 0; index < num_clocks; index++) { | |
235 | ret = of_parse_phandle_with_args(node, "assigned-clocks", | |
236 | "#clock-cells", index, | |
237 | &clkspec); | |
238 | if (ret < 0) | |
239 | return false; | |
240 | ||
241 | if (clkspec.np == node && | |
242 | clkspec.args[0] == IMX6QDL_PLL6_BYPASS) | |
243 | break; | |
244 | } | |
245 | ||
246 | /* PLL6 bypass is not part of the assigned clock list */ | |
247 | if (index == num_clocks) | |
248 | return false; | |
249 | ||
250 | ret = of_parse_phandle_with_args(node, "assigned-clock-parents", | |
251 | "#clock-cells", index, &clkspec); | |
252 | ||
253 | if (clkspec.args[0] != IMX6QDL_CLK_PLL6) | |
254 | return true; | |
255 | ||
256 | return false; | |
257 | } | |
258 | ||
5d283b08 FE |
259 | #define CCM_CCSR 0x0c |
260 | #define CCM_CS2CDR 0x2c | |
261 | ||
5d283b08 | 262 | #define CCSR_PLL3_SW_CLK_SEL BIT(0) |
f13abeff | 263 | |
5d283b08 FE |
264 | #define CS2CDR_LDB_DI0_CLK_SEL_SHIFT 9 |
265 | #define CS2CDR_LDB_DI1_CLK_SEL_SHIFT 12 | |
f13abeff | 266 | |
5d283b08 FE |
267 | /* |
268 | * The only way to disable the MMDC_CH1 clock is to move it to pll3_sw_clk | |
269 | * via periph2_clk2_sel and then to disable pll3_sw_clk by selecting the | |
270 | * bypass clock source, since there is no CG bit for mmdc_ch1. | |
271 | */ | |
272 | static void mmdc_ch1_disable(void __iomem *ccm_base) | |
273 | { | |
274 | unsigned int reg; | |
275 | ||
992b703b AV |
276 | clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk, |
277 | hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); | |
5d283b08 FE |
278 | |
279 | /* Disable pll3_sw_clk by selecting the bypass clock source */ | |
280 | reg = readl_relaxed(ccm_base + CCM_CCSR); | |
281 | reg |= CCSR_PLL3_SW_CLK_SEL; | |
282 | writel_relaxed(reg, ccm_base + CCM_CCSR); | |
283 | } | |
284 | ||
285 | static void mmdc_ch1_reenable(void __iomem *ccm_base) | |
286 | { | |
287 | unsigned int reg; | |
288 | ||
289 | /* Enable pll3_sw_clk by disabling the bypass */ | |
290 | reg = readl_relaxed(ccm_base + CCM_CCSR); | |
291 | reg &= ~CCSR_PLL3_SW_CLK_SEL; | |
292 | writel_relaxed(reg, ccm_base + CCM_CCSR); | |
5d283b08 FE |
293 | } |
294 | ||
295 | /* | |
296 | * We have to follow a strict procedure when changing the LDB clock source, | |
297 | * otherwise we risk introducing a glitch that can lock up the LDB divider. | |
298 | * Things to keep in mind: | |
299 | * | |
300 | * 1. The current and new parent clock inputs to the mux must be disabled. | |
301 | * 2. The default clock input for ldb_di0/1_clk_sel is mmdc_ch1_axi, which | |
302 | * has no CG bit. | |
303 | * 3. pll2_pfd2_396m can not be gated if it is used as memory clock. | |
304 | * 4. In the RTL implementation of the LDB_DI_CLK_SEL muxes the top four | |
305 | * options are in one mux and the PLL3 option along with three unused | |
306 | * inputs is in a second mux. There is a third mux with two inputs used | |
307 | * to decide between the first and second 4-port mux: | |
308 | * | |
309 | * pll5_video_div 0 --|\ | |
310 | * pll2_pfd0_352m 1 --| |_ | |
311 | * pll2_pfd2_396m 2 --| | `-|\ | |
312 | * mmdc_ch1_axi 3 --|/ | | | |
313 | * | |-- | |
314 | * pll3_usb_otg 4 --|\ | | | |
315 | * 5 --| |_,-|/ | |
316 | * 6 --| | | |
317 | * 7 --|/ | |
318 | * | |
319 | * The ldb_di0/1_clk_sel[1:0] bits control both 4-port muxes at the same time. | |
320 | * The ldb_di0/1_clk_sel[2] bit controls the 2-port mux. The code below | |
321 | * switches the parent to the bottom mux first and then manipulates the top | |
322 | * mux to ensure that no glitch will enter the divider. | |
323 | */ | |
324 | static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base) | |
325 | { | |
326 | unsigned int reg; | |
327 | unsigned int sel[2][4]; | |
328 | int i; | |
329 | ||
330 | reg = readl_relaxed(ccm_base + CCM_CS2CDR); | |
331 | sel[0][0] = (reg >> CS2CDR_LDB_DI0_CLK_SEL_SHIFT) & 7; | |
332 | sel[1][0] = (reg >> CS2CDR_LDB_DI1_CLK_SEL_SHIFT) & 7; | |
333 | ||
334 | sel[0][3] = sel[0][2] = sel[0][1] = sel[0][0]; | |
335 | sel[1][3] = sel[1][2] = sel[1][1] = sel[1][0]; | |
336 | ||
337 | of_assigned_ldb_sels(np, &sel[0][3], &sel[1][3]); | |
338 | ||
339 | for (i = 0; i < 2; i++) { | |
340 | /* Warn if a glitch might have been introduced already */ | |
341 | if (sel[i][0] != 3) { | |
342 | pr_warn("ccm: ldb_di%d_sel already changed from reset value: %d\n", | |
343 | i, sel[i][0]); | |
344 | } | |
345 | ||
346 | if (sel[i][0] == sel[i][3]) | |
347 | continue; | |
348 | ||
349 | /* Only switch to or from pll2_pfd2_396m if it is disabled */ | |
350 | if ((sel[i][0] == 2 || sel[i][3] == 2) && | |
992b703b AV |
351 | (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == |
352 | hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)) { | |
5d283b08 FE |
353 | pr_err("ccm: ldb_di%d_sel: couldn't disable pll2_pfd2_396m\n", |
354 | i); | |
355 | sel[i][3] = sel[i][2] = sel[i][1] = sel[i][0]; | |
356 | continue; | |
357 | } | |
358 | ||
359 | /* First switch to the bottom mux */ | |
360 | sel[i][1] = sel[i][0] | 4; | |
361 | ||
362 | /* Then configure the top mux before switching back to it */ | |
363 | sel[i][2] = sel[i][3] | 4; | |
364 | ||
365 | pr_debug("ccm: switching ldb_di%d_sel: %d->%d->%d->%d\n", i, | |
366 | sel[i][0], sel[i][1], sel[i][2], sel[i][3]); | |
367 | } | |
368 | ||
369 | if (sel[0][0] == sel[0][3] && sel[1][0] == sel[1][3]) | |
370 | return; | |
371 | ||
372 | mmdc_ch1_disable(ccm_base); | |
373 | ||
374 | for (i = 1; i < 4; i++) { | |
375 | reg = readl_relaxed(ccm_base + CCM_CS2CDR); | |
376 | reg &= ~((7 << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) | | |
377 | (7 << CS2CDR_LDB_DI1_CLK_SEL_SHIFT)); | |
378 | reg |= ((sel[0][i] << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) | | |
379 | (sel[1][i] << CS2CDR_LDB_DI1_CLK_SEL_SHIFT)); | |
380 | writel_relaxed(reg, ccm_base + CCM_CS2CDR); | |
381 | } | |
382 | ||
383 | mmdc_ch1_reenable(ccm_base); | |
384 | } | |
385 | ||
386 | #define CCM_ANALOG_PLL_VIDEO 0xa0 | |
387 | #define CCM_ANALOG_PFD_480 0xf0 | |
388 | #define CCM_ANALOG_PFD_528 0x100 | |
389 | ||
390 | #define PLL_ENABLE BIT(13) | |
391 | ||
392 | #define PFD0_CLKGATE BIT(7) | |
393 | #define PFD1_CLKGATE BIT(15) | |
394 | #define PFD2_CLKGATE BIT(23) | |
395 | #define PFD3_CLKGATE BIT(31) | |
396 | ||
397 | static void disable_anatop_clocks(void __iomem *anatop_base) | |
398 | { | |
399 | unsigned int reg; | |
400 | ||
401 | /* Make sure PLL2 PFDs 0-2 are gated */ | |
402 | reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528); | |
403 | /* Cannot gate PFD2 if pll2_pfd2_396m is the parent of MMDC clock */ | |
992b703b AV |
404 | if (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == |
405 | hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk) | |
5d283b08 FE |
406 | reg |= PFD0_CLKGATE | PFD1_CLKGATE; |
407 | else | |
408 | reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE; | |
409 | writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528); | |
410 | ||
411 | /* Make sure PLL3 PFDs 0-3 are gated */ | |
412 | reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480); | |
413 | reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE; | |
414 | writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480); | |
415 | ||
416 | /* Make sure PLL5 is disabled */ | |
417 | reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO); | |
418 | reg &= ~PLL_ENABLE; | |
419 | writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO); | |
420 | } | |
421 | ||
0e12248c AB |
422 | static struct clk_hw * __init imx6q_obtain_fixed_clk_hw(struct device_node *np, |
423 | const char *name, | |
424 | unsigned long rate) | |
992b703b AV |
425 | { |
426 | struct clk *clk = of_clk_get_by_name(np, name); | |
427 | struct clk_hw *hw; | |
428 | ||
429 | if (IS_ERR(clk)) | |
430 | hw = imx_obtain_fixed_clock_hw(name, rate); | |
431 | else | |
432 | hw = __clk_get_hw(clk); | |
433 | ||
434 | return hw; | |
435 | } | |
436 | ||
53bb71da | 437 | static void __init imx6q_clocks_init(struct device_node *ccm_node) |
2acd1b6f SG |
438 | { |
439 | struct device_node *np; | |
5d283b08 | 440 | void __iomem *anatop_base, *base; |
a94f8ecb | 441 | int ret; |
992b703b AV |
442 | int i; |
443 | ||
444 | clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, | |
445 | IMX6QDL_CLK_END), GFP_KERNEL); | |
446 | if (WARN_ON(!clk_hw_data)) | |
447 | return; | |
2acd1b6f | 448 | |
992b703b AV |
449 | clk_hw_data->num = IMX6QDL_CLK_END; |
450 | hws = clk_hw_data->hws; | |
a29be918 | 451 | |
992b703b | 452 | hws[IMX6QDL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); |
a29be918 | 453 | |
992b703b AV |
454 | hws[IMX6QDL_CLK_CKIL] = imx6q_obtain_fixed_clk_hw(ccm_node, "ckil", 0); |
455 | hws[IMX6QDL_CLK_CKIH] = imx6q_obtain_fixed_clk_hw(ccm_node, "ckih1", 0); | |
456 | hws[IMX6QDL_CLK_OSC] = imx6q_obtain_fixed_clk_hw(ccm_node, "osc", 0); | |
457 | ||
458 | /* Clock source from external clock via CLK1/2 PADs */ | |
459 | hws[IMX6QDL_CLK_ANACLK1] = imx6q_obtain_fixed_clk_hw(ccm_node, "anaclk1", 0); | |
460 | hws[IMX6QDL_CLK_ANACLK2] = imx6q_obtain_fixed_clk_hw(ccm_node, "anaclk2", 0); | |
2acd1b6f SG |
461 | |
462 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); | |
5d283b08 | 463 | anatop_base = base = of_iomap(np, 0); |
2acd1b6f | 464 | WARN_ON(!base); |
c9ec1d8f | 465 | of_node_put(np); |
2acd1b6f | 466 | |
2df1d026 | 467 | /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ |
961dfd37 | 468 | if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { |
2df1d026 PZ |
469 | post_div_table[1].div = 1; |
470 | post_div_table[2].div = 1; | |
471 | video_div_table[1].div = 1; | |
81ef4479 | 472 | video_div_table[3].div = 1; |
d2a10a17 | 473 | } |
2df1d026 | 474 | |
992b703b AV |
475 | hws[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); |
476 | hws[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
477 | hws[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
478 | hws[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
479 | hws[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
480 | hws[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
481 | hws[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); | |
b1f156db SG |
482 | |
483 | /* type name parent_name base div_mask */ | |
992b703b AV |
484 | hws[IMX6QDL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f); |
485 | hws[IMX6QDL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1); | |
486 | hws[IMX6QDL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3); | |
487 | hws[IMX6QDL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f); | |
488 | hws[IMX6QDL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); | |
489 | hws[IMX6QDL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); | |
490 | hws[IMX6QDL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); | |
491 | ||
492 | hws[IMX6QDL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); | |
493 | hws[IMX6QDL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); | |
494 | hws[IMX6QDL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); | |
495 | hws[IMX6QDL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); | |
496 | hws[IMX6QDL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); | |
497 | hws[IMX6QDL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); | |
498 | hws[IMX6QDL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); | |
b1f156db SG |
499 | |
500 | /* Do not bypass PLLs initially */ | |
992b703b AV |
501 | clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk); |
502 | clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk); | |
503 | clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk); | |
504 | clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk); | |
505 | clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk); | |
506 | clk_set_parent(hws[IMX6QDL_PLL6_BYPASS]->clk, hws[IMX6QDL_CLK_PLL6]->clk); | |
507 | clk_set_parent(hws[IMX6QDL_PLL7_BYPASS]->clk, hws[IMX6QDL_CLK_PLL7]->clk); | |
508 | ||
509 | hws[IMX6QDL_CLK_PLL1_SYS] = imx_clk_hw_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); | |
510 | hws[IMX6QDL_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); | |
511 | hws[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); | |
512 | hws[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); | |
513 | hws[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); | |
514 | hws[IMX6QDL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); | |
515 | hws[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); | |
2acd1b6f | 516 | |
a5120e89 PC |
517 | /* |
518 | * Bit 20 is the reserved and read-only bit, we do this only for: | |
519 | * - Do nothing for usbphy clk_enable/disable | |
520 | * - Keep refcount when do usbphy clk_enable/disable, in that case, | |
521 | * the clk framework may need to enable/disable usbphy's parent | |
522 | */ | |
992b703b AV |
523 | hws[IMX6QDL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); |
524 | hws[IMX6QDL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); | |
a5120e89 PC |
525 | |
526 | /* | |
527 | * usbphy*_gate needs to be on after system boots up, and software | |
528 | * never needs to control it anymore. | |
529 | */ | |
992b703b AV |
530 | hws[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate", "dummy", base + 0x10, 6); |
531 | hws[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate", "dummy", base + 0x20, 6); | |
7571d283 | 532 | |
3cc48976 LS |
533 | /* |
534 | * The ENET PLL is special in that is has multiple outputs with | |
535 | * different post-dividers that are all affected by the single bypass | |
536 | * bit, so a single mux bit affects 3 independent branches of the clock | |
537 | * tree. There is no good way to model this in the clock framework and | |
538 | * dynamically changing the bypass bit, will yield unexpected results. | |
539 | * So we treat any configuration that bypasses the ENET PLL as | |
540 | * essentially static with the divider ratios reflecting the bypass | |
541 | * status. | |
542 | * | |
543 | */ | |
544 | if (!pll6_bypassed(ccm_node)) { | |
992b703b AV |
545 | hws[IMX6QDL_CLK_SATA_REF] = imx_clk_hw_fixed_factor("sata_ref", "pll6_enet", 1, 5); |
546 | hws[IMX6QDL_CLK_PCIE_REF] = imx_clk_hw_fixed_factor("pcie_ref", "pll6_enet", 1, 4); | |
547 | hws[IMX6QDL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, | |
3cc48976 LS |
548 | base + 0xe0, 0, 2, 0, clk_enet_ref_table, |
549 | &imx_ccm_lock); | |
550 | } else { | |
992b703b AV |
551 | hws[IMX6QDL_CLK_SATA_REF] = imx_clk_hw_fixed_factor("sata_ref", "pll6_enet", 1, 1); |
552 | hws[IMX6QDL_CLK_PCIE_REF] = imx_clk_hw_fixed_factor("pcie_ref", "pll6_enet", 1, 1); | |
553 | hws[IMX6QDL_CLK_ENET_REF] = imx_clk_hw_fixed_factor("enet_ref", "pll6_enet", 1, 1); | |
3cc48976 | 554 | } |
7a04092c | 555 | |
992b703b AV |
556 | hws[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_hw_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); |
557 | hws[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_hw_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); | |
7a04092c | 558 | |
992b703b AV |
559 | hws[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_hw_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); |
560 | hws[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_hw_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); | |
bf221721 SC |
561 | |
562 | /* | |
563 | * lvds1_gate and lvds2_gate are pseudo-gates. Both can be | |
564 | * independently configured as clock inputs or outputs. We treat | |
565 | * the "output_enable" bit as a gate, even though it's really just | |
f7542d81 LS |
566 | * enabling clock output. Initially the gate bits are cleared, as |
567 | * otherwise the exclusive configuration gets locked in the setup done | |
568 | * by software running before the clock driver, with no way to change | |
569 | * it. | |
bf221721 | 570 | */ |
f7542d81 | 571 | writel(readl(base + 0x160) & ~0x3c00, base + 0x160); |
992b703b AV |
572 | hws[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_hw_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12)); |
573 | hws[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_hw_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13)); | |
b1f156db | 574 | |
992b703b AV |
575 | hws[IMX6QDL_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); |
576 | hws[IMX6QDL_CLK_LVDS2_IN] = imx_clk_hw_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11)); | |
d2d2e54d SG |
577 | |
578 | /* name parent_name reg idx */ | |
992b703b AV |
579 | hws[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); |
580 | hws[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); | |
581 | hws[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); | |
582 | hws[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_hw_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); | |
583 | hws[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_hw_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); | |
584 | hws[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); | |
585 | hws[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); | |
d2d2e54d SG |
586 | |
587 | /* name parent_name mult div */ | |
992b703b AV |
588 | hws[IMX6QDL_CLK_PLL2_198M] = imx_clk_hw_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); |
589 | hws[IMX6QDL_CLK_PLL3_120M] = imx_clk_hw_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); | |
590 | hws[IMX6QDL_CLK_PLL3_80M] = imx_clk_hw_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); | |
591 | hws[IMX6QDL_CLK_PLL3_60M] = imx_clk_hw_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); | |
592 | hws[IMX6QDL_CLK_TWD] = imx_clk_hw_fixed_factor("twd", "arm", 1, 2); | |
593 | hws[IMX6QDL_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc", 1, 8); | |
594 | hws[IMX6QDL_CLK_VIDEO_27M] = imx_clk_hw_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20); | |
ee360274 | 595 | if (clk_on_imx6dl() || clk_on_imx6qp()) { |
992b703b AV |
596 | hws[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_hw_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); |
597 | hws[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_hw_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); | |
6248c273 | 598 | } |
d2d2e54d | 599 | |
992b703b AV |
600 | hws[IMX6QDL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); |
601 | hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); | |
602 | hws[IMX6QDL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); | |
603 | hws[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); | |
2df1d026 | 604 | |
53bb71da | 605 | np = ccm_node; |
2acd1b6f SG |
606 | base = of_iomap(np, 0); |
607 | WARN_ON(!base); | |
9e8147bb | 608 | |
d2d2e54d | 609 | /* name reg shift width parent_names num_parents */ |
992b703b AV |
610 | hws[IMX6QDL_CLK_STEP] = imx_clk_hw_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); |
611 | hws[IMX6QDL_CLK_PLL1_SW] = imx_clk_hw_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); | |
612 | hws[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_hw_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); | |
613 | hws[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_hw_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); | |
614 | hws[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); | |
615 | hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); | |
616 | hws[IMX6QDL_CLK_AXI_SEL] = imx_clk_hw_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); | |
617 | hws[IMX6QDL_CLK_ESAI_SEL] = imx_clk_hw_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
618 | hws[IMX6QDL_CLK_ASRC_SEL] = imx_clk_hw_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
619 | hws[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); | |
961dfd37 | 620 | if (clk_on_imx6q()) { |
992b703b AV |
621 | hws[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_hw_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); |
622 | hws[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_hw_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); | |
6248c273 | 623 | } |
ee360274 | 624 | if (clk_on_imx6qp()) { |
992b703b AV |
625 | hws[IMX6QDL_CLK_CAN_SEL] = imx_clk_hw_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); |
626 | hws[IMX6QDL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); | |
627 | hws[IMX6QDL_CLK_IPG_PER_SEL] = imx_clk_hw_mux("ipg_per_sel", base + 0x1c, 6, 1, ipg_per_sels, ARRAY_SIZE(ipg_per_sels)); | |
628 | hws[IMX6QDL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); | |
629 | hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels_2, ARRAY_SIZE(gpu2d_core_sels_2)); | |
b1d51b44 | 630 | } else if (clk_on_imx6dl()) { |
992b703b | 631 | hws[IMX6QDL_CLK_MLB_SEL] = imx_clk_hw_mux("mlb_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); |
ee360274 | 632 | } else { |
992b703b | 633 | hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); |
ee360274 | 634 | } |
992b703b | 635 | hws[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_hw_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); |
b1d51b44 | 636 | if (clk_on_imx6dl()) |
992b703b | 637 | hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); |
b1d51b44 | 638 | else |
992b703b AV |
639 | hws[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_hw_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); |
640 | hws[IMX6QDL_CLK_IPU1_SEL] = imx_clk_hw_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); | |
641 | hws[IMX6QDL_CLK_IPU2_SEL] = imx_clk_hw_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); | |
5d283b08 FE |
642 | |
643 | disable_anatop_clocks(anatop_base); | |
644 | ||
c129b6fe | 645 | imx_mmdc_mask_handshake(base, 1); |
5d283b08 | 646 | |
f4a0a6c3 | 647 | if (clk_on_imx6qp()) { |
992b703b AV |
648 | hws[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_hw_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); |
649 | hws[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); | |
f4a0a6c3 LS |
650 | } else { |
651 | /* | |
652 | * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware | |
653 | * bug. Set the muxes to the requested values before registering the | |
654 | * ldb_di_sel clocks. | |
655 | */ | |
656 | init_ldb_clks(np, base); | |
657 | ||
992b703b AV |
658 | hws[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_hw_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); |
659 | hws[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels)); | |
f4a0a6c3 | 660 | } |
992b703b AV |
661 | |
662 | hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); | |
663 | hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); | |
664 | hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); | |
665 | hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); | |
666 | hws[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_hw_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); | |
667 | hws[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_hw_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); | |
668 | ||
ee360274 | 669 | if (clk_on_imx6qp()) { |
992b703b AV |
670 | hws[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_hw_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels_2, ARRAY_SIZE(ipu1_di0_sels_2), CLK_SET_RATE_PARENT); |
671 | hws[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_hw_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels_2, ARRAY_SIZE(ipu1_di1_sels_2), CLK_SET_RATE_PARENT); | |
672 | hws[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_hw_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels_2, ARRAY_SIZE(ipu2_di0_sels_2), CLK_SET_RATE_PARENT); | |
673 | hws[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_hw_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels_2, ARRAY_SIZE(ipu2_di1_sels_2), CLK_SET_RATE_PARENT); | |
674 | hws[IMX6QDL_CLK_SSI1_SEL] = imx_clk_hw_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | |
675 | hws[IMX6QDL_CLK_SSI2_SEL] = imx_clk_hw_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | |
676 | hws[IMX6QDL_CLK_SSI3_SEL] = imx_clk_hw_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); | |
677 | hws[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | |
678 | hws[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | |
679 | hws[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_hw_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | |
680 | hws[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_hw_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); | |
681 | hws[IMX6QDL_CLK_ENFC_SEL] = imx_clk_hw_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels_2, ARRAY_SIZE(enfc_sels_2)); | |
682 | hws[IMX6QDL_CLK_EIM_SEL] = imx_clk_hw_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels)); | |
683 | hws[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_hw_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels)); | |
684 | hws[IMX6QDL_CLK_PRE_AXI] = imx_clk_hw_mux("pre_axi", base + 0x18, 1, 1, pre_axi_sels, ARRAY_SIZE(pre_axi_sels)); | |
ee360274 | 685 | } else { |
992b703b AV |
686 | hws[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_hw_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT); |
687 | hws[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_hw_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT); | |
688 | hws[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_hw_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT); | |
689 | hws[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_hw_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT); | |
690 | hws[IMX6QDL_CLK_SSI1_SEL] = imx_clk_hw_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | |
691 | hws[IMX6QDL_CLK_SSI2_SEL] = imx_clk_hw_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | |
692 | hws[IMX6QDL_CLK_SSI3_SEL] = imx_clk_hw_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | |
693 | hws[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_hw_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
694 | hws[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_hw_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
695 | hws[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_hw_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
696 | hws[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_hw_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); | |
697 | hws[IMX6QDL_CLK_ENFC_SEL] = imx_clk_hw_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); | |
698 | hws[IMX6QDL_CLK_EIM_SEL] = imx_clk_hw_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup); | |
699 | hws[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_hw_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup); | |
ee360274 | 700 | } |
992b703b AV |
701 | |
702 | hws[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_hw_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); | |
703 | hws[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_hw_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); | |
704 | hws[IMX6QDL_CLK_CKO1_SEL] = imx_clk_hw_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); | |
705 | hws[IMX6QDL_CLK_CKO2_SEL] = imx_clk_hw_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); | |
706 | hws[IMX6QDL_CLK_CKO] = imx_clk_hw_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); | |
d2d2e54d SG |
707 | |
708 | /* name reg shift width busy: reg, shift parent_names num_parents */ | |
992b703b AV |
709 | hws[IMX6QDL_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); |
710 | hws[IMX6QDL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); | |
d2d2e54d SG |
711 | |
712 | /* name parent_name reg shift width */ | |
992b703b AV |
713 | hws[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_hw_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); |
714 | hws[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_hw_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); | |
715 | hws[IMX6QDL_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2); | |
716 | hws[IMX6QDL_CLK_ESAI_PRED] = imx_clk_hw_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); | |
717 | hws[IMX6QDL_CLK_ESAI_PODF] = imx_clk_hw_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); | |
718 | hws[IMX6QDL_CLK_ASRC_PRED] = imx_clk_hw_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); | |
719 | hws[IMX6QDL_CLK_ASRC_PODF] = imx_clk_hw_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); | |
720 | hws[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_hw_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); | |
721 | hws[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_hw_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); | |
722 | ||
ee360274 | 723 | if (clk_on_imx6qp()) { |
992b703b AV |
724 | hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_divider("ipg_per", "ipg_per_sel", base + 0x1c, 0, 6); |
725 | hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6); | |
726 | hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "can_sel", base + 0x20, 2, 6); | |
727 | hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6); | |
728 | hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0", 2, 7); | |
729 | hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7); | |
ee360274 | 730 | } else { |
992b703b AV |
731 | hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); |
732 | hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "pll3_60m", base + 0x20, 2, 6); | |
733 | hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); | |
734 | hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); | |
735 | hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); | |
736 | hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); | |
ee360274 | 737 | } |
992b703b | 738 | |
b1d51b44 | 739 | if (clk_on_imx6dl()) |
992b703b | 740 | hws[IMX6QDL_CLK_MLB_PODF] = imx_clk_hw_divider("mlb_podf", "mlb_sel", base + 0x18, 23, 3); |
b1d51b44 | 741 | else |
992b703b AV |
742 | hws[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_hw_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); |
743 | hws[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_hw_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); | |
b1d51b44 | 744 | if (clk_on_imx6dl()) |
992b703b | 745 | hws[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_hw_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 29, 3); |
b1d51b44 | 746 | else |
992b703b AV |
747 | hws[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_hw_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); |
748 | hws[IMX6QDL_CLK_IPU1_PODF] = imx_clk_hw_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); | |
749 | hws[IMX6QDL_CLK_IPU2_PODF] = imx_clk_hw_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); | |
750 | hws[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_hw_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); | |
751 | hws[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_hw_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); | |
752 | hws[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_hw_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); | |
753 | hws[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_hw_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); | |
754 | hws[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_hw_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); | |
755 | hws[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_hw_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); | |
756 | hws[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_hw_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); | |
757 | hws[IMX6QDL_CLK_SSI1_PRED] = imx_clk_hw_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); | |
758 | hws[IMX6QDL_CLK_SSI1_PODF] = imx_clk_hw_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); | |
759 | hws[IMX6QDL_CLK_SSI2_PRED] = imx_clk_hw_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); | |
760 | hws[IMX6QDL_CLK_SSI2_PODF] = imx_clk_hw_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); | |
761 | hws[IMX6QDL_CLK_SSI3_PRED] = imx_clk_hw_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); | |
762 | hws[IMX6QDL_CLK_SSI3_PODF] = imx_clk_hw_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); | |
763 | hws[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); | |
764 | hws[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); | |
765 | hws[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_hw_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); | |
766 | hws[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_hw_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); | |
767 | hws[IMX6QDL_CLK_ENFC_PRED] = imx_clk_hw_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); | |
768 | hws[IMX6QDL_CLK_ENFC_PODF] = imx_clk_hw_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); | |
ee360274 | 769 | if (clk_on_imx6qp()) { |
992b703b AV |
770 | hws[IMX6QDL_CLK_EIM_PODF] = imx_clk_hw_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3); |
771 | hws[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_hw_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3); | |
ee360274 | 772 | } else { |
992b703b AV |
773 | hws[IMX6QDL_CLK_EIM_PODF] = imx_clk_hw_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); |
774 | hws[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_hw_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); | |
ee360274 | 775 | } |
992b703b AV |
776 | |
777 | hws[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_hw_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); | |
778 | hws[IMX6QDL_CLK_CKO1_PODF] = imx_clk_hw_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); | |
779 | hws[IMX6QDL_CLK_CKO2_PODF] = imx_clk_hw_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); | |
d2d2e54d SG |
780 | |
781 | /* name parent_name reg shift width busy: reg, shift */ | |
992b703b AV |
782 | hws[IMX6QDL_CLK_AXI] = imx_clk_hw_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); |
783 | hws[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); | |
ee360274 | 784 | if (clk_on_imx6qp()) { |
992b703b AV |
785 | hws[IMX6QDL_CLK_MMDC_CH1_AXI_CG] = imx_clk_hw_gate("mmdc_ch1_axi_cg", "periph2", base + 0x4, 18); |
786 | hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch1_axi_podf", "mmdc_ch1_axi_cg", base + 0x14, 3, 3, base + 0x48, 2); | |
ee360274 | 787 | } else { |
992b703b | 788 | hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); |
ee360274 | 789 | } |
992b703b AV |
790 | hws[IMX6QDL_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); |
791 | hws[IMX6QDL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); | |
d2d2e54d SG |
792 | |
793 | /* name parent_name reg shift */ | |
992b703b AV |
794 | hws[IMX6QDL_CLK_APBH_DMA] = imx_clk_hw_gate2("apbh_dma", "usdhc3", base + 0x68, 4); |
795 | hws[IMX6QDL_CLK_ASRC] = imx_clk_hw_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc); | |
796 | hws[IMX6QDL_CLK_ASRC_IPG] = imx_clk_hw_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); | |
797 | hws[IMX6QDL_CLK_ASRC_MEM] = imx_clk_hw_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); | |
798 | hws[IMX6QDL_CLK_CAAM_MEM] = imx_clk_hw_gate2("caam_mem", "ahb", base + 0x68, 8); | |
799 | hws[IMX6QDL_CLK_CAAM_ACLK] = imx_clk_hw_gate2("caam_aclk", "ahb", base + 0x68, 10); | |
800 | hws[IMX6QDL_CLK_CAAM_IPG] = imx_clk_hw_gate2("caam_ipg", "ipg", base + 0x68, 12); | |
801 | hws[IMX6QDL_CLK_CAN1_IPG] = imx_clk_hw_gate2("can1_ipg", "ipg", base + 0x68, 14); | |
802 | hws[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_hw_gate2("can1_serial", "can_root", base + 0x68, 16); | |
803 | hws[IMX6QDL_CLK_CAN2_IPG] = imx_clk_hw_gate2("can2_ipg", "ipg", base + 0x68, 18); | |
804 | hws[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_hw_gate2("can2_serial", "can_root", base + 0x68, 20); | |
805 | hws[IMX6QDL_CLK_DCIC1] = imx_clk_hw_gate2("dcic1", "ipu1_podf", base + 0x68, 24); | |
806 | hws[IMX6QDL_CLK_DCIC2] = imx_clk_hw_gate2("dcic2", "ipu2_podf", base + 0x68, 26); | |
807 | hws[IMX6QDL_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); | |
808 | hws[IMX6QDL_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); | |
809 | hws[IMX6QDL_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); | |
810 | hws[IMX6QDL_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); | |
961dfd37 | 811 | if (clk_on_imx6dl()) |
992b703b | 812 | hws[IMX6DL_CLK_I2C4] = imx_clk_hw_gate2("i2c4", "ipg_per", base + 0x6c, 8); |
ee3387f9 | 813 | else |
992b703b AV |
814 | hws[IMX6Q_CLK_ECSPI5] = imx_clk_hw_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); |
815 | hws[IMX6QDL_CLK_ENET] = imx_clk_hw_gate2("enet", "ipg", base + 0x6c, 10); | |
816 | hws[IMX6QDL_CLK_EPIT1] = imx_clk_hw_gate2("epit1", "ipg", base + 0x6c, 12); | |
817 | hws[IMX6QDL_CLK_EPIT2] = imx_clk_hw_gate2("epit2", "ipg", base + 0x6c, 14); | |
818 | hws[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_hw_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai); | |
819 | hws[IMX6QDL_CLK_ESAI_IPG] = imx_clk_hw_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai); | |
820 | hws[IMX6QDL_CLK_ESAI_MEM] = imx_clk_hw_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); | |
821 | hws[IMX6QDL_CLK_GPT_IPG] = imx_clk_hw_gate2("gpt_ipg", "ipg", base + 0x6c, 20); | |
822 | hws[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_hw_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); | |
823 | hws[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_hw_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); | |
824 | hws[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_hw_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); | |
825 | hws[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_hw_gate2("hdmi_iahb", "ahb", base + 0x70, 0); | |
826 | hws[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_hw_gate2("hdmi_isfr", "mipi_core_cfg", base + 0x70, 4); | |
827 | hws[IMX6QDL_CLK_I2C1] = imx_clk_hw_gate2("i2c1", "ipg_per", base + 0x70, 6); | |
828 | hws[IMX6QDL_CLK_I2C2] = imx_clk_hw_gate2("i2c2", "ipg_per", base + 0x70, 8); | |
829 | hws[IMX6QDL_CLK_I2C3] = imx_clk_hw_gate2("i2c3", "ipg_per", base + 0x70, 10); | |
830 | hws[IMX6QDL_CLK_IIM] = imx_clk_hw_gate2("iim", "ipg", base + 0x70, 12); | |
831 | hws[IMX6QDL_CLK_ENFC] = imx_clk_hw_gate2("enfc", "enfc_podf", base + 0x70, 14); | |
832 | hws[IMX6QDL_CLK_VDOA] = imx_clk_hw_gate2("vdoa", "vdo_axi", base + 0x70, 26); | |
833 | hws[IMX6QDL_CLK_IPU1] = imx_clk_hw_gate2("ipu1", "ipu1_podf", base + 0x74, 0); | |
834 | hws[IMX6QDL_CLK_IPU1_DI0] = imx_clk_hw_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); | |
835 | hws[IMX6QDL_CLK_IPU1_DI1] = imx_clk_hw_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); | |
836 | hws[IMX6QDL_CLK_IPU2] = imx_clk_hw_gate2("ipu2", "ipu2_podf", base + 0x74, 6); | |
837 | hws[IMX6QDL_CLK_IPU2_DI0] = imx_clk_hw_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); | |
ee360274 | 838 | if (clk_on_imx6qp()) { |
992b703b AV |
839 | hws[IMX6QDL_CLK_LDB_DI0] = imx_clk_hw_gate2("ldb_di0", "ldb_di0_sel", base + 0x74, 12); |
840 | hws[IMX6QDL_CLK_LDB_DI1] = imx_clk_hw_gate2("ldb_di1", "ldb_di1_sel", base + 0x74, 14); | |
ee360274 | 841 | } else { |
992b703b AV |
842 | hws[IMX6QDL_CLK_LDB_DI0] = imx_clk_hw_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); |
843 | hws[IMX6QDL_CLK_LDB_DI1] = imx_clk_hw_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); | |
ee360274 | 844 | } |
992b703b AV |
845 | hws[IMX6QDL_CLK_IPU2_DI1] = imx_clk_hw_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); |
846 | hws[IMX6QDL_CLK_HSI_TX] = imx_clk_hw_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg); | |
847 | hws[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_hw_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg); | |
848 | hws[IMX6QDL_CLK_MIPI_IPG] = imx_clk_hw_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg); | |
849 | ||
961dfd37 | 850 | if (clk_on_imx6dl()) |
fbcb4412 DB |
851 | /* |
852 | * The multiplexer and divider of the imx6q clock gpu2d get | |
853 | * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl. | |
854 | */ | |
992b703b | 855 | hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb", "mlb_podf", base + 0x74, 18); |
fbcb4412 | 856 | else |
992b703b AV |
857 | hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb", "axi", base + 0x74, 18); |
858 | hws[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_hw_gate2_flags("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20, CLK_IS_CRITICAL); | |
859 | hws[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_hw_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); | |
860 | hws[IMX6QDL_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); | |
861 | hws[IMX6QDL_CLK_OCRAM] = imx_clk_hw_gate2("ocram", "ahb", base + 0x74, 28); | |
862 | hws[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_hw_gate2("openvg_axi", "axi", base + 0x74, 30); | |
863 | hws[IMX6QDL_CLK_PCIE_AXI] = imx_clk_hw_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); | |
864 | hws[IMX6QDL_CLK_PER1_BCH] = imx_clk_hw_gate2("per1_bch", "usdhc3", base + 0x78, 12); | |
865 | hws[IMX6QDL_CLK_PWM1] = imx_clk_hw_gate2("pwm1", "ipg_per", base + 0x78, 16); | |
866 | hws[IMX6QDL_CLK_PWM2] = imx_clk_hw_gate2("pwm2", "ipg_per", base + 0x78, 18); | |
867 | hws[IMX6QDL_CLK_PWM3] = imx_clk_hw_gate2("pwm3", "ipg_per", base + 0x78, 20); | |
868 | hws[IMX6QDL_CLK_PWM4] = imx_clk_hw_gate2("pwm4", "ipg_per", base + 0x78, 22); | |
869 | hws[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_hw_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); | |
870 | hws[IMX6QDL_CLK_GPMI_BCH] = imx_clk_hw_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); | |
871 | hws[IMX6QDL_CLK_GPMI_IO] = imx_clk_hw_gate2("gpmi_io", "enfc", base + 0x78, 28); | |
872 | hws[IMX6QDL_CLK_GPMI_APB] = imx_clk_hw_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); | |
873 | hws[IMX6QDL_CLK_ROM] = imx_clk_hw_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL); | |
874 | hws[IMX6QDL_CLK_SATA] = imx_clk_hw_gate2("sata", "ahb", base + 0x7c, 4); | |
875 | hws[IMX6QDL_CLK_SDMA] = imx_clk_hw_gate2("sdma", "ahb", base + 0x7c, 6); | |
876 | hws[IMX6QDL_CLK_SPBA] = imx_clk_hw_gate2("spba", "ipg", base + 0x7c, 12); | |
877 | hws[IMX6QDL_CLK_SPDIF] = imx_clk_hw_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif); | |
878 | hws[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_hw_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); | |
879 | hws[IMX6QDL_CLK_SSI1_IPG] = imx_clk_hw_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); | |
880 | hws[IMX6QDL_CLK_SSI2_IPG] = imx_clk_hw_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); | |
881 | hws[IMX6QDL_CLK_SSI3_IPG] = imx_clk_hw_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); | |
882 | hws[IMX6QDL_CLK_SSI1] = imx_clk_hw_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); | |
883 | hws[IMX6QDL_CLK_SSI2] = imx_clk_hw_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); | |
884 | hws[IMX6QDL_CLK_SSI3] = imx_clk_hw_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); | |
885 | hws[IMX6QDL_CLK_UART_IPG] = imx_clk_hw_gate2("uart_ipg", "ipg", base + 0x7c, 24); | |
886 | hws[IMX6QDL_CLK_UART_SERIAL] = imx_clk_hw_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); | |
887 | hws[IMX6QDL_CLK_USBOH3] = imx_clk_hw_gate2("usboh3", "ipg", base + 0x80, 0); | |
888 | hws[IMX6QDL_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); | |
889 | hws[IMX6QDL_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); | |
890 | hws[IMX6QDL_CLK_USDHC3] = imx_clk_hw_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); | |
891 | hws[IMX6QDL_CLK_USDHC4] = imx_clk_hw_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); | |
892 | hws[IMX6QDL_CLK_EIM_SLOW] = imx_clk_hw_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10); | |
893 | hws[IMX6QDL_CLK_VDO_AXI] = imx_clk_hw_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); | |
894 | hws[IMX6QDL_CLK_VPU_AXI] = imx_clk_hw_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); | |
ee360274 | 895 | if (clk_on_imx6qp()) { |
992b703b AV |
896 | hws[IMX6QDL_CLK_PRE0] = imx_clk_hw_gate2("pre0", "pre_axi", base + 0x80, 16); |
897 | hws[IMX6QDL_CLK_PRE1] = imx_clk_hw_gate2("pre1", "pre_axi", base + 0x80, 18); | |
898 | hws[IMX6QDL_CLK_PRE2] = imx_clk_hw_gate2("pre2", "pre_axi", base + 0x80, 20); | |
899 | hws[IMX6QDL_CLK_PRE3] = imx_clk_hw_gate2("pre3", "pre_axi", base + 0x80, 22); | |
900 | hws[IMX6QDL_CLK_PRG0_AXI] = imx_clk_hw_gate2_shared("prg0_axi", "ipu1_podf", base + 0x80, 24, &share_count_prg0); | |
901 | hws[IMX6QDL_CLK_PRG1_AXI] = imx_clk_hw_gate2_shared("prg1_axi", "ipu2_podf", base + 0x80, 26, &share_count_prg1); | |
902 | hws[IMX6QDL_CLK_PRG0_APB] = imx_clk_hw_gate2_shared("prg0_apb", "ipg", base + 0x80, 24, &share_count_prg0); | |
903 | hws[IMX6QDL_CLK_PRG1_APB] = imx_clk_hw_gate2_shared("prg1_apb", "ipg", base + 0x80, 26, &share_count_prg1); | |
ee360274 | 904 | } |
992b703b AV |
905 | hws[IMX6QDL_CLK_CKO1] = imx_clk_hw_gate("cko1", "cko1_podf", base + 0x60, 7); |
906 | hws[IMX6QDL_CLK_CKO2] = imx_clk_hw_gate("cko2", "cko2_podf", base + 0x60, 24); | |
2acd1b6f | 907 | |
6f11c69d AH |
908 | /* |
909 | * The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it | |
910 | * to clock gpt_ipg_per to ease the gpt driver code. | |
911 | */ | |
961dfd37 | 912 | if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) |
992b703b | 913 | hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER]; |
6f11c69d | 914 | |
992b703b | 915 | imx_check_clk_hws(hws, IMX6QDL_CLK_END); |
2acd1b6f | 916 | |
992b703b | 917 | of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); |
0e87e043 | 918 | |
992b703b | 919 | clk_hw_register_clkdev(hws[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); |
2acd1b6f | 920 | |
992b703b | 921 | clk_set_rate(hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk, 540000000); |
05e062f9 | 922 | if (clk_on_imx6dl()) |
992b703b | 923 | clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk); |
05e062f9 | 924 | |
992b703b AV |
925 | clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); |
926 | clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); | |
927 | clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); | |
928 | clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); | |
929 | clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI0_PRE]->clk); | |
930 | clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI1_PRE]->clk); | |
931 | clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI0_PRE]->clk); | |
932 | clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI1_PRE]->clk); | |
17b9b3b9 | 933 | |
cc7887c3 HS |
934 | /* |
935 | * The gpmi needs 100MHz frequency in the EDO/Sync mode, | |
936 | * We can not get the 100MHz from the pll2_pfd0_352m. | |
937 | * So choose pll2_pfd2_396m as enfc_sel's parent. | |
938 | */ | |
992b703b | 939 | clk_set_parent(hws[IMX6QDL_CLK_ENFC_SEL]->clk, hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk); |
cc7887c3 | 940 | |
a5120e89 | 941 | if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { |
992b703b AV |
942 | clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY1_GATE]->clk); |
943 | clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY2_GATE]->clk); | |
a5120e89 PC |
944 | } |
945 | ||
a94f8ecb SG |
946 | /* |
947 | * Let's initially set up CLKO with OSC24M, since this configuration | |
948 | * is widely used by imx6q board designs to clock audio codec. | |
949 | */ | |
992b703b | 950 | ret = clk_set_parent(hws[IMX6QDL_CLK_CKO2_SEL]->clk, hws[IMX6QDL_CLK_OSC]->clk); |
a94f8ecb | 951 | if (!ret) |
992b703b | 952 | ret = clk_set_parent(hws[IMX6QDL_CLK_CKO]->clk, hws[IMX6QDL_CLK_CKO2]->clk); |
a94f8ecb SG |
953 | if (ret) |
954 | pr_warn("failed to set up CLKO: %d\n", ret); | |
955 | ||
4390e622 | 956 | /* Audio-related clocks configuration */ |
992b703b | 957 | clk_set_parent(hws[IMX6QDL_CLK_SPDIF_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD3_454M]->clk); |
4390e622 | 958 | |
74b80313 SC |
959 | /* All existing boards with PCIe use LVDS1 */ |
960 | if (IS_ENABLED(CONFIG_PCI_IMX6)) | |
992b703b | 961 | clk_set_parent(hws[IMX6QDL_CLK_LVDS1_SEL]->clk, hws[IMX6QDL_CLK_SATA_REF_100M]->clk); |
0822f933 | 962 | |
d8846023 LS |
963 | /* |
964 | * Initialize the GPU clock muxes, so that the maximum specified clock | |
965 | * rates for the respective SoC are not exceeded. | |
966 | */ | |
967 | if (clk_on_imx6dl()) { | |
992b703b AV |
968 | clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk, |
969 | hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk); | |
970 | clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk, | |
971 | hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk); | |
d8846023 | 972 | } else if (clk_on_imx6q()) { |
992b703b AV |
973 | clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk, |
974 | hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk); | |
975 | clk_set_parent(hws[IMX6QDL_CLK_GPU3D_SHADER_SEL]->clk, | |
976 | hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk); | |
977 | clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk, | |
978 | hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); | |
979 | } | |
980 | ||
981 | for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) { | |
982 | int index = uart_clk_ids[i]; | |
983 | ||
984 | uart_clks[i] = &hws[index]->clk; | |
d8846023 LS |
985 | } |
986 | ||
0822f933 | 987 | imx_register_uart_clocks(uart_clks); |
2acd1b6f | 988 | } |
53bb71da | 989 | CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); |