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e2f744a8 | 1 | /* |
2 | * Copyright (c) 2017 MediaTek Inc. | |
3 | * Author: Weiyi Lu <weiyi.lu@mediatek.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/clk.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/mfd/syscon.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/of_address.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/slab.h> | |
23 | ||
24 | #include "clk-mtk.h" | |
25 | #include "clk-gate.h" | |
26 | ||
27 | #include <dt-bindings/clock/mt2712-clk.h> | |
28 | ||
29 | static DEFINE_SPINLOCK(mt2712_clk_lock); | |
30 | ||
31 | static const struct mtk_fixed_clk top_fixed_clks[] = { | |
32 | FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000), | |
33 | FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000), | |
34 | FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000), | |
35 | FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000), | |
36 | FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000), | |
37 | FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000), | |
38 | FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000), | |
39 | FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000), | |
40 | FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768), | |
41 | FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747), | |
42 | FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000), | |
43 | FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000), | |
44 | }; | |
45 | ||
46 | static const struct mtk_fixed_factor top_early_divs[] = { | |
47 | FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1, | |
48 | 1), | |
49 | FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1, | |
50 | 2), | |
51 | }; | |
52 | ||
53 | static const struct mtk_fixed_factor top_divs[] = { | |
54 | FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1, | |
55 | 1), | |
56 | FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1, | |
57 | 2), | |
58 | FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1, | |
59 | 3), | |
60 | FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1, | |
61 | 1), | |
62 | FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, | |
63 | 1), | |
64 | FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, | |
65 | 2), | |
66 | FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, | |
67 | 2), | |
68 | FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, | |
69 | 4), | |
70 | FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, | |
71 | 8), | |
72 | FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, | |
73 | 16), | |
74 | FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1, | |
75 | 3), | |
76 | FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, | |
77 | 2), | |
78 | FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, | |
79 | 4), | |
80 | FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1, | |
81 | 5), | |
82 | FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, | |
83 | 2), | |
84 | FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, | |
85 | 4), | |
86 | FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1, | |
87 | 7), | |
88 | FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, | |
89 | 2), | |
90 | FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, | |
91 | 4), | |
92 | FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, | |
93 | 1), | |
94 | FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1, | |
95 | 7), | |
96 | FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1, | |
97 | 26), | |
98 | FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1, | |
99 | 52), | |
100 | FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1, | |
101 | 104), | |
102 | FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1, | |
103 | 208), | |
104 | FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, | |
105 | 2), | |
106 | FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, | |
107 | 2), | |
108 | FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, | |
109 | 4), | |
110 | FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, | |
111 | 8), | |
112 | FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1, | |
113 | 3), | |
114 | FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, | |
115 | 2), | |
116 | FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, | |
117 | 4), | |
118 | FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, | |
119 | 8), | |
120 | FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1, | |
121 | 5), | |
122 | FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, | |
123 | 2), | |
124 | FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, | |
125 | 4), | |
126 | FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, | |
127 | 8), | |
128 | FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1, | |
129 | 1), | |
130 | FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1, | |
131 | 1), | |
132 | FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1, | |
133 | 1), | |
134 | FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1, | |
135 | 1), | |
136 | FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1, | |
137 | 1), | |
138 | FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1, | |
139 | 1), | |
140 | FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, | |
141 | 1), | |
142 | FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, | |
143 | 2), | |
144 | FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, | |
145 | 4), | |
146 | FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, | |
147 | 8), | |
148 | FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1, | |
149 | 16), | |
150 | FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, | |
151 | 1), | |
152 | FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, | |
153 | 2), | |
154 | FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, | |
155 | 4), | |
156 | FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, | |
157 | 8), | |
158 | FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1, | |
159 | 16), | |
160 | FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, | |
161 | 1), | |
162 | FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1, | |
163 | 2), | |
164 | FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1, | |
165 | 4), | |
166 | FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1, | |
167 | 8), | |
168 | FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1, | |
169 | 1), | |
170 | FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1, | |
171 | 2), | |
172 | FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1, | |
173 | 4), | |
174 | FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1, | |
175 | 8), | |
176 | FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1, | |
177 | 1), | |
178 | FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1, | |
179 | 1), | |
180 | FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1, | |
181 | 1), | |
182 | FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1, | |
183 | 2), | |
184 | FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, | |
185 | 1), | |
186 | FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, | |
187 | 2), | |
188 | FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, | |
189 | 1), | |
190 | FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1, | |
191 | 2), | |
192 | FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, | |
193 | 1), | |
194 | FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1, | |
195 | 2), | |
196 | FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, | |
197 | 1), | |
198 | FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, | |
199 | 2), | |
200 | FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, | |
201 | 4), | |
202 | FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, | |
203 | 8), | |
204 | FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1, | |
205 | 1), | |
206 | FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1, | |
207 | 2), | |
208 | FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1, | |
209 | 4), | |
210 | FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, | |
211 | 1), | |
212 | FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, | |
213 | 2), | |
214 | FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, | |
215 | 4), | |
216 | FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, | |
217 | 1), | |
218 | FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1, | |
219 | 2), | |
220 | FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1, | |
221 | 4), | |
222 | FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1, | |
223 | 4), | |
f72595cf WL |
224 | FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1, |
225 | 3), | |
51ff86dd WL |
226 | FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1, |
227 | 3), | |
e2f744a8 | 228 | }; |
229 | ||
230 | static const char * const axi_parents[] = { | |
231 | "clk26m", | |
232 | "syspll1_d2", | |
233 | "syspll_d5", | |
234 | "syspll1_d4", | |
235 | "univpll_d5", | |
236 | "univpll2_d2", | |
237 | "msdcpll2_ck" | |
238 | }; | |
239 | ||
240 | static const char * const mem_parents[] = { | |
241 | "clk26m", | |
242 | "dmpll_ck" | |
243 | }; | |
244 | ||
245 | static const char * const mm_parents[] = { | |
246 | "clk26m", | |
247 | "vencpll_ck", | |
248 | "syspll_d3", | |
249 | "syspll1_d2", | |
250 | "syspll_d5", | |
251 | "syspll1_d4", | |
252 | "univpll1_d2", | |
253 | "univpll2_d2" | |
254 | }; | |
255 | ||
256 | static const char * const pwm_parents[] = { | |
257 | "clk26m", | |
258 | "univpll2_d4", | |
259 | "univpll3_d2", | |
260 | "univpll1_d4" | |
261 | }; | |
262 | ||
263 | static const char * const vdec_parents[] = { | |
264 | "clk26m", | |
265 | "vcodecpll_ck", | |
266 | "tvdpll_429m", | |
267 | "univpll_d3", | |
268 | "vencpll_ck", | |
269 | "syspll_d3", | |
270 | "univpll1_d2", | |
271 | "mmpll_d2", | |
272 | "syspll3_d2", | |
273 | "tvdpll_ck" | |
274 | }; | |
275 | ||
276 | static const char * const venc_parents[] = { | |
277 | "clk26m", | |
278 | "univpll1_d2", | |
279 | "mmpll_d2", | |
280 | "tvdpll_d2", | |
281 | "syspll1_d2", | |
282 | "univpll_d5", | |
283 | "vcodecpll_d2", | |
284 | "univpll2_d2", | |
285 | "syspll3_d2" | |
286 | }; | |
287 | ||
288 | static const char * const mfg_parents[] = { | |
289 | "clk26m", | |
290 | "mmpll_ck", | |
291 | "univpll_d3", | |
292 | "clk26m", | |
293 | "clk26m", | |
294 | "clk26m", | |
295 | "clk26m", | |
296 | "clk26m", | |
297 | "clk26m", | |
298 | "syspll_d3", | |
299 | "syspll1_d2", | |
300 | "syspll_d5", | |
301 | "univpll_d3", | |
302 | "univpll1_d2", | |
303 | "univpll_d5", | |
304 | "univpll2_d2" | |
305 | }; | |
306 | ||
307 | static const char * const camtg_parents[] = { | |
308 | "clk26m", | |
309 | "univpll_d52", | |
310 | "univpll_d208", | |
311 | "univpll_d104", | |
312 | "clk26m_d2", | |
313 | "univpll_d26", | |
314 | "univpll2_d8", | |
315 | "syspll3_d4", | |
316 | "syspll3_d2", | |
317 | "univpll1_d4", | |
318 | "univpll2_d2" | |
319 | }; | |
320 | ||
321 | static const char * const uart_parents[] = { | |
322 | "clk26m", | |
323 | "univpll2_d8" | |
324 | }; | |
325 | ||
326 | static const char * const spi_parents[] = { | |
327 | "clk26m", | |
328 | "univpll2_d4", | |
329 | "univpll1_d4", | |
330 | "univpll2_d2", | |
331 | "univpll3_d2", | |
332 | "univpll1_d8" | |
333 | }; | |
334 | ||
335 | static const char * const usb20_parents[] = { | |
336 | "clk26m", | |
337 | "univpll1_d8", | |
338 | "univpll3_d4" | |
339 | }; | |
340 | ||
341 | static const char * const usb30_parents[] = { | |
342 | "clk26m", | |
343 | "univpll3_d2", | |
344 | "univpll3_d4", | |
345 | "univpll2_d4" | |
346 | }; | |
347 | ||
348 | static const char * const msdc50_0_h_parents[] = { | |
349 | "clk26m", | |
350 | "syspll1_d2", | |
351 | "syspll2_d2", | |
352 | "syspll4_d2", | |
353 | "univpll_d5", | |
354 | "univpll1_d4" | |
355 | }; | |
356 | ||
357 | static const char * const msdc50_0_parents[] = { | |
358 | "clk26m", | |
359 | "msdcpll_ck", | |
360 | "msdcpll_d2", | |
361 | "univpll1_d4", | |
362 | "syspll2_d2", | |
363 | "msdcpll_d4", | |
364 | "vencpll_d2", | |
365 | "univpll1_d2", | |
366 | "msdcpll2_ck", | |
367 | "msdcpll2_d2", | |
368 | "msdcpll2_d4" | |
369 | }; | |
370 | ||
371 | static const char * const msdc30_1_parents[] = { | |
372 | "clk26m", | |
373 | "univpll2_d2", | |
374 | "msdcpll_d2", | |
375 | "univpll1_d4", | |
376 | "syspll2_d2", | |
377 | "univpll_d7", | |
378 | "vencpll_d2" | |
379 | }; | |
380 | ||
381 | static const char * const msdc30_3_parents[] = { | |
382 | "clk26m", | |
383 | "msdcpll2_ck", | |
384 | "msdcpll2_d2", | |
385 | "univpll2_d2", | |
386 | "msdcpll2_d4", | |
387 | "univpll1_d4", | |
388 | "syspll2_d2", | |
389 | "syspll_d7", | |
390 | "univpll_d7", | |
391 | "vencpll_d2", | |
392 | "msdcpll_ck", | |
393 | "msdcpll_d2", | |
394 | "msdcpll_d4" | |
395 | }; | |
396 | ||
397 | static const char * const audio_parents[] = { | |
398 | "clk26m", | |
399 | "syspll3_d4", | |
400 | "syspll4_d4", | |
401 | "syspll1_d16" | |
402 | }; | |
403 | ||
404 | static const char * const aud_intbus_parents[] = { | |
405 | "clk26m", | |
406 | "syspll1_d4", | |
407 | "syspll4_d2", | |
408 | "univpll3_d2", | |
409 | "univpll2_d8", | |
410 | "syspll3_d2", | |
411 | "syspll3_d4" | |
412 | }; | |
413 | ||
414 | static const char * const pmicspi_parents[] = { | |
415 | "clk26m", | |
416 | "syspll1_d8", | |
417 | "syspll3_d4", | |
418 | "syspll1_d16", | |
419 | "univpll3_d4", | |
420 | "univpll_d26", | |
421 | "syspll3_d4" | |
422 | }; | |
423 | ||
424 | static const char * const dpilvds1_parents[] = { | |
425 | "clk26m", | |
426 | "lvdspll2_ck", | |
427 | "lvdspll2_d2", | |
428 | "lvdspll2_d4", | |
429 | "lvdspll2_d8", | |
430 | "clkfpc" | |
431 | }; | |
432 | ||
433 | static const char * const atb_parents[] = { | |
434 | "clk26m", | |
435 | "syspll1_d2", | |
436 | "univpll_d5", | |
437 | "syspll_d5" | |
438 | }; | |
439 | ||
440 | static const char * const nr_parents[] = { | |
441 | "clk26m", | |
442 | "univpll1_d4", | |
443 | "syspll2_d2", | |
444 | "syspll1_d4", | |
445 | "univpll1_d8", | |
446 | "univpll3_d2", | |
447 | "univpll2_d2", | |
448 | "syspll_d5" | |
449 | }; | |
450 | ||
451 | static const char * const nfi2x_parents[] = { | |
452 | "clk26m", | |
453 | "syspll4_d4", | |
454 | "univpll3_d4", | |
455 | "univpll1_d8", | |
456 | "syspll2_d4", | |
457 | "univpll3_d2", | |
458 | "syspll_d7", | |
459 | "syspll2_d2", | |
460 | "univpll2_d2", | |
461 | "syspll_d5", | |
462 | "syspll1_d2" | |
463 | }; | |
464 | ||
465 | static const char * const irda_parents[] = { | |
466 | "clk26m", | |
467 | "univpll2_d4", | |
468 | "syspll2_d4", | |
469 | "univpll2_d8" | |
470 | }; | |
471 | ||
472 | static const char * const cci400_parents[] = { | |
473 | "clk26m", | |
474 | "vencpll_ck", | |
475 | "armca35pll_600m", | |
476 | "armca35pll_400m", | |
477 | "univpll_d2", | |
478 | "syspll_d2", | |
479 | "msdcpll_ck", | |
480 | "univpll_d3" | |
481 | }; | |
482 | ||
483 | static const char * const aud_1_parents[] = { | |
484 | "clk26m", | |
485 | "apll1_ck", | |
486 | "univpll2_d4", | |
487 | "univpll2_d8" | |
488 | }; | |
489 | ||
490 | static const char * const aud_2_parents[] = { | |
491 | "clk26m", | |
492 | "apll2_ck", | |
493 | "univpll2_d4", | |
494 | "univpll2_d8" | |
495 | }; | |
496 | ||
497 | static const char * const mem_mfg_parents[] = { | |
498 | "clk26m", | |
499 | "mmpll_ck", | |
500 | "univpll_d3" | |
501 | }; | |
502 | ||
503 | static const char * const axi_mfg_parents[] = { | |
504 | "clk26m", | |
505 | "axi_sel", | |
506 | "univpll_d5" | |
507 | }; | |
508 | ||
509 | static const char * const scam_parents[] = { | |
510 | "clk26m", | |
511 | "syspll3_d2", | |
512 | "univpll2_d4", | |
513 | "syspll2_d4" | |
514 | }; | |
515 | ||
516 | static const char * const nfiecc_parents[] = { | |
517 | "clk26m", | |
518 | "nfi2x_sel", | |
519 | "syspll_d7", | |
520 | "syspll2_d2", | |
521 | "univpll2_d2", | |
522 | "univpll_d5", | |
523 | "syspll1_d2" | |
524 | }; | |
525 | ||
526 | static const char * const pe2_mac_p0_parents[] = { | |
527 | "clk26m", | |
528 | "syspll1_d8", | |
529 | "syspll4_d2", | |
530 | "syspll2_d4", | |
531 | "univpll2_d4", | |
532 | "syspll3_d2" | |
533 | }; | |
534 | ||
535 | static const char * const dpilvds_parents[] = { | |
536 | "clk26m", | |
537 | "lvdspll_ck", | |
538 | "lvdspll_d2", | |
539 | "lvdspll_d4", | |
540 | "lvdspll_d8", | |
541 | "clkfpc" | |
542 | }; | |
543 | ||
544 | static const char * const hdcp_parents[] = { | |
545 | "clk26m", | |
546 | "syspll4_d2", | |
547 | "syspll3_d4", | |
548 | "univpll2_d4" | |
549 | }; | |
550 | ||
551 | static const char * const hdcp_24m_parents[] = { | |
552 | "clk26m", | |
553 | "univpll_d26", | |
554 | "univpll_d52", | |
555 | "univpll2_d8" | |
556 | }; | |
557 | ||
558 | static const char * const rtc_parents[] = { | |
559 | "clkrtc_int", | |
560 | "clkrtc_ext", | |
561 | "clk26m", | |
562 | "univpll3_d8" | |
563 | }; | |
564 | ||
565 | static const char * const spinor_parents[] = { | |
566 | "clk26m", | |
567 | "clk26m_d2", | |
568 | "syspll4_d4", | |
569 | "univpll2_d8", | |
570 | "univpll3_d4", | |
571 | "syspll4_d2", | |
572 | "syspll2_d4", | |
573 | "univpll2_d4", | |
574 | "etherpll_125m", | |
575 | "syspll1_d4" | |
576 | }; | |
577 | ||
578 | static const char * const apll_parents[] = { | |
579 | "clk26m", | |
580 | "apll1_ck", | |
581 | "apll1_d2", | |
582 | "apll1_d4", | |
583 | "apll1_d8", | |
584 | "apll1_d16", | |
585 | "apll2_ck", | |
586 | "apll2_d2", | |
587 | "apll2_d4", | |
588 | "apll2_d8", | |
589 | "apll2_d16", | |
590 | "clk26m", | |
591 | "clk26m" | |
592 | }; | |
593 | ||
594 | static const char * const a1sys_hp_parents[] = { | |
595 | "clk26m", | |
596 | "apll1_ck", | |
597 | "apll1_d2", | |
598 | "apll1_d4", | |
51ff86dd WL |
599 | "apll1_d8", |
600 | "apll1_d3" | |
e2f744a8 | 601 | }; |
602 | ||
603 | static const char * const a2sys_hp_parents[] = { | |
604 | "clk26m", | |
605 | "apll2_ck", | |
606 | "apll2_d2", | |
607 | "apll2_d4", | |
51ff86dd WL |
608 | "apll2_d8", |
609 | "apll2_d3" | |
e2f744a8 | 610 | }; |
611 | ||
612 | static const char * const asm_l_parents[] = { | |
613 | "clk26m", | |
614 | "univpll2_d4", | |
615 | "univpll2_d2", | |
616 | "syspll_d5" | |
617 | }; | |
618 | ||
619 | static const char * const i2so1_parents[] = { | |
620 | "clk26m", | |
621 | "apll1_ck", | |
622 | "apll2_ck" | |
623 | }; | |
624 | ||
625 | static const char * const ether_125m_parents[] = { | |
626 | "clk26m", | |
627 | "etherpll_125m", | |
628 | "univpll3_d2" | |
629 | }; | |
630 | ||
631 | static const char * const ether_50m_parents[] = { | |
632 | "clk26m", | |
633 | "etherpll_50m", | |
f72595cf | 634 | "apll1_d3", |
e2f744a8 | 635 | "univpll3_d4" |
636 | }; | |
637 | ||
638 | static const char * const jpgdec_parents[] = { | |
639 | "clk26m", | |
640 | "univpll_d3", | |
641 | "tvdpll_429m", | |
642 | "vencpll_ck", | |
643 | "syspll_d3", | |
644 | "vcodecpll_ck", | |
645 | "univpll1_d2", | |
646 | "armca35pll_400m", | |
647 | "tvdpll_429m_d2", | |
648 | "tvdpll_429m_d4" | |
649 | }; | |
650 | ||
651 | static const char * const spislv_parents[] = { | |
652 | "clk26m", | |
653 | "univpll2_d4", | |
654 | "univpll1_d4", | |
655 | "univpll2_d2", | |
656 | "univpll3_d2", | |
657 | "univpll1_d8", | |
658 | "univpll1_d2", | |
659 | "univpll_d5" | |
660 | }; | |
661 | ||
662 | static const char * const ether_parents[] = { | |
663 | "clk26m", | |
664 | "etherpll_50m", | |
665 | "univpll_d26" | |
666 | }; | |
667 | ||
668 | static const char * const di_parents[] = { | |
669 | "clk26m", | |
670 | "tvdpll_d2", | |
671 | "tvdpll_d4", | |
672 | "tvdpll_d8", | |
673 | "vencpll_ck", | |
674 | "vencpll_d2", | |
675 | "cvbs", | |
676 | "cvbs_d2" | |
677 | }; | |
678 | ||
679 | static const char * const tvd_parents[] = { | |
680 | "clk26m", | |
681 | "cvbs_d2", | |
682 | "univpll2_d8" | |
683 | }; | |
684 | ||
685 | static const char * const i2c_parents[] = { | |
686 | "clk26m", | |
687 | "univpll_d26", | |
688 | "univpll2_d4", | |
689 | "univpll3_d2", | |
690 | "univpll1_d4" | |
691 | }; | |
692 | ||
693 | static const char * const msdc0p_aes_parents[] = { | |
694 | "clk26m", | |
f72595cf | 695 | "syspll_d2", |
e2f744a8 | 696 | "univpll_d3", |
697 | "vcodecpll_ck" | |
698 | }; | |
699 | ||
700 | static const char * const cmsys_parents[] = { | |
701 | "clk26m", | |
702 | "univpll_d3", | |
703 | "syspll_d3", | |
704 | "syspll1_d2", | |
705 | "syspll2_d2" | |
706 | }; | |
707 | ||
708 | static const char * const gcpu_parents[] = { | |
709 | "clk26m", | |
710 | "syspll_d3", | |
711 | "syspll1_d2", | |
712 | "univpll1_d2", | |
713 | "univpll_d5", | |
714 | "univpll3_d2", | |
715 | "univpll_d3" | |
716 | }; | |
717 | ||
718 | static const char * const aud_apll1_parents[] = { | |
719 | "apll1", | |
720 | "clkaud_ext_i_1" | |
721 | }; | |
722 | ||
723 | static const char * const aud_apll2_parents[] = { | |
724 | "apll2", | |
725 | "clkaud_ext_i_2" | |
726 | }; | |
727 | ||
f72595cf WL |
728 | static const char * const apll1_ref_parents[] = { |
729 | "clkaud_ext_i_2", | |
730 | "clkaud_ext_i_1", | |
731 | "clki2si0_mck_i", | |
732 | "clki2si1_mck_i", | |
733 | "clki2si2_mck_i", | |
734 | "clktdmin_mclk_i", | |
735 | "clki2si2_mck_i", | |
736 | "clktdmin_mclk_i" | |
737 | }; | |
738 | ||
e2f744a8 | 739 | static const char * const audull_vtx_parents[] = { |
740 | "d2a_ulclk_6p5m", | |
741 | "clkaud_ext_i_0" | |
742 | }; | |
743 | ||
744 | static struct mtk_composite top_muxes[] = { | |
745 | /* CLK_CFG_0 */ | |
746 | MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3, | |
747 | 7, CLK_IS_CRITICAL), | |
748 | MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1, | |
749 | 15, CLK_IS_CRITICAL), | |
750 | MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", | |
751 | mm_parents, 0x040, 24, 3, 31), | |
752 | /* CLK_CFG_1 */ | |
753 | MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", | |
754 | pwm_parents, 0x050, 0, 2, 7), | |
755 | MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", | |
756 | vdec_parents, 0x050, 8, 4, 15), | |
757 | MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", | |
758 | venc_parents, 0x050, 16, 4, 23), | |
759 | MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", | |
760 | mfg_parents, 0x050, 24, 4, 31), | |
761 | /* CLK_CFG_2 */ | |
762 | MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", | |
763 | camtg_parents, 0x060, 0, 4, 7), | |
764 | MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", | |
765 | uart_parents, 0x060, 8, 1, 15), | |
766 | MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", | |
767 | spi_parents, 0x060, 16, 3, 23), | |
768 | MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", | |
769 | usb20_parents, 0x060, 24, 2, 31), | |
770 | /* CLK_CFG_3 */ | |
771 | MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", | |
772 | usb30_parents, 0x070, 0, 2, 7), | |
773 | MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel", | |
774 | msdc50_0_h_parents, 0x070, 8, 3, 15), | |
775 | MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", | |
776 | msdc50_0_parents, 0x070, 16, 4, 23), | |
777 | MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", | |
778 | msdc30_1_parents, 0x070, 24, 3, 31), | |
779 | /* CLK_CFG_4 */ | |
780 | MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", | |
781 | msdc30_1_parents, 0x080, 0, 3, 7), | |
782 | MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", | |
783 | msdc30_3_parents, 0x080, 8, 4, 15), | |
784 | MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", | |
785 | audio_parents, 0x080, 16, 2, 23), | |
786 | MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", | |
787 | aud_intbus_parents, 0x080, 24, 3, 31), | |
788 | /* CLK_CFG_5 */ | |
789 | MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", | |
790 | pmicspi_parents, 0x090, 0, 3, 7), | |
791 | MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel", | |
792 | dpilvds1_parents, 0x090, 8, 3, 15), | |
793 | MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", | |
794 | atb_parents, 0x090, 16, 2, 23), | |
795 | MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", | |
796 | nr_parents, 0x090, 24, 3, 31), | |
797 | /* CLK_CFG_6 */ | |
798 | MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", | |
799 | nfi2x_parents, 0x0a0, 0, 4, 7), | |
800 | MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", | |
801 | irda_parents, 0x0a0, 8, 2, 15), | |
802 | MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", | |
803 | cci400_parents, 0x0a0, 16, 3, 23), | |
804 | MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", | |
805 | aud_1_parents, 0x0a0, 24, 2, 31), | |
806 | /* CLK_CFG_7 */ | |
807 | MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", | |
808 | aud_2_parents, 0x0b0, 0, 2, 7), | |
809 | MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel", | |
810 | mem_mfg_parents, 0x0b0, 8, 2, 15), | |
811 | MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel", | |
812 | axi_mfg_parents, 0x0b0, 16, 2, 23), | |
813 | MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", | |
814 | scam_parents, 0x0b0, 24, 2, 31), | |
815 | /* CLK_CFG_8 */ | |
816 | MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel", | |
817 | nfiecc_parents, 0x0c0, 0, 3, 7), | |
818 | MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel", | |
819 | pe2_mac_p0_parents, 0x0c0, 8, 3, 15), | |
820 | MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel", | |
821 | pe2_mac_p0_parents, 0x0c0, 16, 3, 23), | |
822 | MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", | |
823 | dpilvds_parents, 0x0c0, 24, 3, 31), | |
824 | /* CLK_CFG_9 */ | |
825 | MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel", | |
826 | msdc50_0_h_parents, 0x0d0, 0, 3, 7), | |
827 | MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", | |
828 | hdcp_parents, 0x0d0, 8, 2, 15), | |
829 | MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", | |
830 | hdcp_24m_parents, 0x0d0, 16, 2, 23), | |
831 | MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2, | |
832 | 31, CLK_IS_CRITICAL), | |
833 | /* CLK_CFG_10 */ | |
834 | MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel", | |
835 | spinor_parents, 0x500, 0, 4, 7), | |
836 | MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", | |
837 | apll_parents, 0x500, 8, 4, 15), | |
838 | MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel", | |
839 | apll_parents, 0x500, 16, 4, 23), | |
840 | MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", | |
841 | a1sys_hp_parents, 0x500, 24, 3, 31), | |
842 | /* CLK_CFG_11 */ | |
843 | MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", | |
844 | a2sys_hp_parents, 0x510, 0, 3, 7), | |
845 | MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", | |
846 | asm_l_parents, 0x510, 8, 2, 15), | |
847 | MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", | |
848 | asm_l_parents, 0x510, 16, 2, 23), | |
849 | MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", | |
850 | asm_l_parents, 0x510, 24, 2, 31), | |
851 | /* CLK_CFG_12 */ | |
852 | MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel", | |
853 | i2so1_parents, 0x520, 0, 2, 7), | |
854 | MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel", | |
855 | i2so1_parents, 0x520, 8, 2, 15), | |
856 | MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel", | |
857 | i2so1_parents, 0x520, 16, 2, 23), | |
858 | MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel", | |
859 | i2so1_parents, 0x520, 24, 2, 31), | |
860 | /* CLK_CFG_13 */ | |
861 | MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel", | |
862 | i2so1_parents, 0x530, 0, 2, 7), | |
863 | MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel", | |
864 | i2so1_parents, 0x530, 8, 2, 15), | |
865 | MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel", | |
866 | i2so1_parents, 0x530, 16, 2, 23), | |
867 | MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel", | |
868 | i2so1_parents, 0x530, 24, 2, 31), | |
869 | /* CLK_CFG_14 */ | |
870 | MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel", | |
871 | ether_125m_parents, 0x540, 0, 2, 7), | |
872 | MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel", | |
873 | ether_50m_parents, 0x540, 8, 2, 15), | |
874 | MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel", | |
875 | jpgdec_parents, 0x540, 16, 4, 23), | |
876 | MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel", | |
877 | spislv_parents, 0x540, 24, 3, 31), | |
878 | /* CLK_CFG_15 */ | |
879 | MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel", | |
880 | ether_parents, 0x550, 0, 2, 7), | |
881 | MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel", | |
882 | camtg_parents, 0x550, 8, 4, 15), | |
883 | MUX_GATE(CLK_TOP_DI_SEL, "di_sel", | |
884 | di_parents, 0x550, 16, 3, 23), | |
885 | MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel", | |
886 | tvd_parents, 0x550, 24, 2, 31), | |
887 | /* CLK_CFG_16 */ | |
888 | MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel", | |
889 | i2c_parents, 0x560, 0, 3, 7), | |
890 | MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel", | |
891 | pwm_parents, 0x560, 8, 2, 15), | |
892 | MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel", | |
893 | msdc0p_aes_parents, 0x560, 16, 2, 23), | |
894 | MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", | |
895 | cmsys_parents, 0x560, 24, 3, 31), | |
896 | /* CLK_CFG_17 */ | |
897 | MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", | |
898 | gcpu_parents, 0x570, 0, 3, 7), | |
899 | /* CLK_AUDDIV_4 */ | |
900 | MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel", | |
901 | aud_apll1_parents, 0x134, 0, 1), | |
902 | MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel", | |
903 | aud_apll2_parents, 0x134, 1, 1), | |
904 | MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel", | |
905 | audull_vtx_parents, 0x134, 31, 1), | |
f72595cf WL |
906 | MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel", |
907 | apll1_ref_parents, 0x134, 4, 3), | |
908 | MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel", | |
909 | apll1_ref_parents, 0x134, 7, 3), | |
e2f744a8 | 910 | }; |
911 | ||
912 | static const char * const mcu_mp0_parents[] = { | |
913 | "clk26m", | |
914 | "armca35pll_ck", | |
915 | "f_mp0_pll1_ck", | |
916 | "f_mp0_pll2_ck" | |
917 | }; | |
918 | ||
919 | static const char * const mcu_mp2_parents[] = { | |
920 | "clk26m", | |
921 | "armca72pll_ck", | |
922 | "f_big_pll1_ck", | |
923 | "f_big_pll2_ck" | |
924 | }; | |
925 | ||
926 | static const char * const mcu_bus_parents[] = { | |
927 | "clk26m", | |
928 | "cci400_sel", | |
929 | "f_bus_pll1_ck", | |
930 | "f_bus_pll2_ck" | |
931 | }; | |
932 | ||
933 | static struct mtk_composite mcu_muxes[] = { | |
934 | /* mp0_pll_divider_cfg */ | |
935 | MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, | |
936 | 9, 2, -1, CLK_IS_CRITICAL), | |
937 | /* mp2_pll_divider_cfg */ | |
938 | MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, | |
939 | 9, 2, -1, CLK_IS_CRITICAL), | |
940 | /* bus_pll_divider_cfg */ | |
941 | MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, | |
942 | 9, 2, -1, CLK_IS_CRITICAL), | |
943 | }; | |
944 | ||
945 | static const struct mtk_clk_divider top_adj_divs[] = { | |
946 | DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8), | |
947 | DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8), | |
948 | DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8), | |
949 | DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8), | |
950 | DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8), | |
951 | DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8), | |
952 | DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8), | |
953 | DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8), | |
954 | }; | |
955 | ||
f72595cf | 956 | static const struct mtk_gate_regs top0_cg_regs = { |
e2f744a8 | 957 | .set_ofs = 0x120, |
958 | .clr_ofs = 0x120, | |
959 | .sta_ofs = 0x120, | |
960 | }; | |
961 | ||
f72595cf WL |
962 | static const struct mtk_gate_regs top1_cg_regs = { |
963 | .set_ofs = 0x424, | |
964 | .clr_ofs = 0x424, | |
965 | .sta_ofs = 0x424, | |
966 | }; | |
967 | ||
968 | #define GATE_TOP0(_id, _name, _parent, _shift) { \ | |
e2f744a8 | 969 | .id = _id, \ |
970 | .name = _name, \ | |
971 | .parent_name = _parent, \ | |
f72595cf | 972 | .regs = &top0_cg_regs, \ |
e2f744a8 | 973 | .shift = _shift, \ |
974 | .ops = &mtk_clk_gate_ops_no_setclr, \ | |
975 | } | |
976 | ||
f72595cf WL |
977 | #define GATE_TOP1(_id, _name, _parent, _shift) { \ |
978 | .id = _id, \ | |
979 | .name = _name, \ | |
980 | .parent_name = _parent, \ | |
981 | .regs = &top1_cg_regs, \ | |
982 | .shift = _shift, \ | |
983 | .ops = &mtk_clk_gate_ops_no_setclr_inv, \ | |
984 | } | |
985 | ||
e2f744a8 | 986 | static const struct mtk_gate top_clks[] = { |
f72595cf WL |
987 | /* TOP0 */ |
988 | GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0), | |
989 | GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1), | |
990 | GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2), | |
991 | GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3), | |
992 | GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4), | |
993 | GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5), | |
994 | GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6), | |
995 | GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7), | |
996 | /* TOP1 */ | |
997 | GATE_TOP1(CLK_TOP_NFI2X_EN, "nfi2x_en", "nfi2x_sel", 0), | |
998 | GATE_TOP1(CLK_TOP_NFIECC_EN, "nfiecc_en", "nfiecc_sel", 1), | |
999 | GATE_TOP1(CLK_TOP_NFI1X_CK_EN, "nfi1x_ck_en", "nfi2x_sel", 2), | |
e2f744a8 | 1000 | }; |
1001 | ||
1002 | static const struct mtk_gate_regs infra_cg_regs = { | |
1003 | .set_ofs = 0x40, | |
1004 | .clr_ofs = 0x44, | |
f72595cf | 1005 | .sta_ofs = 0x48, |
e2f744a8 | 1006 | }; |
1007 | ||
1008 | #define GATE_INFRA(_id, _name, _parent, _shift) { \ | |
1009 | .id = _id, \ | |
1010 | .name = _name, \ | |
1011 | .parent_name = _parent, \ | |
1012 | .regs = &infra_cg_regs, \ | |
1013 | .shift = _shift, \ | |
1014 | .ops = &mtk_clk_gate_ops_setclr, \ | |
1015 | } | |
1016 | ||
1017 | static const struct mtk_gate infra_clks[] = { | |
1018 | GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), | |
1019 | GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6), | |
1020 | GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), | |
1021 | GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16), | |
1022 | GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24), | |
1023 | GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25), | |
1024 | GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26), | |
1025 | }; | |
1026 | ||
1027 | static const struct mtk_gate_regs peri0_cg_regs = { | |
1028 | .set_ofs = 0x8, | |
1029 | .clr_ofs = 0x10, | |
1030 | .sta_ofs = 0x18, | |
1031 | }; | |
1032 | ||
1033 | static const struct mtk_gate_regs peri1_cg_regs = { | |
1034 | .set_ofs = 0xc, | |
1035 | .clr_ofs = 0x14, | |
1036 | .sta_ofs = 0x1c, | |
1037 | }; | |
1038 | ||
1039 | static const struct mtk_gate_regs peri2_cg_regs = { | |
1040 | .set_ofs = 0x42c, | |
1041 | .clr_ofs = 0x42c, | |
1042 | .sta_ofs = 0x42c, | |
1043 | }; | |
1044 | ||
1045 | #define GATE_PERI0(_id, _name, _parent, _shift) { \ | |
1046 | .id = _id, \ | |
1047 | .name = _name, \ | |
1048 | .parent_name = _parent, \ | |
1049 | .regs = &peri0_cg_regs, \ | |
1050 | .shift = _shift, \ | |
1051 | .ops = &mtk_clk_gate_ops_setclr, \ | |
1052 | } | |
1053 | ||
1054 | #define GATE_PERI1(_id, _name, _parent, _shift) { \ | |
1055 | .id = _id, \ | |
1056 | .name = _name, \ | |
1057 | .parent_name = _parent, \ | |
1058 | .regs = &peri1_cg_regs, \ | |
1059 | .shift = _shift, \ | |
1060 | .ops = &mtk_clk_gate_ops_setclr, \ | |
1061 | } | |
1062 | ||
1063 | #define GATE_PERI2(_id, _name, _parent, _shift) { \ | |
1064 | .id = _id, \ | |
1065 | .name = _name, \ | |
1066 | .parent_name = _parent, \ | |
1067 | .regs = &peri2_cg_regs, \ | |
1068 | .shift = _shift, \ | |
1069 | .ops = &mtk_clk_gate_ops_no_setclr_inv, \ | |
1070 | } | |
1071 | ||
1072 | static const struct mtk_gate peri_clks[] = { | |
1073 | /* PERI0 */ | |
1074 | GATE_PERI0(CLK_PERI_NFI, "per_nfi", | |
1075 | "axi_sel", 0), | |
1076 | GATE_PERI0(CLK_PERI_THERM, "per_therm", | |
1077 | "axi_sel", 1), | |
1078 | GATE_PERI0(CLK_PERI_PWM0, "per_pwm0", | |
1079 | "pwm_sel", 2), | |
1080 | GATE_PERI0(CLK_PERI_PWM1, "per_pwm1", | |
1081 | "pwm_sel", 3), | |
1082 | GATE_PERI0(CLK_PERI_PWM2, "per_pwm2", | |
1083 | "pwm_sel", 4), | |
1084 | GATE_PERI0(CLK_PERI_PWM3, "per_pwm3", | |
1085 | "pwm_sel", 5), | |
1086 | GATE_PERI0(CLK_PERI_PWM4, "per_pwm4", | |
1087 | "pwm_sel", 6), | |
1088 | GATE_PERI0(CLK_PERI_PWM5, "per_pwm5", | |
1089 | "pwm_sel", 7), | |
1090 | GATE_PERI0(CLK_PERI_PWM6, "per_pwm6", | |
1091 | "pwm_sel", 8), | |
1092 | GATE_PERI0(CLK_PERI_PWM7, "per_pwm7", | |
1093 | "pwm_sel", 9), | |
1094 | GATE_PERI0(CLK_PERI_PWM, "per_pwm", | |
1095 | "pwm_sel", 10), | |
1096 | GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma", | |
1097 | "axi_sel", 13), | |
1098 | GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0", | |
1099 | "msdc50_0_sel", 14), | |
1100 | GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1", | |
1101 | "msdc30_1_sel", 15), | |
1102 | GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2", | |
1103 | "msdc30_2_sel", 16), | |
1104 | GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3", | |
1105 | "msdc30_3_sel", 17), | |
1106 | GATE_PERI0(CLK_PERI_UART0, "per_uart0", | |
1107 | "uart_sel", 20), | |
1108 | GATE_PERI0(CLK_PERI_UART1, "per_uart1", | |
1109 | "uart_sel", 21), | |
1110 | GATE_PERI0(CLK_PERI_UART2, "per_uart2", | |
1111 | "uart_sel", 22), | |
1112 | GATE_PERI0(CLK_PERI_UART3, "per_uart3", | |
1113 | "uart_sel", 23), | |
1114 | GATE_PERI0(CLK_PERI_I2C0, "per_i2c0", | |
1115 | "axi_sel", 24), | |
1116 | GATE_PERI0(CLK_PERI_I2C1, "per_i2c1", | |
1117 | "axi_sel", 25), | |
1118 | GATE_PERI0(CLK_PERI_I2C2, "per_i2c2", | |
1119 | "axi_sel", 26), | |
1120 | GATE_PERI0(CLK_PERI_I2C3, "per_i2c3", | |
1121 | "axi_sel", 27), | |
1122 | GATE_PERI0(CLK_PERI_I2C4, "per_i2c4", | |
1123 | "axi_sel", 28), | |
1124 | GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc", | |
1125 | "ltepll_fs26m", 29), | |
1126 | GATE_PERI0(CLK_PERI_SPI0, "per_spi0", | |
1127 | "spi_sel", 30), | |
1128 | /* PERI1 */ | |
1129 | GATE_PERI1(CLK_PERI_SPI, "per_spi", | |
1130 | "spinor_sel", 1), | |
1131 | GATE_PERI1(CLK_PERI_I2C5, "per_i2c5", | |
1132 | "axi_sel", 3), | |
1133 | GATE_PERI1(CLK_PERI_SPI2, "per_spi2", | |
1134 | "spi_sel", 5), | |
1135 | GATE_PERI1(CLK_PERI_SPI3, "per_spi3", | |
1136 | "spi_sel", 6), | |
1137 | GATE_PERI1(CLK_PERI_SPI5, "per_spi5", | |
1138 | "spi_sel", 8), | |
1139 | GATE_PERI1(CLK_PERI_UART4, "per_uart4", | |
1140 | "uart_sel", 9), | |
1141 | GATE_PERI1(CLK_PERI_SFLASH, "per_sflash", | |
1142 | "uart_sel", 11), | |
1143 | GATE_PERI1(CLK_PERI_GMAC, "per_gmac", | |
1144 | "uart_sel", 12), | |
1145 | GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0", | |
1146 | "uart_sel", 14), | |
1147 | GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1", | |
1148 | "uart_sel", 15), | |
1149 | GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk", | |
1150 | "uart_sel", 16), | |
1151 | /* PERI2 */ | |
1152 | GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en", | |
1153 | "msdc50_0_sel", 0), | |
1154 | GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en", | |
1155 | "msdc30_1_sel", 1), | |
1156 | GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en", | |
1157 | "msdc30_2_sel", 2), | |
1158 | GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en", | |
1159 | "msdc30_3_sel", 3), | |
1160 | GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h", | |
1161 | "msdc50_0_h_sel", 4), | |
1162 | GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h", | |
1163 | "msdc50_3_h_sel", 5), | |
f72595cf WL |
1164 | GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q", |
1165 | "axi_sel", 6), | |
1166 | GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q", | |
1167 | "mem_sel", 7), | |
e2f744a8 | 1168 | }; |
1169 | ||
1170 | #define MT2712_PLL_FMAX (3000UL * MHZ) | |
1171 | ||
1172 | #define CON0_MT2712_RST_BAR BIT(24) | |
1173 | ||
1174 | #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ | |
1175 | _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ | |
1176 | _tuner_en_bit, _pcw_reg, _pcw_shift, \ | |
1177 | _div_table) { \ | |
1178 | .id = _id, \ | |
1179 | .name = _name, \ | |
1180 | .reg = _reg, \ | |
1181 | .pwr_reg = _pwr_reg, \ | |
1182 | .en_mask = _en_mask, \ | |
1183 | .flags = _flags, \ | |
1184 | .rst_bar_mask = CON0_MT2712_RST_BAR, \ | |
1185 | .fmax = MT2712_PLL_FMAX, \ | |
1186 | .pcwbits = _pcwbits, \ | |
1187 | .pd_reg = _pd_reg, \ | |
1188 | .pd_shift = _pd_shift, \ | |
1189 | .tuner_reg = _tuner_reg, \ | |
1190 | .tuner_en_reg = _tuner_en_reg, \ | |
1191 | .tuner_en_bit = _tuner_en_bit, \ | |
1192 | .pcw_reg = _pcw_reg, \ | |
1193 | .pcw_shift = _pcw_shift, \ | |
1194 | .div_table = _div_table, \ | |
1195 | } | |
1196 | ||
1197 | #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ | |
1198 | _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ | |
1199 | _tuner_en_bit, _pcw_reg, _pcw_shift) \ | |
1200 | PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ | |
1201 | _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \ | |
1202 | _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ | |
1203 | _pcw_shift, NULL) | |
1204 | ||
1205 | static const struct mtk_pll_div_table armca35pll_div_table[] = { | |
1206 | { .div = 0, .freq = MT2712_PLL_FMAX }, | |
1207 | { .div = 1, .freq = 1202500000 }, | |
1208 | { .div = 2, .freq = 500500000 }, | |
1209 | { .div = 3, .freq = 315250000 }, | |
1210 | { .div = 4, .freq = 157625000 }, | |
1211 | { } /* sentinel */ | |
1212 | }; | |
1213 | ||
1214 | static const struct mtk_pll_div_table armca72pll_div_table[] = { | |
1215 | { .div = 0, .freq = MT2712_PLL_FMAX }, | |
1216 | { .div = 1, .freq = 994500000 }, | |
1217 | { .div = 2, .freq = 520000000 }, | |
1218 | { .div = 3, .freq = 315250000 }, | |
1219 | { .div = 4, .freq = 157625000 }, | |
1220 | { } /* sentinel */ | |
1221 | }; | |
1222 | ||
1223 | static const struct mtk_pll_div_table mmpll_div_table[] = { | |
1224 | { .div = 0, .freq = MT2712_PLL_FMAX }, | |
1225 | { .div = 1, .freq = 1001000000 }, | |
1226 | { .div = 2, .freq = 601250000 }, | |
1227 | { .div = 3, .freq = 250250000 }, | |
1228 | { .div = 4, .freq = 125125000 }, | |
1229 | { } /* sentinel */ | |
1230 | }; | |
1231 | ||
1232 | static const struct mtk_pll_data plls[] = { | |
1233 | PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101, | |
1234 | HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0), | |
1235 | PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101, | |
1236 | HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0), | |
1237 | PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101, | |
1238 | 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0), | |
1239 | PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101, | |
1240 | 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0), | |
1241 | PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101, | |
1242 | 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0), | |
1243 | PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101, | |
1244 | 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0), | |
1245 | PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101, | |
1246 | 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0), | |
1247 | PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101, | |
1248 | 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0), | |
1249 | PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101, | |
1250 | 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0), | |
1251 | PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101, | |
1252 | 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0), | |
1253 | PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101, | |
1254 | 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0), | |
1255 | PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101, | |
1256 | 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, | |
1257 | mmpll_div_table), | |
1258 | PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101, | |
1259 | HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, | |
1260 | armca35pll_div_table), | |
1261 | PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101, | |
1262 | 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, | |
1263 | armca72pll_div_table), | |
1264 | PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101, | |
1265 | 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), | |
1266 | }; | |
1267 | ||
1268 | static int clk_mt2712_apmixed_probe(struct platform_device *pdev) | |
1269 | { | |
1270 | struct clk_onecell_data *clk_data; | |
1271 | int r; | |
1272 | struct device_node *node = pdev->dev.of_node; | |
1273 | ||
1274 | clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); | |
1275 | ||
1276 | mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); | |
1277 | ||
1278 | r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); | |
1279 | ||
1280 | if (r != 0) | |
1281 | pr_err("%s(): could not register clock provider: %d\n", | |
1282 | __func__, r); | |
1283 | ||
1284 | return r; | |
1285 | } | |
1286 | ||
1287 | static struct clk_onecell_data *top_clk_data; | |
1288 | ||
1289 | static void clk_mt2712_top_init_early(struct device_node *node) | |
1290 | { | |
1291 | int r, i; | |
1292 | ||
1293 | if (!top_clk_data) { | |
1294 | top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); | |
1295 | ||
1296 | for (i = 0; i < CLK_TOP_NR_CLK; i++) | |
1297 | top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); | |
1298 | } | |
1299 | ||
1300 | mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), | |
1301 | top_clk_data); | |
1302 | ||
1303 | r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); | |
1304 | if (r) | |
1305 | pr_err("%s(): could not register clock provider: %d\n", | |
1306 | __func__, r); | |
1307 | } | |
1308 | ||
1309 | CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen", | |
1310 | clk_mt2712_top_init_early); | |
1311 | ||
1312 | static int clk_mt2712_top_probe(struct platform_device *pdev) | |
1313 | { | |
1314 | int r, i; | |
1315 | struct device_node *node = pdev->dev.of_node; | |
1316 | void __iomem *base; | |
1317 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1318 | ||
1319 | base = devm_ioremap_resource(&pdev->dev, res); | |
1320 | if (IS_ERR(base)) { | |
1321 | pr_err("%s(): ioremap failed\n", __func__); | |
1322 | return PTR_ERR(base); | |
1323 | } | |
1324 | ||
1325 | if (!top_clk_data) { | |
1326 | top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); | |
1327 | } else { | |
1328 | for (i = 0; i < CLK_TOP_NR_CLK; i++) { | |
1329 | if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER)) | |
1330 | top_clk_data->clks[i] = ERR_PTR(-ENOENT); | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), | |
1335 | top_clk_data); | |
1336 | mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), | |
1337 | top_clk_data); | |
1338 | mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); | |
1339 | mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, | |
1340 | &mt2712_clk_lock, top_clk_data); | |
1341 | mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, | |
1342 | &mt2712_clk_lock, top_clk_data); | |
1343 | mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), | |
1344 | top_clk_data); | |
1345 | ||
1346 | r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); | |
1347 | ||
1348 | if (r != 0) | |
1349 | pr_err("%s(): could not register clock provider: %d\n", | |
1350 | __func__, r); | |
1351 | ||
1352 | return r; | |
1353 | } | |
1354 | ||
1355 | static int clk_mt2712_infra_probe(struct platform_device *pdev) | |
1356 | { | |
1357 | struct clk_onecell_data *clk_data; | |
1358 | int r; | |
1359 | struct device_node *node = pdev->dev.of_node; | |
1360 | ||
1361 | clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); | |
1362 | ||
1363 | mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), | |
1364 | clk_data); | |
1365 | ||
1366 | r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); | |
1367 | ||
1368 | if (r != 0) | |
1369 | pr_err("%s(): could not register clock provider: %d\n", | |
1370 | __func__, r); | |
1371 | ||
1372 | mtk_register_reset_controller(node, 2, 0x30); | |
1373 | ||
1374 | return r; | |
1375 | } | |
1376 | ||
1377 | static int clk_mt2712_peri_probe(struct platform_device *pdev) | |
1378 | { | |
1379 | struct clk_onecell_data *clk_data; | |
1380 | int r; | |
1381 | struct device_node *node = pdev->dev.of_node; | |
1382 | ||
1383 | clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); | |
1384 | ||
1385 | mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), | |
1386 | clk_data); | |
1387 | ||
1388 | r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); | |
1389 | ||
1390 | if (r != 0) | |
1391 | pr_err("%s(): could not register clock provider: %d\n", | |
1392 | __func__, r); | |
1393 | ||
1394 | mtk_register_reset_controller(node, 2, 0); | |
1395 | ||
1396 | return r; | |
1397 | } | |
1398 | ||
1399 | static int clk_mt2712_mcu_probe(struct platform_device *pdev) | |
1400 | { | |
1401 | struct clk_onecell_data *clk_data; | |
1402 | int r; | |
1403 | struct device_node *node = pdev->dev.of_node; | |
1404 | void __iomem *base; | |
1405 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1406 | ||
1407 | base = devm_ioremap_resource(&pdev->dev, res); | |
1408 | if (IS_ERR(base)) { | |
1409 | pr_err("%s(): ioremap failed\n", __func__); | |
1410 | return PTR_ERR(base); | |
1411 | } | |
1412 | ||
1413 | clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); | |
1414 | ||
1415 | mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, | |
1416 | &mt2712_clk_lock, clk_data); | |
1417 | ||
1418 | r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); | |
1419 | ||
1420 | if (r != 0) | |
1421 | pr_err("%s(): could not register clock provider: %d\n", | |
1422 | __func__, r); | |
1423 | ||
1424 | return r; | |
1425 | } | |
1426 | ||
1427 | static const struct of_device_id of_match_clk_mt2712[] = { | |
1428 | { | |
1429 | .compatible = "mediatek,mt2712-apmixedsys", | |
1430 | .data = clk_mt2712_apmixed_probe, | |
1431 | }, { | |
1432 | .compatible = "mediatek,mt2712-topckgen", | |
1433 | .data = clk_mt2712_top_probe, | |
1434 | }, { | |
1435 | .compatible = "mediatek,mt2712-infracfg", | |
1436 | .data = clk_mt2712_infra_probe, | |
1437 | }, { | |
1438 | .compatible = "mediatek,mt2712-pericfg", | |
1439 | .data = clk_mt2712_peri_probe, | |
1440 | }, { | |
1441 | .compatible = "mediatek,mt2712-mcucfg", | |
1442 | .data = clk_mt2712_mcu_probe, | |
1443 | }, { | |
1444 | /* sentinel */ | |
1445 | } | |
1446 | }; | |
1447 | ||
1448 | static int clk_mt2712_probe(struct platform_device *pdev) | |
1449 | { | |
1450 | int (*clk_probe)(struct platform_device *); | |
1451 | int r; | |
1452 | ||
1453 | clk_probe = of_device_get_match_data(&pdev->dev); | |
1454 | if (!clk_probe) | |
1455 | return -EINVAL; | |
1456 | ||
1457 | r = clk_probe(pdev); | |
1458 | if (r != 0) | |
1459 | dev_err(&pdev->dev, | |
1460 | "could not register clock provider: %s: %d\n", | |
1461 | pdev->name, r); | |
1462 | ||
1463 | return r; | |
1464 | } | |
1465 | ||
1466 | static struct platform_driver clk_mt2712_drv = { | |
1467 | .probe = clk_mt2712_probe, | |
1468 | .driver = { | |
1469 | .name = "clk-mt2712", | |
e2f744a8 | 1470 | .of_match_table = of_match_clk_mt2712, |
1471 | }, | |
1472 | }; | |
1473 | ||
1474 | static int __init clk_mt2712_init(void) | |
1475 | { | |
1476 | return platform_driver_register(&clk_mt2712_drv); | |
1477 | } | |
1478 | ||
1479 | arch_initcall(clk_mt2712_init); |