projects / mirror_ubuntu-jammy-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| a6822483 FP |
1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* | |
| 3 | * Copyright (c) 2020 MediaTek Inc. | |
| 4 | * Copyright (c) 2020 BayLibre, SAS | |
| 5 | * Author: James Liao <jamesjj.liao@mediatek.com> | |
| 6 | * Fabien Parent <fparent@baylibre.com> | |
| 7 | */ | |
| 8 | ||
| 9 | #include <linux/clk-provider.h> | |
| 10 | #include <linux/of.h> | |
| 11 | #include <linux/of_address.h> | |
| 12 | #include <linux/of_device.h> | |
| 13 | #include <linux/platform_device.h> | |
| 14 | ||
| 15 | #include "clk-mtk.h" | |
| 16 | #include "clk-gate.h" | |
| 17 | ||
| 18 | #include <dt-bindings/clock/mt8167-clk.h> | |
| 19 | ||
| 20 | static const struct mtk_gate_regs mm0_cg_regs = { | |
| 21 | .set_ofs = 0x104, | |
| 22 | .clr_ofs = 0x108, | |
| 23 | .sta_ofs = 0x100, | |
| 24 | }; | |
| 25 | ||
| 26 | static const struct mtk_gate_regs mm1_cg_regs = { | |
| 27 | .set_ofs = 0x114, | |
| 28 | .clr_ofs = 0x118, | |
| 29 | .sta_ofs = 0x110, | |
| 30 | }; | |
| 31 | ||
| 32 | #define GATE_MM0(_id, _name, _parent, _shift) { \ | |
| 33 | .id = _id, \ | |
| 34 | .name = _name, \ | |
| 35 | .parent_name = _parent, \ | |
| 36 | .regs = &mm0_cg_regs, \ | |
| 37 | .shift = _shift, \ | |
| 38 | .ops = &mtk_clk_gate_ops_setclr, \ | |
| 39 | } | |
| 40 | ||
| 41 | #define GATE_MM1(_id, _name, _parent, _shift) { \ | |
| 42 | .id = _id, \ | |
| 43 | .name = _name, \ | |
| 44 | .parent_name = _parent, \ | |
| 45 | .regs = &mm1_cg_regs, \ | |
| 46 | .shift = _shift, \ | |
| 47 | .ops = &mtk_clk_gate_ops_setclr, \ | |
| 48 | } | |
| 49 | ||
| 50 | static const struct mtk_gate mm_clks[] = { | |
| 51 | /* MM0 */ | |
| 52 | GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "smi_mm", 0), | |
| 53 | GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "smi_mm", 1), | |
| 54 | GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "smi_mm", 2), | |
| 55 | GATE_MM0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "smi_mm", 3), | |
| 56 | GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "smi_mm", 4), | |
| 57 | GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "smi_mm", 5), | |
| 58 | GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "smi_mm", 6), | |
| 59 | GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "smi_mm", 7), | |
| 60 | GATE_MM0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "smi_mm", 8), | |
| 61 | GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "smi_mm", 9), | |
| 62 | GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "smi_mm", 10), | |
| 63 | GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "smi_mm", 11), | |
| 64 | GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "smi_mm", 12), | |
| 65 | GATE_MM0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "smi_mm", 13), | |
| 66 | GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "smi_mm", 14), | |
| 67 | GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "smi_mm", 15), | |
| 68 | GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "smi_mm", 16), | |
| 69 | GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "smi_mm", 17), | |
| 70 | GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "smi_mm", 18), | |
| 71 | GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "smi_mm", 19), | |
| 72 | /* MM1 */ | |
| 73 | GATE_MM1(CLK_MM_DISP_PWM_MM, "mm_disp_pwm_mm", "smi_mm", 0), | |
| 74 | GATE_MM1(CLK_MM_DISP_PWM_26M, "mm_disp_pwm_26m", "smi_mm", 1), | |
| 75 | GATE_MM1(CLK_MM_DSI_ENGINE, "mm_dsi_engine", "smi_mm", 2), | |
| 76 | GATE_MM1(CLK_MM_DSI_DIGITAL, "mm_dsi_digital", "dsi0_lntc_dsick", 3), | |
| 77 | GATE_MM1(CLK_MM_DPI0_ENGINE, "mm_dpi0_engine", "smi_mm", 4), | |
| 78 | GATE_MM1(CLK_MM_DPI0_PXL, "mm_dpi0_pxl", "rg_fdpi0", 5), | |
| 79 | GATE_MM1(CLK_MM_LVDS_PXL, "mm_lvds_pxl", "vpll_dpix", 14), | |
| 80 | GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx_dig_cts", 15), | |
| 81 | GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "smi_mm", 16), | |
| 82 | GATE_MM1(CLK_MM_DPI1_PXL, "mm_dpi1_pxl", "rg_fdpi1", 17), | |
| 83 | GATE_MM1(CLK_MM_HDMI_PXL, "mm_hdmi_pxl", "rg_fdpi1", 18), | |
| 84 | GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll12_div6", 19), | |
| 85 | GATE_MM1(CLK_MM_HDMI_ADSP_BCK, "mm_hdmi_adsp_b", "apll12_div4b", 20), | |
| 86 | GATE_MM1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmtx_dig_cts", 21), | |
| 87 | }; | |
| 88 | ||
| 89 | struct clk_mt8167_mm_driver_data { | |
| 90 | const struct mtk_gate *gates_clk; | |
| 91 | int gates_num; | |
| 92 | }; | |
| 93 | ||
| 94 | static const struct clk_mt8167_mm_driver_data mt8167_mmsys_driver_data = { | |
| 95 | .gates_clk = mm_clks, | |
| 96 | .gates_num = ARRAY_SIZE(mm_clks), | |
| 97 | }; | |
| 98 | ||
| 99 | static int clk_mt8167_mm_probe(struct platform_device *pdev) | |
| 100 | { | |
| 101 | struct device *dev = &pdev->dev; | |
| 102 | struct device_node *node = dev->parent->of_node; | |
| 103 | const struct clk_mt8167_mm_driver_data *data; | |
| 104 | struct clk_onecell_data *clk_data; | |
| 105 | int ret; | |
| 106 | ||
| 107 | clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); | |
| 108 | if (!clk_data) | |
| 109 | return -ENOMEM; | |
| 110 | ||
| 111 | data = &mt8167_mmsys_driver_data; | |
| 112 | ||
| 113 | ret = mtk_clk_register_gates(node, data->gates_clk, data->gates_num, | |
| 114 | clk_data); | |
| 115 | if (ret) | |
| 116 | return ret; | |
| 117 | ||
| 118 | ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); | |
| 119 | if (ret) | |
| 120 | return ret; | |
| 121 | ||
| 122 | return 0; | |
| 123 | } | |
| 124 | ||
| 125 | static struct platform_driver clk_mt8173_mm_drv = { | |
| 126 | .driver = { | |
| 127 | .name = "clk-mt8167-mm", | |
| 128 | }, | |
| 129 | .probe = clk_mt8167_mm_probe, | |
| 130 | }; | |
| 131 | ||
| 132 | builtin_platform_driver(clk_mt8173_mm_drv); |