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7a29a869 CC |
1 | /* |
2 | * Copyright (c) 2015 Endless Mobile, Inc. | |
3 | * Author: Carlo Caione <carlo@endlessm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef __CLKC_H | |
19 | #define __CLKC_H | |
20 | ||
21 | #define PMASK(width) GENMASK(width - 1, 0) | |
22 | #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) | |
23 | #define CLRPMASK(width, shift) (~SETPMASK(width, shift)) | |
24 | ||
25 | #define PARM_GET(width, shift, reg) \ | |
26 | (((reg) & SETPMASK(width, shift)) >> (shift)) | |
27 | #define PARM_SET(width, shift, reg, val) \ | |
1ddfe82e | 28 | (((reg) & CLRPMASK(width, shift)) | ((val) << (shift))) |
7a29a869 CC |
29 | |
30 | #define MESON_PARM_APPLICABLE(p) (!!((p)->width)) | |
31 | ||
32 | struct parm { | |
33 | u16 reg_off; | |
34 | u8 shift; | |
35 | u8 width; | |
36 | }; | |
ec623f2a | 37 | |
7a29a869 CC |
38 | struct pll_rate_table { |
39 | unsigned long rate; | |
40 | u16 m; | |
41 | u16 n; | |
42 | u16 od; | |
4a472951 MT |
43 | u16 od2; |
44 | u16 frac; | |
7a29a869 | 45 | }; |
4a472951 | 46 | |
7a29a869 CC |
47 | #define PLL_RATE(_r, _m, _n, _od) \ |
48 | { \ | |
49 | .rate = (_r), \ | |
50 | .m = (_m), \ | |
51 | .n = (_n), \ | |
52 | .od = (_od), \ | |
53 | } \ | |
54 | ||
4a472951 MT |
55 | #define PLL_FRAC_RATE(_r, _m, _n, _od, _od2, _frac) \ |
56 | { \ | |
57 | .rate = (_r), \ | |
58 | .m = (_m), \ | |
59 | .n = (_n), \ | |
60 | .od = (_od), \ | |
61 | .od2 = (_od2), \ | |
62 | .frac = (_frac), \ | |
63 | } \ | |
64 | ||
45fcbec7 NA |
65 | struct pll_params_table { |
66 | unsigned int reg_off; | |
67 | unsigned int value; | |
68 | }; | |
69 | ||
70 | #define PLL_PARAM(_reg, _val) \ | |
71 | { \ | |
72 | .reg_off = (_reg), \ | |
73 | .value = (_val), \ | |
74 | } | |
75 | ||
76 | struct pll_setup_params { | |
77 | struct pll_params_table *params_table; | |
78 | unsigned int params_count; | |
79 | /* Workaround for GP0, do not reset before configuring */ | |
80 | bool no_init_reset; | |
81 | /* Workaround for GP0, unreset right before checking for lock */ | |
82 | bool clear_reset_for_lock; | |
83 | /* Workaround for GXL GP0, reset in the lock checking loop */ | |
84 | bool reset_lock_loop; | |
85 | }; | |
86 | ||
ec623f2a MT |
87 | struct meson_clk_pll { |
88 | struct clk_hw hw; | |
89 | void __iomem *base; | |
90 | struct parm m; | |
91 | struct parm n; | |
4a472951 | 92 | struct parm frac; |
ec623f2a | 93 | struct parm od; |
4a472951 | 94 | struct parm od2; |
45fcbec7 | 95 | const struct pll_setup_params params; |
ec623f2a MT |
96 | const struct pll_rate_table *rate_table; |
97 | unsigned int rate_count; | |
98 | spinlock_t *lock; | |
7a29a869 CC |
99 | }; |
100 | ||
ec623f2a MT |
101 | #define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw) |
102 | ||
55d42c40 MT |
103 | struct meson_clk_cpu { |
104 | struct clk_hw hw; | |
105 | void __iomem *base; | |
106 | u16 reg_off; | |
107 | struct notifier_block clk_nb; | |
108 | const struct clk_div_table *div_table; | |
109 | }; | |
110 | ||
55d42c40 MT |
111 | int meson_clk_cpu_notifier_cb(struct notifier_block *nb, unsigned long event, |
112 | void *data); | |
ec623f2a | 113 | |
1c50da4f MT |
114 | struct meson_clk_mpll { |
115 | struct clk_hw hw; | |
116 | void __iomem *base; | |
117 | struct parm sdm; | |
007e6e5c | 118 | struct parm sdm_en; |
1c50da4f | 119 | struct parm n2; |
007e6e5c | 120 | struct parm en; |
1c50da4f MT |
121 | spinlock_t *lock; |
122 | }; | |
123 | ||
59e85335 JB |
124 | struct meson_clk_audio_divider { |
125 | struct clk_hw hw; | |
126 | void __iomem *base; | |
127 | struct parm div; | |
128 | u8 flags; | |
129 | spinlock_t *lock; | |
130 | }; | |
131 | ||
73de5c8b | 132 | #define MESON_GATE(_name, _reg, _bit) \ |
7ba64d82 | 133 | struct clk_gate _name = { \ |
73de5c8b MT |
134 | .reg = (void __iomem *) _reg, \ |
135 | .bit_idx = (_bit), \ | |
136 | .lock = &clk_lock, \ | |
137 | .hw.init = &(struct clk_init_data) { \ | |
138 | .name = #_name, \ | |
139 | .ops = &clk_gate_ops, \ | |
140 | .parent_names = (const char *[]){ "clk81" }, \ | |
141 | .num_parents = 1, \ | |
142 | .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ | |
143 | }, \ | |
144 | }; | |
145 | ||
ec623f2a MT |
146 | /* clk_ops */ |
147 | extern const struct clk_ops meson_clk_pll_ro_ops; | |
148 | extern const struct clk_ops meson_clk_pll_ops; | |
55d42c40 | 149 | extern const struct clk_ops meson_clk_cpu_ops; |
1c50da4f | 150 | extern const struct clk_ops meson_clk_mpll_ro_ops; |
007e6e5c | 151 | extern const struct clk_ops meson_clk_mpll_ops; |
59e85335 JB |
152 | extern const struct clk_ops meson_clk_audio_divider_ro_ops; |
153 | extern const struct clk_ops meson_clk_audio_divider_ops; | |
7a29a869 CC |
154 | |
155 | #endif /* __CLKC_H */ |