]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blame - drivers/clk/meson/meson8b.c
projects / mirror_ubuntu-focal-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[mirror_ubuntu-focal-kernel.git] / drivers / clk / meson / meson8b.c
CommitLineData
28b9fcd0 1/*
855f06a1
MB		 2 * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
3 * Driver
a718ce38 4 *
28b9fcd0
CC		 5 * Copyright (c) 2015 Endless Mobile, Inc.
6 * Author: Carlo Caione <carlo@endlessm.com>
7 *
796b9aa8
MT		 8 * Copyright (c) 2016 BayLibre, Inc.
9 * Michael Turquette <mturquette@baylibre.com>
10 *
28b9fcd0
CC		 11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms and conditions of the GNU General Public License,
13 * version 2, as published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program. If not, see <http://www.gnu.org/licenses/>.
22 */
23
55d42c40 24#include <linux/clk.h>
28b9fcd0 25#include <linux/clk-provider.h>
28b9fcd0 26#include <linux/of_address.h>
796b9aa8 27#include <linux/platform_device.h>
18962172
MB		 28#include <linux/reset-controller.h>
29#include <linux/slab.h>
a718ce38 30#include <linux/init.h>
28b9fcd0
CC		 31
32#include "clkc.h"
d0c175da 33#include "meson8b.h"
28b9fcd0 34
c0daa3e6
MT		 35static DEFINE_SPINLOCK(clk_lock);
36
18962172
MB		 37static void __iomem *clk_base;
38
39struct meson8b_clk_reset {
40 struct reset_controller_dev reset;
41 void __iomem *base;
42};
43
28b9fcd0
CC		 44static const struct pll_rate_table sys_pll_rate_table[] = {
45 PLL_RATE(312000000, 52, 1, 2),
46 PLL_RATE(336000000, 56, 1, 2),
47 PLL_RATE(360000000, 60, 1, 2),
48 PLL_RATE(384000000, 64, 1, 2),
49 PLL_RATE(408000000, 68, 1, 2),
50 PLL_RATE(432000000, 72, 1, 2),
51 PLL_RATE(456000000, 76, 1, 2),
52 PLL_RATE(480000000, 80, 1, 2),
53 PLL_RATE(504000000, 84, 1, 2),
54 PLL_RATE(528000000, 88, 1, 2),
55 PLL_RATE(552000000, 92, 1, 2),
56 PLL_RATE(576000000, 96, 1, 2),
57 PLL_RATE(600000000, 50, 1, 1),
58 PLL_RATE(624000000, 52, 1, 1),
59 PLL_RATE(648000000, 54, 1, 1),
60 PLL_RATE(672000000, 56, 1, 1),
61 PLL_RATE(696000000, 58, 1, 1),
62 PLL_RATE(720000000, 60, 1, 1),
63 PLL_RATE(744000000, 62, 1, 1),
64 PLL_RATE(768000000, 64, 1, 1),
65 PLL_RATE(792000000, 66, 1, 1),
66 PLL_RATE(816000000, 68, 1, 1),
67 PLL_RATE(840000000, 70, 1, 1),
68 PLL_RATE(864000000, 72, 1, 1),
69 PLL_RATE(888000000, 74, 1, 1),
70 PLL_RATE(912000000, 76, 1, 1),
71 PLL_RATE(936000000, 78, 1, 1),
72 PLL_RATE(960000000, 80, 1, 1),
73 PLL_RATE(984000000, 82, 1, 1),
74 PLL_RATE(1008000000, 84, 1, 1),
75 PLL_RATE(1032000000, 86, 1, 1),
76 PLL_RATE(1056000000, 88, 1, 1),
77 PLL_RATE(1080000000, 90, 1, 1),
78 PLL_RATE(1104000000, 92, 1, 1),
79 PLL_RATE(1128000000, 94, 1, 1),
80 PLL_RATE(1152000000, 96, 1, 1),
81 PLL_RATE(1176000000, 98, 1, 1),
82 PLL_RATE(1200000000, 50, 1, 0),
83 PLL_RATE(1224000000, 51, 1, 0),
84 PLL_RATE(1248000000, 52, 1, 0),
85 PLL_RATE(1272000000, 53, 1, 0),
86 PLL_RATE(1296000000, 54, 1, 0),
87 PLL_RATE(1320000000, 55, 1, 0),
88 PLL_RATE(1344000000, 56, 1, 0),
89 PLL_RATE(1368000000, 57, 1, 0),
90 PLL_RATE(1392000000, 58, 1, 0),
91 PLL_RATE(1416000000, 59, 1, 0),
92 PLL_RATE(1440000000, 60, 1, 0),
93 PLL_RATE(1464000000, 61, 1, 0),
94 PLL_RATE(1488000000, 62, 1, 0),
95 PLL_RATE(1512000000, 63, 1, 0),
96 PLL_RATE(1536000000, 64, 1, 0),
97 { /* sentinel */ },
98};
99
100static const struct clk_div_table cpu_div_table[] = {
101 { .val = 1, .div = 1 },
102 { .val = 2, .div = 2 },
103 { .val = 3, .div = 3 },
104 { .val = 2, .div = 4 },
105 { .val = 3, .div = 6 },
106 { .val = 4, .div = 8 },
107 { .val = 5, .div = 10 },
108 { .val = 6, .div = 12 },
109 { .val = 7, .div = 14 },
110 { .val = 8, .div = 16 },
111 { /* sentinel */ },
112};
113
e92f7cca
MT		 114static struct clk_fixed_rate meson8b_xtal = {
115 .fixed_rate = 24000000,
116 .hw.init = &(struct clk_init_data){
117 .name = "xtal",
118 .num_parents = 0,
119 .ops = &clk_fixed_rate_ops,
120 },
121};
122
ec623f2a
MT		 123static struct meson_clk_pll meson8b_fixed_pll = {
124 .m = {
e0818a39 125 .reg_off = HHI_MPLL_CNTL,
ec623f2a
MT		 126 .shift = 0,
127 .width = 9,
128 },
129 .n = {
e0818a39 130 .reg_off = HHI_MPLL_CNTL,
ec623f2a
MT		 131 .shift = 9,
132 .width = 5,
133 },
134 .od = {
e0818a39 135 .reg_off = HHI_MPLL_CNTL,
ec623f2a
MT		 136 .shift = 16,
137 .width = 2,
138 },
139 .lock = &clk_lock,
140 .hw.init = &(struct clk_init_data){
141 .name = "fixed_pll",
142 .ops = &meson_clk_pll_ro_ops,
143 .parent_names = (const char *[]){ "xtal" },
144 .num_parents = 1,
145 .flags = CLK_GET_RATE_NOCACHE,
146 },
147};
148
149static struct meson_clk_pll meson8b_vid_pll = {
150 .m = {
e0818a39 151 .reg_off = HHI_VID_PLL_CNTL,
ec623f2a
MT		 152 .shift = 0,
153 .width = 9,
154 },
155 .n = {
e0818a39 156 .reg_off = HHI_VID_PLL_CNTL,
ec623f2a
MT		 157 .shift = 9,
158 .width = 5,
159 },
160 .od = {
e0818a39 161 .reg_off = HHI_VID_PLL_CNTL,
ec623f2a
MT		 162 .shift = 16,
163 .width = 2,
164 },
165 .lock = &clk_lock,
166 .hw.init = &(struct clk_init_data){
167 .name = "vid_pll",
168 .ops = &meson_clk_pll_ro_ops,
169 .parent_names = (const char *[]){ "xtal" },
170 .num_parents = 1,
171 .flags = CLK_GET_RATE_NOCACHE,
172 },
173};
174
175static struct meson_clk_pll meson8b_sys_pll = {
176 .m = {
e0818a39 177 .reg_off = HHI_SYS_PLL_CNTL,
ec623f2a
MT		 178 .shift = 0,
179 .width = 9,
180 },
181 .n = {
e0818a39 182 .reg_off = HHI_SYS_PLL_CNTL,
ec623f2a
MT		 183 .shift = 9,
184 .width = 5,
185 },
186 .od = {
e0818a39 187 .reg_off = HHI_SYS_PLL_CNTL,
ec623f2a
MT		 188 .shift = 16,
189 .width = 2,
190 },
191 .rate_table = sys_pll_rate_table,
192 .rate_count = ARRAY_SIZE(sys_pll_rate_table),
193 .lock = &clk_lock,
194 .hw.init = &(struct clk_init_data){
195 .name = "sys_pll",
196 .ops = &meson_clk_pll_ops,
197 .parent_names = (const char *[]){ "xtal" },
198 .num_parents = 1,
199 .flags = CLK_GET_RATE_NOCACHE,
200 },
201};
202
6282a2da
MT		 203static struct clk_fixed_factor meson8b_fclk_div2 = {
204 .mult = 1,
205 .div = 2,
206 .hw.init = &(struct clk_init_data){
207 .name = "fclk_div2",
208 .ops = &clk_fixed_factor_ops,
209 .parent_names = (const char *[]){ "fixed_pll" },
210 .num_parents = 1,
211 },
212};
213
214static struct clk_fixed_factor meson8b_fclk_div3 = {
215 .mult = 1,
216 .div = 3,
217 .hw.init = &(struct clk_init_data){
218 .name = "fclk_div3",
219 .ops = &clk_fixed_factor_ops,
220 .parent_names = (const char *[]){ "fixed_pll" },
221 .num_parents = 1,
222 },
223};
224
225static struct clk_fixed_factor meson8b_fclk_div4 = {
226 .mult = 1,
227 .div = 4,
228 .hw.init = &(struct clk_init_data){
229 .name = "fclk_div4",
230 .ops = &clk_fixed_factor_ops,
231 .parent_names = (const char *[]){ "fixed_pll" },
232 .num_parents = 1,
233 },
234};
235
236static struct clk_fixed_factor meson8b_fclk_div5 = {
237 .mult = 1,
238 .div = 5,
239 .hw.init = &(struct clk_init_data){
240 .name = "fclk_div5",
241 .ops = &clk_fixed_factor_ops,
242 .parent_names = (const char *[]){ "fixed_pll" },
243 .num_parents = 1,
244 },
245};
246
247static struct clk_fixed_factor meson8b_fclk_div7 = {
248 .mult = 1,
249 .div = 7,
250 .hw.init = &(struct clk_init_data){
251 .name = "fclk_div7",
252 .ops = &clk_fixed_factor_ops,
253 .parent_names = (const char *[]){ "fixed_pll" },
254 .num_parents = 1,
255 },
256};
257
b778f745
JB		 258static struct meson_clk_mpll meson8b_mpll0 = {
259 .sdm = {
260 .reg_off = HHI_MPLL_CNTL7,
261 .shift = 0,
262 .width = 14,
263 },
264 .sdm_en = {
265 .reg_off = HHI_MPLL_CNTL7,
266 .shift = 15,
267 .width = 1,
268 },
269 .n2 = {
270 .reg_off = HHI_MPLL_CNTL7,
271 .shift = 16,
272 .width = 9,
273 },
274 .en = {
275 .reg_off = HHI_MPLL_CNTL7,
276 .shift = 14,
277 .width = 1,
278 },
1f737ffa
JB		 279 .ssen = {
280 .reg_off = HHI_MPLL_CNTL,
281 .shift = 25,
282 .width = 1,
283 },
b778f745
JB		 284 .lock = &clk_lock,
285 .hw.init = &(struct clk_init_data){
286 .name = "mpll0",
287 .ops = &meson_clk_mpll_ops,
288 .parent_names = (const char *[]){ "fixed_pll" },
289 .num_parents = 1,
290 },
291};
292
293static struct meson_clk_mpll meson8b_mpll1 = {
294 .sdm = {
295 .reg_off = HHI_MPLL_CNTL8,
296 .shift = 0,
297 .width = 14,
298 },
299 .sdm_en = {
300 .reg_off = HHI_MPLL_CNTL8,
301 .shift = 15,
302 .width = 1,
303 },
304 .n2 = {
305 .reg_off = HHI_MPLL_CNTL8,
306 .shift = 16,
307 .width = 9,
308 },
309 .en = {
310 .reg_off = HHI_MPLL_CNTL8,
311 .shift = 14,
312 .width = 1,
313 },
314 .lock = &clk_lock,
315 .hw.init = &(struct clk_init_data){
316 .name = "mpll1",
317 .ops = &meson_clk_mpll_ops,
318 .parent_names = (const char *[]){ "fixed_pll" },
319 .num_parents = 1,
320 },
321};
322
323static struct meson_clk_mpll meson8b_mpll2 = {
324 .sdm = {
325 .reg_off = HHI_MPLL_CNTL9,
326 .shift = 0,
327 .width = 14,
328 },
329 .sdm_en = {
330 .reg_off = HHI_MPLL_CNTL9,
331 .shift = 15,
332 .width = 1,
333 },
334 .n2 = {
335 .reg_off = HHI_MPLL_CNTL9,
336 .shift = 16,
337 .width = 9,
338 },
339 .en = {
340 .reg_off = HHI_MPLL_CNTL9,
341 .shift = 14,
342 .width = 1,
343 },
344 .lock = &clk_lock,
345 .hw.init = &(struct clk_init_data){
346 .name = "mpll2",
347 .ops = &meson_clk_mpll_ops,
348 .parent_names = (const char *[]){ "fixed_pll" },
349 .num_parents = 1,
350 },
351};
352
c0daa3e6
MT		 353/*
354 * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
355 * post-dividers and should be modeled with their respective PLLs via the
356 * forthcoming coordinated clock rates feature
357 */
55d42c40 358static struct meson_clk_cpu meson8b_cpu_clk = {
e0818a39 359 .reg_off = HHI_SYS_CPU_CLK_CNTL1,
55d42c40
MT		 360 .div_table = cpu_div_table,
361 .clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
362 .hw.init = &(struct clk_init_data){
363 .name = "cpu_clk",
364 .ops = &meson_clk_cpu_ops,
365 .parent_names = (const char *[]){ "sys_pll" },
366 .num_parents = 1,
367 },
368};
369
c0daa3e6
MT		 370static u32 mux_table_clk81[] = { 6, 5, 7 };
371
372struct clk_mux meson8b_mpeg_clk_sel = {
e0818a39 373 .reg = (void *)HHI_MPEG_CLK_CNTL,
c0daa3e6
MT		 374 .mask = 0x7,
375 .shift = 12,
376 .flags = CLK_MUX_READ_ONLY,
377 .table = mux_table_clk81,
378 .lock = &clk_lock,
379 .hw.init = &(struct clk_init_data){
380 .name = "mpeg_clk_sel",
381 .ops = &clk_mux_ro_ops,
382 /*
383 * FIXME bits 14:12 selects from 8 possible parents:
384 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
385 * fclk_div4, fclk_div3, fclk_div5
386 */
387 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
388 "fclk_div5" },
389 .num_parents = 3,
390 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
391 },
392};
393
394struct clk_divider meson8b_mpeg_clk_div = {
e0818a39 395 .reg = (void *)HHI_MPEG_CLK_CNTL,
c0daa3e6
MT		 396 .shift = 0,
397 .width = 7,
398 .lock = &clk_lock,
399 .hw.init = &(struct clk_init_data){
400 .name = "mpeg_clk_div",
401 .ops = &clk_divider_ops,
402 .parent_names = (const char *[]){ "mpeg_clk_sel" },
403 .num_parents = 1,
404 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
405 },
406};
407
408struct clk_gate meson8b_clk81 = {
e0818a39 409 .reg = (void *)HHI_MPEG_CLK_CNTL,
c0daa3e6
MT		 410 .bit_idx = 7,
411 .lock = &clk_lock,
412 .hw.init = &(struct clk_init_data){
413 .name = "clk81",
414 .ops = &clk_gate_ops,
415 .parent_names = (const char *[]){ "mpeg_clk_div" },
416 .num_parents = 1,
be58e496 417 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
c0daa3e6 418 },
28b9fcd0
CC		 419};
420
e31a1900
AM		 421/* Everything Else (EE) domain gates */
422
423static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
424static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
425static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
426static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
427static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
428static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
429static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
430static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
431static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
432static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
433static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
434static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
435static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
436static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
437static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
438static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
439static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
440static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
441static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
442
443static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
444static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
445static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
446static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
447static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
448static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
449static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
450static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
451static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
452static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
453static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
454static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
455static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
456static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
457static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
458static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
459static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
460static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
461static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
462static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
463static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
464static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
465static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
466static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
467static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
468
469static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
470static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
471static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
472static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
473static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
474static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
475static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
476static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
477static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
478static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
479static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
480static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
481static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
482
483static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
484static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
485static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
486static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
487static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
488static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
489static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
490static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
491static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
492static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
493static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
494static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
495static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
496static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
497static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
498static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
499
500/* Always On (AO) domain gates */
501
502static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
503static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
504static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
505static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
506
e92f7cca
MT		 507static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
508 .hws = {
509 [CLKID_XTAL] = &meson8b_xtal.hw,
ec623f2a
MT		 510 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
511 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
512 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
6282a2da
MT		 513 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
514 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
515 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
516 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
517 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
55d42c40 518 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
c0daa3e6
MT		 519 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
520 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
521 [CLKID_CLK81] = &meson8b_clk81.hw,
e31a1900
AM		 522 [CLKID_DDR] = &meson8b_ddr.hw,
523 [CLKID_DOS] = &meson8b_dos.hw,
524 [CLKID_ISA] = &meson8b_isa.hw,
525 [CLKID_PL301] = &meson8b_pl301.hw,
526 [CLKID_PERIPHS] = &meson8b_periphs.hw,
527 [CLKID_SPICC] = &meson8b_spicc.hw,
528 [CLKID_I2C] = &meson8b_i2c.hw,
529 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
530 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
531 [CLKID_RNG0] = &meson8b_rng0.hw,
532 [CLKID_UART0] = &meson8b_uart0.hw,
533 [CLKID_SDHC] = &meson8b_sdhc.hw,
534 [CLKID_STREAM] = &meson8b_stream.hw,
535 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
536 [CLKID_SDIO] = &meson8b_sdio.hw,
537 [CLKID_ABUF] = &meson8b_abuf.hw,
538 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
539 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
540 [CLKID_SPI] = &meson8b_spi.hw,
541 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
542 [CLKID_ETH] = &meson8b_eth.hw,
543 [CLKID_DEMUX] = &meson8b_demux.hw,
544 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
545 [CLKID_IEC958] = &meson8b_iec958.hw,
546 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
547 [CLKID_AMCLK] = &meson8b_amclk.hw,
548 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
549 [CLKID_MIXER] = &meson8b_mixer.hw,
550 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
551 [CLKID_ADC] = &meson8b_adc.hw,
552 [CLKID_BLKMV] = &meson8b_blkmv.hw,
553 [CLKID_AIU] = &meson8b_aiu.hw,
554 [CLKID_UART1] = &meson8b_uart1.hw,
555 [CLKID_G2D] = &meson8b_g2d.hw,
556 [CLKID_USB0] = &meson8b_usb0.hw,
557 [CLKID_USB1] = &meson8b_usb1.hw,
558 [CLKID_RESET] = &meson8b_reset.hw,
559 [CLKID_NAND] = &meson8b_nand.hw,
560 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
561 [CLKID_USB] = &meson8b_usb.hw,
562 [CLKID_VDIN1] = &meson8b_vdin1.hw,
563 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
564 [CLKID_EFUSE] = &meson8b_efuse.hw,
565 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
566 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
567 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
568 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
569 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
570 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
571 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
572 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
573 [CLKID_DVIN] = &meson8b_dvin.hw,
574 [CLKID_UART2] = &meson8b_uart2.hw,
575 [CLKID_SANA] = &meson8b_sana.hw,
576 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
577 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
578 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
579 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
580 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
581 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
582 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
583 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
0d5aa65e 584 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
e31a1900
AM		 585 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
586 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
587 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
588 [CLKID_ENC480P] = &meson8b_enc480p.hw,
589 [CLKID_RNG1] = &meson8b_rng1.hw,
590 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
591 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
592 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
593 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
594 [CLKID_EDP] = &meson8b_edp.hw,
595 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
596 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
597 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
598 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
b778f745
JB		 599 [CLKID_MPLL0] = &meson8b_mpll0.hw,
600 [CLKID_MPLL1] = &meson8b_mpll1.hw,
601 [CLKID_MPLL2] = &meson8b_mpll2.hw,
de2bc417 602 [CLK_NR_CLKS] = NULL,
e92f7cca
MT		 603 },
604 .num = CLK_NR_CLKS,
605};
606
ec623f2a
MT		 607static struct meson_clk_pll *const meson8b_clk_plls[] = {
608 &meson8b_fixed_pll,
609 &meson8b_vid_pll,
610 &meson8b_sys_pll,
611};
612
b778f745
JB		 613static struct meson_clk_mpll *const meson8b_clk_mplls[] = {
614 &meson8b_mpll0,
615 &meson8b_mpll1,
616 &meson8b_mpll2,
617};
618
f7e3a826 619static struct clk_gate *const meson8b_clk_gates[] = {
e31a1900
AM		 620 &meson8b_clk81,
621 &meson8b_ddr,
622 &meson8b_dos,
623 &meson8b_isa,
624 &meson8b_pl301,
625 &meson8b_periphs,
626 &meson8b_spicc,
627 &meson8b_i2c,
628 &meson8b_sar_adc,
629 &meson8b_smart_card,
630 &meson8b_rng0,
631 &meson8b_uart0,
632 &meson8b_sdhc,
633 &meson8b_stream,
634 &meson8b_async_fifo,
635 &meson8b_sdio,
636 &meson8b_abuf,
637 &meson8b_hiu_iface,
638 &meson8b_assist_misc,
639 &meson8b_spi,
640 &meson8b_i2s_spdif,
641 &meson8b_eth,
642 &meson8b_demux,
643 &meson8b_aiu_glue,
644 &meson8b_iec958,
645 &meson8b_i2s_out,
646 &meson8b_amclk,
647 &meson8b_aififo2,
648 &meson8b_mixer,
649 &meson8b_mixer_iface,
650 &meson8b_adc,
651 &meson8b_blkmv,
652 &meson8b_aiu,
653 &meson8b_uart1,
654 &meson8b_g2d,
655 &meson8b_usb0,
656 &meson8b_usb1,
657 &meson8b_reset,
658 &meson8b_nand,
659 &meson8b_dos_parser,
660 &meson8b_usb,
661 &meson8b_vdin1,
662 &meson8b_ahb_arb0,
663 &meson8b_efuse,
664 &meson8b_boot_rom,
665 &meson8b_ahb_data_bus,
666 &meson8b_ahb_ctrl_bus,
667 &meson8b_hdmi_intr_sync,
668 &meson8b_hdmi_pclk,
669 &meson8b_usb1_ddr_bridge,
670 &meson8b_usb0_ddr_bridge,
671 &meson8b_mmc_pclk,
672 &meson8b_dvin,
673 &meson8b_uart2,
674 &meson8b_sana,
675 &meson8b_vpu_intr,
676 &meson8b_sec_ahb_ahb3_bridge,
677 &meson8b_clk81_a9,
678 &meson8b_vclk2_venci0,
679 &meson8b_vclk2_venci1,
680 &meson8b_vclk2_vencp0,
681 &meson8b_vclk2_vencp1,
682 &meson8b_gclk_venci_int,
683 &meson8b_gclk_vencp_int,
684 &meson8b_dac_clk,
685 &meson8b_aoclk_gate,
686 &meson8b_iec958_gate,
687 &meson8b_enc480p,
688 &meson8b_rng1,
689 &meson8b_gclk_vencl_int,
690 &meson8b_vclk2_venclmcc,
691 &meson8b_vclk2_vencl,
692 &meson8b_vclk2_other,
693 &meson8b_edp,
694 &meson8b_ao_media_cpu,
695 &meson8b_ao_ahb_sram,
696 &meson8b_ao_ahb_bus,
697 &meson8b_ao_iface,
698};
699
e988aae5
JB		 700static struct clk_mux *const meson8b_clk_muxes[] = {
701 &meson8b_mpeg_clk_sel,
702};
703
704static struct clk_divider *const meson8b_clk_dividers[] = {
705 &meson8b_mpeg_clk_div,
706};
707
18962172
MB		 708static const struct meson8b_clk_reset_line {
709 u32 reg;
710 u8 bit_idx;
711} meson8b_clk_reset_bits[] = {
712 [CLKC_RESET_L2_CACHE_SOFT_RESET] = {
713 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30
714 },
715 [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
716 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29
717 },
718 [CLKC_RESET_SCU_SOFT_RESET] = {
719 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28
720 },
721 [CLKC_RESET_CPU3_SOFT_RESET] = {
722 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27
723 },
724 [CLKC_RESET_CPU2_SOFT_RESET] = {
725 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26
726 },
727 [CLKC_RESET_CPU1_SOFT_RESET] = {
728 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25
729 },
730 [CLKC_RESET_CPU0_SOFT_RESET] = {
731 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24
732 },
733 [CLKC_RESET_A5_GLOBAL_RESET] = {
734 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18
735 },
736 [CLKC_RESET_A5_AXI_SOFT_RESET] = {
737 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17
738 },
739 [CLKC_RESET_A5_ABP_SOFT_RESET] = {
740 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16
741 },
742 [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
743 .reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30
744 },
745 [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
746 .reg = HHI_VID_CLK_CNTL, .bit_idx = 15
747 },
748 [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
749 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7
750 },
751 [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
752 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3
753 },
754 [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
755 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1
756 },
757 [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
758 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0
759 },
760};
761
762static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
763 unsigned long id, bool assert)
764{
765 struct meson8b_clk_reset *meson8b_clk_reset =
766 container_of(rcdev, struct meson8b_clk_reset, reset);
767 unsigned long flags;
768 const struct meson8b_clk_reset_line *reset;
769 u32 val;
770
771 if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
772 return -EINVAL;
773
774 reset = &meson8b_clk_reset_bits[id];
775
776 spin_lock_irqsave(&clk_lock, flags);
777
778 val = readl(meson8b_clk_reset->base + reset->reg);
779 if (assert)
780 val |= BIT(reset->bit_idx);
781 else
782 val &= ~BIT(reset->bit_idx);
783 writel(val, meson8b_clk_reset->base + reset->reg);
784
785 spin_unlock_irqrestore(&clk_lock, flags);
786
787 return 0;
788}
789
790static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
791 unsigned long id)
792{
793 return meson8b_clk_reset_update(rcdev, id, true);
794}
795
796static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
797 unsigned long id)
798{
799 return meson8b_clk_reset_update(rcdev, id, false);
800}
801
802static const struct reset_control_ops meson8b_clk_reset_ops = {
803 .assert = meson8b_clk_reset_assert,
804 .deassert = meson8b_clk_reset_deassert,
805};
806
796b9aa8 807static int meson8b_clkc_probe(struct platform_device *pdev)
28b9fcd0 808{
ec623f2a 809 int ret, clkid, i;
55d42c40
MT		 810 struct clk_hw *parent_hw;
811 struct clk *parent_clk;
796b9aa8 812 struct device *dev = &pdev->dev;
28b9fcd0 813
18962172 814 if (!clk_base)
796b9aa8 815 return -ENXIO;
28b9fcd0 816
ec623f2a
MT		 817 /* Populate base address for PLLs */
818 for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
819 meson8b_clk_plls[i]->base = clk_base;
820
b778f745
JB		 821 /* Populate base address for MPLLs */
822 for (i = 0; i < ARRAY_SIZE(meson8b_clk_mplls); i++)
823 meson8b_clk_mplls[i]->base = clk_base;
824
55d42c40
MT		 825 /* Populate the base address for CPU clk */
826 meson8b_cpu_clk.base = clk_base;
827
e31a1900
AM		 828 /* Populate base address for gates */
829 for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
830 meson8b_clk_gates[i]->reg = clk_base +
831 (u32)meson8b_clk_gates[i]->reg;
832
e988aae5
JB		 833 /* Populate base address for muxes */
834 for (i = 0; i < ARRAY_SIZE(meson8b_clk_muxes); i++)
835 meson8b_clk_muxes[i]->reg = clk_base +
836 (u32)meson8b_clk_muxes[i]->reg;
837
838 /* Populate base address for dividers */
839 for (i = 0; i < ARRAY_SIZE(meson8b_clk_dividers); i++)
840 meson8b_clk_dividers[i]->reg = clk_base +
841 (u32)meson8b_clk_dividers[i]->reg;
842
e92f7cca
MT		 843 /*
844 * register all clks
845 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
846 */
847 for (clkid = CLKID_XTAL; clkid < CLK_NR_CLKS; clkid++) {
848 /* array might be sparse */
849 if (!meson8b_hw_onecell_data.hws[clkid])
850 continue;
851
852 /* FIXME convert to devm_clk_register */
796b9aa8 853 ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]);
e92f7cca 854 if (ret)
18962172 855 return ret;
e92f7cca
MT		 856 }
857
55d42c40
MT		 858 /*
859 * Register CPU clk notifier
860 *
861 * FIXME this is wrong for a lot of reasons. First, the muxes should be
862 * struct clk_hw objects. Second, we shouldn't program the muxes in
863 * notifier handlers. The tricky programming sequence will be handled
864 * by the forthcoming coordinated clock rates mechanism once that
865 * feature is released.
866 *
867 * Furthermore, looking up the parent this way is terrible. At some
868 * point we will stop allocating a default struct clk when registering
869 * a new clk_hw, and this hack will no longer work. Releasing the ccr
870 * feature before that time solves the problem :-)
871 */
872 parent_hw = clk_hw_get_parent(&meson8b_cpu_clk.hw);
873 parent_clk = parent_hw->clk;
874 ret = clk_notifier_register(parent_clk, &meson8b_cpu_clk.clk_nb);
875 if (ret) {
876 pr_err("%s: failed to register clock notifier for cpu_clk\n",
877 __func__);
18962172 878 return ret;
55d42c40
MT		 879 }
880
796b9aa8
MT		 881 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
882 &meson8b_hw_onecell_data);
28b9fcd0 883}
796b9aa8
MT		 884
885static const struct of_device_id meson8b_clkc_match_table[] = {
855f06a1 886 { .compatible = "amlogic,meson8-clkc" },
796b9aa8 887 { .compatible = "amlogic,meson8b-clkc" },
855f06a1 888 { .compatible = "amlogic,meson8m2-clkc" },
796b9aa8
MT		 889 { }
890};
796b9aa8
MT		 891
892static struct platform_driver meson8b_driver = {
893 .probe = meson8b_clkc_probe,
894 .driver = {
895 .name = "meson8b-clkc",
896 .of_match_table = meson8b_clkc_match_table,
897 },
898};
899
8edeae56 900builtin_platform_driver(meson8b_driver);
18962172
MB		 901
902static void __init meson8b_clkc_reset_init(struct device_node *np)
903{
904 struct meson8b_clk_reset *rstc;
905 int ret;
906
907 /* Generic clocks, PLLs and some of the reset-bits */
908 clk_base = of_iomap(np, 1);
909 if (!clk_base) {
910 pr_err("%s: Unable to map clk base\n", __func__);
911 return;
912 }
913
914 rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
915 if (!rstc)
916 return;
917
918 /* Reset Controller */
919 rstc->base = clk_base;
920 rstc->reset.ops = &meson8b_clk_reset_ops;
921 rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
922 rstc->reset.of_node = np;
923 ret = reset_controller_register(&rstc->reset);
924 if (ret) {
925 pr_err("%s: Failed to register clkc reset controller: %d\n",
926 __func__, ret);
927 return;
928 }
929}
930
931CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
932 meson8b_clkc_reset_init);
933CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
934 meson8b_clkc_reset_init);
935CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
936 meson8b_clkc_reset_init);
Ubuntu Focal Linux kernel mirror