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ee81f4ee CX |
1 | /* |
2 | * mmp mix(div and mux) clock operation source file | |
3 | * | |
4 | * Copyright (C) 2014 Marvell | |
5 | * Chao Xie <chao.xie@marvell.com> | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/clk-provider.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/err.h> | |
16 | ||
17 | #include "clk.h" | |
18 | ||
19 | /* | |
20 | * The mix clock is a clock combined mux and div type clock. | |
21 | * Because the div field and mux field need to be set at same | |
22 | * time, we can not divide it into 2 types of clock | |
23 | */ | |
24 | ||
25 | #define to_clk_mix(hw) container_of(hw, struct mmp_clk_mix, hw) | |
26 | ||
27 | static unsigned int _get_maxdiv(struct mmp_clk_mix *mix) | |
28 | { | |
29 | unsigned int div_mask = (1 << mix->reg_info.width_div) - 1; | |
30 | unsigned int maxdiv = 0; | |
31 | struct clk_div_table *clkt; | |
32 | ||
33 | if (mix->div_flags & CLK_DIVIDER_ONE_BASED) | |
34 | return div_mask; | |
35 | if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO) | |
36 | return 1 << div_mask; | |
37 | if (mix->div_table) { | |
38 | for (clkt = mix->div_table; clkt->div; clkt++) | |
39 | if (clkt->div > maxdiv) | |
40 | maxdiv = clkt->div; | |
41 | return maxdiv; | |
42 | } | |
43 | return div_mask + 1; | |
44 | } | |
45 | ||
46 | static unsigned int _get_div(struct mmp_clk_mix *mix, unsigned int val) | |
47 | { | |
48 | struct clk_div_table *clkt; | |
49 | ||
50 | if (mix->div_flags & CLK_DIVIDER_ONE_BASED) | |
51 | return val; | |
52 | if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO) | |
53 | return 1 << val; | |
54 | if (mix->div_table) { | |
55 | for (clkt = mix->div_table; clkt->div; clkt++) | |
56 | if (clkt->val == val) | |
57 | return clkt->div; | |
58 | if (clkt->div == 0) | |
59 | return 0; | |
60 | } | |
61 | return val + 1; | |
62 | } | |
63 | ||
64 | static unsigned int _get_mux(struct mmp_clk_mix *mix, unsigned int val) | |
65 | { | |
66 | int num_parents = __clk_get_num_parents(mix->hw.clk); | |
67 | int i; | |
68 | ||
69 | if (mix->mux_flags & CLK_MUX_INDEX_BIT) | |
70 | return ffs(val) - 1; | |
71 | if (mix->mux_flags & CLK_MUX_INDEX_ONE) | |
72 | return val - 1; | |
73 | if (mix->mux_table) { | |
74 | for (i = 0; i < num_parents; i++) | |
75 | if (mix->mux_table[i] == val) | |
76 | return i; | |
77 | if (i == num_parents) | |
78 | return 0; | |
79 | } | |
80 | ||
81 | return val; | |
82 | } | |
83 | static unsigned int _get_div_val(struct mmp_clk_mix *mix, unsigned int div) | |
84 | { | |
85 | struct clk_div_table *clkt; | |
86 | ||
87 | if (mix->div_flags & CLK_DIVIDER_ONE_BASED) | |
88 | return div; | |
89 | if (mix->div_flags & CLK_DIVIDER_POWER_OF_TWO) | |
90 | return __ffs(div); | |
91 | if (mix->div_table) { | |
92 | for (clkt = mix->div_table; clkt->div; clkt++) | |
93 | if (clkt->div == div) | |
94 | return clkt->val; | |
95 | if (clkt->div == 0) | |
96 | return 0; | |
97 | } | |
98 | ||
99 | return div - 1; | |
100 | } | |
101 | ||
102 | static unsigned int _get_mux_val(struct mmp_clk_mix *mix, unsigned int mux) | |
103 | { | |
104 | if (mix->mux_table) | |
105 | return mix->mux_table[mux]; | |
106 | ||
107 | return mux; | |
108 | } | |
109 | ||
110 | static void _filter_clk_table(struct mmp_clk_mix *mix, | |
111 | struct mmp_clk_mix_clk_table *table, | |
112 | unsigned int table_size) | |
113 | { | |
114 | int i; | |
115 | struct mmp_clk_mix_clk_table *item; | |
116 | struct clk *parent, *clk; | |
117 | unsigned long parent_rate; | |
118 | ||
119 | clk = mix->hw.clk; | |
120 | ||
121 | for (i = 0; i < table_size; i++) { | |
122 | item = &table[i]; | |
123 | parent = clk_get_parent_by_index(clk, item->parent_index); | |
124 | parent_rate = __clk_get_rate(parent); | |
125 | if (parent_rate % item->rate) { | |
126 | item->valid = 0; | |
127 | } else { | |
128 | item->divisor = parent_rate / item->rate; | |
129 | item->valid = 1; | |
130 | } | |
131 | } | |
132 | } | |
133 | ||
134 | static int _set_rate(struct mmp_clk_mix *mix, u32 mux_val, u32 div_val, | |
135 | unsigned int change_mux, unsigned int change_div) | |
136 | { | |
137 | struct mmp_clk_mix_reg_info *ri = &mix->reg_info; | |
138 | u8 width, shift; | |
139 | u32 mux_div, fc_req; | |
140 | int ret, timeout = 50; | |
141 | unsigned long flags = 0; | |
142 | ||
143 | if (!change_mux && !change_div) | |
144 | return -EINVAL; | |
145 | ||
146 | if (mix->lock) | |
147 | spin_lock_irqsave(mix->lock, flags); | |
148 | ||
149 | if (mix->type == MMP_CLK_MIX_TYPE_V1 | |
150 | || mix->type == MMP_CLK_MIX_TYPE_V2) | |
151 | mux_div = readl(ri->reg_clk_ctrl); | |
152 | else | |
153 | mux_div = readl(ri->reg_clk_sel); | |
154 | ||
155 | if (change_div) { | |
156 | width = ri->width_div; | |
157 | shift = ri->shift_div; | |
158 | mux_div &= ~MMP_CLK_BITS_MASK(width, shift); | |
159 | mux_div |= MMP_CLK_BITS_SET_VAL(div_val, width, shift); | |
160 | } | |
161 | ||
162 | if (change_mux) { | |
163 | width = ri->width_mux; | |
164 | shift = ri->shift_mux; | |
165 | mux_div &= ~MMP_CLK_BITS_MASK(width, shift); | |
166 | mux_div |= MMP_CLK_BITS_SET_VAL(mux_val, width, shift); | |
167 | } | |
168 | ||
169 | if (mix->type == MMP_CLK_MIX_TYPE_V1) { | |
170 | writel(mux_div, ri->reg_clk_ctrl); | |
171 | } else if (mix->type == MMP_CLK_MIX_TYPE_V2) { | |
172 | mux_div |= (1 << ri->bit_fc); | |
173 | writel(mux_div, ri->reg_clk_ctrl); | |
174 | ||
175 | do { | |
176 | fc_req = readl(ri->reg_clk_ctrl); | |
177 | timeout--; | |
178 | if (!(fc_req & (1 << ri->bit_fc))) | |
179 | break; | |
180 | } while (timeout); | |
181 | ||
182 | if (timeout == 0) { | |
183 | pr_err("%s:%s cannot do frequency change\n", | |
184 | __func__, __clk_get_name(mix->hw.clk)); | |
185 | ret = -EBUSY; | |
186 | goto error; | |
187 | } | |
188 | } else { | |
189 | fc_req = readl(ri->reg_clk_ctrl); | |
190 | fc_req |= 1 << ri->bit_fc; | |
191 | writel(fc_req, ri->reg_clk_ctrl); | |
192 | writel(mux_div, ri->reg_clk_sel); | |
193 | fc_req &= ~(1 << ri->bit_fc); | |
194 | } | |
195 | ||
196 | ret = 0; | |
197 | error: | |
198 | if (mix->lock) | |
199 | spin_unlock_irqrestore(mix->lock, flags); | |
200 | ||
201 | return ret; | |
202 | } | |
203 | ||
0817b62c BB |
204 | static int mmp_clk_mix_determine_rate(struct clk_hw *hw, |
205 | struct clk_rate_request *req) | |
ee81f4ee CX |
206 | { |
207 | struct mmp_clk_mix *mix = to_clk_mix(hw); | |
208 | struct mmp_clk_mix_clk_table *item; | |
209 | struct clk *parent, *parent_best, *mix_clk; | |
210 | unsigned long parent_rate, mix_rate, mix_rate_best, parent_rate_best; | |
211 | unsigned long gap, gap_best; | |
212 | u32 div_val_max; | |
213 | unsigned int div; | |
214 | int i, j; | |
215 | ||
216 | mix_clk = hw->clk; | |
217 | ||
218 | parent = NULL; | |
219 | mix_rate_best = 0; | |
220 | parent_rate_best = 0; | |
57d866e6 | 221 | gap_best = ULONG_MAX; |
ee81f4ee CX |
222 | parent_best = NULL; |
223 | ||
224 | if (mix->table) { | |
225 | for (i = 0; i < mix->table_size; i++) { | |
226 | item = &mix->table[i]; | |
227 | if (item->valid == 0) | |
228 | continue; | |
229 | parent = clk_get_parent_by_index(mix_clk, | |
230 | item->parent_index); | |
231 | parent_rate = __clk_get_rate(parent); | |
232 | mix_rate = parent_rate / item->divisor; | |
0817b62c | 233 | gap = abs(mix_rate - req->rate); |
ee81f4ee CX |
234 | if (parent_best == NULL || gap < gap_best) { |
235 | parent_best = parent; | |
236 | parent_rate_best = parent_rate; | |
237 | mix_rate_best = mix_rate; | |
238 | gap_best = gap; | |
239 | if (gap_best == 0) | |
240 | goto found; | |
241 | } | |
242 | } | |
243 | } else { | |
244 | for (i = 0; i < __clk_get_num_parents(mix_clk); i++) { | |
245 | parent = clk_get_parent_by_index(mix_clk, i); | |
246 | parent_rate = __clk_get_rate(parent); | |
247 | div_val_max = _get_maxdiv(mix); | |
248 | for (j = 0; j < div_val_max; j++) { | |
249 | div = _get_div(mix, j); | |
250 | mix_rate = parent_rate / div; | |
0817b62c | 251 | gap = abs(mix_rate - req->rate); |
ee81f4ee CX |
252 | if (parent_best == NULL || gap < gap_best) { |
253 | parent_best = parent; | |
254 | parent_rate_best = parent_rate; | |
255 | mix_rate_best = mix_rate; | |
256 | gap_best = gap; | |
257 | if (gap_best == 0) | |
258 | goto found; | |
259 | } | |
260 | } | |
261 | } | |
262 | } | |
263 | ||
264 | found: | |
57d866e6 BB |
265 | if (!parent_best) |
266 | return -EINVAL; | |
267 | ||
0817b62c BB |
268 | req->best_parent_rate = parent_rate_best; |
269 | req->best_parent_hw = __clk_get_hw(parent_best); | |
270 | req->rate = mix_rate_best; | |
ee81f4ee | 271 | |
0817b62c | 272 | return 0; |
ee81f4ee CX |
273 | } |
274 | ||
275 | static int mmp_clk_mix_set_rate_and_parent(struct clk_hw *hw, | |
276 | unsigned long rate, | |
277 | unsigned long parent_rate, | |
278 | u8 index) | |
279 | { | |
280 | struct mmp_clk_mix *mix = to_clk_mix(hw); | |
281 | unsigned int div; | |
282 | u32 div_val, mux_val; | |
283 | ||
284 | div = parent_rate / rate; | |
285 | div_val = _get_div_val(mix, div); | |
286 | mux_val = _get_mux_val(mix, index); | |
287 | ||
288 | return _set_rate(mix, mux_val, div_val, 1, 1); | |
289 | } | |
290 | ||
291 | static u8 mmp_clk_mix_get_parent(struct clk_hw *hw) | |
292 | { | |
293 | struct mmp_clk_mix *mix = to_clk_mix(hw); | |
294 | struct mmp_clk_mix_reg_info *ri = &mix->reg_info; | |
295 | unsigned long flags = 0; | |
296 | u32 mux_div = 0; | |
297 | u8 width, shift; | |
298 | u32 mux_val; | |
299 | ||
300 | if (mix->lock) | |
301 | spin_lock_irqsave(mix->lock, flags); | |
302 | ||
303 | if (mix->type == MMP_CLK_MIX_TYPE_V1 | |
304 | || mix->type == MMP_CLK_MIX_TYPE_V2) | |
305 | mux_div = readl(ri->reg_clk_ctrl); | |
306 | else | |
307 | mux_div = readl(ri->reg_clk_sel); | |
308 | ||
309 | if (mix->lock) | |
310 | spin_unlock_irqrestore(mix->lock, flags); | |
311 | ||
312 | width = mix->reg_info.width_mux; | |
313 | shift = mix->reg_info.shift_mux; | |
314 | ||
315 | mux_val = MMP_CLK_BITS_GET_VAL(mux_div, width, shift); | |
316 | ||
317 | return _get_mux(mix, mux_val); | |
318 | } | |
319 | ||
320 | static unsigned long mmp_clk_mix_recalc_rate(struct clk_hw *hw, | |
321 | unsigned long parent_rate) | |
322 | { | |
323 | struct mmp_clk_mix *mix = to_clk_mix(hw); | |
324 | struct mmp_clk_mix_reg_info *ri = &mix->reg_info; | |
325 | unsigned long flags = 0; | |
326 | u32 mux_div = 0; | |
327 | u8 width, shift; | |
328 | unsigned int div; | |
329 | ||
330 | if (mix->lock) | |
331 | spin_lock_irqsave(mix->lock, flags); | |
332 | ||
333 | if (mix->type == MMP_CLK_MIX_TYPE_V1 | |
334 | || mix->type == MMP_CLK_MIX_TYPE_V2) | |
335 | mux_div = readl(ri->reg_clk_ctrl); | |
336 | else | |
337 | mux_div = readl(ri->reg_clk_sel); | |
338 | ||
339 | if (mix->lock) | |
340 | spin_unlock_irqrestore(mix->lock, flags); | |
341 | ||
342 | width = mix->reg_info.width_div; | |
343 | shift = mix->reg_info.shift_div; | |
344 | ||
345 | div = _get_div(mix, MMP_CLK_BITS_GET_VAL(mux_div, width, shift)); | |
346 | ||
347 | return parent_rate / div; | |
348 | } | |
349 | ||
350 | static int mmp_clk_set_parent(struct clk_hw *hw, u8 index) | |
351 | { | |
352 | struct mmp_clk_mix *mix = to_clk_mix(hw); | |
353 | struct mmp_clk_mix_clk_table *item; | |
354 | int i; | |
355 | u32 div_val, mux_val; | |
356 | ||
357 | if (mix->table) { | |
358 | for (i = 0; i < mix->table_size; i++) { | |
359 | item = &mix->table[i]; | |
360 | if (item->valid == 0) | |
361 | continue; | |
362 | if (item->parent_index == index) | |
363 | break; | |
364 | } | |
365 | if (i < mix->table_size) { | |
366 | div_val = _get_div_val(mix, item->divisor); | |
367 | mux_val = _get_mux_val(mix, item->parent_index); | |
368 | } else | |
369 | return -EINVAL; | |
370 | } else { | |
371 | mux_val = _get_mux_val(mix, index); | |
372 | div_val = 0; | |
373 | } | |
374 | ||
375 | return _set_rate(mix, mux_val, div_val, 1, div_val ? 1 : 0); | |
376 | } | |
377 | ||
378 | static int mmp_clk_set_rate(struct clk_hw *hw, unsigned long rate, | |
379 | unsigned long best_parent_rate) | |
380 | { | |
381 | struct mmp_clk_mix *mix = to_clk_mix(hw); | |
382 | struct mmp_clk_mix_clk_table *item; | |
383 | unsigned long parent_rate; | |
384 | unsigned int best_divisor; | |
385 | struct clk *mix_clk, *parent; | |
386 | int i; | |
387 | ||
388 | best_divisor = best_parent_rate / rate; | |
389 | ||
390 | mix_clk = hw->clk; | |
391 | if (mix->table) { | |
392 | for (i = 0; i < mix->table_size; i++) { | |
393 | item = &mix->table[i]; | |
394 | if (item->valid == 0) | |
395 | continue; | |
396 | parent = clk_get_parent_by_index(mix_clk, | |
397 | item->parent_index); | |
398 | parent_rate = __clk_get_rate(parent); | |
399 | if (parent_rate == best_parent_rate | |
400 | && item->divisor == best_divisor) | |
401 | break; | |
402 | } | |
403 | if (i < mix->table_size) | |
404 | return _set_rate(mix, | |
405 | _get_mux_val(mix, item->parent_index), | |
406 | _get_div_val(mix, item->divisor), | |
407 | 1, 1); | |
408 | else | |
409 | return -EINVAL; | |
410 | } else { | |
411 | for (i = 0; i < __clk_get_num_parents(mix_clk); i++) { | |
412 | parent = clk_get_parent_by_index(mix_clk, i); | |
413 | parent_rate = __clk_get_rate(parent); | |
414 | if (parent_rate == best_parent_rate) | |
415 | break; | |
416 | } | |
417 | if (i < __clk_get_num_parents(mix_clk)) | |
418 | return _set_rate(mix, _get_mux_val(mix, i), | |
419 | _get_div_val(mix, best_divisor), 1, 1); | |
420 | else | |
421 | return -EINVAL; | |
422 | } | |
423 | } | |
424 | ||
425 | static void mmp_clk_mix_init(struct clk_hw *hw) | |
426 | { | |
427 | struct mmp_clk_mix *mix = to_clk_mix(hw); | |
428 | ||
429 | if (mix->table) | |
430 | _filter_clk_table(mix, mix->table, mix->table_size); | |
431 | } | |
432 | ||
433 | const struct clk_ops mmp_clk_mix_ops = { | |
434 | .determine_rate = mmp_clk_mix_determine_rate, | |
435 | .set_rate_and_parent = mmp_clk_mix_set_rate_and_parent, | |
436 | .set_rate = mmp_clk_set_rate, | |
437 | .set_parent = mmp_clk_set_parent, | |
438 | .get_parent = mmp_clk_mix_get_parent, | |
439 | .recalc_rate = mmp_clk_mix_recalc_rate, | |
440 | .init = mmp_clk_mix_init, | |
441 | }; | |
442 | ||
443 | struct clk *mmp_clk_register_mix(struct device *dev, | |
444 | const char *name, | |
445 | const char **parent_names, | |
446 | u8 num_parents, | |
447 | unsigned long flags, | |
448 | struct mmp_clk_mix_config *config, | |
449 | spinlock_t *lock) | |
450 | { | |
451 | struct mmp_clk_mix *mix; | |
452 | struct clk *clk; | |
453 | struct clk_init_data init; | |
454 | size_t table_bytes; | |
455 | ||
456 | mix = kzalloc(sizeof(*mix), GFP_KERNEL); | |
457 | if (!mix) { | |
458 | pr_err("%s:%s: could not allocate mmp mix clk\n", | |
459 | __func__, name); | |
460 | return ERR_PTR(-ENOMEM); | |
461 | } | |
462 | ||
463 | init.name = name; | |
464 | init.flags = flags | CLK_GET_RATE_NOCACHE; | |
465 | init.parent_names = parent_names; | |
466 | init.num_parents = num_parents; | |
467 | init.ops = &mmp_clk_mix_ops; | |
468 | ||
469 | memcpy(&mix->reg_info, &config->reg_info, sizeof(config->reg_info)); | |
470 | if (config->table) { | |
471 | table_bytes = sizeof(*config->table) * config->table_size; | |
e8f35aab | 472 | mix->table = kmemdup(config->table, table_bytes, GFP_KERNEL); |
ee81f4ee CX |
473 | if (!mix->table) { |
474 | pr_err("%s:%s: could not allocate mmp mix table\n", | |
475 | __func__, name); | |
476 | kfree(mix); | |
477 | return ERR_PTR(-ENOMEM); | |
478 | } | |
ee81f4ee CX |
479 | mix->table_size = config->table_size; |
480 | } | |
481 | ||
482 | if (config->mux_table) { | |
483 | table_bytes = sizeof(u32) * num_parents; | |
e8f35aab AH |
484 | mix->mux_table = kmemdup(config->mux_table, table_bytes, |
485 | GFP_KERNEL); | |
ee81f4ee CX |
486 | if (!mix->mux_table) { |
487 | pr_err("%s:%s: could not allocate mmp mix mux-table\n", | |
488 | __func__, name); | |
489 | kfree(mix->table); | |
490 | kfree(mix); | |
491 | return ERR_PTR(-ENOMEM); | |
492 | } | |
ee81f4ee CX |
493 | } |
494 | ||
495 | mix->div_flags = config->div_flags; | |
496 | mix->mux_flags = config->mux_flags; | |
497 | mix->lock = lock; | |
498 | mix->hw.init = &init; | |
499 | ||
500 | if (config->reg_info.bit_fc >= 32) | |
501 | mix->type = MMP_CLK_MIX_TYPE_V1; | |
502 | else if (config->reg_info.reg_clk_sel) | |
503 | mix->type = MMP_CLK_MIX_TYPE_V3; | |
504 | else | |
505 | mix->type = MMP_CLK_MIX_TYPE_V2; | |
506 | clk = clk_register(dev, &mix->hw); | |
507 | ||
508 | if (IS_ERR(clk)) { | |
509 | kfree(mix->mux_table); | |
510 | kfree(mix->table); | |
511 | kfree(mix); | |
512 | } | |
513 | ||
514 | return clk; | |
515 | } |