[mirror_ubuntu-focal-kernel.git] / drivers / clk / mvebu / ap806-system-controller.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Marvell Armada AP806 System Controller
 *
 * Copyright (C) 2016 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 */

#define pr_fmt(fmt) "ap806-system-controller: " fmt

#include "armada_ap_cp_helper.h"
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

#define AP806_SAR_REG			0x400
#define AP806_SAR_CLKFREQ_MODE_MASK	0x1f

#define AP806_CLK_NUM			6

static struct clk *ap806_clks[AP806_CLK_NUM];

static struct clk_onecell_data ap806_clk_data = {
	.clks = ap806_clks,
	.clk_num = AP806_CLK_NUM,
};

static int ap806_get_sar_clocks(unsigned int freq_mode,
				unsigned int *cpuclk_freq,
				unsigned int *dclk_freq)
{
	switch (freq_mode) {
	case 0x0:
		*cpuclk_freq = 2000;
		*dclk_freq = 600;
		break;
	case 0x1:
		*cpuclk_freq = 2000;
		*dclk_freq = 525;
		break;
	case 0x6:
		*cpuclk_freq = 1800;
		*dclk_freq = 600;
		break;
	case 0x7:
		*cpuclk_freq = 1800;
		*dclk_freq = 525;
		break;
	case 0x4:
		*cpuclk_freq = 1600;
		*dclk_freq = 400;
		break;
	case 0xB:
		*cpuclk_freq = 1600;
		*dclk_freq = 450;
		break;
	case 0xD:
		*cpuclk_freq = 1600;
		*dclk_freq = 525;
		break;
	case 0x1a:
		*cpuclk_freq = 1400;
		*dclk_freq = 400;
		break;
	case 0x14:
		*cpuclk_freq = 1300;
		*dclk_freq = 400;
		break;
	case 0x17:
		*cpuclk_freq = 1300;
		*dclk_freq = 325;
		break;
	case 0x19:
		*cpuclk_freq = 1200;
		*dclk_freq = 400;
		break;
	case 0x13:
		*cpuclk_freq = 1000;
		*dclk_freq = 325;
		break;
	case 0x1d:
		*cpuclk_freq = 1000;
		*dclk_freq = 400;
		break;
	case 0x1c:
		*cpuclk_freq = 800;
		*dclk_freq = 400;
		break;
	case 0x1b:
		*cpuclk_freq = 600;
		*dclk_freq = 400;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int ap807_get_sar_clocks(unsigned int freq_mode,
				unsigned int *cpuclk_freq,
				unsigned int *dclk_freq)
{
	switch (freq_mode) {
	case 0x0:
		*cpuclk_freq = 2000;
		*dclk_freq = 1200;
		break;
	case 0x6:
		*cpuclk_freq = 2200;
		*dclk_freq = 1200;
		break;
	case 0xD:
		*cpuclk_freq = 1600;
		*dclk_freq = 1200;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int ap806_syscon_common_probe(struct platform_device *pdev,
				     struct device_node *syscon_node)
{
	unsigned int freq_mode, cpuclk_freq, dclk_freq;
	const char *name, *fixedclk_name;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct regmap *regmap;
	u32 reg;
	int ret;

	regmap = syscon_node_to_regmap(syscon_node);
	if (IS_ERR(regmap)) {
		dev_err(dev, "cannot get regmap\n");
		return PTR_ERR(regmap);
	}

	ret = regmap_read(regmap, AP806_SAR_REG, &reg);
	if (ret) {
		dev_err(dev, "cannot read from regmap\n");
		return ret;
	}

	freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;

	if (of_device_is_compatible(pdev->dev.of_node,
				    "marvell,ap806-clock")) {
		ret = ap806_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
	} else if (of_device_is_compatible(pdev->dev.of_node,
					   "marvell,ap807-clock")) {
		ret = ap807_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
	} else {
		dev_err(dev, "compatible not supported\n");
		return -EINVAL;
	}

	if (ret) {
		dev_err(dev, "invalid Sample at Reset value\n");
		return ret;
	}

	/* Convert to hertz */
	cpuclk_freq *= 1000 * 1000;
	dclk_freq *= 1000 * 1000;

	/* CPU clocks depend on the Sample At Reset configuration */
	name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-0");
	ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
						0, cpuclk_freq);
	if (IS_ERR(ap806_clks[0])) {
		ret = PTR_ERR(ap806_clks[0]);
		goto fail0;
	}

	name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-1");
	ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
						cpuclk_freq);
	if (IS_ERR(ap806_clks[1])) {
		ret = PTR_ERR(ap806_clks[1]);
		goto fail1;
	}

	/* Fixed clock is always 1200 Mhz */
	fixedclk_name = ap_cp_unique_name(dev, syscon_node, "fixed");
	ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
						0, 1200 * 1000 * 1000);
	if (IS_ERR(ap806_clks[2])) {
		ret = PTR_ERR(ap806_clks[2]);
		goto fail2;
	}

	/* MSS Clock is fixed clock divided by 6 */
	name = ap_cp_unique_name(dev, syscon_node, "mss");
	ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
						  0, 1, 6);
	if (IS_ERR(ap806_clks[3])) {
		ret = PTR_ERR(ap806_clks[3]);
		goto fail3;
	}

	/* SDIO(/eMMC) Clock is fixed clock divided by 3 */
	name = ap_cp_unique_name(dev, syscon_node, "sdio");
	ap806_clks[4] = clk_register_fixed_factor(NULL, name,
						  fixedclk_name,
						  0, 1, 3);
	if (IS_ERR(ap806_clks[4])) {
		ret = PTR_ERR(ap806_clks[4]);
		goto fail4;
	}

	/* AP-DCLK(HCLK) Clock is DDR clock divided by 2 */
	name = ap_cp_unique_name(dev, syscon_node, "ap-dclk");
	ap806_clks[5] = clk_register_fixed_rate(dev, name, NULL, 0, dclk_freq);
	if (IS_ERR(ap806_clks[5])) {
		ret = PTR_ERR(ap806_clks[5]);
		goto fail5;
	}

	ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
	if (ret)
		goto fail_clk_add;

	return 0;

fail_clk_add:
	clk_unregister_fixed_factor(ap806_clks[5]);
fail5:
	clk_unregister_fixed_factor(ap806_clks[4]);
fail4:
	clk_unregister_fixed_factor(ap806_clks[3]);
fail3:
	clk_unregister_fixed_rate(ap806_clks[2]);
fail2:
	clk_unregister_fixed_rate(ap806_clks[1]);
fail1:
	clk_unregister_fixed_rate(ap806_clks[0]);
fail0:
	return ret;
}

static int ap806_syscon_legacy_probe(struct platform_device *pdev)
{
	dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n");
	dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n");
	dev_warn(&pdev->dev, FW_WARN
		 "This binding won't be supported in future kernel\n");

	return ap806_syscon_common_probe(pdev, pdev->dev.of_node);

}

static int ap806_clock_probe(struct platform_device *pdev)
{
	return ap806_syscon_common_probe(pdev, pdev->dev.of_node->parent);
}

static const struct of_device_id ap806_syscon_legacy_of_match[] = {
	{ .compatible = "marvell,ap806-system-controller", },
	{ }
};

static struct platform_driver ap806_syscon_legacy_driver = {
	.probe = ap806_syscon_legacy_probe,
	.driver		= {
		.name	= "marvell-ap806-system-controller",
		.of_match_table = ap806_syscon_legacy_of_match,
		.suppress_bind_attrs = true,
	},
};
builtin_platform_driver(ap806_syscon_legacy_driver);

static const struct of_device_id ap806_clock_of_match[] = {
	{ .compatible = "marvell,ap806-clock", },
	{ .compatible = "marvell,ap807-clock", },
	{ }
};

static struct platform_driver ap806_clock_driver = {
	.probe = ap806_clock_probe,
	.driver		= {
		.name	= "marvell-ap806-clock",
		.of_match_table = ap806_clock_of_match,
		.suppress_bind_attrs = true,
	},
};
builtin_platform_driver(ap806_clock_driver);
Commit	Line	Data
c3828949	1	// SPDX-License-Identifier: GPL-2.0
89a426b1 TP	2	/*
	3	* Marvell Armada AP806 System Controller
	4	*
	5	* Copyright (C) 2016 Marvell
	6	*
	7	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	8	*
89a426b1 TP	9	*/
	10
	11	#define pr_fmt(fmt) "ap806-system-controller: " fmt
	12
33c02590	13	#include "armada_ap_cp_helper.h"
89a426b1 TP	14	#include <linux/clk-provider.h>
89a426b1 TP	15	#include <linux/mfd/syscon.h>
188e8719	16	#include <linux/init.h>
89a426b1	17	#include <linux/of.h>
89a426b1 TP	18	#include <linux/platform_device.h>
	19	#include <linux/regmap.h>
	20
	21	#define AP806_SAR_REG 0x400
	22	#define AP806_SAR_CLKFREQ_MODE_MASK 0x1f
	23
0099dc44	24	#define AP806_CLK_NUM 6
89a426b1 TP	25
	26	static struct clk *ap806_clks[AP806_CLK_NUM];
	27
	28	static struct clk_onecell_data ap806_clk_data = {
	29	.clks = ap806_clks,
	30	.clk_num = AP806_CLK_NUM,
	31	};
	32
be69e55d BP	33	static int ap806_get_sar_clocks(unsigned int freq_mode,
	34	unsigned int *cpuclk_freq,
	35	unsigned int *dclk_freq)
89a426b1	36	{
89a426b1	37	switch (freq_mode) {
0c70ffc5	38	case 0x0:
be69e55d BP	39	*cpuclk_freq = 2000;
	40	*dclk_freq = 600;
	41	break;
0c70ffc5	42	case 0x1:
be69e55d BP	43	*cpuclk_freq = 2000;
be69e55d BP	44	*dclk_freq = 525;
89a426b1	45	break;
0c70ffc5	46	case 0x6:
be69e55d BP	47	*cpuclk_freq = 1800;
	48	*dclk_freq = 600;
	49	break;
0c70ffc5	50	case 0x7:
be69e55d BP	51	*cpuclk_freq = 1800;
be69e55d BP	52	*dclk_freq = 525;
89a426b1	53	break;
0c70ffc5	54	case 0x4:
be69e55d BP	55	*cpuclk_freq = 1600;
	56	*dclk_freq = 400;
	57	break;
0c70ffc5	58	case 0xB:
be69e55d BP	59	*cpuclk_freq = 1600;
	60	*dclk_freq = 450;
	61	break;
0c70ffc5	62	case 0xD:
be69e55d BP	63	*cpuclk_freq = 1600;
be69e55d BP	64	*dclk_freq = 525;
89a426b1	65	break;
0c70ffc5	66	case 0x1a:
be69e55d BP	67	*cpuclk_freq = 1400;
be69e55d BP	68	*dclk_freq = 400;
89a426b1	69	break;
0c70ffc5	70	case 0x14:
be69e55d BP	71	*cpuclk_freq = 1300;
	72	*dclk_freq = 400;
	73	break;
0c70ffc5	74	case 0x17:
be69e55d BP	75	*cpuclk_freq = 1300;
be69e55d BP	76	*dclk_freq = 325;
89a426b1	77	break;
0c70ffc5	78	case 0x19:
be69e55d BP	79	*cpuclk_freq = 1200;
be69e55d BP	80	*dclk_freq = 400;
0c70ffc5 TP	81	break;
0c70ffc5 TP	82	case 0x13:
be69e55d BP	83	*cpuclk_freq = 1000;
	84	*dclk_freq = 325;
	85	break;
0c70ffc5	86	case 0x1d:
be69e55d BP	87	*cpuclk_freq = 1000;
be69e55d BP	88	*dclk_freq = 400;
0c70ffc5 TP	89	break;
0c70ffc5 TP	90	case 0x1c:
be69e55d BP	91	*cpuclk_freq = 800;
be69e55d BP	92	*dclk_freq = 400;
0c70ffc5 TP	93	break;
0c70ffc5 TP	94	case 0x1b:
be69e55d BP	95	*cpuclk_freq = 600;
be69e55d BP	96	*dclk_freq = 400;
0c70ffc5	97	break;
89a426b1	98	default:
89a426b1 TP	99	return -EINVAL;
	100	}
	101
be69e55d BP	102	return 0;
	103	}
	104
c0448dce BP	105	static int ap807_get_sar_clocks(unsigned int freq_mode,
	106	unsigned int *cpuclk_freq,
	107	unsigned int *dclk_freq)
	108	{
	109	switch (freq_mode) {
	110	case 0x0:
	111	*cpuclk_freq = 2000;
	112	*dclk_freq = 1200;
	113	break;
	114	case 0x6:
	115	*cpuclk_freq = 2200;
	116	*dclk_freq = 1200;
	117	break;
	118	case 0xD:
	119	*cpuclk_freq = 1600;
	120	*dclk_freq = 1200;
	121	break;
	122	default:
	123	return -EINVAL;
	124	}
	125
	126	return 0;
	127	}
	128
be69e55d BP	129	static int ap806_syscon_common_probe(struct platform_device *pdev,
	130	struct device_node *syscon_node)
	131	{
	132	unsigned int freq_mode, cpuclk_freq, dclk_freq;
	133	const char name, fixedclk_name;
	134	struct device *dev = &pdev->dev;
	135	struct device_node *np = dev->of_node;
	136	struct regmap *regmap;
	137	u32 reg;
	138	int ret;
	139
	140	regmap = syscon_node_to_regmap(syscon_node);
	141	if (IS_ERR(regmap)) {
	142	dev_err(dev, "cannot get regmap\n");
	143	return PTR_ERR(regmap);
	144	}
	145
	146	ret = regmap_read(regmap, AP806_SAR_REG, &reg);
	147	if (ret) {
	148	dev_err(dev, "cannot read from regmap\n");
	149	return ret;
	150	}
	151
	152	freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
	153
	154	if (of_device_is_compatible(pdev->dev.of_node,
	155	"marvell,ap806-clock")) {
	156	ret = ap806_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
c0448dce BP	157	} else if (of_device_is_compatible(pdev->dev.of_node,
	158	"marvell,ap807-clock")) {
	159	ret = ap807_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
be69e55d BP	160	} else {
	161	dev_err(dev, "compatible not supported\n");
	162	return -EINVAL;
	163	}
	164
	165	if (ret) {
0099dc44	166	dev_err(dev, "invalid Sample at Reset value\n");
be69e55d	167	return ret;
0099dc44 OI	168	}
0099dc44 OI	169
89a426b1 TP	170	/* Convert to hertz */
89a426b1 TP	171	cpuclk_freq = 1000 1000;
0099dc44	172	dclk_freq = 1000 1000;
89a426b1 TP	173
89a426b1 TP	174	/* CPU clocks depend on the Sample At Reset configuration */
baf4c10f	175	name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-0");
d9ff21ee	176	ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
89a426b1 TP	177	0, cpuclk_freq);
	178	if (IS_ERR(ap806_clks[0])) {
	179	ret = PTR_ERR(ap806_clks[0]);
	180	goto fail0;
	181	}
	182
baf4c10f	183	name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-1");
d9ff21ee	184	ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
89a426b1 TP	185	cpuclk_freq);
	186	if (IS_ERR(ap806_clks[1])) {
	187	ret = PTR_ERR(ap806_clks[1]);
	188	goto fail1;
	189	}
	190
	191	/* Fixed clock is always 1200 Mhz */
33c02590	192	fixedclk_name = ap_cp_unique_name(dev, syscon_node, "fixed");
d9ff21ee	193	ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
89a426b1 TP	194	0, 1200 * 1000 * 1000);
	195	if (IS_ERR(ap806_clks[2])) {
	196	ret = PTR_ERR(ap806_clks[2]);
	197	goto fail2;
	198	}
	199
	200	/* MSS Clock is fixed clock divided by 6 */
33c02590	201	name = ap_cp_unique_name(dev, syscon_node, "mss");
89a426b1 TP	202	ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
	203	0, 1, 6);
	204	if (IS_ERR(ap806_clks[3])) {
	205	ret = PTR_ERR(ap806_clks[3]);
	206	goto fail3;
	207	}
	208
55de4d06	209	/* SDIO(/eMMC) Clock is fixed clock divided by 3 */
33c02590	210	name = ap_cp_unique_name(dev, syscon_node, "sdio");
55de4d06 GC	211	ap806_clks[4] = clk_register_fixed_factor(NULL, name,
	212	fixedclk_name,
	213	0, 1, 3);
	214	if (IS_ERR(ap806_clks[4])) {
	215	ret = PTR_ERR(ap806_clks[4]);
	216	goto fail4;
a8309ced KP	217	}
a8309ced KP	218
0099dc44 OI	219	/* AP-DCLK(HCLK) Clock is DDR clock divided by 2 */
	220	name = ap_cp_unique_name(dev, syscon_node, "ap-dclk");
	221	ap806_clks[5] = clk_register_fixed_rate(dev, name, NULL, 0, dclk_freq);
	222	if (IS_ERR(ap806_clks[5])) {
	223	ret = PTR_ERR(ap806_clks[5]);
	224	goto fail5;
	225	}
	226
89a426b1 TP	227	ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
	228	if (ret)
	229	goto fail_clk_add;
	230
	231	return 0;
	232
	233	fail_clk_add:
0099dc44 OI	234	clk_unregister_fixed_factor(ap806_clks[5]);
0099dc44 OI	235	fail5:
a8309ced KP	236	clk_unregister_fixed_factor(ap806_clks[4]);
a8309ced KP	237	fail4:
89a426b1 TP	238	clk_unregister_fixed_factor(ap806_clks[3]);
	239	fail3:
	240	clk_unregister_fixed_rate(ap806_clks[2]);
	241	fail2:
	242	clk_unregister_fixed_rate(ap806_clks[1]);
	243	fail1:
	244	clk_unregister_fixed_rate(ap806_clks[0]);
	245	fail0:
	246	return ret;
	247	}
	248
b90da675 GC	249	static int ap806_syscon_legacy_probe(struct platform_device *pdev)
	250	{
	251	dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n");
	252	dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n");
	253	dev_warn(&pdev->dev, FW_WARN
	254	"This binding won't be supported in future kernel\n");
	255
	256	return ap806_syscon_common_probe(pdev, pdev->dev.of_node);
	257
	258	}
	259
	260	static int ap806_clock_probe(struct platform_device *pdev)
	261	{
	262	return ap806_syscon_common_probe(pdev, pdev->dev.of_node->parent);
	263	}
	264
	265	static const struct of_device_id ap806_syscon_legacy_of_match[] = {
89a426b1 TP	266	{ .compatible = "marvell,ap806-system-controller", },
	267	{ }
	268	};
89a426b1	269
b90da675 GC	270	static struct platform_driver ap806_syscon_legacy_driver = {
b90da675 GC	271	.probe = ap806_syscon_legacy_probe,
89a426b1 TP	272	.driver = {
89a426b1 TP	273	.name = "marvell-ap806-system-controller",
b90da675 GC	274	.of_match_table = ap806_syscon_legacy_of_match,
	275	.suppress_bind_attrs = true,
	276	},
	277	};
	278	builtin_platform_driver(ap806_syscon_legacy_driver);
	279
	280	static const struct of_device_id ap806_clock_of_match[] = {
	281	{ .compatible = "marvell,ap806-clock", },
c0448dce	282	{ .compatible = "marvell,ap807-clock", },
b90da675 GC	283	{ }
	284	};
	285
	286	static struct platform_driver ap806_clock_driver = {
	287	.probe = ap806_clock_probe,
	288	.driver = {
	289	.name = "marvell-ap806-clock",
	290	.of_match_table = ap806_clock_of_match,
188e8719	291	.suppress_bind_attrs = true,
89a426b1 TP	292	},
89a426b1 TP	293	};
b90da675	294	builtin_platform_driver(ap806_clock_driver);