[mirror_ubuntu-artful-kernel.git] / drivers / clk / mvebu / ap806-system-controller.c

/*
 * Marvell Armada AP806 System Controller
 *
 * Copyright (C) 2016 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#define pr_fmt(fmt) "ap806-system-controller: " fmt

#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

#define AP806_SAR_REG			0x400
#define AP806_SAR_CLKFREQ_MODE_MASK	0x1f

#define AP806_CLK_NUM			4

static struct clk *ap806_clks[AP806_CLK_NUM];

static struct clk_onecell_data ap806_clk_data = {
	.clks = ap806_clks,
	.clk_num = AP806_CLK_NUM,
};

static int ap806_syscon_clk_probe(struct platform_device *pdev)
{
	unsigned int freq_mode, cpuclk_freq;
	const char *name, *fixedclk_name;
	struct device_node *np = pdev->dev.of_node;
	struct regmap *regmap;
	u32 reg;
	int ret;

	regmap = syscon_node_to_regmap(np);
	if (IS_ERR(regmap)) {
		dev_err(&pdev->dev, "cannot get regmap\n");
		return PTR_ERR(regmap);
	}

	ret = regmap_read(regmap, AP806_SAR_REG, &reg);
	if (ret) {
		dev_err(&pdev->dev, "cannot read from regmap\n");
		return ret;
	}

	freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
	switch (freq_mode) {
	case 0x0:
	case 0x1:
		cpuclk_freq = 2000;
		break;
	case 0x6:
	case 0x7:
		cpuclk_freq = 1800;
		break;
	case 0x4:
	case 0xB:
	case 0xD:
		cpuclk_freq = 1600;
		break;
	case 0x1a:
		cpuclk_freq = 1400;
		break;
	case 0x14:
	case 0x17:
		cpuclk_freq = 1300;
		break;
	case 0x19:
		cpuclk_freq = 1200;
		break;
	case 0x13:
	case 0x1d:
		cpuclk_freq = 1000;
		break;
	case 0x1c:
		cpuclk_freq = 800;
		break;
	case 0x1b:
		cpuclk_freq = 600;
		break;
	default:
		dev_err(&pdev->dev, "invalid SAR value\n");
		return -EINVAL;
	}

	/* Convert to hertz */
	cpuclk_freq *= 1000 * 1000;

	/* CPU clocks depend on the Sample At Reset configuration */
	of_property_read_string_index(np, "clock-output-names",
				      0, &name);
	ap806_clks[0] = clk_register_fixed_rate(&pdev->dev, name, NULL,
						0, cpuclk_freq);
	if (IS_ERR(ap806_clks[0])) {
		ret = PTR_ERR(ap806_clks[0]);
		goto fail0;
	}

	of_property_read_string_index(np, "clock-output-names",
				      1, &name);
	ap806_clks[1] = clk_register_fixed_rate(&pdev->dev, name, NULL, 0,
						cpuclk_freq);
	if (IS_ERR(ap806_clks[1])) {
		ret = PTR_ERR(ap806_clks[1]);
		goto fail1;
	}

	/* Fixed clock is always 1200 Mhz */
	of_property_read_string_index(np, "clock-output-names",
				      2, &fixedclk_name);
	ap806_clks[2] = clk_register_fixed_rate(&pdev->dev, fixedclk_name, NULL,
						0, 1200 * 1000 * 1000);
	if (IS_ERR(ap806_clks[2])) {
		ret = PTR_ERR(ap806_clks[2]);
		goto fail2;
	}

	/* MSS Clock is fixed clock divided by 6 */
	of_property_read_string_index(np, "clock-output-names",
				      3, &name);
	ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
						  0, 1, 6);
	if (IS_ERR(ap806_clks[3])) {
		ret = PTR_ERR(ap806_clks[3]);
		goto fail3;
	}

	ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
	if (ret)
		goto fail_clk_add;

	return 0;

fail_clk_add:
	clk_unregister_fixed_factor(ap806_clks[3]);
fail3:
	clk_unregister_fixed_rate(ap806_clks[2]);
fail2:
	clk_unregister_fixed_rate(ap806_clks[1]);
fail1:
	clk_unregister_fixed_rate(ap806_clks[0]);
fail0:
	return ret;
}

static const struct of_device_id ap806_syscon_of_match[] = {
	{ .compatible = "marvell,ap806-system-controller", },
	{ }
};

static struct platform_driver ap806_syscon_driver = {
	.probe = ap806_syscon_clk_probe,
	.driver		= {
		.name	= "marvell-ap806-system-controller",
		.of_match_table = ap806_syscon_of_match,
		.suppress_bind_attrs = true,
	},
};
builtin_platform_driver(ap806_syscon_driver);
Commit	Line	Data
89a426b1 TP	1	/*
	2	* Marvell Armada AP806 System Controller
	3	*
	4	* Copyright (C) 2016 Marvell
	5	*
	6	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#define pr_fmt(fmt) "ap806-system-controller: " fmt
	14
	15	#include <linux/clk-provider.h>
	16	#include <linux/mfd/syscon.h>
188e8719	17	#include <linux/init.h>
89a426b1 TP	18	#include <linux/of.h>
	19	#include <linux/of_address.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/regmap.h>
	22
	23	#define AP806_SAR_REG 0x400
	24	#define AP806_SAR_CLKFREQ_MODE_MASK 0x1f
	25
	26	#define AP806_CLK_NUM 4
	27
	28	static struct clk *ap806_clks[AP806_CLK_NUM];
	29
	30	static struct clk_onecell_data ap806_clk_data = {
	31	.clks = ap806_clks,
	32	.clk_num = AP806_CLK_NUM,
	33	};
	34
	35	static int ap806_syscon_clk_probe(struct platform_device *pdev)
	36	{
	37	unsigned int freq_mode, cpuclk_freq;
	38	const char name, fixedclk_name;
	39	struct device_node *np = pdev->dev.of_node;
	40	struct regmap *regmap;
	41	u32 reg;
	42	int ret;
	43
	44	regmap = syscon_node_to_regmap(np);
	45	if (IS_ERR(regmap)) {
	46	dev_err(&pdev->dev, "cannot get regmap\n");
	47	return PTR_ERR(regmap);
	48	}
	49
	50	ret = regmap_read(regmap, AP806_SAR_REG, &reg);
	51	if (ret) {
	52	dev_err(&pdev->dev, "cannot read from regmap\n");
	53	return ret;
	54	}
	55
	56	freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
	57	switch (freq_mode) {
0c70ffc5 TP	58	case 0x0:
0c70ffc5 TP	59	case 0x1:
89a426b1 TP	60	cpuclk_freq = 2000;
89a426b1 TP	61	break;
0c70ffc5 TP	62	case 0x6:
0c70ffc5 TP	63	case 0x7:
89a426b1 TP	64	cpuclk_freq = 1800;
89a426b1 TP	65	break;
0c70ffc5 TP	66	case 0x4:
	67	case 0xB:
	68	case 0xD:
89a426b1 TP	69	cpuclk_freq = 1600;
89a426b1 TP	70	break;
0c70ffc5	71	case 0x1a:
89a426b1 TP	72	cpuclk_freq = 1400;
89a426b1 TP	73	break;
0c70ffc5 TP	74	case 0x14:
0c70ffc5 TP	75	case 0x17:
89a426b1 TP	76	cpuclk_freq = 1300;
89a426b1 TP	77	break;
0c70ffc5 TP	78	case 0x19:
	79	cpuclk_freq = 1200;
	80	break;
	81	case 0x13:
	82	case 0x1d:
	83	cpuclk_freq = 1000;
	84	break;
	85	case 0x1c:
	86	cpuclk_freq = 800;
	87	break;
	88	case 0x1b:
	89	cpuclk_freq = 600;
	90	break;
89a426b1 TP	91	default:
	92	dev_err(&pdev->dev, "invalid SAR value\n");
	93	return -EINVAL;
	94	}
	95
	96	/* Convert to hertz */
	97	cpuclk_freq = 1000 1000;
	98
	99	/* CPU clocks depend on the Sample At Reset configuration */
	100	of_property_read_string_index(np, "clock-output-names",
	101	0, &name);
	102	ap806_clks[0] = clk_register_fixed_rate(&pdev->dev, name, NULL,
	103	0, cpuclk_freq);
	104	if (IS_ERR(ap806_clks[0])) {
	105	ret = PTR_ERR(ap806_clks[0]);
	106	goto fail0;
	107	}
	108
	109	of_property_read_string_index(np, "clock-output-names",
	110	1, &name);
	111	ap806_clks[1] = clk_register_fixed_rate(&pdev->dev, name, NULL, 0,
	112	cpuclk_freq);
	113	if (IS_ERR(ap806_clks[1])) {
	114	ret = PTR_ERR(ap806_clks[1]);
	115	goto fail1;
	116	}
	117
	118	/* Fixed clock is always 1200 Mhz */
	119	of_property_read_string_index(np, "clock-output-names",
	120	2, &fixedclk_name);
	121	ap806_clks[2] = clk_register_fixed_rate(&pdev->dev, fixedclk_name, NULL,
	122	0, 1200 * 1000 * 1000);
	123	if (IS_ERR(ap806_clks[2])) {
	124	ret = PTR_ERR(ap806_clks[2]);
	125	goto fail2;
	126	}
	127
	128	/* MSS Clock is fixed clock divided by 6 */
	129	of_property_read_string_index(np, "clock-output-names",
	130	3, &name);
	131	ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
	132	0, 1, 6);
	133	if (IS_ERR(ap806_clks[3])) {
	134	ret = PTR_ERR(ap806_clks[3]);
	135	goto fail3;
	136	}
	137
	138	ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
	139	if (ret)
	140	goto fail_clk_add;
	141
	142	return 0;
	143
	144	fail_clk_add:
	145	clk_unregister_fixed_factor(ap806_clks[3]);
	146	fail3:
	147	clk_unregister_fixed_rate(ap806_clks[2]);
	148	fail2:
	149	clk_unregister_fixed_rate(ap806_clks[1]);
	150	fail1:
	151	clk_unregister_fixed_rate(ap806_clks[0]);
	152	fail0:
	153	return ret;
	154	}
155
89a426b1 TP	156	static const struct of_device_id ap806_syscon_of_match[] = {
	157	{ .compatible = "marvell,ap806-system-controller", },
	158	{ }
	159	};
89a426b1 TP	160
	161	static struct platform_driver ap806_syscon_driver = {
	162	.probe = ap806_syscon_clk_probe,
89a426b1 TP	163	.driver = {
	164	.name = "marvell-ap806-system-controller",
	165	.of_match_table = ap806_syscon_of_match,
188e8719	166	.suppress_bind_attrs = true,
89a426b1 TP	167	},
89a426b1 TP	168	};
188e8719	169	builtin_platform_driver(ap806_syscon_driver);