[mirror_ubuntu-focal-kernel.git] / drivers / clk / mvebu / ap806-system-controller.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Marvell Armada AP806 System Controller
 *
 * Copyright (C) 2016 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 */

#define pr_fmt(fmt) "ap806-system-controller: " fmt

#include "armada_ap_cp_helper.h"
#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

#define AP806_SAR_REG			0x400
#define AP806_SAR_CLKFREQ_MODE_MASK	0x1f

#define AP806_CLK_NUM			6

static struct clk *ap806_clks[AP806_CLK_NUM];

static struct clk_onecell_data ap806_clk_data = {
	.clks = ap806_clks,
	.clk_num = AP806_CLK_NUM,
};

static int ap806_get_sar_clocks(unsigned int freq_mode,
				unsigned int *cpuclk_freq,
				unsigned int *dclk_freq)
{
	switch (freq_mode) {
	case 0x0:
		*cpuclk_freq = 2000;
		*dclk_freq = 600;
		break;
	case 0x1:
		*cpuclk_freq = 2000;
		*dclk_freq = 525;
		break;
	case 0x6:
		*cpuclk_freq = 1800;
		*dclk_freq = 600;
		break;
	case 0x7:
		*cpuclk_freq = 1800;
		*dclk_freq = 525;
		break;
	case 0x4:
		*cpuclk_freq = 1600;
		*dclk_freq = 400;
		break;
	case 0xB:
		*cpuclk_freq = 1600;
		*dclk_freq = 450;
		break;
	case 0xD:
		*cpuclk_freq = 1600;
		*dclk_freq = 525;
		break;
	case 0x1a:
		*cpuclk_freq = 1400;
		*dclk_freq = 400;
		break;
	case 0x14:
		*cpuclk_freq = 1300;
		*dclk_freq = 400;
		break;
	case 0x17:
		*cpuclk_freq = 1300;
		*dclk_freq = 325;
		break;
	case 0x19:
		*cpuclk_freq = 1200;
		*dclk_freq = 400;
		break;
	case 0x13:
		*cpuclk_freq = 1000;
		*dclk_freq = 325;
		break;
	case 0x1d:
		*cpuclk_freq = 1000;
		*dclk_freq = 400;
		break;
	case 0x1c:
		*cpuclk_freq = 800;
		*dclk_freq = 400;
		break;
	case 0x1b:
		*cpuclk_freq = 600;
		*dclk_freq = 400;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int ap806_syscon_common_probe(struct platform_device *pdev,
				     struct device_node *syscon_node)
{
	unsigned int freq_mode, cpuclk_freq, dclk_freq;
	const char *name, *fixedclk_name;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct regmap *regmap;
	u32 reg;
	int ret;

	regmap = syscon_node_to_regmap(syscon_node);
	if (IS_ERR(regmap)) {
		dev_err(dev, "cannot get regmap\n");
		return PTR_ERR(regmap);
	}

	ret = regmap_read(regmap, AP806_SAR_REG, &reg);
	if (ret) {
		dev_err(dev, "cannot read from regmap\n");
		return ret;
	}

	freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;

	if (of_device_is_compatible(pdev->dev.of_node,
				    "marvell,ap806-clock")) {
		ret = ap806_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
	} else {
		dev_err(dev, "compatible not supported\n");
		return -EINVAL;
	}

	if (ret) {
		dev_err(dev, "invalid Sample at Reset value\n");
		return ret;
	}

	/* Convert to hertz */
	cpuclk_freq *= 1000 * 1000;
	dclk_freq *= 1000 * 1000;

	/* CPU clocks depend on the Sample At Reset configuration */
	name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-0");
	ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
						0, cpuclk_freq);
	if (IS_ERR(ap806_clks[0])) {
		ret = PTR_ERR(ap806_clks[0]);
		goto fail0;
	}

	name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-1");
	ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
						cpuclk_freq);
	if (IS_ERR(ap806_clks[1])) {
		ret = PTR_ERR(ap806_clks[1]);
		goto fail1;
	}

	/* Fixed clock is always 1200 Mhz */
	fixedclk_name = ap_cp_unique_name(dev, syscon_node, "fixed");
	ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
						0, 1200 * 1000 * 1000);
	if (IS_ERR(ap806_clks[2])) {
		ret = PTR_ERR(ap806_clks[2]);
		goto fail2;
	}

	/* MSS Clock is fixed clock divided by 6 */
	name = ap_cp_unique_name(dev, syscon_node, "mss");
	ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
						  0, 1, 6);
	if (IS_ERR(ap806_clks[3])) {
		ret = PTR_ERR(ap806_clks[3]);
		goto fail3;
	}

	/* SDIO(/eMMC) Clock is fixed clock divided by 3 */
	name = ap_cp_unique_name(dev, syscon_node, "sdio");
	ap806_clks[4] = clk_register_fixed_factor(NULL, name,
						  fixedclk_name,
						  0, 1, 3);
	if (IS_ERR(ap806_clks[4])) {
		ret = PTR_ERR(ap806_clks[4]);
		goto fail4;
	}

	/* AP-DCLK(HCLK) Clock is DDR clock divided by 2 */
	name = ap_cp_unique_name(dev, syscon_node, "ap-dclk");
	ap806_clks[5] = clk_register_fixed_rate(dev, name, NULL, 0, dclk_freq);
	if (IS_ERR(ap806_clks[5])) {
		ret = PTR_ERR(ap806_clks[5]);
		goto fail5;
	}

	ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
	if (ret)
		goto fail_clk_add;

	return 0;

fail_clk_add:
	clk_unregister_fixed_factor(ap806_clks[5]);
fail5:
	clk_unregister_fixed_factor(ap806_clks[4]);
fail4:
	clk_unregister_fixed_factor(ap806_clks[3]);
fail3:
	clk_unregister_fixed_rate(ap806_clks[2]);
fail2:
	clk_unregister_fixed_rate(ap806_clks[1]);
fail1:
	clk_unregister_fixed_rate(ap806_clks[0]);
fail0:
	return ret;
}

static int ap806_syscon_legacy_probe(struct platform_device *pdev)
{
	dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n");
	dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n");
	dev_warn(&pdev->dev, FW_WARN
		 "This binding won't be supported in future kernel\n");

	return ap806_syscon_common_probe(pdev, pdev->dev.of_node);

}

static int ap806_clock_probe(struct platform_device *pdev)
{
	return ap806_syscon_common_probe(pdev, pdev->dev.of_node->parent);
}

static const struct of_device_id ap806_syscon_legacy_of_match[] = {
	{ .compatible = "marvell,ap806-system-controller", },
	{ }
};

static struct platform_driver ap806_syscon_legacy_driver = {
	.probe = ap806_syscon_legacy_probe,
	.driver		= {
		.name	= "marvell-ap806-system-controller",
		.of_match_table = ap806_syscon_legacy_of_match,
		.suppress_bind_attrs = true,
	},
};
builtin_platform_driver(ap806_syscon_legacy_driver);

static const struct of_device_id ap806_clock_of_match[] = {
	{ .compatible = "marvell,ap806-clock", },
	{ }
};

static struct platform_driver ap806_clock_driver = {
	.probe = ap806_clock_probe,
	.driver		= {
		.name	= "marvell-ap806-clock",
		.of_match_table = ap806_clock_of_match,
		.suppress_bind_attrs = true,
	},
};
builtin_platform_driver(ap806_clock_driver);
Commit	Line	Data
c3828949	1	// SPDX-License-Identifier: GPL-2.0
89a426b1 TP	2	/*
	3	* Marvell Armada AP806 System Controller
	4	*
	5	* Copyright (C) 2016 Marvell
	6	*
	7	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	8	*
89a426b1 TP	9	*/
	10
	11	#define pr_fmt(fmt) "ap806-system-controller: " fmt
	12
33c02590	13	#include "armada_ap_cp_helper.h"
89a426b1 TP	14	#include <linux/clk-provider.h>
89a426b1 TP	15	#include <linux/mfd/syscon.h>
188e8719	16	#include <linux/init.h>
89a426b1	17	#include <linux/of.h>
89a426b1 TP	18	#include <linux/platform_device.h>
	19	#include <linux/regmap.h>
	20
	21	#define AP806_SAR_REG 0x400
	22	#define AP806_SAR_CLKFREQ_MODE_MASK 0x1f
	23
0099dc44	24	#define AP806_CLK_NUM 6
89a426b1 TP	25
	26	static struct clk *ap806_clks[AP806_CLK_NUM];
	27
	28	static struct clk_onecell_data ap806_clk_data = {
	29	.clks = ap806_clks,
	30	.clk_num = AP806_CLK_NUM,
	31	};
	32
be69e55d BP	33	static int ap806_get_sar_clocks(unsigned int freq_mode,
	34	unsigned int *cpuclk_freq,
	35	unsigned int *dclk_freq)
89a426b1	36	{
89a426b1	37	switch (freq_mode) {
0c70ffc5	38	case 0x0:
be69e55d BP	39	*cpuclk_freq = 2000;
	40	*dclk_freq = 600;
	41	break;
0c70ffc5	42	case 0x1:
be69e55d BP	43	*cpuclk_freq = 2000;
be69e55d BP	44	*dclk_freq = 525;
89a426b1	45	break;
0c70ffc5	46	case 0x6:
be69e55d BP	47	*cpuclk_freq = 1800;
	48	*dclk_freq = 600;
	49	break;
0c70ffc5	50	case 0x7:
be69e55d BP	51	*cpuclk_freq = 1800;
be69e55d BP	52	*dclk_freq = 525;
89a426b1	53	break;
0c70ffc5	54	case 0x4:
be69e55d BP	55	*cpuclk_freq = 1600;
	56	*dclk_freq = 400;
	57	break;
0c70ffc5	58	case 0xB:
be69e55d BP	59	*cpuclk_freq = 1600;
	60	*dclk_freq = 450;
	61	break;
0c70ffc5	62	case 0xD:
be69e55d BP	63	*cpuclk_freq = 1600;
be69e55d BP	64	*dclk_freq = 525;
89a426b1	65	break;
0c70ffc5	66	case 0x1a:
be69e55d BP	67	*cpuclk_freq = 1400;
be69e55d BP	68	*dclk_freq = 400;
89a426b1	69	break;
0c70ffc5	70	case 0x14:
be69e55d BP	71	*cpuclk_freq = 1300;
	72	*dclk_freq = 400;
	73	break;
0c70ffc5	74	case 0x17:
be69e55d BP	75	*cpuclk_freq = 1300;
be69e55d BP	76	*dclk_freq = 325;
89a426b1	77	break;
0c70ffc5	78	case 0x19:
be69e55d BP	79	*cpuclk_freq = 1200;
be69e55d BP	80	*dclk_freq = 400;
0c70ffc5 TP	81	break;
0c70ffc5 TP	82	case 0x13:
be69e55d BP	83	*cpuclk_freq = 1000;
	84	*dclk_freq = 325;
	85	break;
0c70ffc5	86	case 0x1d:
be69e55d BP	87	*cpuclk_freq = 1000;
be69e55d BP	88	*dclk_freq = 400;
0c70ffc5 TP	89	break;
0c70ffc5 TP	90	case 0x1c:
be69e55d BP	91	*cpuclk_freq = 800;
be69e55d BP	92	*dclk_freq = 400;
0c70ffc5 TP	93	break;
0c70ffc5 TP	94	case 0x1b:
be69e55d BP	95	*cpuclk_freq = 600;
be69e55d BP	96	*dclk_freq = 400;
0c70ffc5	97	break;
89a426b1	98	default:
89a426b1 TP	99	return -EINVAL;
	100	}
	101
be69e55d BP	102	return 0;
	103	}
	104
	105	static int ap806_syscon_common_probe(struct platform_device *pdev,
	106	struct device_node *syscon_node)
	107	{
	108	unsigned int freq_mode, cpuclk_freq, dclk_freq;
	109	const char name, fixedclk_name;
	110	struct device *dev = &pdev->dev;
	111	struct device_node *np = dev->of_node;
	112	struct regmap *regmap;
	113	u32 reg;
	114	int ret;
	115
	116	regmap = syscon_node_to_regmap(syscon_node);
	117	if (IS_ERR(regmap)) {
	118	dev_err(dev, "cannot get regmap\n");
	119	return PTR_ERR(regmap);
	120	}
	121
	122	ret = regmap_read(regmap, AP806_SAR_REG, &reg);
	123	if (ret) {
	124	dev_err(dev, "cannot read from regmap\n");
	125	return ret;
	126	}
	127
	128	freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
	129
	130	if (of_device_is_compatible(pdev->dev.of_node,
	131	"marvell,ap806-clock")) {
	132	ret = ap806_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
	133	} else {
	134	dev_err(dev, "compatible not supported\n");
	135	return -EINVAL;
	136	}
	137
	138	if (ret) {
0099dc44	139	dev_err(dev, "invalid Sample at Reset value\n");
be69e55d	140	return ret;
0099dc44 OI	141	}
0099dc44 OI	142
89a426b1 TP	143	/* Convert to hertz */
89a426b1 TP	144	cpuclk_freq = 1000 1000;
0099dc44	145	dclk_freq = 1000 1000;
89a426b1 TP	146
89a426b1 TP	147	/* CPU clocks depend on the Sample At Reset configuration */
baf4c10f	148	name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-0");
d9ff21ee	149	ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
89a426b1 TP	150	0, cpuclk_freq);
	151	if (IS_ERR(ap806_clks[0])) {
	152	ret = PTR_ERR(ap806_clks[0]);
	153	goto fail0;
	154	}
	155
baf4c10f	156	name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-1");
d9ff21ee	157	ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
89a426b1 TP	158	cpuclk_freq);
	159	if (IS_ERR(ap806_clks[1])) {
	160	ret = PTR_ERR(ap806_clks[1]);
	161	goto fail1;
	162	}
	163
	164	/* Fixed clock is always 1200 Mhz */
33c02590	165	fixedclk_name = ap_cp_unique_name(dev, syscon_node, "fixed");
d9ff21ee	166	ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
89a426b1 TP	167	0, 1200 * 1000 * 1000);
	168	if (IS_ERR(ap806_clks[2])) {
	169	ret = PTR_ERR(ap806_clks[2]);
	170	goto fail2;
	171	}
	172
	173	/* MSS Clock is fixed clock divided by 6 */
33c02590	174	name = ap_cp_unique_name(dev, syscon_node, "mss");
89a426b1 TP	175	ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
	176	0, 1, 6);
	177	if (IS_ERR(ap806_clks[3])) {
	178	ret = PTR_ERR(ap806_clks[3]);
	179	goto fail3;
	180	}
	181
55de4d06	182	/* SDIO(/eMMC) Clock is fixed clock divided by 3 */
33c02590	183	name = ap_cp_unique_name(dev, syscon_node, "sdio");
55de4d06 GC	184	ap806_clks[4] = clk_register_fixed_factor(NULL, name,
	185	fixedclk_name,
	186	0, 1, 3);
	187	if (IS_ERR(ap806_clks[4])) {
	188	ret = PTR_ERR(ap806_clks[4]);
	189	goto fail4;
a8309ced KP	190	}
a8309ced KP	191
0099dc44 OI	192	/* AP-DCLK(HCLK) Clock is DDR clock divided by 2 */
	193	name = ap_cp_unique_name(dev, syscon_node, "ap-dclk");
	194	ap806_clks[5] = clk_register_fixed_rate(dev, name, NULL, 0, dclk_freq);
	195	if (IS_ERR(ap806_clks[5])) {
	196	ret = PTR_ERR(ap806_clks[5]);
	197	goto fail5;
	198	}
	199
89a426b1 TP	200	ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
	201	if (ret)
	202	goto fail_clk_add;
	203
	204	return 0;
	205
	206	fail_clk_add:
0099dc44 OI	207	clk_unregister_fixed_factor(ap806_clks[5]);
0099dc44 OI	208	fail5:
a8309ced KP	209	clk_unregister_fixed_factor(ap806_clks[4]);
a8309ced KP	210	fail4:
89a426b1 TP	211	clk_unregister_fixed_factor(ap806_clks[3]);
	212	fail3:
	213	clk_unregister_fixed_rate(ap806_clks[2]);
	214	fail2:
	215	clk_unregister_fixed_rate(ap806_clks[1]);
	216	fail1:
	217	clk_unregister_fixed_rate(ap806_clks[0]);
	218	fail0:
	219	return ret;
	220	}
	221
b90da675 GC	222	static int ap806_syscon_legacy_probe(struct platform_device *pdev)
	223	{
	224	dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n");
	225	dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n");
	226	dev_warn(&pdev->dev, FW_WARN
	227	"This binding won't be supported in future kernel\n");
	228
	229	return ap806_syscon_common_probe(pdev, pdev->dev.of_node);
	230
	231	}
	232
	233	static int ap806_clock_probe(struct platform_device *pdev)
	234	{
	235	return ap806_syscon_common_probe(pdev, pdev->dev.of_node->parent);
	236	}
	237
	238	static const struct of_device_id ap806_syscon_legacy_of_match[] = {
89a426b1 TP	239	{ .compatible = "marvell,ap806-system-controller", },
	240	{ }
	241	};
89a426b1	242
b90da675 GC	243	static struct platform_driver ap806_syscon_legacy_driver = {
b90da675 GC	244	.probe = ap806_syscon_legacy_probe,
89a426b1 TP	245	.driver = {
89a426b1 TP	246	.name = "marvell-ap806-system-controller",
b90da675 GC	247	.of_match_table = ap806_syscon_legacy_of_match,
	248	.suppress_bind_attrs = true,
	249	},
	250	};
	251	builtin_platform_driver(ap806_syscon_legacy_driver);
	252
	253	static const struct of_device_id ap806_clock_of_match[] = {
	254	{ .compatible = "marvell,ap806-clock", },
	255	{ }
	256	};
	257
	258	static struct platform_driver ap806_clock_driver = {
	259	.probe = ap806_clock_probe,
	260	.driver = {
	261	.name = "marvell-ap806-clock",
	262	.of_match_table = ap806_clock_of_match,
188e8719	263	.suppress_bind_attrs = true,
89a426b1 TP	264	},
89a426b1 TP	265	};
b90da675	266	builtin_platform_driver(ap806_clock_driver);