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8ca4746a GC |
1 | /* |
2 | * Marvell Armada 37xx SoC Peripheral clocks | |
3 | * | |
4 | * Copyright (C) 2016 Marvell | |
5 | * | |
6 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2 or later. This program is licensed "as is" | |
10 | * without any warranty of any kind, whether express or implied. | |
11 | * | |
12 | * Most of the peripheral clocks can be modelled like this: | |
13 | * _____ _______ _______ | |
14 | * TBG-A-P --| | | | | | ______ | |
15 | * TBG-B-P --| Mux |--| /div1 |--| /div2 |--| Gate |--> perip_clk | |
16 | * TBG-A-S --| | | | | | |______| | |
17 | * TBG-B-S --|_____| |_______| |_______| | |
18 | * | |
19 | * However some clocks may use only one or two block or and use the | |
20 | * xtal clock as parent. | |
21 | */ | |
22 | ||
23 | #include <linux/clk-provider.h> | |
24 | #include <linux/of.h> | |
25 | #include <linux/of_device.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/slab.h> | |
28 | ||
29 | #define TBG_SEL 0x0 | |
30 | #define DIV_SEL0 0x4 | |
31 | #define DIV_SEL1 0x8 | |
32 | #define DIV_SEL2 0xC | |
33 | #define CLK_SEL 0x10 | |
34 | #define CLK_DIS 0x14 | |
35 | ||
36 | struct clk_periph_driver_data { | |
37 | struct clk_hw_onecell_data *hw_data; | |
38 | spinlock_t lock; | |
39 | }; | |
40 | ||
41 | struct clk_double_div { | |
42 | struct clk_hw hw; | |
43 | void __iomem *reg1; | |
44 | u8 shift1; | |
45 | void __iomem *reg2; | |
46 | u8 shift2; | |
47 | }; | |
48 | ||
49 | #define to_clk_double_div(_hw) container_of(_hw, struct clk_double_div, hw) | |
50 | ||
51 | struct clk_periph_data { | |
52 | const char *name; | |
53 | const char * const *parent_names; | |
54 | int num_parents; | |
55 | struct clk_hw *mux_hw; | |
56 | struct clk_hw *rate_hw; | |
57 | struct clk_hw *gate_hw; | |
58 | bool is_double_div; | |
59 | }; | |
60 | ||
61 | static const struct clk_div_table clk_table6[] = { | |
62 | { .val = 1, .div = 1, }, | |
63 | { .val = 2, .div = 2, }, | |
64 | { .val = 3, .div = 3, }, | |
65 | { .val = 4, .div = 4, }, | |
66 | { .val = 5, .div = 5, }, | |
67 | { .val = 6, .div = 6, }, | |
68 | { .val = 0, .div = 0, }, /* last entry */ | |
69 | }; | |
70 | ||
71 | static const struct clk_div_table clk_table1[] = { | |
72 | { .val = 0, .div = 1, }, | |
73 | { .val = 1, .div = 2, }, | |
74 | { .val = 0, .div = 0, }, /* last entry */ | |
75 | }; | |
76 | ||
77 | static const struct clk_div_table clk_table2[] = { | |
78 | { .val = 0, .div = 2, }, | |
79 | { .val = 1, .div = 4, }, | |
80 | { .val = 0, .div = 0, }, /* last entry */ | |
81 | }; | |
adf4e289 | 82 | |
8ca4746a GC |
83 | static const struct clk_ops clk_double_div_ops; |
84 | ||
85 | #define PERIPH_GATE(_name, _bit) \ | |
86 | struct clk_gate gate_##_name = { \ | |
87 | .reg = (void *)CLK_DIS, \ | |
88 | .bit_idx = _bit, \ | |
89 | .hw.init = &(struct clk_init_data){ \ | |
90 | .ops = &clk_gate_ops, \ | |
91 | } \ | |
92 | }; | |
93 | ||
94 | #define PERIPH_MUX(_name, _shift) \ | |
95 | struct clk_mux mux_##_name = { \ | |
96 | .reg = (void *)TBG_SEL, \ | |
97 | .shift = _shift, \ | |
98 | .mask = 3, \ | |
99 | .hw.init = &(struct clk_init_data){ \ | |
100 | .ops = &clk_mux_ro_ops, \ | |
101 | } \ | |
102 | }; | |
103 | ||
104 | #define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \ | |
105 | struct clk_double_div rate_##_name = { \ | |
106 | .reg1 = (void *)_reg1, \ | |
107 | .reg2 = (void *)_reg2, \ | |
108 | .shift1 = _shift1, \ | |
109 | .shift2 = _shift2, \ | |
110 | .hw.init = &(struct clk_init_data){ \ | |
111 | .ops = &clk_double_div_ops, \ | |
112 | } \ | |
113 | }; | |
114 | ||
115 | #define PERIPH_DIV(_name, _reg, _shift, _table) \ | |
116 | struct clk_divider rate_##_name = { \ | |
117 | .reg = (void *)_reg, \ | |
118 | .table = _table, \ | |
119 | .shift = _shift, \ | |
120 | .hw.init = &(struct clk_init_data){ \ | |
121 | .ops = &clk_divider_ro_ops, \ | |
122 | } \ | |
123 | }; | |
124 | ||
125 | #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\ | |
126 | static PERIPH_GATE(_name, _bit); \ | |
127 | static PERIPH_MUX(_name, _shift); \ | |
128 | static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2); | |
129 | ||
130 | #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ | |
131 | static PERIPH_GATE(_name, _bit); \ | |
132 | static PERIPH_MUX(_name, _shift); \ | |
133 | static PERIPH_DIV(_name, _reg, _shift1, _table); | |
134 | ||
135 | #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ | |
136 | static PERIPH_GATE(_name, _bit); \ | |
137 | static PERIPH_DIV(_name, _reg, _shift, _table); | |
138 | ||
139 | #define PERIPH_CLK_MUX_DIV(_name, _shift, _reg, _shift_div, _table) \ | |
140 | static PERIPH_MUX(_name, _shift); \ | |
141 | static PERIPH_DIV(_name, _reg, _shift_div, _table); | |
142 | ||
143 | #define PERIPH_CLK_MUX_DD(_name, _shift, _reg1, _reg2, _shift1, _shift2)\ | |
144 | static PERIPH_MUX(_name, _shift); \ | |
145 | static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2); | |
146 | ||
147 | #define REF_CLK_FULL(_name) \ | |
148 | { .name = #_name, \ | |
149 | .parent_names = (const char *[]){ "TBG-A-P", \ | |
150 | "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \ | |
151 | .num_parents = 4, \ | |
152 | .mux_hw = &mux_##_name.hw, \ | |
153 | .gate_hw = &gate_##_name.hw, \ | |
154 | .rate_hw = &rate_##_name.hw, \ | |
155 | } | |
156 | ||
157 | #define REF_CLK_FULL_DD(_name) \ | |
158 | { .name = #_name, \ | |
159 | .parent_names = (const char *[]){ "TBG-A-P", \ | |
160 | "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \ | |
161 | .num_parents = 4, \ | |
162 | .mux_hw = &mux_##_name.hw, \ | |
163 | .gate_hw = &gate_##_name.hw, \ | |
164 | .rate_hw = &rate_##_name.hw, \ | |
165 | .is_double_div = true, \ | |
166 | } | |
167 | ||
168 | #define REF_CLK_GATE(_name, _parent_name) \ | |
169 | { .name = #_name, \ | |
170 | .parent_names = (const char *[]){ _parent_name}, \ | |
171 | .num_parents = 1, \ | |
172 | .gate_hw = &gate_##_name.hw, \ | |
173 | } | |
174 | ||
175 | #define REF_CLK_GATE_DIV(_name, _parent_name) \ | |
176 | { .name = #_name, \ | |
177 | .parent_names = (const char *[]){ _parent_name}, \ | |
178 | .num_parents = 1, \ | |
179 | .gate_hw = &gate_##_name.hw, \ | |
180 | .rate_hw = &rate_##_name.hw, \ | |
181 | } | |
182 | ||
183 | #define REF_CLK_MUX_DIV(_name) \ | |
184 | { .name = #_name, \ | |
185 | .parent_names = (const char *[]){ "TBG-A-P", \ | |
186 | "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \ | |
187 | .num_parents = 4, \ | |
188 | .mux_hw = &mux_##_name.hw, \ | |
189 | .rate_hw = &rate_##_name.hw, \ | |
190 | } | |
191 | ||
192 | #define REF_CLK_MUX_DD(_name) \ | |
193 | { .name = #_name, \ | |
194 | .parent_names = (const char *[]){ "TBG-A-P", \ | |
195 | "TBG-B-P", "TBG-A-S", "TBG-B-S"}, \ | |
196 | .num_parents = 4, \ | |
197 | .mux_hw = &mux_##_name.hw, \ | |
198 | .rate_hw = &rate_##_name.hw, \ | |
199 | .is_double_div = true, \ | |
200 | } | |
201 | ||
202 | /* NB periph clocks */ | |
203 | PERIPH_CLK_FULL_DD(mmc, 2, 0, DIV_SEL2, DIV_SEL2, 16, 13); | |
204 | PERIPH_CLK_FULL_DD(sata_host, 3, 2, DIV_SEL2, DIV_SEL2, 10, 7); | |
205 | PERIPH_CLK_FULL_DD(sec_at, 6, 4, DIV_SEL1, DIV_SEL1, 3, 0); | |
206 | PERIPH_CLK_FULL_DD(sec_dap, 7, 6, DIV_SEL1, DIV_SEL1, 9, 6); | |
207 | PERIPH_CLK_FULL_DD(tscem, 8, 8, DIV_SEL1, DIV_SEL1, 15, 12); | |
208 | PERIPH_CLK_FULL(tscem_tmx, 10, 10, DIV_SEL1, 18, clk_table6); | |
209 | static PERIPH_GATE(avs, 11); | |
210 | PERIPH_CLK_FULL_DD(pwm, 13, 14, DIV_SEL0, DIV_SEL0, 3, 0); | |
211 | PERIPH_CLK_FULL_DD(sqf, 12, 12, DIV_SEL1, DIV_SEL1, 27, 24); | |
212 | static PERIPH_GATE(i2c_2, 16); | |
213 | static PERIPH_GATE(i2c_1, 17); | |
214 | PERIPH_CLK_GATE_DIV(ddr_phy, 19, DIV_SEL0, 18, clk_table2); | |
215 | PERIPH_CLK_FULL_DD(ddr_fclk, 21, 16, DIV_SEL0, DIV_SEL0, 15, 12); | |
216 | PERIPH_CLK_FULL(trace, 22, 18, DIV_SEL0, 20, clk_table6); | |
217 | PERIPH_CLK_FULL(counter, 23, 20, DIV_SEL0, 23, clk_table6); | |
218 | PERIPH_CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19); | |
219 | PERIPH_CLK_MUX_DIV(cpu, 22, DIV_SEL0, 28, clk_table6); | |
220 | ||
adf4e289 | 221 | static struct clk_periph_data data_nb[] = { |
8ca4746a GC |
222 | REF_CLK_FULL_DD(mmc), |
223 | REF_CLK_FULL_DD(sata_host), | |
224 | REF_CLK_FULL_DD(sec_at), | |
225 | REF_CLK_FULL_DD(sec_dap), | |
226 | REF_CLK_FULL_DD(tscem), | |
227 | REF_CLK_FULL(tscem_tmx), | |
228 | REF_CLK_GATE(avs, "xtal"), | |
229 | REF_CLK_FULL_DD(sqf), | |
230 | REF_CLK_FULL_DD(pwm), | |
231 | REF_CLK_GATE(i2c_2, "xtal"), | |
232 | REF_CLK_GATE(i2c_1, "xtal"), | |
233 | REF_CLK_GATE_DIV(ddr_phy, "TBG-A-S"), | |
234 | REF_CLK_FULL_DD(ddr_fclk), | |
235 | REF_CLK_FULL(trace), | |
236 | REF_CLK_FULL(counter), | |
237 | REF_CLK_FULL_DD(eip97), | |
238 | REF_CLK_MUX_DIV(cpu), | |
239 | { }, | |
240 | }; | |
241 | ||
242 | /* SB periph clocks */ | |
243 | PERIPH_CLK_MUX_DD(gbe_50, 6, DIV_SEL2, DIV_SEL2, 6, 9); | |
244 | PERIPH_CLK_MUX_DD(gbe_core, 8, DIV_SEL1, DIV_SEL1, 18, 21); | |
245 | PERIPH_CLK_MUX_DD(gbe_125, 10, DIV_SEL1, DIV_SEL1, 6, 9); | |
246 | static PERIPH_GATE(gbe1_50, 0); | |
247 | static PERIPH_GATE(gbe0_50, 1); | |
248 | static PERIPH_GATE(gbe1_125, 2); | |
249 | static PERIPH_GATE(gbe0_125, 3); | |
250 | PERIPH_CLK_GATE_DIV(gbe1_core, 4, DIV_SEL1, 13, clk_table1); | |
251 | PERIPH_CLK_GATE_DIV(gbe0_core, 5, DIV_SEL1, 14, clk_table1); | |
252 | PERIPH_CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, clk_table1); | |
253 | PERIPH_CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6); | |
254 | PERIPH_CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12); | |
255 | PERIPH_CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18); | |
256 | ||
257 | static struct clk_periph_data data_sb[] = { | |
258 | REF_CLK_MUX_DD(gbe_50), | |
259 | REF_CLK_MUX_DD(gbe_core), | |
260 | REF_CLK_MUX_DD(gbe_125), | |
261 | REF_CLK_GATE(gbe1_50, "gbe_50"), | |
262 | REF_CLK_GATE(gbe0_50, "gbe_50"), | |
263 | REF_CLK_GATE(gbe1_125, "gbe_125"), | |
264 | REF_CLK_GATE(gbe0_125, "gbe_125"), | |
265 | REF_CLK_GATE_DIV(gbe1_core, "gbe_core"), | |
266 | REF_CLK_GATE_DIV(gbe0_core, "gbe_core"), | |
267 | REF_CLK_GATE_DIV(gbe_bm, "gbe_core"), | |
268 | REF_CLK_FULL_DD(sdio), | |
269 | REF_CLK_FULL_DD(usb32_usb2_sys), | |
270 | REF_CLK_FULL_DD(usb32_ss_sys), | |
271 | { }, | |
272 | }; | |
273 | ||
274 | static unsigned int get_div(void __iomem *reg, int shift) | |
275 | { | |
276 | u32 val; | |
277 | ||
278 | val = (readl(reg) >> shift) & 0x7; | |
279 | if (val > 6) | |
280 | return 0; | |
281 | return val; | |
282 | } | |
283 | ||
284 | static unsigned long clk_double_div_recalc_rate(struct clk_hw *hw, | |
adf4e289 | 285 | unsigned long parent_rate) |
8ca4746a GC |
286 | { |
287 | struct clk_double_div *double_div = to_clk_double_div(hw); | |
288 | unsigned int div; | |
289 | ||
290 | div = get_div(double_div->reg1, double_div->shift1); | |
291 | div *= get_div(double_div->reg2, double_div->shift2); | |
292 | ||
293 | return DIV_ROUND_UP_ULL((u64)parent_rate, div); | |
294 | } | |
295 | ||
296 | static const struct clk_ops clk_double_div_ops = { | |
297 | .recalc_rate = clk_double_div_recalc_rate, | |
298 | }; | |
299 | ||
300 | static const struct of_device_id armada_3700_periph_clock_of_match[] = { | |
301 | { .compatible = "marvell,armada-3700-periph-clock-nb", | |
302 | .data = data_nb, }, | |
303 | { .compatible = "marvell,armada-3700-periph-clock-sb", | |
304 | .data = data_sb, }, | |
305 | { } | |
306 | }; | |
adf4e289 | 307 | |
8ca4746a GC |
308 | static int armada_3700_add_composite_clk(const struct clk_periph_data *data, |
309 | void __iomem *reg, spinlock_t *lock, | |
981e1bea | 310 | struct device *dev, struct clk_hw **hw) |
8ca4746a GC |
311 | { |
312 | const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, | |
313 | *rate_ops = NULL; | |
314 | struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *rate_hw = NULL; | |
315 | ||
316 | if (data->mux_hw) { | |
317 | struct clk_mux *mux; | |
318 | ||
319 | mux_hw = data->mux_hw; | |
320 | mux = to_clk_mux(mux_hw); | |
321 | mux->lock = lock; | |
322 | mux_ops = mux_hw->init->ops; | |
323 | mux->reg = reg + (u64)mux->reg; | |
324 | } | |
325 | ||
326 | if (data->gate_hw) { | |
327 | struct clk_gate *gate; | |
328 | ||
329 | gate_hw = data->gate_hw; | |
330 | gate = to_clk_gate(gate_hw); | |
331 | gate->lock = lock; | |
332 | gate_ops = gate_hw->init->ops; | |
333 | gate->reg = reg + (u64)gate->reg; | |
4aa6c99d | 334 | gate->flags = CLK_GATE_SET_TO_DISABLE; |
8ca4746a GC |
335 | } |
336 | ||
337 | if (data->rate_hw) { | |
338 | rate_hw = data->rate_hw; | |
339 | rate_ops = rate_hw->init->ops; | |
340 | if (data->is_double_div) { | |
341 | struct clk_double_div *rate; | |
342 | ||
343 | rate = to_clk_double_div(rate_hw); | |
344 | rate->reg1 = reg + (u64)rate->reg1; | |
345 | rate->reg2 = reg + (u64)rate->reg2; | |
346 | } else { | |
347 | struct clk_divider *rate = to_clk_divider(rate_hw); | |
348 | const struct clk_div_table *clkt; | |
349 | int table_size = 0; | |
350 | ||
351 | rate->reg = reg + (u64)rate->reg; | |
352 | for (clkt = rate->table; clkt->div; clkt++) | |
353 | table_size++; | |
354 | rate->width = order_base_2(table_size); | |
355 | rate->lock = lock; | |
356 | } | |
357 | } | |
358 | ||
981e1bea | 359 | *hw = clk_hw_register_composite(dev, data->name, data->parent_names, |
adf4e289 GC |
360 | data->num_parents, mux_hw, |
361 | mux_ops, rate_hw, rate_ops, | |
362 | gate_hw, gate_ops, CLK_IGNORE_UNUSED); | |
8ca4746a | 363 | |
981e1bea GC |
364 | if (IS_ERR(*hw)) |
365 | return PTR_ERR(*hw); | |
8ca4746a GC |
366 | |
367 | return 0; | |
368 | } | |
369 | ||
370 | static int armada_3700_periph_clock_probe(struct platform_device *pdev) | |
371 | { | |
372 | struct clk_periph_driver_data *driver_data; | |
373 | struct device_node *np = pdev->dev.of_node; | |
374 | const struct clk_periph_data *data; | |
375 | struct device *dev = &pdev->dev; | |
376 | int num_periph = 0, i, ret; | |
377 | struct resource *res; | |
378 | void __iomem *reg; | |
379 | ||
380 | data = of_device_get_match_data(dev); | |
381 | if (!data) | |
382 | return -ENODEV; | |
383 | ||
384 | while (data[num_periph].name) | |
385 | num_periph++; | |
386 | ||
387 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
388 | reg = devm_ioremap_resource(dev, res); | |
0f7dd7ac | 389 | if (IS_ERR(reg)) |
8ca4746a | 390 | return PTR_ERR(reg); |
8ca4746a GC |
391 | |
392 | driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL); | |
393 | if (!driver_data) | |
394 | return -ENOMEM; | |
395 | ||
396 | driver_data->hw_data = devm_kzalloc(dev, sizeof(*driver_data->hw_data) + | |
397 | sizeof(*driver_data->hw_data->hws) * num_periph, | |
398 | GFP_KERNEL); | |
399 | if (!driver_data->hw_data) | |
400 | return -ENOMEM; | |
401 | driver_data->hw_data->num = num_periph; | |
402 | ||
403 | spin_lock_init(&driver_data->lock); | |
404 | ||
405 | for (i = 0; i < num_periph; i++) { | |
981e1bea | 406 | struct clk_hw **hw = &driver_data->hw_data->hws[i]; |
8ca4746a GC |
407 | |
408 | if (armada_3700_add_composite_clk(&data[i], reg, | |
409 | &driver_data->lock, dev, hw)) | |
410 | dev_err(dev, "Can't register periph clock %s\n", | |
adf4e289 | 411 | data[i].name); |
8ca4746a GC |
412 | } |
413 | ||
414 | ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, | |
adf4e289 | 415 | driver_data->hw_data); |
8ca4746a GC |
416 | if (ret) { |
417 | for (i = 0; i < num_periph; i++) | |
418 | clk_hw_unregister(driver_data->hw_data->hws[i]); | |
419 | return ret; | |
420 | } | |
421 | ||
422 | platform_set_drvdata(pdev, driver_data); | |
423 | return 0; | |
424 | } | |
425 | ||
426 | static int armada_3700_periph_clock_remove(struct platform_device *pdev) | |
427 | { | |
428 | struct clk_periph_driver_data *data = platform_get_drvdata(pdev); | |
429 | struct clk_hw_onecell_data *hw_data = data->hw_data; | |
430 | int i; | |
431 | ||
432 | of_clk_del_provider(pdev->dev.of_node); | |
433 | ||
434 | for (i = 0; i < hw_data->num; i++) | |
435 | clk_hw_unregister(hw_data->hws[i]); | |
436 | ||
437 | return 0; | |
438 | } | |
439 | ||
440 | static struct platform_driver armada_3700_periph_clock_driver = { | |
441 | .probe = armada_3700_periph_clock_probe, | |
442 | .remove = armada_3700_periph_clock_remove, | |
443 | .driver = { | |
444 | .name = "marvell-armada-3700-periph-clock", | |
445 | .of_match_table = armada_3700_periph_clock_of_match, | |
446 | }, | |
447 | }; | |
448 | ||
449 | builtin_platform_driver(armada_3700_periph_clock_driver); |