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ff261b7f SG |
1 | /* |
2 | * Copyright 2012 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
7274e23e | 12 | #include <linux/clk/mxs.h> |
bb0bf354 | 13 | #include <linux/clk.h> |
dd03ee9a | 14 | #include <linux/clk-provider.h> |
ff261b7f SG |
15 | #include <linux/err.h> |
16 | #include <linux/init.h> | |
17 | #include <linux/io.h> | |
53f9443d | 18 | #include <linux/of.h> |
38d6590f | 19 | #include <linux/of_address.h> |
ff261b7f SG |
20 | #include "clk.h" |
21 | ||
38d6590f SG |
22 | static void __iomem *clkctrl; |
23 | static void __iomem *digctrl; | |
24 | ||
25 | #define CLKCTRL clkctrl | |
26 | #define DIGCTRL digctrl | |
27 | ||
ff261b7f SG |
28 | #define PLLCTRL0 (CLKCTRL + 0x0000) |
29 | #define CPU (CLKCTRL + 0x0020) | |
30 | #define HBUS (CLKCTRL + 0x0030) | |
31 | #define XBUS (CLKCTRL + 0x0040) | |
32 | #define XTAL (CLKCTRL + 0x0050) | |
33 | #define PIX (CLKCTRL + 0x0060) | |
34 | #define SSP (CLKCTRL + 0x0070) | |
35 | #define GPMI (CLKCTRL + 0x0080) | |
36 | #define SPDIF (CLKCTRL + 0x0090) | |
37 | #define EMI (CLKCTRL + 0x00a0) | |
38 | #define SAIF (CLKCTRL + 0x00c0) | |
39 | #define TV (CLKCTRL + 0x00d0) | |
40 | #define ETM (CLKCTRL + 0x00e0) | |
41 | #define FRAC (CLKCTRL + 0x00f0) | |
42 | #define CLKSEQ (CLKCTRL + 0x0110) | |
43 | ||
44 | #define BP_CPU_INTERRUPT_WAIT 12 | |
45 | #define BP_CLKSEQ_BYPASS_SAIF 0 | |
46 | #define BP_CLKSEQ_BYPASS_SSP 5 | |
47 | #define BP_SAIF_DIV_FRAC_EN 16 | |
48 | #define BP_FRAC_IOFRAC 24 | |
49 | ||
50 | static void __init clk_misc_init(void) | |
51 | { | |
52 | u32 val; | |
53 | ||
54 | /* Gate off cpu clock in WFI for power saving */ | |
0c672aae | 55 | writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); |
ff261b7f SG |
56 | |
57 | /* Clear BYPASS for SAIF */ | |
0c672aae | 58 | writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR); |
ff261b7f SG |
59 | |
60 | /* SAIF has to use frac div for functional operation */ | |
61 | val = readl_relaxed(SAIF); | |
62 | val |= 1 << BP_SAIF_DIV_FRAC_EN; | |
63 | writel_relaxed(val, SAIF); | |
64 | ||
65 | /* | |
66 | * Source ssp clock from ref_io than ref_xtal, | |
67 | * as ref_xtal only provides 24 MHz as maximum. | |
68 | */ | |
0c672aae | 69 | writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR); |
ff261b7f SG |
70 | |
71 | /* | |
72 | * 480 MHz seems too high to be ssp clock source directly, | |
73 | * so set frac to get a 288 MHz ref_io. | |
74 | */ | |
0c672aae SG |
75 | writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR); |
76 | writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET); | |
ff261b7f SG |
77 | } |
78 | ||
4a1caed3 UKK |
79 | static const char *const sel_pll[] __initconst = { "pll", "ref_xtal", }; |
80 | static const char *const sel_cpu[] __initconst = { "ref_cpu", "ref_xtal", }; | |
81 | static const char *const sel_pix[] __initconst = { "ref_pix", "ref_xtal", }; | |
82 | static const char *const sel_io[] __initconst = { "ref_io", "ref_xtal", }; | |
83 | static const char *const cpu_sels[] __initconst = { "cpu_pll", "cpu_xtal", }; | |
84 | static const char *const emi_sels[] __initconst = { "emi_pll", "emi_xtal", }; | |
ff261b7f SG |
85 | |
86 | enum imx23_clk { | |
87 | ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel, | |
88 | lcdif_sel, gpmi_sel, ssp_sel, emi_sel, cpu, etm_sel, cpu_pll, | |
89 | cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll, | |
90 | emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div, | |
91 | clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif, | |
f5894539 | 92 | lcdif, etm, usb, usb_phy, |
ff261b7f SG |
93 | clk_max |
94 | }; | |
95 | ||
96 | static struct clk *clks[clk_max]; | |
53f9443d | 97 | static struct clk_onecell_data clk_data; |
ff261b7f SG |
98 | |
99 | static enum imx23_clk clks_init_on[] __initdata = { | |
100 | cpu, hbus, xbus, emi, uart, | |
101 | }; | |
102 | ||
dd03ee9a | 103 | static void __init mx23_clocks_init(struct device_node *np) |
ff261b7f | 104 | { |
dd03ee9a | 105 | struct device_node *dcnp; |
38a8b096 | 106 | u32 i; |
ff261b7f | 107 | |
dd03ee9a SH |
108 | dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl"); |
109 | digctrl = of_iomap(dcnp, 0); | |
38d6590f | 110 | WARN_ON(!digctrl); |
dd03ee9a | 111 | of_node_put(dcnp); |
38d6590f | 112 | |
38d6590f SG |
113 | clkctrl = of_iomap(np, 0); |
114 | WARN_ON(!clkctrl); | |
115 | ||
ff261b7f SG |
116 | clk_misc_init(); |
117 | ||
118 | clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); | |
119 | clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); | |
120 | clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); | |
121 | clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); | |
122 | clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); | |
123 | clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); | |
124 | clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll)); | |
125 | clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix)); | |
126 | clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io)); | |
127 | clks[ssp_sel] = mxs_clk_mux("ssp_sel", CLKSEQ, 5, 1, sel_io, ARRAY_SIZE(sel_io)); | |
128 | clks[emi_sel] = mxs_clk_mux("emi_sel", CLKSEQ, 6, 1, emi_sels, ARRAY_SIZE(emi_sels)); | |
129 | clks[cpu] = mxs_clk_mux("cpu", CLKSEQ, 7, 1, cpu_sels, ARRAY_SIZE(cpu_sels)); | |
130 | clks[etm_sel] = mxs_clk_mux("etm_sel", CLKSEQ, 8, 1, sel_cpu, ARRAY_SIZE(sel_cpu)); | |
131 | clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28); | |
132 | clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29); | |
133 | clks[hbus] = mxs_clk_div("hbus", "cpu", HBUS, 0, 5, 29); | |
134 | clks[xbus] = mxs_clk_div("xbus", "ref_xtal", XBUS, 0, 10, 31); | |
135 | clks[lcdif_div] = mxs_clk_div("lcdif_div", "lcdif_sel", PIX, 0, 12, 29); | |
136 | clks[ssp_div] = mxs_clk_div("ssp_div", "ssp_sel", SSP, 0, 9, 29); | |
137 | clks[gpmi_div] = mxs_clk_div("gpmi_div", "gpmi_sel", GPMI, 0, 10, 29); | |
138 | clks[emi_pll] = mxs_clk_div("emi_pll", "ref_emi", EMI, 0, 6, 28); | |
139 | clks[emi_xtal] = mxs_clk_div("emi_xtal", "ref_xtal", EMI, 8, 4, 29); | |
140 | clks[etm_div] = mxs_clk_div("etm_div", "etm_sel", ETM, 0, 6, 29); | |
141 | clks[saif_div] = mxs_clk_frac("saif_div", "saif_sel", SAIF, 0, 16, 29); | |
142 | clks[clk32k_div] = mxs_clk_fixed_factor("clk32k_div", "ref_xtal", 1, 750); | |
143 | clks[rtc] = mxs_clk_fixed_factor("rtc", "ref_xtal", 1, 768); | |
144 | clks[adc] = mxs_clk_fixed_factor("adc", "clk32k", 1, 16); | |
145 | clks[spdif_div] = mxs_clk_fixed_factor("spdif_div", "pll", 1, 4); | |
146 | clks[clk32k] = mxs_clk_gate("clk32k", "clk32k_div", XTAL, 26); | |
147 | clks[dri] = mxs_clk_gate("dri", "ref_xtal", XTAL, 28); | |
148 | clks[pwm] = mxs_clk_gate("pwm", "ref_xtal", XTAL, 29); | |
149 | clks[filt] = mxs_clk_gate("filt", "ref_xtal", XTAL, 30); | |
150 | clks[uart] = mxs_clk_gate("uart", "ref_xtal", XTAL, 31); | |
151 | clks[ssp] = mxs_clk_gate("ssp", "ssp_div", SSP, 31); | |
152 | clks[gpmi] = mxs_clk_gate("gpmi", "gpmi_div", GPMI, 31); | |
153 | clks[spdif] = mxs_clk_gate("spdif", "spdif_div", SPDIF, 31); | |
154 | clks[emi] = mxs_clk_gate("emi", "emi_sel", EMI, 31); | |
155 | clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31); | |
156 | clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31); | |
157 | clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); | |
f5894539 FE |
158 | clks[usb] = mxs_clk_gate("usb", "usb_phy", DIGCTRL, 2); |
159 | clks[usb_phy] = clk_register_gate(NULL, "usb_phy", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock); | |
ff261b7f SG |
160 | |
161 | for (i = 0; i < ARRAY_SIZE(clks); i++) | |
162 | if (IS_ERR(clks[i])) { | |
163 | pr_err("i.MX23 clk %d: register failed with %ld\n", | |
164 | i, PTR_ERR(clks[i])); | |
dd03ee9a | 165 | return; |
ff261b7f SG |
166 | } |
167 | ||
38d6590f SG |
168 | clk_data.clks = clks; |
169 | clk_data.clk_num = ARRAY_SIZE(clks); | |
170 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | |
53f9443d | 171 | |
ff261b7f SG |
172 | for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) |
173 | clk_prepare_enable(clks[clks_init_on[i]]); | |
174 | ||
ff261b7f | 175 | } |
dd03ee9a | 176 | CLK_OF_DECLARE(imx23_clkctrl, "fsl,imx23-clkctrl", mx23_clocks_init); |