[mirror_ubuntu-jammy-kernel.git] / drivers / clk / qcom / clk-alpha-pll.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */

#ifndef __QCOM_CLK_ALPHA_PLL_H__
#define __QCOM_CLK_ALPHA_PLL_H__

#include <linux/clk-provider.h>
#include "clk-regmap.h"

/* Alpha PLL types */
enum {
	CLK_ALPHA_PLL_TYPE_DEFAULT,
	CLK_ALPHA_PLL_TYPE_HUAYRA,
	CLK_ALPHA_PLL_TYPE_BRAMMO,
	CLK_ALPHA_PLL_TYPE_FABIA,
	CLK_ALPHA_PLL_TYPE_TRION,
	CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
	CLK_ALPHA_PLL_TYPE_MAX,
};

enum {
	PLL_OFF_L_VAL,
	PLL_OFF_CAL_L_VAL,
	PLL_OFF_ALPHA_VAL,
	PLL_OFF_ALPHA_VAL_U,
	PLL_OFF_USER_CTL,
	PLL_OFF_USER_CTL_U,
	PLL_OFF_USER_CTL_U1,
	PLL_OFF_CONFIG_CTL,
	PLL_OFF_CONFIG_CTL_U,
	PLL_OFF_CONFIG_CTL_U1,
	PLL_OFF_TEST_CTL,
	PLL_OFF_TEST_CTL_U,
	PLL_OFF_TEST_CTL_U1,
	PLL_OFF_STATUS,
	PLL_OFF_OPMODE,
	PLL_OFF_FRAC,
	PLL_OFF_CAL_VAL,
	PLL_OFF_MAX_REGS
};

extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];

struct pll_vco {
	unsigned long min_freq;
	unsigned long max_freq;
	u32 val;
};

#define VCO(a, b, c) { \
	.val = a,\
	.min_freq = b,\
	.max_freq = c,\
}

/**
 * struct clk_alpha_pll - phase locked loop (PLL)
 * @offset: base address of registers
 * @vco_table: array of VCO settings
 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
 * @clkr: regmap clock handle
 */
struct clk_alpha_pll {
	u32 offset;
	const u8 *regs;

	const struct pll_vco *vco_table;
	size_t num_vco;
#define SUPPORTS_OFFLINE_REQ	BIT(0)
#define SUPPORTS_FSM_MODE	BIT(2)
#define SUPPORTS_DYNAMIC_UPDATE	BIT(3)
	u8 flags;

	struct clk_regmap clkr;
};

/**
 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
 * @offset: base address of registers
 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
 * @width: width of post-divider
 * @post_div_shift: shift to differentiate between odd & even post-divider
 * @post_div_table: table with PLL odd and even post-divider settings
 * @num_post_div: Number of PLL post-divider settings
 *
 * @clkr: regmap clock handle
 */
struct clk_alpha_pll_postdiv {
	u32 offset;
	u8 width;
	const u8 *regs;

	struct clk_regmap clkr;
	int post_div_shift;
	const struct clk_div_table *post_div_table;
	size_t num_post_div;
};

struct alpha_pll_config {
	u32 l;
	u32 alpha;
	u32 alpha_hi;
	u32 config_ctl_val;
	u32 config_ctl_hi_val;
	u32 config_ctl_hi1_val;
	u32 user_ctl_val;
	u32 user_ctl_hi_val;
	u32 user_ctl_hi1_val;
	u32 test_ctl_val;
	u32 test_ctl_hi_val;
	u32 test_ctl_hi1_val;
	u32 main_output_mask;
	u32 aux_output_mask;
	u32 aux2_output_mask;
	u32 early_output_mask;
	u32 alpha_en_mask;
	u32 alpha_mode_mask;
	u32 pre_div_val;
	u32 pre_div_mask;
	u32 post_div_val;
	u32 post_div_mask;
	u32 vco_val;
	u32 vco_mask;
};

extern const struct clk_ops clk_alpha_pll_ops;
extern const struct clk_ops clk_alpha_pll_fixed_ops;
extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_ops;
extern const struct clk_ops clk_alpha_pll_huayra_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;

extern const struct clk_ops clk_alpha_pll_fabia_ops;
extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;

extern const struct clk_ops clk_alpha_pll_trion_ops;
extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;

extern const struct clk_ops clk_alpha_pll_lucid_ops;
#define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;

void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
			     const struct alpha_pll_config *config);
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
				const struct alpha_pll_config *config);
void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
			     const struct alpha_pll_config *config);
#define clk_lucid_pll_configure(pll, regmap, config) \
	clk_trion_pll_configure(pll, regmap, config)


#endif
Commit	Line	Data
f9419783 TD	1	/* SPDX-License-Identifier: GPL-2.0 */
f9419783 TD	2	/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */
8ff1f4c4 SB	3
	4	#ifndef __QCOM_CLK_ALPHA_PLL_H__
	5	#define __QCOM_CLK_ALPHA_PLL_H__
	6
	7	#include <linux/clk-provider.h>
	8	#include "clk-regmap.h"
	9
28d3f06e AS	10	/* Alpha PLL types */
	11	enum {
	12	CLK_ALPHA_PLL_TYPE_DEFAULT,
134b55b7	13	CLK_ALPHA_PLL_TYPE_HUAYRA,
c23e8a1f	14	CLK_ALPHA_PLL_TYPE_BRAMMO,
687d7a0c	15	CLK_ALPHA_PLL_TYPE_FABIA,
548a9095	16	CLK_ALPHA_PLL_TYPE_TRION,
0b014894	17	CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
28d3f06e AS	18	CLK_ALPHA_PLL_TYPE_MAX,
	19	};
	20
	21	enum {
	22	PLL_OFF_L_VAL,
548a9095	23	PLL_OFF_CAL_L_VAL,
28d3f06e AS	24	PLL_OFF_ALPHA_VAL,
	25	PLL_OFF_ALPHA_VAL_U,
	26	PLL_OFF_USER_CTL,
	27	PLL_OFF_USER_CTL_U,
548a9095	28	PLL_OFF_USER_CTL_U1,
28d3f06e AS	29	PLL_OFF_CONFIG_CTL,
28d3f06e AS	30	PLL_OFF_CONFIG_CTL_U,
548a9095	31	PLL_OFF_CONFIG_CTL_U1,
28d3f06e AS	32	PLL_OFF_TEST_CTL,
28d3f06e AS	33	PLL_OFF_TEST_CTL_U,
59128c20	34	PLL_OFF_TEST_CTL_U1,
28d3f06e	35	PLL_OFF_STATUS,
687d7a0c AN	36	PLL_OFF_OPMODE,
687d7a0c AN	37	PLL_OFF_FRAC,
548a9095	38	PLL_OFF_CAL_VAL,
28d3f06e AS	39	PLL_OFF_MAX_REGS
	40	};
	41
	42	extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
	43
8ff1f4c4 SB	44	struct pll_vco {
	45	unsigned long min_freq;
	46	unsigned long max_freq;
	47	u32 val;
	48	};
	49
03e342dc LP	50	#define VCO(a, b, c) { \
	51	.val = a,\
	52	.min_freq = b,\
	53	.max_freq = c,\
	54	}
	55
8ff1f4c4 SB	56	/**
	57	* struct clk_alpha_pll - phase locked loop (PLL)
	58	* @offset: base address of registers
	59	* @vco_table: array of VCO settings
28d3f06e	60	* @regs: alpha pll register map (see @clk_alpha_pll_regs)
8ff1f4c4 SB	61	* @clkr: regmap clock handle
	62	*/
	63	struct clk_alpha_pll {
	64	u32 offset;
28d3f06e	65	const u8 *regs;
8ff1f4c4 SB	66
	67	const struct pll_vco *vco_table;
	68	size_t num_vco;
feb65645	69	#define SUPPORTS_OFFLINE_REQ BIT(0)
400d9fda	70	#define SUPPORTS_FSM_MODE BIT(2)
472796de	71	#define SUPPORTS_DYNAMIC_UPDATE BIT(3)
feb65645	72	u8 flags;
8ff1f4c4 SB	73
	74	struct clk_regmap clkr;
	75	};
	76
	77	/**
	78	* struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
	79	* @offset: base address of registers
28d3f06e	80	* @regs: alpha pll register map (see @clk_alpha_pll_regs)
8ff1f4c4	81	* @width: width of post-divider
687d7a0c AN	82	* @post_div_shift: shift to differentiate between odd & even post-divider
	83	* @post_div_table: table with PLL odd and even post-divider settings
	84	* @num_post_div: Number of PLL post-divider settings
	85	*
8ff1f4c4 SB	86	* @clkr: regmap clock handle
	87	*/
	88	struct clk_alpha_pll_postdiv {
	89	u32 offset;
	90	u8 width;
28d3f06e	91	const u8 *regs;
8ff1f4c4 SB	92
8ff1f4c4 SB	93	struct clk_regmap clkr;
687d7a0c AN	94	int post_div_shift;
	95	const struct clk_div_table *post_div_table;
	96	size_t num_post_div;
8ff1f4c4 SB	97	};
8ff1f4c4 SB	98
9f4e6277 RN	99	struct alpha_pll_config {
	100	u32 l;
	101	u32 alpha;
c45ae598	102	u32 alpha_hi;
9f4e6277 RN	103	u32 config_ctl_val;
9f4e6277 RN	104	u32 config_ctl_hi_val;
59128c20	105	u32 config_ctl_hi1_val;
691865ba TD	106	u32 user_ctl_val;
691865ba TD	107	u32 user_ctl_hi_val;
59128c20	108	u32 user_ctl_hi1_val;
691865ba TD	109	u32 test_ctl_val;
691865ba TD	110	u32 test_ctl_hi_val;
59128c20	111	u32 test_ctl_hi1_val;
9f4e6277 RN	112	u32 main_output_mask;
	113	u32 aux_output_mask;
	114	u32 aux2_output_mask;
	115	u32 early_output_mask;
c45ae598 AS	116	u32 alpha_en_mask;
c45ae598 AS	117	u32 alpha_mode_mask;
9f4e6277 RN	118	u32 pre_div_val;
	119	u32 pre_div_mask;
	120	u32 post_div_val;
	121	u32 post_div_mask;
	122	u32 vco_val;
	123	u32 vco_mask;
	124	};
	125
8ff1f4c4	126	extern const struct clk_ops clk_alpha_pll_ops;
4168c1ca	127	extern const struct clk_ops clk_alpha_pll_fixed_ops;
feb65645	128	extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
8ff1f4c4	129	extern const struct clk_ops clk_alpha_pll_postdiv_ops;
134b55b7	130	extern const struct clk_ops clk_alpha_pll_huayra_ops;
23c68cc9	131	extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
8ff1f4c4	132
687d7a0c AN	133	extern const struct clk_ops clk_alpha_pll_fabia_ops;
	134	extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
	135	extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
	136
0b014894 JM	137	extern const struct clk_ops clk_alpha_pll_trion_ops;
	138	extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
	139	extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
	140
d28b503c	141	extern const struct clk_ops clk_alpha_pll_lucid_ops;
0b014894	142	#define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
59128c20 TD	143	extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
59128c20 TD	144
9f4e6277 RN	145	void clk_alpha_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
9f4e6277 RN	146	const struct alpha_pll_config *config);
687d7a0c AN	147	void clk_fabia_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
687d7a0c AN	148	const struct alpha_pll_config *config);
0b014894	149	void clk_trion_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
59128c20	150	const struct alpha_pll_config *config);
0b014894 JM	151	#define clk_lucid_pll_configure(pll, regmap, config) \
	152	clk_trion_pll_configure(pll, regmap, config)
	153
59128c20	154
9f4e6277	155
8ff1f4c4	156	#endif