]>
Commit | Line | Data |
---|---|---|
f9419783 TD |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */ | |
8ff1f4c4 SB |
3 | |
4 | #ifndef __QCOM_CLK_ALPHA_PLL_H__ | |
5 | #define __QCOM_CLK_ALPHA_PLL_H__ | |
6 | ||
7 | #include <linux/clk-provider.h> | |
8 | #include "clk-regmap.h" | |
9 | ||
28d3f06e AS |
10 | /* Alpha PLL types */ |
11 | enum { | |
12 | CLK_ALPHA_PLL_TYPE_DEFAULT, | |
134b55b7 | 13 | CLK_ALPHA_PLL_TYPE_HUAYRA, |
c23e8a1f | 14 | CLK_ALPHA_PLL_TYPE_BRAMMO, |
687d7a0c | 15 | CLK_ALPHA_PLL_TYPE_FABIA, |
548a9095 | 16 | CLK_ALPHA_PLL_TYPE_TRION, |
28d3f06e AS |
17 | CLK_ALPHA_PLL_TYPE_MAX, |
18 | }; | |
19 | ||
20 | enum { | |
21 | PLL_OFF_L_VAL, | |
548a9095 | 22 | PLL_OFF_CAL_L_VAL, |
28d3f06e AS |
23 | PLL_OFF_ALPHA_VAL, |
24 | PLL_OFF_ALPHA_VAL_U, | |
25 | PLL_OFF_USER_CTL, | |
26 | PLL_OFF_USER_CTL_U, | |
548a9095 | 27 | PLL_OFF_USER_CTL_U1, |
28d3f06e AS |
28 | PLL_OFF_CONFIG_CTL, |
29 | PLL_OFF_CONFIG_CTL_U, | |
548a9095 | 30 | PLL_OFF_CONFIG_CTL_U1, |
28d3f06e AS |
31 | PLL_OFF_TEST_CTL, |
32 | PLL_OFF_TEST_CTL_U, | |
33 | PLL_OFF_STATUS, | |
687d7a0c AN |
34 | PLL_OFF_OPMODE, |
35 | PLL_OFF_FRAC, | |
548a9095 | 36 | PLL_OFF_CAL_VAL, |
28d3f06e AS |
37 | PLL_OFF_MAX_REGS |
38 | }; | |
39 | ||
40 | extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; | |
41 | ||
8ff1f4c4 SB |
42 | struct pll_vco { |
43 | unsigned long min_freq; | |
44 | unsigned long max_freq; | |
45 | u32 val; | |
46 | }; | |
47 | ||
48 | /** | |
49 | * struct clk_alpha_pll - phase locked loop (PLL) | |
50 | * @offset: base address of registers | |
51 | * @vco_table: array of VCO settings | |
28d3f06e | 52 | * @regs: alpha pll register map (see @clk_alpha_pll_regs) |
8ff1f4c4 SB |
53 | * @clkr: regmap clock handle |
54 | */ | |
55 | struct clk_alpha_pll { | |
56 | u32 offset; | |
28d3f06e | 57 | const u8 *regs; |
8ff1f4c4 SB |
58 | |
59 | const struct pll_vco *vco_table; | |
60 | size_t num_vco; | |
feb65645 | 61 | #define SUPPORTS_OFFLINE_REQ BIT(0) |
400d9fda | 62 | #define SUPPORTS_FSM_MODE BIT(2) |
472796de | 63 | #define SUPPORTS_DYNAMIC_UPDATE BIT(3) |
feb65645 | 64 | u8 flags; |
8ff1f4c4 SB |
65 | |
66 | struct clk_regmap clkr; | |
67 | }; | |
68 | ||
69 | /** | |
70 | * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider | |
71 | * @offset: base address of registers | |
28d3f06e | 72 | * @regs: alpha pll register map (see @clk_alpha_pll_regs) |
8ff1f4c4 | 73 | * @width: width of post-divider |
687d7a0c AN |
74 | * @post_div_shift: shift to differentiate between odd & even post-divider |
75 | * @post_div_table: table with PLL odd and even post-divider settings | |
76 | * @num_post_div: Number of PLL post-divider settings | |
77 | * | |
8ff1f4c4 SB |
78 | * @clkr: regmap clock handle |
79 | */ | |
80 | struct clk_alpha_pll_postdiv { | |
81 | u32 offset; | |
82 | u8 width; | |
28d3f06e | 83 | const u8 *regs; |
8ff1f4c4 SB |
84 | |
85 | struct clk_regmap clkr; | |
687d7a0c AN |
86 | int post_div_shift; |
87 | const struct clk_div_table *post_div_table; | |
88 | size_t num_post_div; | |
8ff1f4c4 SB |
89 | }; |
90 | ||
9f4e6277 RN |
91 | struct alpha_pll_config { |
92 | u32 l; | |
93 | u32 alpha; | |
c45ae598 | 94 | u32 alpha_hi; |
9f4e6277 RN |
95 | u32 config_ctl_val; |
96 | u32 config_ctl_hi_val; | |
97 | u32 main_output_mask; | |
98 | u32 aux_output_mask; | |
99 | u32 aux2_output_mask; | |
100 | u32 early_output_mask; | |
c45ae598 AS |
101 | u32 alpha_en_mask; |
102 | u32 alpha_mode_mask; | |
9f4e6277 RN |
103 | u32 pre_div_val; |
104 | u32 pre_div_mask; | |
105 | u32 post_div_val; | |
106 | u32 post_div_mask; | |
107 | u32 vco_val; | |
108 | u32 vco_mask; | |
109 | }; | |
110 | ||
8ff1f4c4 | 111 | extern const struct clk_ops clk_alpha_pll_ops; |
feb65645 | 112 | extern const struct clk_ops clk_alpha_pll_hwfsm_ops; |
8ff1f4c4 | 113 | extern const struct clk_ops clk_alpha_pll_postdiv_ops; |
134b55b7 | 114 | extern const struct clk_ops clk_alpha_pll_huayra_ops; |
23c68cc9 | 115 | extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; |
8ff1f4c4 | 116 | |
687d7a0c AN |
117 | extern const struct clk_ops clk_alpha_pll_fabia_ops; |
118 | extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; | |
119 | extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops; | |
120 | ||
9f4e6277 RN |
121 | void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, |
122 | const struct alpha_pll_config *config); | |
687d7a0c AN |
123 | void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, |
124 | const struct alpha_pll_config *config); | |
548a9095 DK |
125 | extern const struct clk_ops clk_trion_fixed_pll_ops; |
126 | extern const struct clk_ops clk_trion_pll_postdiv_ops; | |
9f4e6277 | 127 | |
8ff1f4c4 | 128 | #endif |