[mirror_ubuntu-eoan-kernel.git] / drivers / clk / qcom / clk-rcg.c

/*
 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>

#include <asm/div64.h>

#include "clk-rcg.h"
#include "common.h"

static u32 ns_to_src(struct src_sel *s, u32 ns)
{
	ns >>= s->src_sel_shift;
	ns &= SRC_SEL_MASK;
	return ns;
}

static u32 src_to_ns(struct src_sel *s, u8 src, u32 ns)
{
	u32 mask;

	mask = SRC_SEL_MASK;
	mask <<= s->src_sel_shift;
	ns &= ~mask;

	ns |= src << s->src_sel_shift;
	return ns;
}

static u8 clk_rcg_get_parent(struct clk_hw *hw)
{
	struct clk_rcg *rcg = to_clk_rcg(hw);
	int num_parents = clk_hw_get_num_parents(hw);
	u32 ns;
	int i, ret;

	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
	if (ret)
		goto err;
	ns = ns_to_src(&rcg->s, ns);
	for (i = 0; i < num_parents; i++)
		if (ns == rcg->s.parent_map[i].cfg)
			return i;

err:
	pr_debug("%s: Clock %s has invalid parent, using default.\n",
		 __func__, clk_hw_get_name(hw));
	return 0;
}

static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
{
	bank &= BIT(rcg->mux_sel_bit);
	return !!bank;
}

static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
{
	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
	int num_parents = clk_hw_get_num_parents(hw);
	u32 ns, reg;
	int bank;
	int i, ret;
	struct src_sel *s;

	ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
	if (ret)
		goto err;
	bank = reg_to_bank(rcg, reg);
	s = &rcg->s[bank];

	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
	if (ret)
		goto err;
	ns = ns_to_src(s, ns);

	for (i = 0; i < num_parents; i++)
		if (ns == s->parent_map[i].cfg)
			return i;

err:
	pr_debug("%s: Clock %s has invalid parent, using default.\n",
		 __func__, clk_hw_get_name(hw));
	return 0;
}

static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
{
	struct clk_rcg *rcg = to_clk_rcg(hw);
	u32 ns;

	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
	ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);
	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);

	return 0;
}

static u32 md_to_m(struct mn *mn, u32 md)
{
	md >>= mn->m_val_shift;
	md &= BIT(mn->width) - 1;
	return md;
}

static u32 ns_to_pre_div(struct pre_div *p, u32 ns)
{
	ns >>= p->pre_div_shift;
	ns &= BIT(p->pre_div_width) - 1;
	return ns;
}

static u32 pre_div_to_ns(struct pre_div *p, u8 pre_div, u32 ns)
{
	u32 mask;

	mask = BIT(p->pre_div_width) - 1;
	mask <<= p->pre_div_shift;
	ns &= ~mask;

	ns |= pre_div << p->pre_div_shift;
	return ns;
}

static u32 mn_to_md(struct mn *mn, u32 m, u32 n, u32 md)
{
	u32 mask, mask_w;

	mask_w = BIT(mn->width) - 1;
	mask = (mask_w << mn->m_val_shift) | mask_w;
	md &= ~mask;

	if (n) {
		m <<= mn->m_val_shift;
		md |= m;
		md |= ~n & mask_w;
	}

	return md;
}

static u32 ns_m_to_n(struct mn *mn, u32 ns, u32 m)
{
	ns = ~ns >> mn->n_val_shift;
	ns &= BIT(mn->width) - 1;
	return ns + m;
}

static u32 reg_to_mnctr_mode(struct mn *mn, u32 val)
{
	val >>= mn->mnctr_mode_shift;
	val &= MNCTR_MODE_MASK;
	return val;
}

static u32 mn_to_ns(struct mn *mn, u32 m, u32 n, u32 ns)
{
	u32 mask;

	mask = BIT(mn->width) - 1;
	mask <<= mn->n_val_shift;
	ns &= ~mask;

	if (n) {
		n = n - m;
		n = ~n;
		n &= BIT(mn->width) - 1;
		n <<= mn->n_val_shift;
		ns |= n;
	}

	return ns;
}

static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
{
	u32 mask;

	mask = MNCTR_MODE_MASK << mn->mnctr_mode_shift;
	mask |= BIT(mn->mnctr_en_bit);
	val &= ~mask;

	if (n) {
		val |= BIT(mn->mnctr_en_bit);
		val |= MNCTR_MODE_DUAL << mn->mnctr_mode_shift;
	}

	return val;
}

static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
{
	u32 ns, md, reg;
	int bank, new_bank, ret, index;
	struct mn *mn;
	struct pre_div *p;
	struct src_sel *s;
	bool enabled;
	u32 md_reg, ns_reg;
	bool banked_mn = !!rcg->mn[1].width;
	bool banked_p = !!rcg->p[1].pre_div_width;
	struct clk_hw *hw = &rcg->clkr.hw;

	enabled = __clk_is_enabled(hw->clk);

	ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
	if (ret)
		return ret;
	bank = reg_to_bank(rcg, reg);
	new_bank = enabled ? !bank : bank;

	ns_reg = rcg->ns_reg[new_bank];
	ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns);
	if (ret)
		return ret;

	if (banked_mn) {
		mn = &rcg->mn[new_bank];
		md_reg = rcg->md_reg[new_bank];

		ns |= BIT(mn->mnctr_reset_bit);
		ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
		if (ret)
			return ret;

		ret = regmap_read(rcg->clkr.regmap, md_reg, &md);
		if (ret)
			return ret;
		md = mn_to_md(mn, f->m, f->n, md);
		ret = regmap_write(rcg->clkr.regmap, md_reg, md);
		if (ret)
			return ret;
		ns = mn_to_ns(mn, f->m, f->n, ns);
		ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
		if (ret)
			return ret;

		/* Two NS registers means mode control is in NS register */
		if (rcg->ns_reg[0] != rcg->ns_reg[1]) {
			ns = mn_to_reg(mn, f->m, f->n, ns);
			ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
			if (ret)
				return ret;
		} else {
			reg = mn_to_reg(mn, f->m, f->n, reg);
			ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg,
					   reg);
			if (ret)
				return ret;
		}

		ns &= ~BIT(mn->mnctr_reset_bit);
		ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
		if (ret)
			return ret;
	}

	if (banked_p) {
		p = &rcg->p[new_bank];
		ns = pre_div_to_ns(p, f->pre_div - 1, ns);
	}

	s = &rcg->s[new_bank];
	index = qcom_find_src_index(hw, s->parent_map, f->src);
	if (index < 0)
		return index;
	ns = src_to_ns(s, s->parent_map[index].cfg, ns);
	ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
	if (ret)
		return ret;

	if (enabled) {
		ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
		if (ret)
			return ret;
		reg ^= BIT(rcg->mux_sel_bit);
		ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
		if (ret)
			return ret;
	}
	return 0;
}

static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
{
	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
	u32 ns, md, reg;
	int bank;
	struct freq_tbl f = { 0 };
	bool banked_mn = !!rcg->mn[1].width;
	bool banked_p = !!rcg->p[1].pre_div_width;

	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
	bank = reg_to_bank(rcg, reg);

	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);

	if (banked_mn) {
		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
		f.m = md_to_m(&rcg->mn[bank], md);
		f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);
	}

	if (banked_p)
		f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;

	f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index);
	return configure_bank(rcg, &f);
}

/*
 * Calculate m/n:d rate
 *
 *          parent_rate     m
 *   rate = ----------- x  ---
 *            pre_div       n
 */
static unsigned long
calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div)
{
	if (pre_div)
		rate /= pre_div + 1;

	if (mode) {
		u64 tmp = rate;
		tmp *= m;
		do_div(tmp, n);
		rate = tmp;
	}

	return rate;
}

static unsigned long
clk_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
	struct clk_rcg *rcg = to_clk_rcg(hw);
	u32 pre_div, m = 0, n = 0, ns, md, mode = 0;
	struct mn *mn = &rcg->mn;

	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
	pre_div = ns_to_pre_div(&rcg->p, ns);

	if (rcg->mn.width) {
		regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
		m = md_to_m(mn, md);
		n = ns_m_to_n(mn, ns, m);
		/* MN counter mode is in hw.enable_reg sometimes */
		if (rcg->clkr.enable_reg != rcg->ns_reg)
			regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode);
		else
			mode = ns;
		mode = reg_to_mnctr_mode(mn, mode);
	}

	return calc_rate(parent_rate, m, n, mode, pre_div);
}

static unsigned long
clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
	u32 m, n, pre_div, ns, md, mode, reg;
	int bank;
	struct mn *mn;
	bool banked_p = !!rcg->p[1].pre_div_width;
	bool banked_mn = !!rcg->mn[1].width;

	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
	bank = reg_to_bank(rcg, reg);

	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
	m = n = pre_div = mode = 0;

	if (banked_mn) {
		mn = &rcg->mn[bank];
		regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
		m = md_to_m(mn, md);
		n = ns_m_to_n(mn, ns, m);
		/* Two NS registers means mode control is in NS register */
		if (rcg->ns_reg[0] != rcg->ns_reg[1])
			reg = ns;
		mode = reg_to_mnctr_mode(mn, reg);
	}

	if (banked_p)
		pre_div = ns_to_pre_div(&rcg->p[bank], ns);

	return calc_rate(parent_rate, m, n, mode, pre_div);
}

static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
		struct clk_rate_request *req,
		const struct parent_map *parent_map)
{
	unsigned long clk_flags, rate = req->rate;
	struct clk_hw *p;
	int index;

	f = qcom_find_freq(f, rate);
	if (!f)
		return -EINVAL;

	index = qcom_find_src_index(hw, parent_map, f->src);
	if (index < 0)
		return index;

	clk_flags = clk_hw_get_flags(hw);
	p = clk_hw_get_parent_by_index(hw, index);
	if (clk_flags & CLK_SET_RATE_PARENT) {
		rate = rate * f->pre_div;
		if (f->n) {
			u64 tmp = rate;
			tmp = tmp * f->n;
			do_div(tmp, f->m);
			rate = tmp;
		}
	} else {
		rate =  clk_hw_get_rate(p);
	}
	req->best_parent_hw = p;
	req->best_parent_rate = rate;
	req->rate = f->freq;

	return 0;
}

static int clk_rcg_determine_rate(struct clk_hw *hw,
				  struct clk_rate_request *req)
{
	struct clk_rcg *rcg = to_clk_rcg(hw);

	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req,
					rcg->s.parent_map);
}

static int clk_dyn_rcg_determine_rate(struct clk_hw *hw,
				      struct clk_rate_request *req)
{
	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
	u32 reg;
	int bank;
	struct src_sel *s;

	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
	bank = reg_to_bank(rcg, reg);
	s = &rcg->s[bank];

	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, s->parent_map);
}

static int clk_rcg_bypass_determine_rate(struct clk_hw *hw,
					 struct clk_rate_request *req)
{
	struct clk_rcg *rcg = to_clk_rcg(hw);
	const struct freq_tbl *f = rcg->freq_tbl;
	struct clk_hw *p;
	int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src);

	req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index);
	req->best_parent_rate = clk_hw_round_rate(p, req->rate);
	req->rate = req->best_parent_rate;

	return 0;
}

static int __clk_rcg_set_rate(struct clk_rcg *rcg, const struct freq_tbl *f)
{
	u32 ns, md, ctl;
	struct mn *mn = &rcg->mn;
	u32 mask = 0;
	unsigned int reset_reg;

	if (rcg->mn.reset_in_cc)
		reset_reg = rcg->clkr.enable_reg;
	else
		reset_reg = rcg->ns_reg;

	if (rcg->mn.width) {
		mask = BIT(mn->mnctr_reset_bit);
		regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask);

		regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
		md = mn_to_md(mn, f->m, f->n, md);
		regmap_write(rcg->clkr.regmap, rcg->md_reg, md);

		regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
		/* MN counter mode is in hw.enable_reg sometimes */
		if (rcg->clkr.enable_reg != rcg->ns_reg) {
			regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
			ctl = mn_to_reg(mn, f->m, f->n, ctl);
			regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);
		} else {
			ns = mn_to_reg(mn, f->m, f->n, ns);
		}
		ns = mn_to_ns(mn, f->m, f->n, ns);
	} else {
		regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
	}

	ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns);
	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);

	regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0);

	return 0;
}

static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
			    unsigned long parent_rate)
{
	struct clk_rcg *rcg = to_clk_rcg(hw);
	const struct freq_tbl *f;

	f = qcom_find_freq(rcg->freq_tbl, rate);
	if (!f)
		return -EINVAL;

	return __clk_rcg_set_rate(rcg, f);
}

static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{
	struct clk_rcg *rcg = to_clk_rcg(hw);

	return __clk_rcg_set_rate(rcg, rcg->freq_tbl);
}

/*
 * This type of clock has a glitch-free mux that switches between the output of
 * the M/N counter and an always on clock source (XO). When clk_set_rate() is
 * called we need to make sure that we don't switch to the M/N counter if it
 * isn't clocking because the mux will get stuck and the clock will stop
 * outputting a clock. This can happen if the framework isn't aware that this
 * clock is on and so clk_set_rate() doesn't turn on the new parent. To fix
 * this we switch the mux in the enable/disable ops and reprogram the M/N
 * counter in the set_rate op. We also make sure to switch away from the M/N
 * counter in set_rate if software thinks the clock is off.
 */
static int clk_rcg_lcc_set_rate(struct clk_hw *hw, unsigned long rate,
				unsigned long parent_rate)
{
	struct clk_rcg *rcg = to_clk_rcg(hw);
	const struct freq_tbl *f;
	int ret;
	u32 gfm = BIT(10);

	f = qcom_find_freq(rcg->freq_tbl, rate);
	if (!f)
		return -EINVAL;

	/* Switch to XO to avoid glitches */
	regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
	ret = __clk_rcg_set_rate(rcg, f);
	/* Switch back to M/N if it's clocking */
	if (__clk_is_enabled(hw->clk))
		regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);

	return ret;
}

static int clk_rcg_lcc_enable(struct clk_hw *hw)
{
	struct clk_rcg *rcg = to_clk_rcg(hw);
	u32 gfm = BIT(10);

	/* Use M/N */
	return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
}

static void clk_rcg_lcc_disable(struct clk_hw *hw)
{
	struct clk_rcg *rcg = to_clk_rcg(hw);
	u32 gfm = BIT(10);

	/* Use XO */
	regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
}

static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
{
	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
	const struct freq_tbl *f;

	f = qcom_find_freq(rcg->freq_tbl, rate);
	if (!f)
		return -EINVAL;

	return configure_bank(rcg, f);
}

static int clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
			    unsigned long parent_rate)
{
	return __clk_dyn_rcg_set_rate(hw, rate);
}

static int clk_dyn_rcg_set_rate_and_parent(struct clk_hw *hw,
		unsigned long rate, unsigned long parent_rate, u8 index)
{
	return __clk_dyn_rcg_set_rate(hw, rate);
}

const struct clk_ops clk_rcg_ops = {
	.enable = clk_enable_regmap,
	.disable = clk_disable_regmap,
	.get_parent = clk_rcg_get_parent,
	.set_parent = clk_rcg_set_parent,
	.recalc_rate = clk_rcg_recalc_rate,
	.determine_rate = clk_rcg_determine_rate,
	.set_rate = clk_rcg_set_rate,
};
EXPORT_SYMBOL_GPL(clk_rcg_ops);

const struct clk_ops clk_rcg_bypass_ops = {
	.enable = clk_enable_regmap,
	.disable = clk_disable_regmap,
	.get_parent = clk_rcg_get_parent,
	.set_parent = clk_rcg_set_parent,
	.recalc_rate = clk_rcg_recalc_rate,
	.determine_rate = clk_rcg_bypass_determine_rate,
	.set_rate = clk_rcg_bypass_set_rate,
};
EXPORT_SYMBOL_GPL(clk_rcg_bypass_ops);

const struct clk_ops clk_rcg_lcc_ops = {
	.enable = clk_rcg_lcc_enable,
	.disable = clk_rcg_lcc_disable,
	.get_parent = clk_rcg_get_parent,
	.set_parent = clk_rcg_set_parent,
	.recalc_rate = clk_rcg_recalc_rate,
	.determine_rate = clk_rcg_determine_rate,
	.set_rate = clk_rcg_lcc_set_rate,
};
EXPORT_SYMBOL_GPL(clk_rcg_lcc_ops);

const struct clk_ops clk_dyn_rcg_ops = {
	.enable = clk_enable_regmap,
	.is_enabled = clk_is_enabled_regmap,
	.disable = clk_disable_regmap,
	.get_parent = clk_dyn_rcg_get_parent,
	.set_parent = clk_dyn_rcg_set_parent,
	.recalc_rate = clk_dyn_rcg_recalc_rate,
	.determine_rate = clk_dyn_rcg_determine_rate,
	.set_rate = clk_dyn_rcg_set_rate,
	.set_rate_and_parent = clk_dyn_rcg_set_rate_and_parent,
};
EXPORT_SYMBOL_GPL(clk_dyn_rcg_ops);
Commit	Line	Data
bcd61c0f SB	1	/*
	2	* Copyright (c) 2013, The Linux Foundation. All rights reserved.
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/bitops.h>
	16	#include <linux/err.h>
	17	#include <linux/export.h>
	18	#include <linux/clk-provider.h>
	19	#include <linux/regmap.h>
	20
	21	#include <asm/div64.h>
	22
	23	#include "clk-rcg.h"
50c6a503	24	#include "common.h"
bcd61c0f SB	25
	26	static u32 ns_to_src(struct src_sel *s, u32 ns)
	27	{
	28	ns >>= s->src_sel_shift;
	29	ns &= SRC_SEL_MASK;
	30	return ns;
	31	}
	32
	33	static u32 src_to_ns(struct src_sel *s, u8 src, u32 ns)
	34	{
	35	u32 mask;
	36
	37	mask = SRC_SEL_MASK;
	38	mask <<= s->src_sel_shift;
	39	ns &= ~mask;
	40
	41	ns \|= src << s->src_sel_shift;
	42	return ns;
	43	}
	44
	45	static u8 clk_rcg_get_parent(struct clk_hw *hw)
	46	{
	47	struct clk_rcg *rcg = to_clk_rcg(hw);
497295af	48	int num_parents = clk_hw_get_num_parents(hw);
bcd61c0f	49	u32 ns;
7f218978	50	int i, ret;
bcd61c0f	51
7f218978 GD	52	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
	53	if (ret)
	54	goto err;
bcd61c0f SB	55	ns = ns_to_src(&rcg->s, ns);
bcd61c0f SB	56	for (i = 0; i < num_parents; i++)
293d2e97	57	if (ns == rcg->s.parent_map[i].cfg)
bcd61c0f SB	58	return i;
bcd61c0f SB	59
7f218978 GD	60	err:
7f218978 GD	61	pr_debug("%s: Clock %s has invalid parent, using default.\n",
ac269395	62	__func__, clk_hw_get_name(hw));
7f218978	63	return 0;
bcd61c0f SB	64	}
	65
	66	static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
	67	{
	68	bank &= BIT(rcg->mux_sel_bit);
	69	return !!bank;
	70	}
	71
	72	static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
	73	{
	74	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
497295af	75	int num_parents = clk_hw_get_num_parents(hw);
229fd4a5	76	u32 ns, reg;
bcd61c0f	77	int bank;
7f218978	78	int i, ret;
bcd61c0f SB	79	struct src_sel *s;
bcd61c0f SB	80
7f218978 GD	81	ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
	82	if (ret)
	83	goto err;
229fd4a5	84	bank = reg_to_bank(rcg, reg);
bcd61c0f SB	85	s = &rcg->s[bank];
bcd61c0f SB	86
7f218978 GD	87	ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
	88	if (ret)
	89	goto err;
bcd61c0f SB	90	ns = ns_to_src(s, ns);
	91
	92	for (i = 0; i < num_parents; i++)
293d2e97	93	if (ns == s->parent_map[i].cfg)
bcd61c0f SB	94	return i;
bcd61c0f SB	95
7f218978 GD	96	err:
7f218978 GD	97	pr_debug("%s: Clock %s has invalid parent, using default.\n",
ac269395	98	__func__, clk_hw_get_name(hw));
7f218978	99	return 0;
bcd61c0f SB	100	}
	101
	102	static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
	103	{
	104	struct clk_rcg *rcg = to_clk_rcg(hw);
	105	u32 ns;
	106
	107	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
293d2e97	108	ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);
bcd61c0f SB	109	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
	110
	111	return 0;
	112	}
	113
	114	static u32 md_to_m(struct mn *mn, u32 md)
	115	{
	116	md >>= mn->m_val_shift;
	117	md &= BIT(mn->width) - 1;
	118	return md;
	119	}
	120
	121	static u32 ns_to_pre_div(struct pre_div *p, u32 ns)
	122	{
	123	ns >>= p->pre_div_shift;
	124	ns &= BIT(p->pre_div_width) - 1;
	125	return ns;
	126	}
	127
	128	static u32 pre_div_to_ns(struct pre_div *p, u8 pre_div, u32 ns)
	129	{
	130	u32 mask;
	131
	132	mask = BIT(p->pre_div_width) - 1;
	133	mask <<= p->pre_div_shift;
	134	ns &= ~mask;
	135
	136	ns \|= pre_div << p->pre_div_shift;
	137	return ns;
	138	}
	139
	140	static u32 mn_to_md(struct mn *mn, u32 m, u32 n, u32 md)
	141	{
	142	u32 mask, mask_w;
	143
	144	mask_w = BIT(mn->width) - 1;
	145	mask = (mask_w << mn->m_val_shift) \| mask_w;
	146	md &= ~mask;
	147
	148	if (n) {
	149	m <<= mn->m_val_shift;
	150	md \|= m;
	151	md \|= ~n & mask_w;
	152	}
	153
	154	return md;
	155	}
	156
	157	static u32 ns_m_to_n(struct mn *mn, u32 ns, u32 m)
	158	{
	159	ns = ~ns >> mn->n_val_shift;
	160	ns &= BIT(mn->width) - 1;
	161	return ns + m;
	162	}
	163
	164	static u32 reg_to_mnctr_mode(struct mn *mn, u32 val)
	165	{
	166	val >>= mn->mnctr_mode_shift;
	167	val &= MNCTR_MODE_MASK;
	168	return val;
	169	}
	170
	171	static u32 mn_to_ns(struct mn *mn, u32 m, u32 n, u32 ns)
	172	{
173	u32 mask;
174
175	mask = BIT(mn->width) - 1;
176	mask <<= mn->n_val_shift;
177	ns &= ~mask;
178
179	if (n) {
180	n = n - m;
181	n = ~n;
182	n &= BIT(mn->width) - 1;
183	n <<= mn->n_val_shift;
184	ns \|= n;
185	}
186
187	return ns;
188	}
189
190	static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
191	{
192	u32 mask;
193
194	mask = MNCTR_MODE_MASK << mn->mnctr_mode_shift;
195	mask \|= BIT(mn->mnctr_en_bit);
196	val &= ~mask;
197
198	if (n) {
199	val \|= BIT(mn->mnctr_en_bit);
200	val \|= MNCTR_MODE_DUAL << mn->mnctr_mode_shift;
201	}
202
203	return val;
204	}
205
fae507af	206	static int configure_bank(struct clk_dyn_rcg rcg, const struct freq_tbl f)
bcd61c0f	207	{
229fd4a5	208	u32 ns, md, reg;
293d2e97	209	int bank, new_bank, ret, index;
bcd61c0f SB	210	struct mn *mn;
	211	struct pre_div *p;
	212	struct src_sel *s;
	213	bool enabled;
229fd4a5	214	u32 md_reg, ns_reg;
bcd61c0f	215	bool banked_mn = !!rcg->mn[1].width;
229fd4a5	216	bool banked_p = !!rcg->p[1].pre_div_width;
bcd61c0f SB	217	struct clk_hw *hw = &rcg->clkr.hw;
	218
	219	enabled = __clk_is_enabled(hw->clk);
	220
fae507af GD	221	ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
	222	if (ret)
	223	return ret;
229fd4a5	224	bank = reg_to_bank(rcg, reg);
bcd61c0f SB	225	new_bank = enabled ? !bank : bank;
bcd61c0f SB	226
229fd4a5	227	ns_reg = rcg->ns_reg[new_bank];
fae507af GD	228	ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns);
	229	if (ret)
	230	return ret;
229fd4a5	231
bcd61c0f SB	232	if (banked_mn) {
	233	mn = &rcg->mn[new_bank];
	234	md_reg = rcg->md_reg[new_bank];
	235
	236	ns \|= BIT(mn->mnctr_reset_bit);
fae507af GD	237	ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
	238	if (ret)
	239	return ret;
bcd61c0f	240
fae507af GD	241	ret = regmap_read(rcg->clkr.regmap, md_reg, &md);
	242	if (ret)
	243	return ret;
bcd61c0f	244	md = mn_to_md(mn, f->m, f->n, md);
fae507af GD	245	ret = regmap_write(rcg->clkr.regmap, md_reg, md);
	246	if (ret)
	247	return ret;
bcd61c0f	248	ns = mn_to_ns(mn, f->m, f->n, ns);
fae507af GD	249	ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
	250	if (ret)
	251	return ret;
229fd4a5 SB	252
	253	/* Two NS registers means mode control is in NS register */
	254	if (rcg->ns_reg[0] != rcg->ns_reg[1]) {
	255	ns = mn_to_reg(mn, f->m, f->n, ns);
fae507af GD	256	ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
	257	if (ret)
	258	return ret;
229fd4a5 SB	259	} else {
229fd4a5 SB	260	reg = mn_to_reg(mn, f->m, f->n, reg);
fae507af GD	261	ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg,
	262	reg);
	263	if (ret)
	264	return ret;
229fd4a5	265	}
bcd61c0f SB	266
bcd61c0f SB	267	ns &= ~BIT(mn->mnctr_reset_bit);
fae507af GD	268	ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
	269	if (ret)
	270	return ret;
229fd4a5 SB	271	}
	272
	273	if (banked_p) {
bcd61c0f SB	274	p = &rcg->p[new_bank];
	275	ns = pre_div_to_ns(p, f->pre_div - 1, ns);
	276	}
	277
	278	s = &rcg->s[new_bank];
293d2e97 GD	279	index = qcom_find_src_index(hw, s->parent_map, f->src);
	280	if (index < 0)
	281	return index;
	282	ns = src_to_ns(s, s->parent_map[index].cfg, ns);
fae507af GD	283	ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
	284	if (ret)
	285	return ret;
bcd61c0f SB	286
bcd61c0f SB	287	if (enabled) {
fae507af GD	288	ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
	289	if (ret)
	290	return ret;
229fd4a5	291	reg ^= BIT(rcg->mux_sel_bit);
fae507af GD	292	ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
	293	if (ret)
	294	return ret;
bcd61c0f	295	}
fae507af	296	return 0;
bcd61c0f SB	297	}
	298
	299	static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
	300	{
	301	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
229fd4a5	302	u32 ns, md, reg;
bcd61c0f SB	303	int bank;
	304	struct freq_tbl f = { 0 };
	305	bool banked_mn = !!rcg->mn[1].width;
229fd4a5	306	bool banked_p = !!rcg->p[1].pre_div_width;
bcd61c0f	307
229fd4a5	308	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
bcd61c0f SB	309	bank = reg_to_bank(rcg, reg);
bcd61c0f SB	310
229fd4a5 SB	311	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
229fd4a5 SB	312
bcd61c0f SB	313	if (banked_mn) {
	314	regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
	315	f.m = md_to_m(&rcg->mn[bank], md);
	316	f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);
bcd61c0f	317	}
bcd61c0f	318
229fd4a5 SB	319	if (banked_p)
	320	f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
	321
2f272e7b	322	f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index);
fae507af	323	return configure_bank(rcg, &f);
bcd61c0f SB	324	}
	325
	326	/*
	327	* Calculate m/n:d rate
	328	*
	329	* parent_rate m
	330	* rate = ----------- x ---
	331	* pre_div n
	332	*/
	333	static unsigned long
	334	calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div)
	335	{
	336	if (pre_div)
	337	rate /= pre_div + 1;
	338
	339	if (mode) {
	340	u64 tmp = rate;
	341	tmp *= m;
	342	do_div(tmp, n);
	343	rate = tmp;
	344	}
	345
	346	return rate;
	347	}
	348
	349	static unsigned long
	350	clk_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
	351	{
	352	struct clk_rcg *rcg = to_clk_rcg(hw);
	353	u32 pre_div, m = 0, n = 0, ns, md, mode = 0;
	354	struct mn *mn = &rcg->mn;
	355
	356	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
	357	pre_div = ns_to_pre_div(&rcg->p, ns);
	358
	359	if (rcg->mn.width) {
	360	regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
	361	m = md_to_m(mn, md);
	362	n = ns_m_to_n(mn, ns, m);
	363	/* MN counter mode is in hw.enable_reg sometimes */
	364	if (rcg->clkr.enable_reg != rcg->ns_reg)
	365	regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode);
	366	else
	367	mode = ns;
	368	mode = reg_to_mnctr_mode(mn, mode);
	369	}
	370
	371	return calc_rate(parent_rate, m, n, mode, pre_div);
	372	}
	373
	374	static unsigned long
	375	clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
	376	{
	377	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
	378	u32 m, n, pre_div, ns, md, mode, reg;
	379	int bank;
	380	struct mn *mn;
229fd4a5	381	bool banked_p = !!rcg->p[1].pre_div_width;
bcd61c0f SB	382	bool banked_mn = !!rcg->mn[1].width;
bcd61c0f SB	383
229fd4a5	384	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
bcd61c0f SB	385	bank = reg_to_bank(rcg, reg);
bcd61c0f SB	386
229fd4a5 SB	387	regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
	388	m = n = pre_div = mode = 0;
	389
bcd61c0f SB	390	if (banked_mn) {
	391	mn = &rcg->mn[bank];
	392	regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
	393	m = md_to_m(mn, md);
	394	n = ns_m_to_n(mn, ns, m);
229fd4a5 SB	395	/* Two NS registers means mode control is in NS register */
	396	if (rcg->ns_reg[0] != rcg->ns_reg[1])
	397	reg = ns;
bcd61c0f	398	mode = reg_to_mnctr_mode(mn, reg);
bcd61c0f	399	}
229fd4a5 SB	400
	401	if (banked_p)
	402	pre_div = ns_to_pre_div(&rcg->p[bank], ns);
	403
	404	return calc_rate(parent_rate, m, n, mode, pre_div);
bcd61c0f SB	405	}
bcd61c0f SB	406
0817b62c BB	407	static int _freq_tbl_determine_rate(struct clk_hw hw, const struct freq_tbl f,
0817b62c BB	408	struct clk_rate_request *req,
2f272e7b	409	const struct parent_map *parent_map)
bcd61c0f	410	{
0817b62c	411	unsigned long clk_flags, rate = req->rate;
ac269395	412	struct clk_hw *p;
2f272e7b	413	int index;
bcd61c0f	414
50c6a503	415	f = qcom_find_freq(f, rate);
bcd61c0f SB	416	if (!f)
	417	return -EINVAL;
	418
2f272e7b GD	419	index = qcom_find_src_index(hw, parent_map, f->src);
	420	if (index < 0)
	421	return index;
	422
98d8a60e	423	clk_flags = clk_hw_get_flags(hw);
ac269395	424	p = clk_hw_get_parent_by_index(hw, index);
bcd61c0f SB	425	if (clk_flags & CLK_SET_RATE_PARENT) {
	426	rate = rate * f->pre_div;
	427	if (f->n) {
	428	u64 tmp = rate;
	429	tmp = tmp * f->n;
	430	do_div(tmp, f->m);
	431	rate = tmp;
	432	}
	433	} else {
ac269395	434	rate = clk_hw_get_rate(p);
bcd61c0f	435	}
ac269395	436	req->best_parent_hw = p;
0817b62c BB	437	req->best_parent_rate = rate;
0817b62c BB	438	req->rate = f->freq;
bcd61c0f	439
0817b62c	440	return 0;
bcd61c0f SB	441	}
bcd61c0f SB	442
0817b62c BB	443	static int clk_rcg_determine_rate(struct clk_hw *hw,
0817b62c BB	444	struct clk_rate_request *req)
bcd61c0f SB	445	{
	446	struct clk_rcg *rcg = to_clk_rcg(hw);
	447
0817b62c BB	448	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req,
0817b62c BB	449	rcg->s.parent_map);
bcd61c0f SB	450	}
bcd61c0f SB	451
0817b62c BB	452	static int clk_dyn_rcg_determine_rate(struct clk_hw *hw,
0817b62c BB	453	struct clk_rate_request *req)
bcd61c0f SB	454	{
bcd61c0f SB	455	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
2f272e7b GD	456	u32 reg;
	457	int bank;
	458	struct src_sel *s;
	459
	460	regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
	461	bank = reg_to_bank(rcg, reg);
	462	s = &rcg->s[bank];
bcd61c0f	463
0817b62c	464	return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, s->parent_map);
bcd61c0f SB	465	}
bcd61c0f SB	466
0817b62c BB	467	static int clk_rcg_bypass_determine_rate(struct clk_hw *hw,
0817b62c BB	468	struct clk_rate_request *req)
bcd61c0f SB	469	{
bcd61c0f SB	470	struct clk_rcg *rcg = to_clk_rcg(hw);
404c1ff6	471	const struct freq_tbl *f = rcg->freq_tbl;
ac269395	472	struct clk_hw *p;
2f272e7b	473	int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src);
404c1ff6	474
ac269395 SB	475	req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index);
ac269395 SB	476	req->best_parent_rate = clk_hw_round_rate(p, req->rate);
0817b62c	477	req->rate = req->best_parent_rate;
404c1ff6	478
0817b62c	479	return 0;
404c1ff6 SB	480	}
	481
	482	static int __clk_rcg_set_rate(struct clk_rcg rcg, const struct freq_tbl f)
	483	{
bcd61c0f SB	484	u32 ns, md, ctl;
	485	struct mn *mn = &rcg->mn;
	486	u32 mask = 0;
	487	unsigned int reset_reg;
	488
bcd61c0f SB	489	if (rcg->mn.reset_in_cc)
	490	reset_reg = rcg->clkr.enable_reg;
	491	else
	492	reset_reg = rcg->ns_reg;
	493
	494	if (rcg->mn.width) {
	495	mask = BIT(mn->mnctr_reset_bit);
	496	regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask);
	497
	498	regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
	499	md = mn_to_md(mn, f->m, f->n, md);
	500	regmap_write(rcg->clkr.regmap, rcg->md_reg, md);
	501
	502	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
	503	/* MN counter mode is in hw.enable_reg sometimes */
	504	if (rcg->clkr.enable_reg != rcg->ns_reg) {
	505	regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
	506	ctl = mn_to_reg(mn, f->m, f->n, ctl);
	507	regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);
	508	} else {
	509	ns = mn_to_reg(mn, f->m, f->n, ns);
	510	}
	511	ns = mn_to_ns(mn, f->m, f->n, ns);
	512	} else {
	513	regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
	514	}
	515
	516	ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns);
	517	regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
	518
	519	regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0);
	520
	521	return 0;
	522	}
	523
404c1ff6 SB	524	static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
	525	unsigned long parent_rate)
	526	{
	527	struct clk_rcg *rcg = to_clk_rcg(hw);
	528	const struct freq_tbl *f;
	529
50c6a503	530	f = qcom_find_freq(rcg->freq_tbl, rate);
404c1ff6 SB	531	if (!f)
	532	return -EINVAL;
	533
	534	return __clk_rcg_set_rate(rcg, f);
	535	}
	536
	537	static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
	538	unsigned long parent_rate)
	539	{
	540	struct clk_rcg *rcg = to_clk_rcg(hw);
	541
	542	return __clk_rcg_set_rate(rcg, rcg->freq_tbl);
	543	}
	544
9d3745d4 SB	545	/*
	546	* This type of clock has a glitch-free mux that switches between the output of
	547	* the M/N counter and an always on clock source (XO). When clk_set_rate() is
	548	* called we need to make sure that we don't switch to the M/N counter if it
	549	* isn't clocking because the mux will get stuck and the clock will stop
	550	* outputting a clock. This can happen if the framework isn't aware that this
	551	* clock is on and so clk_set_rate() doesn't turn on the new parent. To fix
	552	* this we switch the mux in the enable/disable ops and reprogram the M/N
	553	* counter in the set_rate op. We also make sure to switch away from the M/N
	554	* counter in set_rate if software thinks the clock is off.
	555	*/
	556	static int clk_rcg_lcc_set_rate(struct clk_hw *hw, unsigned long rate,
	557	unsigned long parent_rate)
	558	{
	559	struct clk_rcg *rcg = to_clk_rcg(hw);
	560	const struct freq_tbl *f;
	561	int ret;
	562	u32 gfm = BIT(10);
	563
	564	f = qcom_find_freq(rcg->freq_tbl, rate);
	565	if (!f)
	566	return -EINVAL;
	567
	568	/* Switch to XO to avoid glitches */
	569	regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
	570	ret = __clk_rcg_set_rate(rcg, f);
	571	/* Switch back to M/N if it's clocking */
	572	if (__clk_is_enabled(hw->clk))
	573	regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
	574
	575	return ret;
	576	}
	577
	578	static int clk_rcg_lcc_enable(struct clk_hw *hw)
	579	{
	580	struct clk_rcg *rcg = to_clk_rcg(hw);
	581	u32 gfm = BIT(10);
	582
	583	/* Use M/N */
	584	return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
	585	}
	586
	587	static void clk_rcg_lcc_disable(struct clk_hw *hw)
	588	{
	589	struct clk_rcg *rcg = to_clk_rcg(hw);
	590	u32 gfm = BIT(10);
	591
	592	/* Use XO */
	593	regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
	594	}
	595
bcd61c0f SB	596	static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
	597	{
	598	struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
	599	const struct freq_tbl *f;
	600
50c6a503	601	f = qcom_find_freq(rcg->freq_tbl, rate);
bcd61c0f SB	602	if (!f)
	603	return -EINVAL;
	604
fae507af	605	return configure_bank(rcg, f);
bcd61c0f SB	606	}
	607
	608	static int clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
	609	unsigned long parent_rate)
	610	{
	611	return __clk_dyn_rcg_set_rate(hw, rate);
	612	}
	613
	614	static int clk_dyn_rcg_set_rate_and_parent(struct clk_hw *hw,
	615	unsigned long rate, unsigned long parent_rate, u8 index)
	616	{
	617	return __clk_dyn_rcg_set_rate(hw, rate);
	618	}
	619
	620	const struct clk_ops clk_rcg_ops = {
	621	.enable = clk_enable_regmap,
	622	.disable = clk_disable_regmap,
	623	.get_parent = clk_rcg_get_parent,
	624	.set_parent = clk_rcg_set_parent,
	625	.recalc_rate = clk_rcg_recalc_rate,
	626	.determine_rate = clk_rcg_determine_rate,
	627	.set_rate = clk_rcg_set_rate,
	628	};
	629	EXPORT_SYMBOL_GPL(clk_rcg_ops);
	630
404c1ff6 SB	631	const struct clk_ops clk_rcg_bypass_ops = {
	632	.enable = clk_enable_regmap,
	633	.disable = clk_disable_regmap,
	634	.get_parent = clk_rcg_get_parent,
	635	.set_parent = clk_rcg_set_parent,
	636	.recalc_rate = clk_rcg_recalc_rate,
	637	.determine_rate = clk_rcg_bypass_determine_rate,
	638	.set_rate = clk_rcg_bypass_set_rate,
	639	};
	640	EXPORT_SYMBOL_GPL(clk_rcg_bypass_ops);
	641
9d3745d4 SB	642	const struct clk_ops clk_rcg_lcc_ops = {
	643	.enable = clk_rcg_lcc_enable,
	644	.disable = clk_rcg_lcc_disable,
	645	.get_parent = clk_rcg_get_parent,
	646	.set_parent = clk_rcg_set_parent,
	647	.recalc_rate = clk_rcg_recalc_rate,
	648	.determine_rate = clk_rcg_determine_rate,
	649	.set_rate = clk_rcg_lcc_set_rate,
	650	};
	651	EXPORT_SYMBOL_GPL(clk_rcg_lcc_ops);
	652
bcd61c0f SB	653	const struct clk_ops clk_dyn_rcg_ops = {
	654	.enable = clk_enable_regmap,
	655	.is_enabled = clk_is_enabled_regmap,
	656	.disable = clk_disable_regmap,
	657	.get_parent = clk_dyn_rcg_get_parent,
	658	.set_parent = clk_dyn_rcg_set_parent,
	659	.recalc_rate = clk_dyn_rcg_recalc_rate,
	660	.determine_rate = clk_dyn_rcg_determine_rate,
	661	.set_rate = clk_dyn_rcg_set_rate,
	662	.set_rate_and_parent = clk_dyn_rcg_set_rate_and_parent,
	663	};
	664	EXPORT_SYMBOL_GPL(clk_dyn_rcg_ops);