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02824653 GD |
1 | /* |
2 | * Copyright (c) 2014, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/clk-provider.h> | |
22 | #include <linux/regmap.h> | |
23 | #include <linux/reset-controller.h> | |
24 | ||
25 | #include <dt-bindings/clock/qcom,gcc-apq8084.h> | |
26 | #include <dt-bindings/reset/qcom,gcc-apq8084.h> | |
27 | ||
28 | #include "common.h" | |
29 | #include "clk-regmap.h" | |
30 | #include "clk-pll.h" | |
31 | #include "clk-rcg.h" | |
32 | #include "clk-branch.h" | |
33 | #include "reset.h" | |
639af949 | 34 | #include "gdsc.h" |
02824653 | 35 | |
293d2e97 GD |
36 | enum { |
37 | P_XO, | |
38 | P_GPLL0, | |
39 | P_GPLL1, | |
40 | P_GPLL4, | |
41 | P_PCIE_0_1_PIPE_CLK, | |
42 | P_SATA_ASIC0_CLK, | |
43 | P_SATA_RX_CLK, | |
44 | P_SLEEP_CLK, | |
45 | }; | |
02824653 | 46 | |
293d2e97 GD |
47 | static const struct parent_map gcc_xo_gpll0_map[] = { |
48 | { P_XO, 0 }, | |
49 | { P_GPLL0, 1 } | |
02824653 GD |
50 | }; |
51 | ||
adb11a40 | 52 | static const char * const gcc_xo_gpll0[] = { |
02824653 GD |
53 | "xo", |
54 | "gpll0_vote", | |
55 | }; | |
56 | ||
293d2e97 GD |
57 | static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { |
58 | { P_XO, 0 }, | |
59 | { P_GPLL0, 1 }, | |
60 | { P_GPLL4, 5 } | |
02824653 GD |
61 | }; |
62 | ||
adb11a40 | 63 | static const char * const gcc_xo_gpll0_gpll4[] = { |
02824653 GD |
64 | "xo", |
65 | "gpll0_vote", | |
66 | "gpll4_vote", | |
67 | }; | |
68 | ||
293d2e97 GD |
69 | static const struct parent_map gcc_xo_sata_asic0_map[] = { |
70 | { P_XO, 0 }, | |
71 | { P_SATA_ASIC0_CLK, 2 } | |
5424e102 GD |
72 | }; |
73 | ||
adb11a40 | 74 | static const char * const gcc_xo_sata_asic0[] = { |
5424e102 GD |
75 | "xo", |
76 | "sata_asic0_clk", | |
77 | }; | |
78 | ||
293d2e97 GD |
79 | static const struct parent_map gcc_xo_sata_rx_map[] = { |
80 | { P_XO, 0 }, | |
81 | { P_SATA_RX_CLK, 2} | |
5424e102 GD |
82 | }; |
83 | ||
adb11a40 | 84 | static const char * const gcc_xo_sata_rx[] = { |
5424e102 GD |
85 | "xo", |
86 | "sata_rx_clk", | |
87 | }; | |
88 | ||
293d2e97 GD |
89 | static const struct parent_map gcc_xo_pcie_map[] = { |
90 | { P_XO, 0 }, | |
91 | { P_PCIE_0_1_PIPE_CLK, 2 } | |
5424e102 GD |
92 | }; |
93 | ||
adb11a40 | 94 | static const char * const gcc_xo_pcie[] = { |
5424e102 GD |
95 | "xo", |
96 | "pcie_pipe", | |
97 | }; | |
98 | ||
293d2e97 GD |
99 | static const struct parent_map gcc_xo_pcie_sleep_map[] = { |
100 | { P_XO, 0 }, | |
101 | { P_SLEEP_CLK, 6 } | |
5424e102 GD |
102 | }; |
103 | ||
adb11a40 | 104 | static const char * const gcc_xo_pcie_sleep[] = { |
5424e102 GD |
105 | "xo", |
106 | "sleep_clk_src", | |
107 | }; | |
108 | ||
02824653 GD |
109 | #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } |
110 | ||
111 | static struct clk_pll gpll0 = { | |
112 | .l_reg = 0x0004, | |
113 | .m_reg = 0x0008, | |
114 | .n_reg = 0x000c, | |
115 | .config_reg = 0x0014, | |
116 | .mode_reg = 0x0000, | |
117 | .status_reg = 0x001c, | |
118 | .status_bit = 17, | |
119 | .clkr.hw.init = &(struct clk_init_data){ | |
120 | .name = "gpll0", | |
121 | .parent_names = (const char *[]){ "xo" }, | |
122 | .num_parents = 1, | |
123 | .ops = &clk_pll_ops, | |
124 | }, | |
125 | }; | |
126 | ||
127 | static struct clk_regmap gpll0_vote = { | |
128 | .enable_reg = 0x1480, | |
129 | .enable_mask = BIT(0), | |
130 | .hw.init = &(struct clk_init_data){ | |
131 | .name = "gpll0_vote", | |
132 | .parent_names = (const char *[]){ "gpll0" }, | |
133 | .num_parents = 1, | |
134 | .ops = &clk_pll_vote_ops, | |
135 | }, | |
136 | }; | |
137 | ||
138 | static struct clk_rcg2 config_noc_clk_src = { | |
139 | .cmd_rcgr = 0x0150, | |
140 | .hid_width = 5, | |
141 | .parent_map = gcc_xo_gpll0_map, | |
142 | .clkr.hw.init = &(struct clk_init_data){ | |
143 | .name = "config_noc_clk_src", | |
144 | .parent_names = gcc_xo_gpll0, | |
145 | .num_parents = 2, | |
146 | .ops = &clk_rcg2_ops, | |
147 | }, | |
148 | }; | |
149 | ||
150 | static struct clk_rcg2 periph_noc_clk_src = { | |
151 | .cmd_rcgr = 0x0190, | |
152 | .hid_width = 5, | |
153 | .parent_map = gcc_xo_gpll0_map, | |
154 | .clkr.hw.init = &(struct clk_init_data){ | |
155 | .name = "periph_noc_clk_src", | |
156 | .parent_names = gcc_xo_gpll0, | |
157 | .num_parents = 2, | |
158 | .ops = &clk_rcg2_ops, | |
159 | }, | |
160 | }; | |
161 | ||
162 | static struct clk_rcg2 system_noc_clk_src = { | |
163 | .cmd_rcgr = 0x0120, | |
164 | .hid_width = 5, | |
165 | .parent_map = gcc_xo_gpll0_map, | |
166 | .clkr.hw.init = &(struct clk_init_data){ | |
167 | .name = "system_noc_clk_src", | |
168 | .parent_names = gcc_xo_gpll0, | |
169 | .num_parents = 2, | |
170 | .ops = &clk_rcg2_ops, | |
171 | }, | |
172 | }; | |
173 | ||
174 | static struct clk_pll gpll1 = { | |
175 | .l_reg = 0x0044, | |
176 | .m_reg = 0x0048, | |
177 | .n_reg = 0x004c, | |
178 | .config_reg = 0x0054, | |
179 | .mode_reg = 0x0040, | |
180 | .status_reg = 0x005c, | |
181 | .status_bit = 17, | |
182 | .clkr.hw.init = &(struct clk_init_data){ | |
183 | .name = "gpll1", | |
184 | .parent_names = (const char *[]){ "xo" }, | |
185 | .num_parents = 1, | |
186 | .ops = &clk_pll_ops, | |
187 | }, | |
188 | }; | |
189 | ||
190 | static struct clk_regmap gpll1_vote = { | |
191 | .enable_reg = 0x1480, | |
192 | .enable_mask = BIT(1), | |
193 | .hw.init = &(struct clk_init_data){ | |
194 | .name = "gpll1_vote", | |
195 | .parent_names = (const char *[]){ "gpll1" }, | |
196 | .num_parents = 1, | |
197 | .ops = &clk_pll_vote_ops, | |
198 | }, | |
199 | }; | |
200 | ||
201 | static struct clk_pll gpll4 = { | |
202 | .l_reg = 0x1dc4, | |
203 | .m_reg = 0x1dc8, | |
204 | .n_reg = 0x1dcc, | |
205 | .config_reg = 0x1dd4, | |
206 | .mode_reg = 0x1dc0, | |
207 | .status_reg = 0x1ddc, | |
208 | .status_bit = 17, | |
209 | .clkr.hw.init = &(struct clk_init_data){ | |
210 | .name = "gpll4", | |
211 | .parent_names = (const char *[]){ "xo" }, | |
212 | .num_parents = 1, | |
213 | .ops = &clk_pll_ops, | |
214 | }, | |
215 | }; | |
216 | ||
217 | static struct clk_regmap gpll4_vote = { | |
218 | .enable_reg = 0x1480, | |
219 | .enable_mask = BIT(4), | |
220 | .hw.init = &(struct clk_init_data){ | |
221 | .name = "gpll4_vote", | |
222 | .parent_names = (const char *[]){ "gpll4" }, | |
223 | .num_parents = 1, | |
224 | .ops = &clk_pll_vote_ops, | |
225 | }, | |
226 | }; | |
227 | ||
5424e102 GD |
228 | static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = { |
229 | F(100000000, P_GPLL0, 6, 0, 0), | |
230 | F(200000000, P_GPLL0, 3, 0, 0), | |
231 | F(240000000, P_GPLL0, 2.5, 0, 0), | |
232 | { } | |
233 | }; | |
234 | ||
235 | static struct clk_rcg2 ufs_axi_clk_src = { | |
236 | .cmd_rcgr = 0x1d64, | |
237 | .mnd_width = 8, | |
238 | .hid_width = 5, | |
239 | .parent_map = gcc_xo_gpll0_map, | |
240 | .freq_tbl = ftbl_gcc_ufs_axi_clk, | |
241 | .clkr.hw.init = &(struct clk_init_data){ | |
242 | .name = "ufs_axi_clk_src", | |
243 | .parent_names = gcc_xo_gpll0, | |
244 | .num_parents = 2, | |
245 | .ops = &clk_rcg2_ops, | |
246 | }, | |
247 | }; | |
248 | ||
02824653 GD |
249 | static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = { |
250 | F(125000000, P_GPLL0, 1, 5, 24), | |
251 | { } | |
252 | }; | |
253 | ||
254 | static struct clk_rcg2 usb30_master_clk_src = { | |
255 | .cmd_rcgr = 0x03d4, | |
256 | .mnd_width = 8, | |
257 | .hid_width = 5, | |
258 | .parent_map = gcc_xo_gpll0_map, | |
259 | .freq_tbl = ftbl_gcc_usb30_master_clk, | |
260 | .clkr.hw.init = &(struct clk_init_data){ | |
261 | .name = "usb30_master_clk_src", | |
262 | .parent_names = gcc_xo_gpll0, | |
263 | .num_parents = 2, | |
264 | .ops = &clk_rcg2_ops, | |
265 | }, | |
266 | }; | |
267 | ||
268 | static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk[] = { | |
269 | F(125000000, P_GPLL0, 1, 5, 24), | |
270 | { } | |
271 | }; | |
272 | ||
273 | static struct clk_rcg2 usb30_sec_master_clk_src = { | |
274 | .cmd_rcgr = 0x1bd4, | |
275 | .mnd_width = 8, | |
276 | .hid_width = 5, | |
277 | .parent_map = gcc_xo_gpll0_map, | |
278 | .freq_tbl = ftbl_gcc_usb30_sec_master_clk, | |
279 | .clkr.hw.init = &(struct clk_init_data){ | |
280 | .name = "usb30_sec_master_clk_src", | |
281 | .parent_names = gcc_xo_gpll0, | |
282 | .num_parents = 2, | |
283 | .ops = &clk_rcg2_ops, | |
284 | }, | |
285 | }; | |
286 | ||
287 | static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { | |
288 | .halt_reg = 0x1bd0, | |
289 | .clkr = { | |
290 | .enable_reg = 0x1bd0, | |
291 | .enable_mask = BIT(0), | |
292 | .hw.init = &(struct clk_init_data){ | |
293 | .name = "gcc_usb30_sec_mock_utmi_clk", | |
294 | .parent_names = (const char *[]){ | |
295 | "usb30_sec_mock_utmi_clk_src", | |
296 | }, | |
297 | .num_parents = 1, | |
298 | .flags = CLK_SET_RATE_PARENT, | |
299 | .ops = &clk_branch2_ops, | |
300 | }, | |
301 | }, | |
302 | }; | |
303 | ||
304 | static struct clk_branch gcc_usb30_sec_sleep_clk = { | |
305 | .halt_reg = 0x1bcc, | |
306 | .clkr = { | |
307 | .enable_reg = 0x1bcc, | |
308 | .enable_mask = BIT(0), | |
309 | .hw.init = &(struct clk_init_data){ | |
310 | .name = "gcc_usb30_sec_sleep_clk", | |
311 | .parent_names = (const char *[]){ | |
312 | "sleep_clk_src", | |
313 | }, | |
314 | .num_parents = 1, | |
315 | .flags = CLK_SET_RATE_PARENT, | |
316 | .ops = &clk_branch2_ops, | |
317 | }, | |
318 | }, | |
319 | }; | |
320 | ||
321 | static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = { | |
322 | F(19200000, P_XO, 1, 0, 0), | |
323 | F(50000000, P_GPLL0, 12, 0, 0), | |
324 | { } | |
325 | }; | |
326 | ||
327 | static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { | |
328 | .cmd_rcgr = 0x0660, | |
329 | .hid_width = 5, | |
330 | .parent_map = gcc_xo_gpll0_map, | |
331 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
332 | .clkr.hw.init = &(struct clk_init_data){ | |
333 | .name = "blsp1_qup1_i2c_apps_clk_src", | |
334 | .parent_names = gcc_xo_gpll0, | |
335 | .num_parents = 2, | |
336 | .ops = &clk_rcg2_ops, | |
337 | }, | |
338 | }; | |
339 | ||
340 | static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = { | |
341 | F(960000, P_XO, 10, 1, 2), | |
342 | F(4800000, P_XO, 4, 0, 0), | |
343 | F(9600000, P_XO, 2, 0, 0), | |
344 | F(15000000, P_GPLL0, 10, 1, 4), | |
345 | F(19200000, P_XO, 1, 0, 0), | |
346 | F(25000000, P_GPLL0, 12, 1, 2), | |
347 | F(50000000, P_GPLL0, 12, 0, 0), | |
348 | { } | |
349 | }; | |
350 | ||
351 | static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { | |
352 | .cmd_rcgr = 0x064c, | |
353 | .mnd_width = 8, | |
354 | .hid_width = 5, | |
355 | .parent_map = gcc_xo_gpll0_map, | |
356 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
357 | .clkr.hw.init = &(struct clk_init_data){ | |
358 | .name = "blsp1_qup1_spi_apps_clk_src", | |
359 | .parent_names = gcc_xo_gpll0, | |
360 | .num_parents = 2, | |
361 | .ops = &clk_rcg2_ops, | |
362 | }, | |
363 | }; | |
364 | ||
365 | static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { | |
366 | .cmd_rcgr = 0x06e0, | |
367 | .hid_width = 5, | |
368 | .parent_map = gcc_xo_gpll0_map, | |
369 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
370 | .clkr.hw.init = &(struct clk_init_data){ | |
371 | .name = "blsp1_qup2_i2c_apps_clk_src", | |
372 | .parent_names = gcc_xo_gpll0, | |
373 | .num_parents = 2, | |
374 | .ops = &clk_rcg2_ops, | |
375 | }, | |
376 | }; | |
377 | ||
378 | static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { | |
379 | .cmd_rcgr = 0x06cc, | |
380 | .mnd_width = 8, | |
381 | .hid_width = 5, | |
382 | .parent_map = gcc_xo_gpll0_map, | |
383 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
384 | .clkr.hw.init = &(struct clk_init_data){ | |
385 | .name = "blsp1_qup2_spi_apps_clk_src", | |
386 | .parent_names = gcc_xo_gpll0, | |
387 | .num_parents = 2, | |
388 | .ops = &clk_rcg2_ops, | |
389 | }, | |
390 | }; | |
391 | ||
392 | static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { | |
393 | .cmd_rcgr = 0x0760, | |
394 | .hid_width = 5, | |
395 | .parent_map = gcc_xo_gpll0_map, | |
396 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
397 | .clkr.hw.init = &(struct clk_init_data){ | |
398 | .name = "blsp1_qup3_i2c_apps_clk_src", | |
399 | .parent_names = gcc_xo_gpll0, | |
400 | .num_parents = 2, | |
401 | .ops = &clk_rcg2_ops, | |
402 | }, | |
403 | }; | |
404 | ||
405 | static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { | |
406 | .cmd_rcgr = 0x074c, | |
407 | .mnd_width = 8, | |
408 | .hid_width = 5, | |
409 | .parent_map = gcc_xo_gpll0_map, | |
410 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
411 | .clkr.hw.init = &(struct clk_init_data){ | |
412 | .name = "blsp1_qup3_spi_apps_clk_src", | |
413 | .parent_names = gcc_xo_gpll0, | |
414 | .num_parents = 2, | |
415 | .ops = &clk_rcg2_ops, | |
416 | }, | |
417 | }; | |
418 | ||
419 | static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { | |
420 | .cmd_rcgr = 0x07e0, | |
421 | .hid_width = 5, | |
422 | .parent_map = gcc_xo_gpll0_map, | |
423 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
424 | .clkr.hw.init = &(struct clk_init_data){ | |
425 | .name = "blsp1_qup4_i2c_apps_clk_src", | |
426 | .parent_names = gcc_xo_gpll0, | |
427 | .num_parents = 2, | |
428 | .ops = &clk_rcg2_ops, | |
429 | }, | |
430 | }; | |
431 | ||
432 | static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { | |
433 | .cmd_rcgr = 0x07cc, | |
434 | .mnd_width = 8, | |
435 | .hid_width = 5, | |
436 | .parent_map = gcc_xo_gpll0_map, | |
437 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
438 | .clkr.hw.init = &(struct clk_init_data){ | |
439 | .name = "blsp1_qup4_spi_apps_clk_src", | |
440 | .parent_names = gcc_xo_gpll0, | |
441 | .num_parents = 2, | |
442 | .ops = &clk_rcg2_ops, | |
443 | }, | |
444 | }; | |
445 | ||
446 | static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { | |
447 | .cmd_rcgr = 0x0860, | |
448 | .hid_width = 5, | |
449 | .parent_map = gcc_xo_gpll0_map, | |
450 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
451 | .clkr.hw.init = &(struct clk_init_data){ | |
452 | .name = "blsp1_qup5_i2c_apps_clk_src", | |
453 | .parent_names = gcc_xo_gpll0, | |
454 | .num_parents = 2, | |
455 | .ops = &clk_rcg2_ops, | |
456 | }, | |
457 | }; | |
458 | ||
459 | static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { | |
460 | .cmd_rcgr = 0x084c, | |
461 | .mnd_width = 8, | |
462 | .hid_width = 5, | |
463 | .parent_map = gcc_xo_gpll0_map, | |
464 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
465 | .clkr.hw.init = &(struct clk_init_data){ | |
466 | .name = "blsp1_qup5_spi_apps_clk_src", | |
467 | .parent_names = gcc_xo_gpll0, | |
468 | .num_parents = 2, | |
469 | .ops = &clk_rcg2_ops, | |
470 | }, | |
471 | }; | |
472 | ||
473 | static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { | |
474 | .cmd_rcgr = 0x08e0, | |
475 | .hid_width = 5, | |
476 | .parent_map = gcc_xo_gpll0_map, | |
477 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
478 | .clkr.hw.init = &(struct clk_init_data){ | |
479 | .name = "blsp1_qup6_i2c_apps_clk_src", | |
480 | .parent_names = gcc_xo_gpll0, | |
481 | .num_parents = 2, | |
482 | .ops = &clk_rcg2_ops, | |
483 | }, | |
484 | }; | |
485 | ||
486 | static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { | |
487 | .cmd_rcgr = 0x08cc, | |
488 | .mnd_width = 8, | |
489 | .hid_width = 5, | |
490 | .parent_map = gcc_xo_gpll0_map, | |
491 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
492 | .clkr.hw.init = &(struct clk_init_data){ | |
493 | .name = "blsp1_qup6_spi_apps_clk_src", | |
494 | .parent_names = gcc_xo_gpll0, | |
495 | .num_parents = 2, | |
496 | .ops = &clk_rcg2_ops, | |
497 | }, | |
498 | }; | |
499 | ||
500 | static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = { | |
501 | F(3686400, P_GPLL0, 1, 96, 15625), | |
502 | F(7372800, P_GPLL0, 1, 192, 15625), | |
503 | F(14745600, P_GPLL0, 1, 384, 15625), | |
504 | F(16000000, P_GPLL0, 5, 2, 15), | |
505 | F(19200000, P_XO, 1, 0, 0), | |
506 | F(24000000, P_GPLL0, 5, 1, 5), | |
507 | F(32000000, P_GPLL0, 1, 4, 75), | |
508 | F(40000000, P_GPLL0, 15, 0, 0), | |
509 | F(46400000, P_GPLL0, 1, 29, 375), | |
510 | F(48000000, P_GPLL0, 12.5, 0, 0), | |
511 | F(51200000, P_GPLL0, 1, 32, 375), | |
512 | F(56000000, P_GPLL0, 1, 7, 75), | |
513 | F(58982400, P_GPLL0, 1, 1536, 15625), | |
514 | F(60000000, P_GPLL0, 10, 0, 0), | |
515 | F(63160000, P_GPLL0, 9.5, 0, 0), | |
516 | { } | |
517 | }; | |
518 | ||
519 | static struct clk_rcg2 blsp1_uart1_apps_clk_src = { | |
520 | .cmd_rcgr = 0x068c, | |
521 | .mnd_width = 16, | |
522 | .hid_width = 5, | |
523 | .parent_map = gcc_xo_gpll0_map, | |
524 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
525 | .clkr.hw.init = &(struct clk_init_data){ | |
526 | .name = "blsp1_uart1_apps_clk_src", | |
527 | .parent_names = gcc_xo_gpll0, | |
528 | .num_parents = 2, | |
529 | .ops = &clk_rcg2_ops, | |
530 | }, | |
531 | }; | |
532 | ||
533 | static struct clk_rcg2 blsp1_uart2_apps_clk_src = { | |
534 | .cmd_rcgr = 0x070c, | |
535 | .mnd_width = 16, | |
536 | .hid_width = 5, | |
537 | .parent_map = gcc_xo_gpll0_map, | |
538 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
539 | .clkr.hw.init = &(struct clk_init_data){ | |
540 | .name = "blsp1_uart2_apps_clk_src", | |
541 | .parent_names = gcc_xo_gpll0, | |
542 | .num_parents = 2, | |
543 | .ops = &clk_rcg2_ops, | |
544 | }, | |
545 | }; | |
546 | ||
547 | static struct clk_rcg2 blsp1_uart3_apps_clk_src = { | |
548 | .cmd_rcgr = 0x078c, | |
549 | .mnd_width = 16, | |
550 | .hid_width = 5, | |
551 | .parent_map = gcc_xo_gpll0_map, | |
552 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
553 | .clkr.hw.init = &(struct clk_init_data){ | |
554 | .name = "blsp1_uart3_apps_clk_src", | |
555 | .parent_names = gcc_xo_gpll0, | |
556 | .num_parents = 2, | |
557 | .ops = &clk_rcg2_ops, | |
558 | }, | |
559 | }; | |
560 | ||
561 | static struct clk_rcg2 blsp1_uart4_apps_clk_src = { | |
562 | .cmd_rcgr = 0x080c, | |
563 | .mnd_width = 16, | |
564 | .hid_width = 5, | |
565 | .parent_map = gcc_xo_gpll0_map, | |
566 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
567 | .clkr.hw.init = &(struct clk_init_data){ | |
568 | .name = "blsp1_uart4_apps_clk_src", | |
569 | .parent_names = gcc_xo_gpll0, | |
570 | .num_parents = 2, | |
571 | .ops = &clk_rcg2_ops, | |
572 | }, | |
573 | }; | |
574 | ||
575 | static struct clk_rcg2 blsp1_uart5_apps_clk_src = { | |
576 | .cmd_rcgr = 0x088c, | |
577 | .mnd_width = 16, | |
578 | .hid_width = 5, | |
579 | .parent_map = gcc_xo_gpll0_map, | |
580 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
581 | .clkr.hw.init = &(struct clk_init_data){ | |
582 | .name = "blsp1_uart5_apps_clk_src", | |
583 | .parent_names = gcc_xo_gpll0, | |
584 | .num_parents = 2, | |
585 | .ops = &clk_rcg2_ops, | |
586 | }, | |
587 | }; | |
588 | ||
589 | static struct clk_rcg2 blsp1_uart6_apps_clk_src = { | |
590 | .cmd_rcgr = 0x090c, | |
591 | .mnd_width = 16, | |
592 | .hid_width = 5, | |
593 | .parent_map = gcc_xo_gpll0_map, | |
594 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
595 | .clkr.hw.init = &(struct clk_init_data){ | |
596 | .name = "blsp1_uart6_apps_clk_src", | |
597 | .parent_names = gcc_xo_gpll0, | |
598 | .num_parents = 2, | |
599 | .ops = &clk_rcg2_ops, | |
600 | }, | |
601 | }; | |
602 | ||
603 | static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { | |
604 | .cmd_rcgr = 0x09a0, | |
605 | .hid_width = 5, | |
606 | .parent_map = gcc_xo_gpll0_map, | |
607 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
608 | .clkr.hw.init = &(struct clk_init_data){ | |
609 | .name = "blsp2_qup1_i2c_apps_clk_src", | |
610 | .parent_names = gcc_xo_gpll0, | |
611 | .num_parents = 2, | |
612 | .ops = &clk_rcg2_ops, | |
613 | }, | |
614 | }; | |
615 | ||
616 | static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { | |
617 | .cmd_rcgr = 0x098c, | |
618 | .mnd_width = 8, | |
619 | .hid_width = 5, | |
620 | .parent_map = gcc_xo_gpll0_map, | |
621 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
622 | .clkr.hw.init = &(struct clk_init_data){ | |
623 | .name = "blsp2_qup1_spi_apps_clk_src", | |
624 | .parent_names = gcc_xo_gpll0, | |
625 | .num_parents = 2, | |
626 | .ops = &clk_rcg2_ops, | |
627 | }, | |
628 | }; | |
629 | ||
630 | static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { | |
631 | .cmd_rcgr = 0x0a20, | |
632 | .hid_width = 5, | |
633 | .parent_map = gcc_xo_gpll0_map, | |
634 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
635 | .clkr.hw.init = &(struct clk_init_data){ | |
636 | .name = "blsp2_qup2_i2c_apps_clk_src", | |
637 | .parent_names = gcc_xo_gpll0, | |
638 | .num_parents = 2, | |
639 | .ops = &clk_rcg2_ops, | |
640 | }, | |
641 | }; | |
642 | ||
643 | static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { | |
644 | .cmd_rcgr = 0x0a0c, | |
645 | .mnd_width = 8, | |
646 | .hid_width = 5, | |
647 | .parent_map = gcc_xo_gpll0_map, | |
648 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
649 | .clkr.hw.init = &(struct clk_init_data){ | |
650 | .name = "blsp2_qup2_spi_apps_clk_src", | |
651 | .parent_names = gcc_xo_gpll0, | |
652 | .num_parents = 2, | |
653 | .ops = &clk_rcg2_ops, | |
654 | }, | |
655 | }; | |
656 | ||
657 | static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { | |
658 | .cmd_rcgr = 0x0aa0, | |
659 | .hid_width = 5, | |
660 | .parent_map = gcc_xo_gpll0_map, | |
661 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
662 | .clkr.hw.init = &(struct clk_init_data){ | |
663 | .name = "blsp2_qup3_i2c_apps_clk_src", | |
664 | .parent_names = gcc_xo_gpll0, | |
665 | .num_parents = 2, | |
666 | .ops = &clk_rcg2_ops, | |
667 | }, | |
668 | }; | |
669 | ||
670 | static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { | |
671 | .cmd_rcgr = 0x0a8c, | |
672 | .mnd_width = 8, | |
673 | .hid_width = 5, | |
674 | .parent_map = gcc_xo_gpll0_map, | |
675 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
676 | .clkr.hw.init = &(struct clk_init_data){ | |
677 | .name = "blsp2_qup3_spi_apps_clk_src", | |
678 | .parent_names = gcc_xo_gpll0, | |
679 | .num_parents = 2, | |
680 | .ops = &clk_rcg2_ops, | |
681 | }, | |
682 | }; | |
683 | ||
684 | static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { | |
685 | .cmd_rcgr = 0x0b20, | |
686 | .hid_width = 5, | |
687 | .parent_map = gcc_xo_gpll0_map, | |
688 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
689 | .clkr.hw.init = &(struct clk_init_data){ | |
690 | .name = "blsp2_qup4_i2c_apps_clk_src", | |
691 | .parent_names = gcc_xo_gpll0, | |
692 | .num_parents = 2, | |
693 | .ops = &clk_rcg2_ops, | |
694 | }, | |
695 | }; | |
696 | ||
697 | static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { | |
698 | .cmd_rcgr = 0x0b0c, | |
699 | .mnd_width = 8, | |
700 | .hid_width = 5, | |
701 | .parent_map = gcc_xo_gpll0_map, | |
702 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
703 | .clkr.hw.init = &(struct clk_init_data){ | |
704 | .name = "blsp2_qup4_spi_apps_clk_src", | |
705 | .parent_names = gcc_xo_gpll0, | |
706 | .num_parents = 2, | |
707 | .ops = &clk_rcg2_ops, | |
708 | }, | |
709 | }; | |
710 | ||
711 | static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { | |
712 | .cmd_rcgr = 0x0ba0, | |
713 | .hid_width = 5, | |
714 | .parent_map = gcc_xo_gpll0_map, | |
715 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
716 | .clkr.hw.init = &(struct clk_init_data){ | |
717 | .name = "blsp2_qup5_i2c_apps_clk_src", | |
718 | .parent_names = gcc_xo_gpll0, | |
719 | .num_parents = 2, | |
720 | .ops = &clk_rcg2_ops, | |
721 | }, | |
722 | }; | |
723 | ||
724 | static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { | |
725 | .cmd_rcgr = 0x0b8c, | |
726 | .mnd_width = 8, | |
727 | .hid_width = 5, | |
728 | .parent_map = gcc_xo_gpll0_map, | |
729 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
730 | .clkr.hw.init = &(struct clk_init_data){ | |
731 | .name = "blsp2_qup5_spi_apps_clk_src", | |
732 | .parent_names = gcc_xo_gpll0, | |
733 | .num_parents = 2, | |
734 | .ops = &clk_rcg2_ops, | |
735 | }, | |
736 | }; | |
737 | ||
738 | static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { | |
739 | .cmd_rcgr = 0x0c20, | |
740 | .hid_width = 5, | |
741 | .parent_map = gcc_xo_gpll0_map, | |
742 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk, | |
743 | .clkr.hw.init = &(struct clk_init_data){ | |
744 | .name = "blsp2_qup6_i2c_apps_clk_src", | |
745 | .parent_names = gcc_xo_gpll0, | |
746 | .num_parents = 2, | |
747 | .ops = &clk_rcg2_ops, | |
748 | }, | |
749 | }; | |
750 | ||
751 | static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { | |
752 | .cmd_rcgr = 0x0c0c, | |
753 | .mnd_width = 8, | |
754 | .hid_width = 5, | |
755 | .parent_map = gcc_xo_gpll0_map, | |
756 | .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk, | |
757 | .clkr.hw.init = &(struct clk_init_data){ | |
758 | .name = "blsp2_qup6_spi_apps_clk_src", | |
759 | .parent_names = gcc_xo_gpll0, | |
760 | .num_parents = 2, | |
761 | .ops = &clk_rcg2_ops, | |
762 | }, | |
763 | }; | |
764 | ||
765 | static struct clk_rcg2 blsp2_uart1_apps_clk_src = { | |
766 | .cmd_rcgr = 0x09cc, | |
767 | .mnd_width = 16, | |
768 | .hid_width = 5, | |
769 | .parent_map = gcc_xo_gpll0_map, | |
770 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
771 | .clkr.hw.init = &(struct clk_init_data){ | |
772 | .name = "blsp2_uart1_apps_clk_src", | |
773 | .parent_names = gcc_xo_gpll0, | |
774 | .num_parents = 2, | |
775 | .ops = &clk_rcg2_ops, | |
776 | }, | |
777 | }; | |
778 | ||
779 | static struct clk_rcg2 blsp2_uart2_apps_clk_src = { | |
780 | .cmd_rcgr = 0x0a4c, | |
781 | .mnd_width = 16, | |
782 | .hid_width = 5, | |
783 | .parent_map = gcc_xo_gpll0_map, | |
784 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
785 | .clkr.hw.init = &(struct clk_init_data){ | |
786 | .name = "blsp2_uart2_apps_clk_src", | |
787 | .parent_names = gcc_xo_gpll0, | |
788 | .num_parents = 2, | |
789 | .ops = &clk_rcg2_ops, | |
790 | }, | |
791 | }; | |
792 | ||
793 | static struct clk_rcg2 blsp2_uart3_apps_clk_src = { | |
794 | .cmd_rcgr = 0x0acc, | |
795 | .mnd_width = 16, | |
796 | .hid_width = 5, | |
797 | .parent_map = gcc_xo_gpll0_map, | |
798 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
799 | .clkr.hw.init = &(struct clk_init_data){ | |
800 | .name = "blsp2_uart3_apps_clk_src", | |
801 | .parent_names = gcc_xo_gpll0, | |
802 | .num_parents = 2, | |
803 | .ops = &clk_rcg2_ops, | |
804 | }, | |
805 | }; | |
806 | ||
807 | static struct clk_rcg2 blsp2_uart4_apps_clk_src = { | |
808 | .cmd_rcgr = 0x0b4c, | |
809 | .mnd_width = 16, | |
810 | .hid_width = 5, | |
811 | .parent_map = gcc_xo_gpll0_map, | |
812 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
813 | .clkr.hw.init = &(struct clk_init_data){ | |
814 | .name = "blsp2_uart4_apps_clk_src", | |
815 | .parent_names = gcc_xo_gpll0, | |
816 | .num_parents = 2, | |
817 | .ops = &clk_rcg2_ops, | |
818 | }, | |
819 | }; | |
820 | ||
821 | static struct clk_rcg2 blsp2_uart5_apps_clk_src = { | |
822 | .cmd_rcgr = 0x0bcc, | |
823 | .mnd_width = 16, | |
824 | .hid_width = 5, | |
825 | .parent_map = gcc_xo_gpll0_map, | |
826 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
827 | .clkr.hw.init = &(struct clk_init_data){ | |
828 | .name = "blsp2_uart5_apps_clk_src", | |
829 | .parent_names = gcc_xo_gpll0, | |
830 | .num_parents = 2, | |
831 | .ops = &clk_rcg2_ops, | |
832 | }, | |
833 | }; | |
834 | ||
835 | static struct clk_rcg2 blsp2_uart6_apps_clk_src = { | |
836 | .cmd_rcgr = 0x0c4c, | |
837 | .mnd_width = 16, | |
838 | .hid_width = 5, | |
839 | .parent_map = gcc_xo_gpll0_map, | |
840 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, | |
841 | .clkr.hw.init = &(struct clk_init_data){ | |
842 | .name = "blsp2_uart6_apps_clk_src", | |
843 | .parent_names = gcc_xo_gpll0, | |
844 | .num_parents = 2, | |
845 | .ops = &clk_rcg2_ops, | |
846 | }, | |
847 | }; | |
848 | ||
849 | static const struct freq_tbl ftbl_gcc_ce1_clk[] = { | |
850 | F(50000000, P_GPLL0, 12, 0, 0), | |
851 | F(85710000, P_GPLL0, 7, 0, 0), | |
852 | F(100000000, P_GPLL0, 6, 0, 0), | |
853 | F(171430000, P_GPLL0, 3.5, 0, 0), | |
854 | { } | |
855 | }; | |
856 | ||
857 | static struct clk_rcg2 ce1_clk_src = { | |
858 | .cmd_rcgr = 0x1050, | |
859 | .hid_width = 5, | |
860 | .parent_map = gcc_xo_gpll0_map, | |
861 | .freq_tbl = ftbl_gcc_ce1_clk, | |
862 | .clkr.hw.init = &(struct clk_init_data){ | |
863 | .name = "ce1_clk_src", | |
864 | .parent_names = gcc_xo_gpll0, | |
865 | .num_parents = 2, | |
866 | .ops = &clk_rcg2_ops, | |
867 | }, | |
868 | }; | |
869 | ||
870 | static const struct freq_tbl ftbl_gcc_ce2_clk[] = { | |
871 | F(50000000, P_GPLL0, 12, 0, 0), | |
872 | F(85710000, P_GPLL0, 7, 0, 0), | |
873 | F(100000000, P_GPLL0, 6, 0, 0), | |
874 | F(171430000, P_GPLL0, 3.5, 0, 0), | |
875 | { } | |
876 | }; | |
877 | ||
878 | static struct clk_rcg2 ce2_clk_src = { | |
879 | .cmd_rcgr = 0x1090, | |
880 | .hid_width = 5, | |
881 | .parent_map = gcc_xo_gpll0_map, | |
882 | .freq_tbl = ftbl_gcc_ce2_clk, | |
883 | .clkr.hw.init = &(struct clk_init_data){ | |
884 | .name = "ce2_clk_src", | |
885 | .parent_names = gcc_xo_gpll0, | |
886 | .num_parents = 2, | |
887 | .ops = &clk_rcg2_ops, | |
888 | }, | |
889 | }; | |
890 | ||
891 | static const struct freq_tbl ftbl_gcc_ce3_clk[] = { | |
892 | F(50000000, P_GPLL0, 12, 0, 0), | |
893 | F(85710000, P_GPLL0, 7, 0, 0), | |
894 | F(100000000, P_GPLL0, 6, 0, 0), | |
895 | F(171430000, P_GPLL0, 3.5, 0, 0), | |
896 | { } | |
897 | }; | |
898 | ||
899 | static struct clk_rcg2 ce3_clk_src = { | |
900 | .cmd_rcgr = 0x1d10, | |
901 | .hid_width = 5, | |
902 | .parent_map = gcc_xo_gpll0_map, | |
903 | .freq_tbl = ftbl_gcc_ce3_clk, | |
904 | .clkr.hw.init = &(struct clk_init_data){ | |
905 | .name = "ce3_clk_src", | |
906 | .parent_names = gcc_xo_gpll0, | |
907 | .num_parents = 2, | |
908 | .ops = &clk_rcg2_ops, | |
909 | }, | |
910 | }; | |
911 | ||
912 | static const struct freq_tbl ftbl_gcc_gp_clk[] = { | |
913 | F(19200000, P_XO, 1, 0, 0), | |
914 | F(100000000, P_GPLL0, 6, 0, 0), | |
915 | F(200000000, P_GPLL0, 3, 0, 0), | |
916 | { } | |
917 | }; | |
918 | ||
919 | static struct clk_rcg2 gp1_clk_src = { | |
920 | .cmd_rcgr = 0x1904, | |
921 | .mnd_width = 8, | |
922 | .hid_width = 5, | |
923 | .parent_map = gcc_xo_gpll0_map, | |
924 | .freq_tbl = ftbl_gcc_gp_clk, | |
925 | .clkr.hw.init = &(struct clk_init_data){ | |
926 | .name = "gp1_clk_src", | |
927 | .parent_names = gcc_xo_gpll0, | |
928 | .num_parents = 2, | |
929 | .ops = &clk_rcg2_ops, | |
930 | }, | |
931 | }; | |
932 | ||
933 | static struct clk_rcg2 gp2_clk_src = { | |
934 | .cmd_rcgr = 0x1944, | |
935 | .mnd_width = 8, | |
936 | .hid_width = 5, | |
937 | .parent_map = gcc_xo_gpll0_map, | |
938 | .freq_tbl = ftbl_gcc_gp_clk, | |
939 | .clkr.hw.init = &(struct clk_init_data){ | |
940 | .name = "gp2_clk_src", | |
941 | .parent_names = gcc_xo_gpll0, | |
942 | .num_parents = 2, | |
943 | .ops = &clk_rcg2_ops, | |
944 | }, | |
945 | }; | |
946 | ||
947 | static struct clk_rcg2 gp3_clk_src = { | |
948 | .cmd_rcgr = 0x1984, | |
949 | .mnd_width = 8, | |
950 | .hid_width = 5, | |
951 | .parent_map = gcc_xo_gpll0_map, | |
952 | .freq_tbl = ftbl_gcc_gp_clk, | |
953 | .clkr.hw.init = &(struct clk_init_data){ | |
954 | .name = "gp3_clk_src", | |
955 | .parent_names = gcc_xo_gpll0, | |
956 | .num_parents = 2, | |
957 | .ops = &clk_rcg2_ops, | |
958 | }, | |
959 | }; | |
960 | ||
5424e102 GD |
961 | static const struct freq_tbl ftbl_gcc_pcie_0_1_aux_clk[] = { |
962 | F(1010000, P_XO, 1, 1, 19), | |
963 | { } | |
964 | }; | |
965 | ||
966 | static struct clk_rcg2 pcie_0_aux_clk_src = { | |
967 | .cmd_rcgr = 0x1b2c, | |
968 | .mnd_width = 16, | |
969 | .hid_width = 5, | |
970 | .parent_map = gcc_xo_pcie_sleep_map, | |
971 | .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk, | |
972 | .clkr.hw.init = &(struct clk_init_data){ | |
973 | .name = "pcie_0_aux_clk_src", | |
974 | .parent_names = gcc_xo_pcie_sleep, | |
975 | .num_parents = 2, | |
976 | .ops = &clk_rcg2_ops, | |
977 | }, | |
978 | }; | |
979 | ||
980 | static struct clk_rcg2 pcie_1_aux_clk_src = { | |
981 | .cmd_rcgr = 0x1bac, | |
982 | .mnd_width = 16, | |
983 | .hid_width = 5, | |
984 | .parent_map = gcc_xo_pcie_sleep_map, | |
985 | .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk, | |
986 | .clkr.hw.init = &(struct clk_init_data){ | |
987 | .name = "pcie_1_aux_clk_src", | |
988 | .parent_names = gcc_xo_pcie_sleep, | |
989 | .num_parents = 2, | |
990 | .ops = &clk_rcg2_ops, | |
991 | }, | |
992 | }; | |
993 | ||
994 | static const struct freq_tbl ftbl_gcc_pcie_0_1_pipe_clk[] = { | |
995 | F(125000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0), | |
996 | F(250000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0), | |
997 | { } | |
998 | }; | |
999 | ||
1000 | static struct clk_rcg2 pcie_0_pipe_clk_src = { | |
1001 | .cmd_rcgr = 0x1b18, | |
1002 | .hid_width = 5, | |
1003 | .parent_map = gcc_xo_pcie_map, | |
1004 | .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk, | |
1005 | .clkr.hw.init = &(struct clk_init_data){ | |
1006 | .name = "pcie_0_pipe_clk_src", | |
1007 | .parent_names = gcc_xo_pcie, | |
1008 | .num_parents = 2, | |
1009 | .ops = &clk_rcg2_ops, | |
1010 | }, | |
1011 | }; | |
1012 | ||
1013 | static struct clk_rcg2 pcie_1_pipe_clk_src = { | |
1014 | .cmd_rcgr = 0x1b98, | |
1015 | .hid_width = 5, | |
1016 | .parent_map = gcc_xo_pcie_map, | |
1017 | .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk, | |
1018 | .clkr.hw.init = &(struct clk_init_data){ | |
1019 | .name = "pcie_1_pipe_clk_src", | |
1020 | .parent_names = gcc_xo_pcie, | |
1021 | .num_parents = 2, | |
1022 | .ops = &clk_rcg2_ops, | |
1023 | }, | |
1024 | }; | |
1025 | ||
02824653 GD |
1026 | static const struct freq_tbl ftbl_gcc_pdm2_clk[] = { |
1027 | F(60000000, P_GPLL0, 10, 0, 0), | |
1028 | { } | |
1029 | }; | |
1030 | ||
1031 | static struct clk_rcg2 pdm2_clk_src = { | |
1032 | .cmd_rcgr = 0x0cd0, | |
1033 | .hid_width = 5, | |
1034 | .parent_map = gcc_xo_gpll0_map, | |
1035 | .freq_tbl = ftbl_gcc_pdm2_clk, | |
1036 | .clkr.hw.init = &(struct clk_init_data){ | |
1037 | .name = "pdm2_clk_src", | |
1038 | .parent_names = gcc_xo_gpll0, | |
1039 | .num_parents = 2, | |
1040 | .ops = &clk_rcg2_ops, | |
1041 | }, | |
1042 | }; | |
1043 | ||
5424e102 GD |
1044 | static const struct freq_tbl ftbl_gcc_sata_asic0_clk[] = { |
1045 | F(75000000, P_SATA_ASIC0_CLK, 1, 0, 0), | |
1046 | F(150000000, P_SATA_ASIC0_CLK, 1, 0, 0), | |
1047 | F(300000000, P_SATA_ASIC0_CLK, 1, 0, 0), | |
1048 | { } | |
1049 | }; | |
1050 | ||
1051 | static struct clk_rcg2 sata_asic0_clk_src = { | |
1052 | .cmd_rcgr = 0x1c94, | |
1053 | .hid_width = 5, | |
1054 | .parent_map = gcc_xo_sata_asic0_map, | |
1055 | .freq_tbl = ftbl_gcc_sata_asic0_clk, | |
1056 | .clkr.hw.init = &(struct clk_init_data){ | |
1057 | .name = "sata_asic0_clk_src", | |
1058 | .parent_names = gcc_xo_sata_asic0, | |
1059 | .num_parents = 2, | |
1060 | .ops = &clk_rcg2_ops, | |
1061 | }, | |
1062 | }; | |
1063 | ||
1064 | static const struct freq_tbl ftbl_gcc_sata_pmalive_clk[] = { | |
1065 | F(19200000, P_XO, 1, 0, 0), | |
1066 | F(50000000, P_GPLL0, 12, 0, 0), | |
1067 | F(100000000, P_GPLL0, 6, 0, 0), | |
1068 | { } | |
1069 | }; | |
1070 | ||
1071 | static struct clk_rcg2 sata_pmalive_clk_src = { | |
1072 | .cmd_rcgr = 0x1c80, | |
1073 | .hid_width = 5, | |
1074 | .parent_map = gcc_xo_gpll0_map, | |
1075 | .freq_tbl = ftbl_gcc_sata_pmalive_clk, | |
1076 | .clkr.hw.init = &(struct clk_init_data){ | |
1077 | .name = "sata_pmalive_clk_src", | |
1078 | .parent_names = gcc_xo_gpll0, | |
1079 | .num_parents = 2, | |
1080 | .ops = &clk_rcg2_ops, | |
1081 | }, | |
1082 | }; | |
1083 | ||
1084 | static const struct freq_tbl ftbl_gcc_sata_rx_clk[] = { | |
1085 | F(75000000, P_SATA_RX_CLK, 1, 0, 0), | |
1086 | F(150000000, P_SATA_RX_CLK, 1, 0, 0), | |
1087 | F(300000000, P_SATA_RX_CLK, 1, 0, 0), | |
1088 | { } | |
1089 | }; | |
1090 | ||
1091 | static struct clk_rcg2 sata_rx_clk_src = { | |
1092 | .cmd_rcgr = 0x1ca8, | |
1093 | .hid_width = 5, | |
1094 | .parent_map = gcc_xo_sata_rx_map, | |
1095 | .freq_tbl = ftbl_gcc_sata_rx_clk, | |
1096 | .clkr.hw.init = &(struct clk_init_data){ | |
1097 | .name = "sata_rx_clk_src", | |
1098 | .parent_names = gcc_xo_sata_rx, | |
1099 | .num_parents = 2, | |
1100 | .ops = &clk_rcg2_ops, | |
1101 | }, | |
1102 | }; | |
1103 | ||
1104 | static const struct freq_tbl ftbl_gcc_sata_rx_oob_clk[] = { | |
1105 | F(100000000, P_GPLL0, 6, 0, 0), | |
1106 | { } | |
1107 | }; | |
1108 | ||
1109 | static struct clk_rcg2 sata_rx_oob_clk_src = { | |
1110 | .cmd_rcgr = 0x1c5c, | |
1111 | .hid_width = 5, | |
1112 | .parent_map = gcc_xo_gpll0_map, | |
1113 | .freq_tbl = ftbl_gcc_sata_rx_oob_clk, | |
1114 | .clkr.hw.init = &(struct clk_init_data){ | |
1115 | .name = "sata_rx_oob_clk_src", | |
1116 | .parent_names = gcc_xo_gpll0, | |
1117 | .num_parents = 2, | |
1118 | .ops = &clk_rcg2_ops, | |
1119 | }, | |
1120 | }; | |
1121 | ||
02824653 GD |
1122 | static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = { |
1123 | F(144000, P_XO, 16, 3, 25), | |
1124 | F(400000, P_XO, 12, 1, 4), | |
1125 | F(20000000, P_GPLL0, 15, 1, 2), | |
1126 | F(25000000, P_GPLL0, 12, 1, 2), | |
1127 | F(50000000, P_GPLL0, 12, 0, 0), | |
1128 | F(100000000, P_GPLL0, 6, 0, 0), | |
1129 | F(192000000, P_GPLL4, 4, 0, 0), | |
1130 | F(200000000, P_GPLL0, 3, 0, 0), | |
1131 | F(384000000, P_GPLL4, 2, 0, 0), | |
1132 | { } | |
1133 | }; | |
1134 | ||
1135 | static struct clk_rcg2 sdcc1_apps_clk_src = { | |
1136 | .cmd_rcgr = 0x04d0, | |
1137 | .mnd_width = 8, | |
1138 | .hid_width = 5, | |
1139 | .parent_map = gcc_xo_gpll0_gpll4_map, | |
1140 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, | |
1141 | .clkr.hw.init = &(struct clk_init_data){ | |
1142 | .name = "sdcc1_apps_clk_src", | |
1143 | .parent_names = gcc_xo_gpll0_gpll4, | |
1144 | .num_parents = 3, | |
1145 | .ops = &clk_rcg2_ops, | |
1146 | }, | |
1147 | }; | |
1148 | ||
1149 | static struct clk_rcg2 sdcc2_apps_clk_src = { | |
1150 | .cmd_rcgr = 0x0510, | |
1151 | .mnd_width = 8, | |
1152 | .hid_width = 5, | |
1153 | .parent_map = gcc_xo_gpll0_map, | |
1154 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, | |
1155 | .clkr.hw.init = &(struct clk_init_data){ | |
1156 | .name = "sdcc2_apps_clk_src", | |
1157 | .parent_names = gcc_xo_gpll0, | |
1158 | .num_parents = 2, | |
1159 | .ops = &clk_rcg2_ops, | |
1160 | }, | |
1161 | }; | |
1162 | ||
1163 | static struct clk_rcg2 sdcc3_apps_clk_src = { | |
1164 | .cmd_rcgr = 0x0550, | |
1165 | .mnd_width = 8, | |
1166 | .hid_width = 5, | |
1167 | .parent_map = gcc_xo_gpll0_map, | |
1168 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, | |
1169 | .clkr.hw.init = &(struct clk_init_data){ | |
1170 | .name = "sdcc3_apps_clk_src", | |
1171 | .parent_names = gcc_xo_gpll0, | |
1172 | .num_parents = 2, | |
1173 | .ops = &clk_rcg2_ops, | |
1174 | }, | |
1175 | }; | |
1176 | ||
1177 | static struct clk_rcg2 sdcc4_apps_clk_src = { | |
1178 | .cmd_rcgr = 0x0590, | |
1179 | .mnd_width = 8, | |
1180 | .hid_width = 5, | |
1181 | .parent_map = gcc_xo_gpll0_map, | |
1182 | .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk, | |
1183 | .clkr.hw.init = &(struct clk_init_data){ | |
1184 | .name = "sdcc4_apps_clk_src", | |
1185 | .parent_names = gcc_xo_gpll0, | |
1186 | .num_parents = 2, | |
1187 | .ops = &clk_rcg2_ops, | |
1188 | }, | |
1189 | }; | |
1190 | ||
1191 | static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = { | |
1192 | F(105000, P_XO, 2, 1, 91), | |
1193 | { } | |
1194 | }; | |
1195 | ||
1196 | static struct clk_rcg2 tsif_ref_clk_src = { | |
1197 | .cmd_rcgr = 0x0d90, | |
1198 | .mnd_width = 8, | |
1199 | .hid_width = 5, | |
1200 | .parent_map = gcc_xo_gpll0_map, | |
1201 | .freq_tbl = ftbl_gcc_tsif_ref_clk, | |
1202 | .clkr.hw.init = &(struct clk_init_data){ | |
1203 | .name = "tsif_ref_clk_src", | |
1204 | .parent_names = gcc_xo_gpll0, | |
1205 | .num_parents = 2, | |
1206 | .ops = &clk_rcg2_ops, | |
1207 | }, | |
1208 | }; | |
1209 | ||
1210 | static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = { | |
1211 | F(60000000, P_GPLL0, 10, 0, 0), | |
1212 | { } | |
1213 | }; | |
1214 | ||
1215 | static struct clk_rcg2 usb30_mock_utmi_clk_src = { | |
1216 | .cmd_rcgr = 0x03e8, | |
1217 | .hid_width = 5, | |
1218 | .parent_map = gcc_xo_gpll0_map, | |
1219 | .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk, | |
1220 | .clkr.hw.init = &(struct clk_init_data){ | |
1221 | .name = "usb30_mock_utmi_clk_src", | |
1222 | .parent_names = gcc_xo_gpll0, | |
1223 | .num_parents = 2, | |
1224 | .ops = &clk_rcg2_ops, | |
1225 | }, | |
1226 | }; | |
1227 | ||
1228 | static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = { | |
1229 | F(125000000, P_GPLL0, 1, 5, 24), | |
1230 | { } | |
1231 | }; | |
1232 | ||
1233 | static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = { | |
1234 | .cmd_rcgr = 0x1be8, | |
1235 | .hid_width = 5, | |
1236 | .parent_map = gcc_xo_gpll0_map, | |
1237 | .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk, | |
1238 | .clkr.hw.init = &(struct clk_init_data){ | |
1239 | .name = "usb30_sec_mock_utmi_clk_src", | |
1240 | .parent_names = gcc_xo_gpll0, | |
1241 | .num_parents = 2, | |
1242 | .ops = &clk_rcg2_ops, | |
1243 | }, | |
1244 | }; | |
1245 | ||
1246 | static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { | |
1247 | F(75000000, P_GPLL0, 8, 0, 0), | |
1248 | { } | |
1249 | }; | |
1250 | ||
1251 | static struct clk_rcg2 usb_hs_system_clk_src = { | |
1252 | .cmd_rcgr = 0x0490, | |
1253 | .hid_width = 5, | |
1254 | .parent_map = gcc_xo_gpll0_map, | |
1255 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, | |
1256 | .clkr.hw.init = &(struct clk_init_data){ | |
1257 | .name = "usb_hs_system_clk_src", | |
1258 | .parent_names = gcc_xo_gpll0, | |
1259 | .num_parents = 2, | |
1260 | .ops = &clk_rcg2_ops, | |
1261 | }, | |
1262 | }; | |
1263 | ||
1264 | static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = { | |
1265 | F(480000000, P_GPLL1, 1, 0, 0), | |
1266 | { } | |
1267 | }; | |
1268 | ||
293d2e97 GD |
1269 | static const struct parent_map usb_hsic_clk_src_map[] = { |
1270 | { P_XO, 0 }, | |
1271 | { P_GPLL1, 4 } | |
02824653 GD |
1272 | }; |
1273 | ||
1274 | static struct clk_rcg2 usb_hsic_clk_src = { | |
1275 | .cmd_rcgr = 0x0440, | |
1276 | .hid_width = 5, | |
1277 | .parent_map = usb_hsic_clk_src_map, | |
1278 | .freq_tbl = ftbl_gcc_usb_hsic_clk, | |
1279 | .clkr.hw.init = &(struct clk_init_data){ | |
1280 | .name = "usb_hsic_clk_src", | |
1281 | .parent_names = (const char *[]){ | |
1282 | "xo", | |
1283 | "gpll1_vote", | |
1284 | }, | |
1285 | .num_parents = 2, | |
1286 | .ops = &clk_rcg2_ops, | |
1287 | }, | |
1288 | }; | |
1289 | ||
1290 | static const struct freq_tbl ftbl_gcc_usb_hsic_ahb_clk_src[] = { | |
1291 | F(60000000, P_GPLL1, 8, 0, 0), | |
1292 | { } | |
1293 | }; | |
1294 | ||
1295 | static struct clk_rcg2 usb_hsic_ahb_clk_src = { | |
1296 | .cmd_rcgr = 0x046c, | |
1297 | .mnd_width = 8, | |
1298 | .hid_width = 5, | |
1299 | .parent_map = usb_hsic_clk_src_map, | |
1300 | .freq_tbl = ftbl_gcc_usb_hsic_ahb_clk_src, | |
1301 | .clkr.hw.init = &(struct clk_init_data){ | |
1302 | .name = "usb_hsic_ahb_clk_src", | |
1303 | .parent_names = (const char *[]){ | |
1304 | "xo", | |
1305 | "gpll1_vote", | |
1306 | }, | |
1307 | .num_parents = 2, | |
1308 | .ops = &clk_rcg2_ops, | |
1309 | }, | |
1310 | }; | |
1311 | ||
1312 | static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = { | |
1313 | F(9600000, P_XO, 2, 0, 0), | |
1314 | { } | |
1315 | }; | |
1316 | ||
1317 | static struct clk_rcg2 usb_hsic_io_cal_clk_src = { | |
1318 | .cmd_rcgr = 0x0458, | |
1319 | .hid_width = 5, | |
1320 | .parent_map = gcc_xo_gpll0_map, | |
1321 | .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk, | |
1322 | .clkr.hw.init = &(struct clk_init_data){ | |
1323 | .name = "usb_hsic_io_cal_clk_src", | |
1324 | .parent_names = gcc_xo_gpll0, | |
1325 | .num_parents = 1, | |
1326 | .ops = &clk_rcg2_ops, | |
1327 | }, | |
1328 | }; | |
1329 | ||
1330 | static struct clk_branch gcc_usb_hsic_mock_utmi_clk = { | |
1331 | .halt_reg = 0x1f14, | |
1332 | .clkr = { | |
1333 | .enable_reg = 0x1f14, | |
1334 | .enable_mask = BIT(0), | |
1335 | .hw.init = &(struct clk_init_data){ | |
1336 | .name = "gcc_usb_hsic_mock_utmi_clk", | |
1337 | .parent_names = (const char *[]){ | |
1338 | "usb_hsic_mock_utmi_clk_src", | |
1339 | }, | |
1340 | .num_parents = 1, | |
1341 | .flags = CLK_SET_RATE_PARENT, | |
1342 | .ops = &clk_branch2_ops, | |
1343 | }, | |
1344 | }, | |
1345 | }; | |
1346 | ||
1347 | static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk[] = { | |
1348 | F(60000000, P_GPLL0, 10, 0, 0), | |
1349 | { } | |
1350 | }; | |
1351 | ||
1352 | static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = { | |
1353 | .cmd_rcgr = 0x1f00, | |
1354 | .hid_width = 5, | |
1355 | .parent_map = gcc_xo_gpll0_map, | |
1356 | .freq_tbl = ftbl_gcc_usb_hsic_mock_utmi_clk, | |
1357 | .clkr.hw.init = &(struct clk_init_data){ | |
1358 | .name = "usb_hsic_mock_utmi_clk_src", | |
1359 | .parent_names = gcc_xo_gpll0, | |
1360 | .num_parents = 1, | |
1361 | .ops = &clk_rcg2_ops, | |
1362 | }, | |
1363 | }; | |
1364 | ||
1365 | static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = { | |
1366 | F(75000000, P_GPLL0, 8, 0, 0), | |
1367 | { } | |
1368 | }; | |
1369 | ||
1370 | static struct clk_rcg2 usb_hsic_system_clk_src = { | |
1371 | .cmd_rcgr = 0x041c, | |
1372 | .hid_width = 5, | |
1373 | .parent_map = gcc_xo_gpll0_map, | |
1374 | .freq_tbl = ftbl_gcc_usb_hsic_system_clk, | |
1375 | .clkr.hw.init = &(struct clk_init_data){ | |
1376 | .name = "usb_hsic_system_clk_src", | |
1377 | .parent_names = gcc_xo_gpll0, | |
1378 | .num_parents = 2, | |
1379 | .ops = &clk_rcg2_ops, | |
1380 | }, | |
1381 | }; | |
1382 | ||
1383 | static struct clk_branch gcc_bam_dma_ahb_clk = { | |
1384 | .halt_reg = 0x0d44, | |
1385 | .halt_check = BRANCH_HALT_VOTED, | |
1386 | .clkr = { | |
1387 | .enable_reg = 0x1484, | |
1388 | .enable_mask = BIT(12), | |
1389 | .hw.init = &(struct clk_init_data){ | |
1390 | .name = "gcc_bam_dma_ahb_clk", | |
1391 | .parent_names = (const char *[]){ | |
1392 | "periph_noc_clk_src", | |
1393 | }, | |
1394 | .num_parents = 1, | |
1395 | .ops = &clk_branch2_ops, | |
1396 | }, | |
1397 | }, | |
1398 | }; | |
1399 | ||
1400 | static struct clk_branch gcc_blsp1_ahb_clk = { | |
1401 | .halt_reg = 0x05c4, | |
1402 | .halt_check = BRANCH_HALT_VOTED, | |
1403 | .clkr = { | |
1404 | .enable_reg = 0x1484, | |
1405 | .enable_mask = BIT(17), | |
1406 | .hw.init = &(struct clk_init_data){ | |
1407 | .name = "gcc_blsp1_ahb_clk", | |
1408 | .parent_names = (const char *[]){ | |
1409 | "periph_noc_clk_src", | |
1410 | }, | |
1411 | .num_parents = 1, | |
1412 | .ops = &clk_branch2_ops, | |
1413 | }, | |
1414 | }, | |
1415 | }; | |
1416 | ||
1417 | static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { | |
1418 | .halt_reg = 0x0648, | |
1419 | .clkr = { | |
1420 | .enable_reg = 0x0648, | |
1421 | .enable_mask = BIT(0), | |
1422 | .hw.init = &(struct clk_init_data){ | |
1423 | .name = "gcc_blsp1_qup1_i2c_apps_clk", | |
1424 | .parent_names = (const char *[]){ | |
1425 | "blsp1_qup1_i2c_apps_clk_src", | |
1426 | }, | |
1427 | .num_parents = 1, | |
1428 | .flags = CLK_SET_RATE_PARENT, | |
1429 | .ops = &clk_branch2_ops, | |
1430 | }, | |
1431 | }, | |
1432 | }; | |
1433 | ||
1434 | static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { | |
1435 | .halt_reg = 0x0644, | |
1436 | .clkr = { | |
1437 | .enable_reg = 0x0644, | |
1438 | .enable_mask = BIT(0), | |
1439 | .hw.init = &(struct clk_init_data){ | |
1440 | .name = "gcc_blsp1_qup1_spi_apps_clk", | |
1441 | .parent_names = (const char *[]){ | |
1442 | "blsp1_qup1_spi_apps_clk_src", | |
1443 | }, | |
1444 | .num_parents = 1, | |
1445 | .flags = CLK_SET_RATE_PARENT, | |
1446 | .ops = &clk_branch2_ops, | |
1447 | }, | |
1448 | }, | |
1449 | }; | |
1450 | ||
1451 | static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { | |
1452 | .halt_reg = 0x06c8, | |
1453 | .clkr = { | |
1454 | .enable_reg = 0x06c8, | |
1455 | .enable_mask = BIT(0), | |
1456 | .hw.init = &(struct clk_init_data){ | |
1457 | .name = "gcc_blsp1_qup2_i2c_apps_clk", | |
1458 | .parent_names = (const char *[]){ | |
1459 | "blsp1_qup2_i2c_apps_clk_src", | |
1460 | }, | |
1461 | .num_parents = 1, | |
1462 | .flags = CLK_SET_RATE_PARENT, | |
1463 | .ops = &clk_branch2_ops, | |
1464 | }, | |
1465 | }, | |
1466 | }; | |
1467 | ||
1468 | static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { | |
1469 | .halt_reg = 0x06c4, | |
1470 | .clkr = { | |
1471 | .enable_reg = 0x06c4, | |
1472 | .enable_mask = BIT(0), | |
1473 | .hw.init = &(struct clk_init_data){ | |
1474 | .name = "gcc_blsp1_qup2_spi_apps_clk", | |
1475 | .parent_names = (const char *[]){ | |
1476 | "blsp1_qup2_spi_apps_clk_src", | |
1477 | }, | |
1478 | .num_parents = 1, | |
1479 | .flags = CLK_SET_RATE_PARENT, | |
1480 | .ops = &clk_branch2_ops, | |
1481 | }, | |
1482 | }, | |
1483 | }; | |
1484 | ||
1485 | static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { | |
1486 | .halt_reg = 0x0748, | |
1487 | .clkr = { | |
1488 | .enable_reg = 0x0748, | |
1489 | .enable_mask = BIT(0), | |
1490 | .hw.init = &(struct clk_init_data){ | |
1491 | .name = "gcc_blsp1_qup3_i2c_apps_clk", | |
1492 | .parent_names = (const char *[]){ | |
1493 | "blsp1_qup3_i2c_apps_clk_src", | |
1494 | }, | |
1495 | .num_parents = 1, | |
1496 | .flags = CLK_SET_RATE_PARENT, | |
1497 | .ops = &clk_branch2_ops, | |
1498 | }, | |
1499 | }, | |
1500 | }; | |
1501 | ||
1502 | static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { | |
1503 | .halt_reg = 0x0744, | |
1504 | .clkr = { | |
1505 | .enable_reg = 0x0744, | |
1506 | .enable_mask = BIT(0), | |
1507 | .hw.init = &(struct clk_init_data){ | |
1508 | .name = "gcc_blsp1_qup3_spi_apps_clk", | |
1509 | .parent_names = (const char *[]){ | |
1510 | "blsp1_qup3_spi_apps_clk_src", | |
1511 | }, | |
1512 | .num_parents = 1, | |
1513 | .flags = CLK_SET_RATE_PARENT, | |
1514 | .ops = &clk_branch2_ops, | |
1515 | }, | |
1516 | }, | |
1517 | }; | |
1518 | ||
1519 | static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { | |
1520 | .halt_reg = 0x07c8, | |
1521 | .clkr = { | |
1522 | .enable_reg = 0x07c8, | |
1523 | .enable_mask = BIT(0), | |
1524 | .hw.init = &(struct clk_init_data){ | |
1525 | .name = "gcc_blsp1_qup4_i2c_apps_clk", | |
1526 | .parent_names = (const char *[]){ | |
1527 | "blsp1_qup4_i2c_apps_clk_src", | |
1528 | }, | |
1529 | .num_parents = 1, | |
1530 | .flags = CLK_SET_RATE_PARENT, | |
1531 | .ops = &clk_branch2_ops, | |
1532 | }, | |
1533 | }, | |
1534 | }; | |
1535 | ||
1536 | static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { | |
1537 | .halt_reg = 0x07c4, | |
1538 | .clkr = { | |
1539 | .enable_reg = 0x07c4, | |
1540 | .enable_mask = BIT(0), | |
1541 | .hw.init = &(struct clk_init_data){ | |
1542 | .name = "gcc_blsp1_qup4_spi_apps_clk", | |
1543 | .parent_names = (const char *[]){ | |
1544 | "blsp1_qup4_spi_apps_clk_src", | |
1545 | }, | |
1546 | .num_parents = 1, | |
1547 | .flags = CLK_SET_RATE_PARENT, | |
1548 | .ops = &clk_branch2_ops, | |
1549 | }, | |
1550 | }, | |
1551 | }; | |
1552 | ||
1553 | static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { | |
1554 | .halt_reg = 0x0848, | |
1555 | .clkr = { | |
1556 | .enable_reg = 0x0848, | |
1557 | .enable_mask = BIT(0), | |
1558 | .hw.init = &(struct clk_init_data){ | |
1559 | .name = "gcc_blsp1_qup5_i2c_apps_clk", | |
1560 | .parent_names = (const char *[]){ | |
1561 | "blsp1_qup5_i2c_apps_clk_src", | |
1562 | }, | |
1563 | .num_parents = 1, | |
1564 | .flags = CLK_SET_RATE_PARENT, | |
1565 | .ops = &clk_branch2_ops, | |
1566 | }, | |
1567 | }, | |
1568 | }; | |
1569 | ||
1570 | static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { | |
1571 | .halt_reg = 0x0844, | |
1572 | .clkr = { | |
1573 | .enable_reg = 0x0844, | |
1574 | .enable_mask = BIT(0), | |
1575 | .hw.init = &(struct clk_init_data){ | |
1576 | .name = "gcc_blsp1_qup5_spi_apps_clk", | |
1577 | .parent_names = (const char *[]){ | |
1578 | "blsp1_qup5_spi_apps_clk_src", | |
1579 | }, | |
1580 | .num_parents = 1, | |
1581 | .flags = CLK_SET_RATE_PARENT, | |
1582 | .ops = &clk_branch2_ops, | |
1583 | }, | |
1584 | }, | |
1585 | }; | |
1586 | ||
1587 | static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { | |
1588 | .halt_reg = 0x08c8, | |
1589 | .clkr = { | |
1590 | .enable_reg = 0x08c8, | |
1591 | .enable_mask = BIT(0), | |
1592 | .hw.init = &(struct clk_init_data){ | |
1593 | .name = "gcc_blsp1_qup6_i2c_apps_clk", | |
1594 | .parent_names = (const char *[]){ | |
1595 | "blsp1_qup6_i2c_apps_clk_src", | |
1596 | }, | |
1597 | .num_parents = 1, | |
1598 | .flags = CLK_SET_RATE_PARENT, | |
1599 | .ops = &clk_branch2_ops, | |
1600 | }, | |
1601 | }, | |
1602 | }; | |
1603 | ||
1604 | static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { | |
1605 | .halt_reg = 0x08c4, | |
1606 | .clkr = { | |
1607 | .enable_reg = 0x08c4, | |
1608 | .enable_mask = BIT(0), | |
1609 | .hw.init = &(struct clk_init_data){ | |
1610 | .name = "gcc_blsp1_qup6_spi_apps_clk", | |
1611 | .parent_names = (const char *[]){ | |
1612 | "blsp1_qup6_spi_apps_clk_src", | |
1613 | }, | |
1614 | .num_parents = 1, | |
1615 | .flags = CLK_SET_RATE_PARENT, | |
1616 | .ops = &clk_branch2_ops, | |
1617 | }, | |
1618 | }, | |
1619 | }; | |
1620 | ||
1621 | static struct clk_branch gcc_blsp1_uart1_apps_clk = { | |
1622 | .halt_reg = 0x0684, | |
1623 | .clkr = { | |
1624 | .enable_reg = 0x0684, | |
1625 | .enable_mask = BIT(0), | |
1626 | .hw.init = &(struct clk_init_data){ | |
1627 | .name = "gcc_blsp1_uart1_apps_clk", | |
1628 | .parent_names = (const char *[]){ | |
1629 | "blsp1_uart1_apps_clk_src", | |
1630 | }, | |
1631 | .num_parents = 1, | |
1632 | .flags = CLK_SET_RATE_PARENT, | |
1633 | .ops = &clk_branch2_ops, | |
1634 | }, | |
1635 | }, | |
1636 | }; | |
1637 | ||
1638 | static struct clk_branch gcc_blsp1_uart2_apps_clk = { | |
1639 | .halt_reg = 0x0704, | |
1640 | .clkr = { | |
1641 | .enable_reg = 0x0704, | |
1642 | .enable_mask = BIT(0), | |
1643 | .hw.init = &(struct clk_init_data){ | |
1644 | .name = "gcc_blsp1_uart2_apps_clk", | |
1645 | .parent_names = (const char *[]){ | |
1646 | "blsp1_uart2_apps_clk_src", | |
1647 | }, | |
1648 | .num_parents = 1, | |
1649 | .flags = CLK_SET_RATE_PARENT, | |
1650 | .ops = &clk_branch2_ops, | |
1651 | }, | |
1652 | }, | |
1653 | }; | |
1654 | ||
1655 | static struct clk_branch gcc_blsp1_uart3_apps_clk = { | |
1656 | .halt_reg = 0x0784, | |
1657 | .clkr = { | |
1658 | .enable_reg = 0x0784, | |
1659 | .enable_mask = BIT(0), | |
1660 | .hw.init = &(struct clk_init_data){ | |
1661 | .name = "gcc_blsp1_uart3_apps_clk", | |
1662 | .parent_names = (const char *[]){ | |
1663 | "blsp1_uart3_apps_clk_src", | |
1664 | }, | |
1665 | .num_parents = 1, | |
1666 | .flags = CLK_SET_RATE_PARENT, | |
1667 | .ops = &clk_branch2_ops, | |
1668 | }, | |
1669 | }, | |
1670 | }; | |
1671 | ||
1672 | static struct clk_branch gcc_blsp1_uart4_apps_clk = { | |
1673 | .halt_reg = 0x0804, | |
1674 | .clkr = { | |
1675 | .enable_reg = 0x0804, | |
1676 | .enable_mask = BIT(0), | |
1677 | .hw.init = &(struct clk_init_data){ | |
1678 | .name = "gcc_blsp1_uart4_apps_clk", | |
1679 | .parent_names = (const char *[]){ | |
1680 | "blsp1_uart4_apps_clk_src", | |
1681 | }, | |
1682 | .num_parents = 1, | |
1683 | .flags = CLK_SET_RATE_PARENT, | |
1684 | .ops = &clk_branch2_ops, | |
1685 | }, | |
1686 | }, | |
1687 | }; | |
1688 | ||
1689 | static struct clk_branch gcc_blsp1_uart5_apps_clk = { | |
1690 | .halt_reg = 0x0884, | |
1691 | .clkr = { | |
1692 | .enable_reg = 0x0884, | |
1693 | .enable_mask = BIT(0), | |
1694 | .hw.init = &(struct clk_init_data){ | |
1695 | .name = "gcc_blsp1_uart5_apps_clk", | |
1696 | .parent_names = (const char *[]){ | |
1697 | "blsp1_uart5_apps_clk_src", | |
1698 | }, | |
1699 | .num_parents = 1, | |
1700 | .flags = CLK_SET_RATE_PARENT, | |
1701 | .ops = &clk_branch2_ops, | |
1702 | }, | |
1703 | }, | |
1704 | }; | |
1705 | ||
1706 | static struct clk_branch gcc_blsp1_uart6_apps_clk = { | |
1707 | .halt_reg = 0x0904, | |
1708 | .clkr = { | |
1709 | .enable_reg = 0x0904, | |
1710 | .enable_mask = BIT(0), | |
1711 | .hw.init = &(struct clk_init_data){ | |
1712 | .name = "gcc_blsp1_uart6_apps_clk", | |
1713 | .parent_names = (const char *[]){ | |
1714 | "blsp1_uart6_apps_clk_src", | |
1715 | }, | |
1716 | .num_parents = 1, | |
1717 | .flags = CLK_SET_RATE_PARENT, | |
1718 | .ops = &clk_branch2_ops, | |
1719 | }, | |
1720 | }, | |
1721 | }; | |
1722 | ||
1723 | static struct clk_branch gcc_blsp2_ahb_clk = { | |
1724 | .halt_reg = 0x0944, | |
1725 | .halt_check = BRANCH_HALT_VOTED, | |
1726 | .clkr = { | |
1727 | .enable_reg = 0x1484, | |
1728 | .enable_mask = BIT(15), | |
1729 | .hw.init = &(struct clk_init_data){ | |
1730 | .name = "gcc_blsp2_ahb_clk", | |
1731 | .parent_names = (const char *[]){ | |
1732 | "periph_noc_clk_src", | |
1733 | }, | |
1734 | .num_parents = 1, | |
1735 | .ops = &clk_branch2_ops, | |
1736 | }, | |
1737 | }, | |
1738 | }; | |
1739 | ||
1740 | static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { | |
1741 | .halt_reg = 0x0988, | |
1742 | .clkr = { | |
1743 | .enable_reg = 0x0988, | |
1744 | .enable_mask = BIT(0), | |
1745 | .hw.init = &(struct clk_init_data){ | |
1746 | .name = "gcc_blsp2_qup1_i2c_apps_clk", | |
1747 | .parent_names = (const char *[]){ | |
1748 | "blsp2_qup1_i2c_apps_clk_src", | |
1749 | }, | |
1750 | .num_parents = 1, | |
1751 | .flags = CLK_SET_RATE_PARENT, | |
1752 | .ops = &clk_branch2_ops, | |
1753 | }, | |
1754 | }, | |
1755 | }; | |
1756 | ||
1757 | static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { | |
1758 | .halt_reg = 0x0984, | |
1759 | .clkr = { | |
1760 | .enable_reg = 0x0984, | |
1761 | .enable_mask = BIT(0), | |
1762 | .hw.init = &(struct clk_init_data){ | |
1763 | .name = "gcc_blsp2_qup1_spi_apps_clk", | |
1764 | .parent_names = (const char *[]){ | |
1765 | "blsp2_qup1_spi_apps_clk_src", | |
1766 | }, | |
1767 | .num_parents = 1, | |
1768 | .flags = CLK_SET_RATE_PARENT, | |
1769 | .ops = &clk_branch2_ops, | |
1770 | }, | |
1771 | }, | |
1772 | }; | |
1773 | ||
1774 | static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { | |
1775 | .halt_reg = 0x0a08, | |
1776 | .clkr = { | |
1777 | .enable_reg = 0x0a08, | |
1778 | .enable_mask = BIT(0), | |
1779 | .hw.init = &(struct clk_init_data){ | |
1780 | .name = "gcc_blsp2_qup2_i2c_apps_clk", | |
1781 | .parent_names = (const char *[]){ | |
1782 | "blsp2_qup2_i2c_apps_clk_src", | |
1783 | }, | |
1784 | .num_parents = 1, | |
1785 | .flags = CLK_SET_RATE_PARENT, | |
1786 | .ops = &clk_branch2_ops, | |
1787 | }, | |
1788 | }, | |
1789 | }; | |
1790 | ||
1791 | static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { | |
1792 | .halt_reg = 0x0a04, | |
1793 | .clkr = { | |
1794 | .enable_reg = 0x0a04, | |
1795 | .enable_mask = BIT(0), | |
1796 | .hw.init = &(struct clk_init_data){ | |
1797 | .name = "gcc_blsp2_qup2_spi_apps_clk", | |
1798 | .parent_names = (const char *[]){ | |
1799 | "blsp2_qup2_spi_apps_clk_src", | |
1800 | }, | |
1801 | .num_parents = 1, | |
1802 | .flags = CLK_SET_RATE_PARENT, | |
1803 | .ops = &clk_branch2_ops, | |
1804 | }, | |
1805 | }, | |
1806 | }; | |
1807 | ||
1808 | static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { | |
1809 | .halt_reg = 0x0a88, | |
1810 | .clkr = { | |
1811 | .enable_reg = 0x0a88, | |
1812 | .enable_mask = BIT(0), | |
1813 | .hw.init = &(struct clk_init_data){ | |
1814 | .name = "gcc_blsp2_qup3_i2c_apps_clk", | |
1815 | .parent_names = (const char *[]){ | |
1816 | "blsp2_qup3_i2c_apps_clk_src", | |
1817 | }, | |
1818 | .num_parents = 1, | |
1819 | .flags = CLK_SET_RATE_PARENT, | |
1820 | .ops = &clk_branch2_ops, | |
1821 | }, | |
1822 | }, | |
1823 | }; | |
1824 | ||
1825 | static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { | |
1826 | .halt_reg = 0x0a84, | |
1827 | .clkr = { | |
1828 | .enable_reg = 0x0a84, | |
1829 | .enable_mask = BIT(0), | |
1830 | .hw.init = &(struct clk_init_data){ | |
1831 | .name = "gcc_blsp2_qup3_spi_apps_clk", | |
1832 | .parent_names = (const char *[]){ | |
1833 | "blsp2_qup3_spi_apps_clk_src", | |
1834 | }, | |
1835 | .num_parents = 1, | |
1836 | .flags = CLK_SET_RATE_PARENT, | |
1837 | .ops = &clk_branch2_ops, | |
1838 | }, | |
1839 | }, | |
1840 | }; | |
1841 | ||
1842 | static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { | |
1843 | .halt_reg = 0x0b08, | |
1844 | .clkr = { | |
1845 | .enable_reg = 0x0b08, | |
1846 | .enable_mask = BIT(0), | |
1847 | .hw.init = &(struct clk_init_data){ | |
1848 | .name = "gcc_blsp2_qup4_i2c_apps_clk", | |
1849 | .parent_names = (const char *[]){ | |
1850 | "blsp2_qup4_i2c_apps_clk_src", | |
1851 | }, | |
1852 | .num_parents = 1, | |
1853 | .flags = CLK_SET_RATE_PARENT, | |
1854 | .ops = &clk_branch2_ops, | |
1855 | }, | |
1856 | }, | |
1857 | }; | |
1858 | ||
1859 | static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { | |
1860 | .halt_reg = 0x0b04, | |
1861 | .clkr = { | |
1862 | .enable_reg = 0x0b04, | |
1863 | .enable_mask = BIT(0), | |
1864 | .hw.init = &(struct clk_init_data){ | |
1865 | .name = "gcc_blsp2_qup4_spi_apps_clk", | |
1866 | .parent_names = (const char *[]){ | |
1867 | "blsp2_qup4_spi_apps_clk_src", | |
1868 | }, | |
1869 | .num_parents = 1, | |
1870 | .flags = CLK_SET_RATE_PARENT, | |
1871 | .ops = &clk_branch2_ops, | |
1872 | }, | |
1873 | }, | |
1874 | }; | |
1875 | ||
1876 | static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = { | |
1877 | .halt_reg = 0x0b88, | |
1878 | .clkr = { | |
1879 | .enable_reg = 0x0b88, | |
1880 | .enable_mask = BIT(0), | |
1881 | .hw.init = &(struct clk_init_data){ | |
1882 | .name = "gcc_blsp2_qup5_i2c_apps_clk", | |
1883 | .parent_names = (const char *[]){ | |
1884 | "blsp2_qup5_i2c_apps_clk_src", | |
1885 | }, | |
1886 | .num_parents = 1, | |
1887 | .flags = CLK_SET_RATE_PARENT, | |
1888 | .ops = &clk_branch2_ops, | |
1889 | }, | |
1890 | }, | |
1891 | }; | |
1892 | ||
1893 | static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = { | |
1894 | .halt_reg = 0x0b84, | |
1895 | .clkr = { | |
1896 | .enable_reg = 0x0b84, | |
1897 | .enable_mask = BIT(0), | |
1898 | .hw.init = &(struct clk_init_data){ | |
1899 | .name = "gcc_blsp2_qup5_spi_apps_clk", | |
1900 | .parent_names = (const char *[]){ | |
1901 | "blsp2_qup5_spi_apps_clk_src", | |
1902 | }, | |
1903 | .num_parents = 1, | |
1904 | .flags = CLK_SET_RATE_PARENT, | |
1905 | .ops = &clk_branch2_ops, | |
1906 | }, | |
1907 | }, | |
1908 | }; | |
1909 | ||
1910 | static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = { | |
1911 | .halt_reg = 0x0c08, | |
1912 | .clkr = { | |
1913 | .enable_reg = 0x0c08, | |
1914 | .enable_mask = BIT(0), | |
1915 | .hw.init = &(struct clk_init_data){ | |
1916 | .name = "gcc_blsp2_qup6_i2c_apps_clk", | |
1917 | .parent_names = (const char *[]){ | |
1918 | "blsp2_qup6_i2c_apps_clk_src", | |
1919 | }, | |
1920 | .num_parents = 1, | |
1921 | .flags = CLK_SET_RATE_PARENT, | |
1922 | .ops = &clk_branch2_ops, | |
1923 | }, | |
1924 | }, | |
1925 | }; | |
1926 | ||
1927 | static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = { | |
1928 | .halt_reg = 0x0c04, | |
1929 | .clkr = { | |
1930 | .enable_reg = 0x0c04, | |
1931 | .enable_mask = BIT(0), | |
1932 | .hw.init = &(struct clk_init_data){ | |
1933 | .name = "gcc_blsp2_qup6_spi_apps_clk", | |
1934 | .parent_names = (const char *[]){ | |
1935 | "blsp2_qup6_spi_apps_clk_src", | |
1936 | }, | |
1937 | .num_parents = 1, | |
1938 | .flags = CLK_SET_RATE_PARENT, | |
1939 | .ops = &clk_branch2_ops, | |
1940 | }, | |
1941 | }, | |
1942 | }; | |
1943 | ||
1944 | static struct clk_branch gcc_blsp2_uart1_apps_clk = { | |
1945 | .halt_reg = 0x09c4, | |
1946 | .clkr = { | |
1947 | .enable_reg = 0x09c4, | |
1948 | .enable_mask = BIT(0), | |
1949 | .hw.init = &(struct clk_init_data){ | |
1950 | .name = "gcc_blsp2_uart1_apps_clk", | |
1951 | .parent_names = (const char *[]){ | |
1952 | "blsp2_uart1_apps_clk_src", | |
1953 | }, | |
1954 | .num_parents = 1, | |
1955 | .flags = CLK_SET_RATE_PARENT, | |
1956 | .ops = &clk_branch2_ops, | |
1957 | }, | |
1958 | }, | |
1959 | }; | |
1960 | ||
1961 | static struct clk_branch gcc_blsp2_uart2_apps_clk = { | |
1962 | .halt_reg = 0x0a44, | |
1963 | .clkr = { | |
1964 | .enable_reg = 0x0a44, | |
1965 | .enable_mask = BIT(0), | |
1966 | .hw.init = &(struct clk_init_data){ | |
1967 | .name = "gcc_blsp2_uart2_apps_clk", | |
1968 | .parent_names = (const char *[]){ | |
1969 | "blsp2_uart2_apps_clk_src", | |
1970 | }, | |
1971 | .num_parents = 1, | |
1972 | .flags = CLK_SET_RATE_PARENT, | |
1973 | .ops = &clk_branch2_ops, | |
1974 | }, | |
1975 | }, | |
1976 | }; | |
1977 | ||
1978 | static struct clk_branch gcc_blsp2_uart3_apps_clk = { | |
1979 | .halt_reg = 0x0ac4, | |
1980 | .clkr = { | |
1981 | .enable_reg = 0x0ac4, | |
1982 | .enable_mask = BIT(0), | |
1983 | .hw.init = &(struct clk_init_data){ | |
1984 | .name = "gcc_blsp2_uart3_apps_clk", | |
1985 | .parent_names = (const char *[]){ | |
1986 | "blsp2_uart3_apps_clk_src", | |
1987 | }, | |
1988 | .num_parents = 1, | |
1989 | .flags = CLK_SET_RATE_PARENT, | |
1990 | .ops = &clk_branch2_ops, | |
1991 | }, | |
1992 | }, | |
1993 | }; | |
1994 | ||
1995 | static struct clk_branch gcc_blsp2_uart4_apps_clk = { | |
1996 | .halt_reg = 0x0b44, | |
1997 | .clkr = { | |
1998 | .enable_reg = 0x0b44, | |
1999 | .enable_mask = BIT(0), | |
2000 | .hw.init = &(struct clk_init_data){ | |
2001 | .name = "gcc_blsp2_uart4_apps_clk", | |
2002 | .parent_names = (const char *[]){ | |
2003 | "blsp2_uart4_apps_clk_src", | |
2004 | }, | |
2005 | .num_parents = 1, | |
2006 | .flags = CLK_SET_RATE_PARENT, | |
2007 | .ops = &clk_branch2_ops, | |
2008 | }, | |
2009 | }, | |
2010 | }; | |
2011 | ||
2012 | static struct clk_branch gcc_blsp2_uart5_apps_clk = { | |
2013 | .halt_reg = 0x0bc4, | |
2014 | .clkr = { | |
2015 | .enable_reg = 0x0bc4, | |
2016 | .enable_mask = BIT(0), | |
2017 | .hw.init = &(struct clk_init_data){ | |
2018 | .name = "gcc_blsp2_uart5_apps_clk", | |
2019 | .parent_names = (const char *[]){ | |
2020 | "blsp2_uart5_apps_clk_src", | |
2021 | }, | |
2022 | .num_parents = 1, | |
2023 | .flags = CLK_SET_RATE_PARENT, | |
2024 | .ops = &clk_branch2_ops, | |
2025 | }, | |
2026 | }, | |
2027 | }; | |
2028 | ||
2029 | static struct clk_branch gcc_blsp2_uart6_apps_clk = { | |
2030 | .halt_reg = 0x0c44, | |
2031 | .clkr = { | |
2032 | .enable_reg = 0x0c44, | |
2033 | .enable_mask = BIT(0), | |
2034 | .hw.init = &(struct clk_init_data){ | |
2035 | .name = "gcc_blsp2_uart6_apps_clk", | |
2036 | .parent_names = (const char *[]){ | |
2037 | "blsp2_uart6_apps_clk_src", | |
2038 | }, | |
2039 | .num_parents = 1, | |
2040 | .flags = CLK_SET_RATE_PARENT, | |
2041 | .ops = &clk_branch2_ops, | |
2042 | }, | |
2043 | }, | |
2044 | }; | |
2045 | ||
2046 | static struct clk_branch gcc_boot_rom_ahb_clk = { | |
2047 | .halt_reg = 0x0e04, | |
2048 | .halt_check = BRANCH_HALT_VOTED, | |
2049 | .clkr = { | |
2050 | .enable_reg = 0x1484, | |
2051 | .enable_mask = BIT(10), | |
2052 | .hw.init = &(struct clk_init_data){ | |
2053 | .name = "gcc_boot_rom_ahb_clk", | |
2054 | .parent_names = (const char *[]){ | |
2055 | "config_noc_clk_src", | |
2056 | }, | |
2057 | .num_parents = 1, | |
2058 | .ops = &clk_branch2_ops, | |
2059 | }, | |
2060 | }, | |
2061 | }; | |
2062 | ||
2063 | static struct clk_branch gcc_ce1_ahb_clk = { | |
2064 | .halt_reg = 0x104c, | |
2065 | .halt_check = BRANCH_HALT_VOTED, | |
2066 | .clkr = { | |
2067 | .enable_reg = 0x1484, | |
2068 | .enable_mask = BIT(3), | |
2069 | .hw.init = &(struct clk_init_data){ | |
2070 | .name = "gcc_ce1_ahb_clk", | |
2071 | .parent_names = (const char *[]){ | |
2072 | "config_noc_clk_src", | |
2073 | }, | |
2074 | .num_parents = 1, | |
2075 | .ops = &clk_branch2_ops, | |
2076 | }, | |
2077 | }, | |
2078 | }; | |
2079 | ||
2080 | static struct clk_branch gcc_ce1_axi_clk = { | |
2081 | .halt_reg = 0x1048, | |
2082 | .halt_check = BRANCH_HALT_VOTED, | |
2083 | .clkr = { | |
2084 | .enable_reg = 0x1484, | |
2085 | .enable_mask = BIT(4), | |
2086 | .hw.init = &(struct clk_init_data){ | |
2087 | .name = "gcc_ce1_axi_clk", | |
2088 | .parent_names = (const char *[]){ | |
2089 | "system_noc_clk_src", | |
2090 | }, | |
2091 | .num_parents = 1, | |
2092 | .ops = &clk_branch2_ops, | |
2093 | }, | |
2094 | }, | |
2095 | }; | |
2096 | ||
2097 | static struct clk_branch gcc_ce1_clk = { | |
2098 | .halt_reg = 0x1050, | |
2099 | .halt_check = BRANCH_HALT_VOTED, | |
2100 | .clkr = { | |
2101 | .enable_reg = 0x1484, | |
2102 | .enable_mask = BIT(5), | |
2103 | .hw.init = &(struct clk_init_data){ | |
2104 | .name = "gcc_ce1_clk", | |
2105 | .parent_names = (const char *[]){ | |
2106 | "ce1_clk_src", | |
2107 | }, | |
2108 | .num_parents = 1, | |
d7a304e9 | 2109 | .flags = CLK_SET_RATE_PARENT, |
02824653 GD |
2110 | .ops = &clk_branch2_ops, |
2111 | }, | |
2112 | }, | |
2113 | }; | |
2114 | ||
2115 | static struct clk_branch gcc_ce2_ahb_clk = { | |
2116 | .halt_reg = 0x108c, | |
2117 | .halt_check = BRANCH_HALT_VOTED, | |
2118 | .clkr = { | |
2119 | .enable_reg = 0x1484, | |
2120 | .enable_mask = BIT(0), | |
2121 | .hw.init = &(struct clk_init_data){ | |
2122 | .name = "gcc_ce2_ahb_clk", | |
2123 | .parent_names = (const char *[]){ | |
2124 | "config_noc_clk_src", | |
2125 | }, | |
2126 | .num_parents = 1, | |
2127 | .ops = &clk_branch2_ops, | |
2128 | }, | |
2129 | }, | |
2130 | }; | |
2131 | ||
2132 | static struct clk_branch gcc_ce2_axi_clk = { | |
2133 | .halt_reg = 0x1088, | |
2134 | .halt_check = BRANCH_HALT_VOTED, | |
2135 | .clkr = { | |
2136 | .enable_reg = 0x1484, | |
2137 | .enable_mask = BIT(1), | |
2138 | .hw.init = &(struct clk_init_data){ | |
2139 | .name = "gcc_ce2_axi_clk", | |
2140 | .parent_names = (const char *[]){ | |
2141 | "system_noc_clk_src", | |
2142 | }, | |
2143 | .num_parents = 1, | |
2144 | .ops = &clk_branch2_ops, | |
2145 | }, | |
2146 | }, | |
2147 | }; | |
2148 | ||
2149 | static struct clk_branch gcc_ce2_clk = { | |
2150 | .halt_reg = 0x1090, | |
2151 | .halt_check = BRANCH_HALT_VOTED, | |
2152 | .clkr = { | |
2153 | .enable_reg = 0x1484, | |
2154 | .enable_mask = BIT(2), | |
2155 | .hw.init = &(struct clk_init_data){ | |
2156 | .name = "gcc_ce2_clk", | |
2157 | .parent_names = (const char *[]){ | |
2158 | "ce2_clk_src", | |
2159 | }, | |
2160 | .num_parents = 1, | |
2161 | .flags = CLK_SET_RATE_PARENT, | |
2162 | .ops = &clk_branch2_ops, | |
2163 | }, | |
2164 | }, | |
2165 | }; | |
2166 | ||
2167 | static struct clk_branch gcc_ce3_ahb_clk = { | |
2168 | .halt_reg = 0x1d0c, | |
2169 | .halt_check = BRANCH_HALT_VOTED, | |
2170 | .clkr = { | |
2171 | .enable_reg = 0x1d0c, | |
2172 | .enable_mask = BIT(0), | |
2173 | .hw.init = &(struct clk_init_data){ | |
2174 | .name = "gcc_ce3_ahb_clk", | |
2175 | .parent_names = (const char *[]){ | |
2176 | "config_noc_clk_src", | |
2177 | }, | |
2178 | .num_parents = 1, | |
2179 | .ops = &clk_branch2_ops, | |
2180 | }, | |
2181 | }, | |
2182 | }; | |
2183 | ||
2184 | static struct clk_branch gcc_ce3_axi_clk = { | |
2185 | .halt_reg = 0x1088, | |
2186 | .halt_check = BRANCH_HALT_VOTED, | |
2187 | .clkr = { | |
2188 | .enable_reg = 0x1d08, | |
2189 | .enable_mask = BIT(0), | |
2190 | .hw.init = &(struct clk_init_data){ | |
2191 | .name = "gcc_ce3_axi_clk", | |
2192 | .parent_names = (const char *[]){ | |
2193 | "system_noc_clk_src", | |
2194 | }, | |
2195 | .num_parents = 1, | |
2196 | .ops = &clk_branch2_ops, | |
2197 | }, | |
2198 | }, | |
2199 | }; | |
2200 | ||
2201 | static struct clk_branch gcc_ce3_clk = { | |
2202 | .halt_reg = 0x1090, | |
2203 | .halt_check = BRANCH_HALT_VOTED, | |
2204 | .clkr = { | |
2205 | .enable_reg = 0x1d04, | |
2206 | .enable_mask = BIT(0), | |
2207 | .hw.init = &(struct clk_init_data){ | |
2208 | .name = "gcc_ce3_clk", | |
2209 | .parent_names = (const char *[]){ | |
2210 | "ce3_clk_src", | |
2211 | }, | |
2212 | .num_parents = 1, | |
2213 | .flags = CLK_SET_RATE_PARENT, | |
2214 | .ops = &clk_branch2_ops, | |
2215 | }, | |
2216 | }, | |
2217 | }; | |
2218 | ||
2219 | static struct clk_branch gcc_gp1_clk = { | |
2220 | .halt_reg = 0x1900, | |
2221 | .clkr = { | |
2222 | .enable_reg = 0x1900, | |
2223 | .enable_mask = BIT(0), | |
2224 | .hw.init = &(struct clk_init_data){ | |
2225 | .name = "gcc_gp1_clk", | |
2226 | .parent_names = (const char *[]){ | |
2227 | "gp1_clk_src", | |
2228 | }, | |
2229 | .num_parents = 1, | |
2230 | .flags = CLK_SET_RATE_PARENT, | |
2231 | .ops = &clk_branch2_ops, | |
2232 | }, | |
2233 | }, | |
2234 | }; | |
2235 | ||
2236 | static struct clk_branch gcc_gp2_clk = { | |
2237 | .halt_reg = 0x1940, | |
2238 | .clkr = { | |
2239 | .enable_reg = 0x1940, | |
2240 | .enable_mask = BIT(0), | |
2241 | .hw.init = &(struct clk_init_data){ | |
2242 | .name = "gcc_gp2_clk", | |
2243 | .parent_names = (const char *[]){ | |
2244 | "gp2_clk_src", | |
2245 | }, | |
2246 | .num_parents = 1, | |
2247 | .flags = CLK_SET_RATE_PARENT, | |
2248 | .ops = &clk_branch2_ops, | |
2249 | }, | |
2250 | }, | |
2251 | }; | |
2252 | ||
2253 | static struct clk_branch gcc_gp3_clk = { | |
2254 | .halt_reg = 0x1980, | |
2255 | .clkr = { | |
2256 | .enable_reg = 0x1980, | |
2257 | .enable_mask = BIT(0), | |
2258 | .hw.init = &(struct clk_init_data){ | |
2259 | .name = "gcc_gp3_clk", | |
2260 | .parent_names = (const char *[]){ | |
2261 | "gp3_clk_src", | |
2262 | }, | |
2263 | .num_parents = 1, | |
2264 | .flags = CLK_SET_RATE_PARENT, | |
2265 | .ops = &clk_branch2_ops, | |
2266 | }, | |
2267 | }, | |
2268 | }; | |
2269 | ||
2270 | static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = { | |
2271 | .halt_reg = 0x0248, | |
2272 | .clkr = { | |
2273 | .enable_reg = 0x0248, | |
2274 | .enable_mask = BIT(0), | |
2275 | .hw.init = &(struct clk_init_data){ | |
2276 | .name = "gcc_ocmem_noc_cfg_ahb_clk", | |
2277 | .parent_names = (const char *[]){ | |
2278 | "config_noc_clk_src", | |
2279 | }, | |
2280 | .num_parents = 1, | |
2281 | .ops = &clk_branch2_ops, | |
2282 | }, | |
2283 | }, | |
2284 | }; | |
2285 | ||
5424e102 GD |
2286 | static struct clk_branch gcc_pcie_0_aux_clk = { |
2287 | .halt_reg = 0x1b10, | |
2288 | .clkr = { | |
2289 | .enable_reg = 0x1b10, | |
2290 | .enable_mask = BIT(0), | |
2291 | .hw.init = &(struct clk_init_data){ | |
2292 | .name = "gcc_pcie_0_aux_clk", | |
2293 | .parent_names = (const char *[]){ | |
2294 | "pcie_0_aux_clk_src", | |
2295 | }, | |
2296 | .num_parents = 1, | |
2297 | .flags = CLK_SET_RATE_PARENT, | |
2298 | .ops = &clk_branch2_ops, | |
2299 | }, | |
2300 | }, | |
2301 | }; | |
2302 | ||
2303 | static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { | |
2304 | .halt_reg = 0x1b0c, | |
2305 | .clkr = { | |
2306 | .enable_reg = 0x1b0c, | |
2307 | .enable_mask = BIT(0), | |
2308 | .hw.init = &(struct clk_init_data){ | |
2309 | .name = "gcc_pcie_0_cfg_ahb_clk", | |
2310 | .parent_names = (const char *[]){ | |
2311 | "config_noc_clk_src", | |
2312 | }, | |
2313 | .num_parents = 1, | |
2314 | .flags = CLK_SET_RATE_PARENT, | |
2315 | .ops = &clk_branch2_ops, | |
2316 | }, | |
2317 | }, | |
2318 | }; | |
2319 | ||
2320 | static struct clk_branch gcc_pcie_0_mstr_axi_clk = { | |
2321 | .halt_reg = 0x1b08, | |
2322 | .clkr = { | |
2323 | .enable_reg = 0x1b08, | |
2324 | .enable_mask = BIT(0), | |
2325 | .hw.init = &(struct clk_init_data){ | |
2326 | .name = "gcc_pcie_0_mstr_axi_clk", | |
2327 | .parent_names = (const char *[]){ | |
2328 | "config_noc_clk_src", | |
2329 | }, | |
2330 | .num_parents = 1, | |
2331 | .flags = CLK_SET_RATE_PARENT, | |
2332 | .ops = &clk_branch2_ops, | |
2333 | }, | |
2334 | }, | |
2335 | }; | |
2336 | ||
2337 | static struct clk_branch gcc_pcie_0_pipe_clk = { | |
2338 | .halt_reg = 0x1b14, | |
2339 | .clkr = { | |
2340 | .enable_reg = 0x1b14, | |
2341 | .enable_mask = BIT(0), | |
2342 | .hw.init = &(struct clk_init_data){ | |
2343 | .name = "gcc_pcie_0_pipe_clk", | |
2344 | .parent_names = (const char *[]){ | |
2345 | "pcie_0_pipe_clk_src", | |
2346 | }, | |
2347 | .num_parents = 1, | |
2348 | .flags = CLK_SET_RATE_PARENT, | |
2349 | .ops = &clk_branch2_ops, | |
2350 | }, | |
2351 | }, | |
2352 | }; | |
2353 | ||
2354 | static struct clk_branch gcc_pcie_0_slv_axi_clk = { | |
2355 | .halt_reg = 0x1b04, | |
2356 | .clkr = { | |
2357 | .enable_reg = 0x1b04, | |
2358 | .enable_mask = BIT(0), | |
2359 | .hw.init = &(struct clk_init_data){ | |
2360 | .name = "gcc_pcie_0_slv_axi_clk", | |
2361 | .parent_names = (const char *[]){ | |
2362 | "config_noc_clk_src", | |
2363 | }, | |
2364 | .num_parents = 1, | |
2365 | .flags = CLK_SET_RATE_PARENT, | |
2366 | .ops = &clk_branch2_ops, | |
2367 | }, | |
2368 | }, | |
2369 | }; | |
2370 | ||
2371 | static struct clk_branch gcc_pcie_1_aux_clk = { | |
2372 | .halt_reg = 0x1b90, | |
2373 | .clkr = { | |
2374 | .enable_reg = 0x1b90, | |
2375 | .enable_mask = BIT(0), | |
2376 | .hw.init = &(struct clk_init_data){ | |
2377 | .name = "gcc_pcie_1_aux_clk", | |
2378 | .parent_names = (const char *[]){ | |
2379 | "pcie_1_aux_clk_src", | |
2380 | }, | |
2381 | .num_parents = 1, | |
2382 | .flags = CLK_SET_RATE_PARENT, | |
2383 | .ops = &clk_branch2_ops, | |
2384 | }, | |
2385 | }, | |
2386 | }; | |
2387 | ||
2388 | static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { | |
2389 | .halt_reg = 0x1b8c, | |
2390 | .clkr = { | |
2391 | .enable_reg = 0x1b8c, | |
2392 | .enable_mask = BIT(0), | |
2393 | .hw.init = &(struct clk_init_data){ | |
2394 | .name = "gcc_pcie_1_cfg_ahb_clk", | |
2395 | .parent_names = (const char *[]){ | |
2396 | "config_noc_clk_src", | |
2397 | }, | |
2398 | .num_parents = 1, | |
2399 | .flags = CLK_SET_RATE_PARENT, | |
2400 | .ops = &clk_branch2_ops, | |
2401 | }, | |
2402 | }, | |
2403 | }; | |
2404 | ||
2405 | static struct clk_branch gcc_pcie_1_mstr_axi_clk = { | |
2406 | .halt_reg = 0x1b88, | |
2407 | .clkr = { | |
2408 | .enable_reg = 0x1b88, | |
2409 | .enable_mask = BIT(0), | |
2410 | .hw.init = &(struct clk_init_data){ | |
2411 | .name = "gcc_pcie_1_mstr_axi_clk", | |
2412 | .parent_names = (const char *[]){ | |
2413 | "config_noc_clk_src", | |
2414 | }, | |
2415 | .num_parents = 1, | |
2416 | .flags = CLK_SET_RATE_PARENT, | |
2417 | .ops = &clk_branch2_ops, | |
2418 | }, | |
2419 | }, | |
2420 | }; | |
2421 | ||
2422 | static struct clk_branch gcc_pcie_1_pipe_clk = { | |
2423 | .halt_reg = 0x1b94, | |
2424 | .clkr = { | |
2425 | .enable_reg = 0x1b94, | |
2426 | .enable_mask = BIT(0), | |
2427 | .hw.init = &(struct clk_init_data){ | |
2428 | .name = "gcc_pcie_1_pipe_clk", | |
2429 | .parent_names = (const char *[]){ | |
2430 | "pcie_1_pipe_clk_src", | |
2431 | }, | |
2432 | .num_parents = 1, | |
2433 | .flags = CLK_SET_RATE_PARENT, | |
2434 | .ops = &clk_branch2_ops, | |
2435 | }, | |
2436 | }, | |
2437 | }; | |
2438 | ||
2439 | static struct clk_branch gcc_pcie_1_slv_axi_clk = { | |
2440 | .halt_reg = 0x1b84, | |
2441 | .clkr = { | |
2442 | .enable_reg = 0x1b84, | |
2443 | .enable_mask = BIT(0), | |
2444 | .hw.init = &(struct clk_init_data){ | |
2445 | .name = "gcc_pcie_1_slv_axi_clk", | |
2446 | .parent_names = (const char *[]){ | |
2447 | "config_noc_clk_src", | |
2448 | }, | |
2449 | .num_parents = 1, | |
2450 | .flags = CLK_SET_RATE_PARENT, | |
2451 | .ops = &clk_branch2_ops, | |
2452 | }, | |
2453 | }, | |
2454 | }; | |
2455 | ||
02824653 GD |
2456 | static struct clk_branch gcc_pdm2_clk = { |
2457 | .halt_reg = 0x0ccc, | |
2458 | .clkr = { | |
2459 | .enable_reg = 0x0ccc, | |
2460 | .enable_mask = BIT(0), | |
2461 | .hw.init = &(struct clk_init_data){ | |
2462 | .name = "gcc_pdm2_clk", | |
2463 | .parent_names = (const char *[]){ | |
2464 | "pdm2_clk_src", | |
2465 | }, | |
2466 | .num_parents = 1, | |
2467 | .flags = CLK_SET_RATE_PARENT, | |
2468 | .ops = &clk_branch2_ops, | |
2469 | }, | |
2470 | }, | |
2471 | }; | |
2472 | ||
2473 | static struct clk_branch gcc_pdm_ahb_clk = { | |
2474 | .halt_reg = 0x0cc4, | |
2475 | .clkr = { | |
2476 | .enable_reg = 0x0cc4, | |
2477 | .enable_mask = BIT(0), | |
2478 | .hw.init = &(struct clk_init_data){ | |
2479 | .name = "gcc_pdm_ahb_clk", | |
2480 | .parent_names = (const char *[]){ | |
2481 | "periph_noc_clk_src", | |
2482 | }, | |
2483 | .num_parents = 1, | |
2484 | .ops = &clk_branch2_ops, | |
2485 | }, | |
2486 | }, | |
2487 | }; | |
2488 | ||
2489 | static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk = { | |
2490 | .halt_reg = 0x01a4, | |
2491 | .clkr = { | |
2492 | .enable_reg = 0x01a4, | |
2493 | .enable_mask = BIT(0), | |
2494 | .hw.init = &(struct clk_init_data){ | |
2495 | .name = "gcc_periph_noc_usb_hsic_ahb_clk", | |
2496 | .parent_names = (const char *[]){ | |
2497 | "usb_hsic_ahb_clk_src", | |
2498 | }, | |
2499 | .num_parents = 1, | |
2500 | .flags = CLK_SET_RATE_PARENT, | |
2501 | .ops = &clk_branch2_ops, | |
2502 | }, | |
2503 | }, | |
2504 | }; | |
2505 | ||
2506 | static struct clk_branch gcc_prng_ahb_clk = { | |
2507 | .halt_reg = 0x0d04, | |
2508 | .halt_check = BRANCH_HALT_VOTED, | |
2509 | .clkr = { | |
2510 | .enable_reg = 0x1484, | |
2511 | .enable_mask = BIT(13), | |
2512 | .hw.init = &(struct clk_init_data){ | |
2513 | .name = "gcc_prng_ahb_clk", | |
2514 | .parent_names = (const char *[]){ | |
2515 | "periph_noc_clk_src", | |
2516 | }, | |
2517 | .num_parents = 1, | |
2518 | .ops = &clk_branch2_ops, | |
2519 | }, | |
2520 | }, | |
2521 | }; | |
2522 | ||
5424e102 GD |
2523 | static struct clk_branch gcc_sata_asic0_clk = { |
2524 | .halt_reg = 0x1c54, | |
2525 | .clkr = { | |
2526 | .enable_reg = 0x1c54, | |
2527 | .enable_mask = BIT(0), | |
2528 | .hw.init = &(struct clk_init_data){ | |
2529 | .name = "gcc_sata_asic0_clk", | |
2530 | .parent_names = (const char *[]){ | |
2531 | "sata_asic0_clk_src", | |
2532 | }, | |
2533 | .num_parents = 1, | |
2534 | .flags = CLK_SET_RATE_PARENT, | |
2535 | .ops = &clk_branch2_ops, | |
2536 | }, | |
2537 | }, | |
2538 | }; | |
2539 | ||
2540 | static struct clk_branch gcc_sata_axi_clk = { | |
2541 | .halt_reg = 0x1c44, | |
2542 | .clkr = { | |
2543 | .enable_reg = 0x1c44, | |
2544 | .enable_mask = BIT(0), | |
2545 | .hw.init = &(struct clk_init_data){ | |
2546 | .name = "gcc_sata_axi_clk", | |
2547 | .parent_names = (const char *[]){ | |
2548 | "config_noc_clk_src", | |
2549 | }, | |
2550 | .num_parents = 1, | |
2551 | .flags = CLK_SET_RATE_PARENT, | |
2552 | .ops = &clk_branch2_ops, | |
2553 | }, | |
2554 | }, | |
2555 | }; | |
2556 | ||
2557 | static struct clk_branch gcc_sata_cfg_ahb_clk = { | |
2558 | .halt_reg = 0x1c48, | |
2559 | .clkr = { | |
2560 | .enable_reg = 0x1c48, | |
2561 | .enable_mask = BIT(0), | |
2562 | .hw.init = &(struct clk_init_data){ | |
2563 | .name = "gcc_sata_cfg_ahb_clk", | |
2564 | .parent_names = (const char *[]){ | |
2565 | "config_noc_clk_src", | |
2566 | }, | |
2567 | .num_parents = 1, | |
2568 | .flags = CLK_SET_RATE_PARENT, | |
2569 | .ops = &clk_branch2_ops, | |
2570 | }, | |
2571 | }, | |
2572 | }; | |
2573 | ||
2574 | static struct clk_branch gcc_sata_pmalive_clk = { | |
2575 | .halt_reg = 0x1c50, | |
2576 | .clkr = { | |
2577 | .enable_reg = 0x1c50, | |
2578 | .enable_mask = BIT(0), | |
2579 | .hw.init = &(struct clk_init_data){ | |
2580 | .name = "gcc_sata_pmalive_clk", | |
2581 | .parent_names = (const char *[]){ | |
2582 | "sata_pmalive_clk_src", | |
2583 | }, | |
2584 | .num_parents = 1, | |
2585 | .flags = CLK_SET_RATE_PARENT, | |
2586 | .ops = &clk_branch2_ops, | |
2587 | }, | |
2588 | }, | |
2589 | }; | |
2590 | ||
2591 | static struct clk_branch gcc_sata_rx_clk = { | |
2592 | .halt_reg = 0x1c58, | |
2593 | .clkr = { | |
2594 | .enable_reg = 0x1c58, | |
2595 | .enable_mask = BIT(0), | |
2596 | .hw.init = &(struct clk_init_data){ | |
2597 | .name = "gcc_sata_rx_clk", | |
2598 | .parent_names = (const char *[]){ | |
2599 | "sata_rx_clk_src", | |
2600 | }, | |
2601 | .num_parents = 1, | |
2602 | .flags = CLK_SET_RATE_PARENT, | |
2603 | .ops = &clk_branch2_ops, | |
2604 | }, | |
2605 | }, | |
2606 | }; | |
2607 | ||
2608 | static struct clk_branch gcc_sata_rx_oob_clk = { | |
2609 | .halt_reg = 0x1c4c, | |
2610 | .clkr = { | |
2611 | .enable_reg = 0x1c4c, | |
2612 | .enable_mask = BIT(0), | |
2613 | .hw.init = &(struct clk_init_data){ | |
2614 | .name = "gcc_sata_rx_oob_clk", | |
2615 | .parent_names = (const char *[]){ | |
2616 | "sata_rx_oob_clk_src", | |
2617 | }, | |
2618 | .num_parents = 1, | |
2619 | .flags = CLK_SET_RATE_PARENT, | |
2620 | .ops = &clk_branch2_ops, | |
2621 | }, | |
2622 | }, | |
2623 | }; | |
2624 | ||
02824653 GD |
2625 | static struct clk_branch gcc_sdcc1_ahb_clk = { |
2626 | .halt_reg = 0x04c8, | |
2627 | .clkr = { | |
2628 | .enable_reg = 0x04c8, | |
2629 | .enable_mask = BIT(0), | |
2630 | .hw.init = &(struct clk_init_data){ | |
2631 | .name = "gcc_sdcc1_ahb_clk", | |
2632 | .parent_names = (const char *[]){ | |
2633 | "periph_noc_clk_src", | |
2634 | }, | |
2635 | .num_parents = 1, | |
2636 | .ops = &clk_branch2_ops, | |
2637 | }, | |
2638 | }, | |
2639 | }; | |
2640 | ||
2641 | static struct clk_branch gcc_sdcc1_apps_clk = { | |
2642 | .halt_reg = 0x04c4, | |
2643 | .clkr = { | |
2644 | .enable_reg = 0x04c4, | |
2645 | .enable_mask = BIT(0), | |
2646 | .hw.init = &(struct clk_init_data){ | |
2647 | .name = "gcc_sdcc1_apps_clk", | |
2648 | .parent_names = (const char *[]){ | |
2649 | "sdcc1_apps_clk_src", | |
2650 | }, | |
2651 | .num_parents = 1, | |
2652 | .flags = CLK_SET_RATE_PARENT, | |
2653 | .ops = &clk_branch2_ops, | |
2654 | }, | |
2655 | }, | |
2656 | }; | |
2657 | ||
2658 | static struct clk_branch gcc_sdcc1_cdccal_ff_clk = { | |
2659 | .halt_reg = 0x04e8, | |
2660 | .clkr = { | |
2661 | .enable_reg = 0x04e8, | |
2662 | .enable_mask = BIT(0), | |
2663 | .hw.init = &(struct clk_init_data){ | |
2664 | .name = "gcc_sdcc1_cdccal_ff_clk", | |
2665 | .parent_names = (const char *[]){ | |
2666 | "xo" | |
2667 | }, | |
2668 | .num_parents = 1, | |
2669 | .ops = &clk_branch2_ops, | |
2670 | }, | |
2671 | }, | |
2672 | }; | |
2673 | ||
2674 | static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = { | |
2675 | .halt_reg = 0x04e4, | |
2676 | .clkr = { | |
2677 | .enable_reg = 0x04e4, | |
2678 | .enable_mask = BIT(0), | |
2679 | .hw.init = &(struct clk_init_data){ | |
2680 | .name = "gcc_sdcc1_cdccal_sleep_clk", | |
2681 | .parent_names = (const char *[]){ | |
2682 | "sleep_clk_src" | |
2683 | }, | |
2684 | .num_parents = 1, | |
2685 | .ops = &clk_branch2_ops, | |
2686 | }, | |
2687 | }, | |
2688 | }; | |
2689 | ||
2690 | static struct clk_branch gcc_sdcc2_ahb_clk = { | |
2691 | .halt_reg = 0x0508, | |
2692 | .clkr = { | |
2693 | .enable_reg = 0x0508, | |
2694 | .enable_mask = BIT(0), | |
2695 | .hw.init = &(struct clk_init_data){ | |
2696 | .name = "gcc_sdcc2_ahb_clk", | |
2697 | .parent_names = (const char *[]){ | |
2698 | "periph_noc_clk_src", | |
2699 | }, | |
2700 | .num_parents = 1, | |
2701 | .ops = &clk_branch2_ops, | |
2702 | }, | |
2703 | }, | |
2704 | }; | |
2705 | ||
2706 | static struct clk_branch gcc_sdcc2_apps_clk = { | |
2707 | .halt_reg = 0x0504, | |
2708 | .clkr = { | |
2709 | .enable_reg = 0x0504, | |
2710 | .enable_mask = BIT(0), | |
2711 | .hw.init = &(struct clk_init_data){ | |
2712 | .name = "gcc_sdcc2_apps_clk", | |
2713 | .parent_names = (const char *[]){ | |
2714 | "sdcc2_apps_clk_src", | |
2715 | }, | |
2716 | .num_parents = 1, | |
2717 | .flags = CLK_SET_RATE_PARENT, | |
2718 | .ops = &clk_branch2_ops, | |
2719 | }, | |
2720 | }, | |
2721 | }; | |
2722 | ||
2723 | static struct clk_branch gcc_sdcc3_ahb_clk = { | |
2724 | .halt_reg = 0x0548, | |
2725 | .clkr = { | |
2726 | .enable_reg = 0x0548, | |
2727 | .enable_mask = BIT(0), | |
2728 | .hw.init = &(struct clk_init_data){ | |
2729 | .name = "gcc_sdcc3_ahb_clk", | |
2730 | .parent_names = (const char *[]){ | |
2731 | "periph_noc_clk_src", | |
2732 | }, | |
2733 | .num_parents = 1, | |
2734 | .ops = &clk_branch2_ops, | |
2735 | }, | |
2736 | }, | |
2737 | }; | |
2738 | ||
2739 | static struct clk_branch gcc_sdcc3_apps_clk = { | |
2740 | .halt_reg = 0x0544, | |
2741 | .clkr = { | |
2742 | .enable_reg = 0x0544, | |
2743 | .enable_mask = BIT(0), | |
2744 | .hw.init = &(struct clk_init_data){ | |
2745 | .name = "gcc_sdcc3_apps_clk", | |
2746 | .parent_names = (const char *[]){ | |
2747 | "sdcc3_apps_clk_src", | |
2748 | }, | |
2749 | .num_parents = 1, | |
2750 | .flags = CLK_SET_RATE_PARENT, | |
2751 | .ops = &clk_branch2_ops, | |
2752 | }, | |
2753 | }, | |
2754 | }; | |
2755 | ||
2756 | static struct clk_branch gcc_sdcc4_ahb_clk = { | |
2757 | .halt_reg = 0x0588, | |
2758 | .clkr = { | |
2759 | .enable_reg = 0x0588, | |
2760 | .enable_mask = BIT(0), | |
2761 | .hw.init = &(struct clk_init_data){ | |
2762 | .name = "gcc_sdcc4_ahb_clk", | |
2763 | .parent_names = (const char *[]){ | |
2764 | "periph_noc_clk_src", | |
2765 | }, | |
2766 | .num_parents = 1, | |
2767 | .ops = &clk_branch2_ops, | |
2768 | }, | |
2769 | }, | |
2770 | }; | |
2771 | ||
2772 | static struct clk_branch gcc_sdcc4_apps_clk = { | |
2773 | .halt_reg = 0x0584, | |
2774 | .clkr = { | |
2775 | .enable_reg = 0x0584, | |
2776 | .enable_mask = BIT(0), | |
2777 | .hw.init = &(struct clk_init_data){ | |
2778 | .name = "gcc_sdcc4_apps_clk", | |
2779 | .parent_names = (const char *[]){ | |
2780 | "sdcc4_apps_clk_src", | |
2781 | }, | |
2782 | .num_parents = 1, | |
2783 | .flags = CLK_SET_RATE_PARENT, | |
2784 | .ops = &clk_branch2_ops, | |
2785 | }, | |
2786 | }, | |
2787 | }; | |
2788 | ||
5424e102 GD |
2789 | static struct clk_branch gcc_sys_noc_ufs_axi_clk = { |
2790 | .halt_reg = 0x013c, | |
2791 | .clkr = { | |
2792 | .enable_reg = 0x013c, | |
2793 | .enable_mask = BIT(0), | |
2794 | .hw.init = &(struct clk_init_data){ | |
2795 | .name = "gcc_sys_noc_ufs_axi_clk", | |
2796 | .parent_names = (const char *[]){ | |
2797 | "ufs_axi_clk_src", | |
2798 | }, | |
2799 | .num_parents = 1, | |
2800 | .flags = CLK_SET_RATE_PARENT, | |
2801 | .ops = &clk_branch2_ops, | |
2802 | }, | |
2803 | }, | |
2804 | }; | |
2805 | ||
02824653 GD |
2806 | static struct clk_branch gcc_sys_noc_usb3_axi_clk = { |
2807 | .halt_reg = 0x0108, | |
2808 | .clkr = { | |
2809 | .enable_reg = 0x0108, | |
2810 | .enable_mask = BIT(0), | |
2811 | .hw.init = &(struct clk_init_data){ | |
2812 | .name = "gcc_sys_noc_usb3_axi_clk", | |
2813 | .parent_names = (const char *[]){ | |
2814 | "usb30_master_clk_src", | |
2815 | }, | |
2816 | .num_parents = 1, | |
2817 | .flags = CLK_SET_RATE_PARENT, | |
2818 | .ops = &clk_branch2_ops, | |
2819 | }, | |
2820 | }, | |
2821 | }; | |
2822 | ||
2823 | static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk = { | |
2824 | .halt_reg = 0x0138, | |
2825 | .clkr = { | |
2826 | .enable_reg = 0x0138, | |
2827 | .enable_mask = BIT(0), | |
2828 | .hw.init = &(struct clk_init_data){ | |
2829 | .name = "gcc_sys_noc_usb3_sec_axi_clk", | |
2830 | .parent_names = (const char *[]){ | |
2831 | "usb30_sec_master_clk_src", | |
2832 | }, | |
2833 | .num_parents = 1, | |
2834 | .flags = CLK_SET_RATE_PARENT, | |
2835 | .ops = &clk_branch2_ops, | |
2836 | }, | |
2837 | }, | |
2838 | }; | |
2839 | ||
2840 | static struct clk_branch gcc_tsif_ahb_clk = { | |
2841 | .halt_reg = 0x0d84, | |
2842 | .clkr = { | |
2843 | .enable_reg = 0x0d84, | |
2844 | .enable_mask = BIT(0), | |
2845 | .hw.init = &(struct clk_init_data){ | |
2846 | .name = "gcc_tsif_ahb_clk", | |
2847 | .parent_names = (const char *[]){ | |
2848 | "periph_noc_clk_src", | |
2849 | }, | |
2850 | .num_parents = 1, | |
2851 | .ops = &clk_branch2_ops, | |
2852 | }, | |
2853 | }, | |
2854 | }; | |
2855 | ||
2856 | static struct clk_branch gcc_tsif_inactivity_timers_clk = { | |
2857 | .halt_reg = 0x0d8c, | |
2858 | .clkr = { | |
2859 | .enable_reg = 0x0d8c, | |
2860 | .enable_mask = BIT(0), | |
2861 | .hw.init = &(struct clk_init_data){ | |
2862 | .name = "gcc_tsif_inactivity_timers_clk", | |
2863 | .parent_names = (const char *[]){ | |
2864 | "sleep_clk_src", | |
2865 | }, | |
2866 | .num_parents = 1, | |
2867 | .flags = CLK_SET_RATE_PARENT, | |
2868 | .ops = &clk_branch2_ops, | |
2869 | }, | |
2870 | }, | |
2871 | }; | |
2872 | ||
2873 | static struct clk_branch gcc_tsif_ref_clk = { | |
2874 | .halt_reg = 0x0d88, | |
2875 | .clkr = { | |
2876 | .enable_reg = 0x0d88, | |
2877 | .enable_mask = BIT(0), | |
2878 | .hw.init = &(struct clk_init_data){ | |
2879 | .name = "gcc_tsif_ref_clk", | |
2880 | .parent_names = (const char *[]){ | |
2881 | "tsif_ref_clk_src", | |
2882 | }, | |
2883 | .num_parents = 1, | |
2884 | .flags = CLK_SET_RATE_PARENT, | |
2885 | .ops = &clk_branch2_ops, | |
2886 | }, | |
2887 | }, | |
2888 | }; | |
2889 | ||
5424e102 GD |
2890 | static struct clk_branch gcc_ufs_ahb_clk = { |
2891 | .halt_reg = 0x1d48, | |
2892 | .clkr = { | |
2893 | .enable_reg = 0x1d48, | |
2894 | .enable_mask = BIT(0), | |
2895 | .hw.init = &(struct clk_init_data){ | |
2896 | .name = "gcc_ufs_ahb_clk", | |
2897 | .parent_names = (const char *[]){ | |
2898 | "config_noc_clk_src", | |
2899 | }, | |
2900 | .num_parents = 1, | |
2901 | .flags = CLK_SET_RATE_PARENT, | |
2902 | .ops = &clk_branch2_ops, | |
2903 | }, | |
2904 | }, | |
2905 | }; | |
2906 | ||
2907 | static struct clk_branch gcc_ufs_axi_clk = { | |
2908 | .halt_reg = 0x1d44, | |
2909 | .clkr = { | |
2910 | .enable_reg = 0x1d44, | |
2911 | .enable_mask = BIT(0), | |
2912 | .hw.init = &(struct clk_init_data){ | |
2913 | .name = "gcc_ufs_axi_clk", | |
2914 | .parent_names = (const char *[]){ | |
2915 | "ufs_axi_clk_src", | |
2916 | }, | |
2917 | .num_parents = 1, | |
2918 | .flags = CLK_SET_RATE_PARENT, | |
2919 | .ops = &clk_branch2_ops, | |
2920 | }, | |
2921 | }, | |
2922 | }; | |
2923 | ||
2924 | static struct clk_branch gcc_ufs_rx_cfg_clk = { | |
2925 | .halt_reg = 0x1d50, | |
2926 | .clkr = { | |
2927 | .enable_reg = 0x1d50, | |
2928 | .enable_mask = BIT(0), | |
2929 | .hw.init = &(struct clk_init_data){ | |
2930 | .name = "gcc_ufs_rx_cfg_clk", | |
2931 | .parent_names = (const char *[]){ | |
2932 | "ufs_axi_clk_src", | |
2933 | }, | |
2934 | .num_parents = 1, | |
2935 | .flags = CLK_SET_RATE_PARENT, | |
2936 | .ops = &clk_branch2_ops, | |
2937 | }, | |
2938 | }, | |
2939 | }; | |
2940 | ||
2941 | static struct clk_branch gcc_ufs_rx_symbol_0_clk = { | |
2942 | .halt_reg = 0x1d5c, | |
2943 | .clkr = { | |
2944 | .enable_reg = 0x1d5c, | |
2945 | .enable_mask = BIT(0), | |
2946 | .hw.init = &(struct clk_init_data){ | |
2947 | .name = "gcc_ufs_rx_symbol_0_clk", | |
2948 | .parent_names = (const char *[]){ | |
2949 | "ufs_rx_symbol_0_clk_src", | |
2950 | }, | |
2951 | .num_parents = 1, | |
2952 | .flags = CLK_SET_RATE_PARENT, | |
2953 | .ops = &clk_branch2_ops, | |
2954 | }, | |
2955 | }, | |
2956 | }; | |
2957 | ||
2958 | static struct clk_branch gcc_ufs_rx_symbol_1_clk = { | |
2959 | .halt_reg = 0x1d60, | |
2960 | .clkr = { | |
2961 | .enable_reg = 0x1d60, | |
2962 | .enable_mask = BIT(0), | |
2963 | .hw.init = &(struct clk_init_data){ | |
2964 | .name = "gcc_ufs_rx_symbol_1_clk", | |
2965 | .parent_names = (const char *[]){ | |
2966 | "ufs_rx_symbol_1_clk_src", | |
2967 | }, | |
2968 | .num_parents = 1, | |
2969 | .flags = CLK_SET_RATE_PARENT, | |
2970 | .ops = &clk_branch2_ops, | |
2971 | }, | |
2972 | }, | |
2973 | }; | |
2974 | ||
2975 | static struct clk_branch gcc_ufs_tx_cfg_clk = { | |
2976 | .halt_reg = 0x1d4c, | |
2977 | .clkr = { | |
2978 | .enable_reg = 0x1d4c, | |
2979 | .enable_mask = BIT(0), | |
2980 | .hw.init = &(struct clk_init_data){ | |
2981 | .name = "gcc_ufs_tx_cfg_clk", | |
2982 | .parent_names = (const char *[]){ | |
2983 | "ufs_axi_clk_src", | |
2984 | }, | |
2985 | .num_parents = 1, | |
2986 | .flags = CLK_SET_RATE_PARENT, | |
2987 | .ops = &clk_branch2_ops, | |
2988 | }, | |
2989 | }, | |
2990 | }; | |
2991 | ||
2992 | static struct clk_branch gcc_ufs_tx_symbol_0_clk = { | |
2993 | .halt_reg = 0x1d54, | |
2994 | .clkr = { | |
2995 | .enable_reg = 0x1d54, | |
2996 | .enable_mask = BIT(0), | |
2997 | .hw.init = &(struct clk_init_data){ | |
2998 | .name = "gcc_ufs_tx_symbol_0_clk", | |
2999 | .parent_names = (const char *[]){ | |
3000 | "ufs_tx_symbol_0_clk_src", | |
3001 | }, | |
3002 | .num_parents = 1, | |
3003 | .flags = CLK_SET_RATE_PARENT, | |
3004 | .ops = &clk_branch2_ops, | |
3005 | }, | |
3006 | }, | |
3007 | }; | |
3008 | ||
3009 | static struct clk_branch gcc_ufs_tx_symbol_1_clk = { | |
3010 | .halt_reg = 0x1d58, | |
3011 | .clkr = { | |
3012 | .enable_reg = 0x1d58, | |
3013 | .enable_mask = BIT(0), | |
3014 | .hw.init = &(struct clk_init_data){ | |
3015 | .name = "gcc_ufs_tx_symbol_1_clk", | |
3016 | .parent_names = (const char *[]){ | |
3017 | "ufs_tx_symbol_1_clk_src", | |
3018 | }, | |
3019 | .num_parents = 1, | |
3020 | .flags = CLK_SET_RATE_PARENT, | |
3021 | .ops = &clk_branch2_ops, | |
3022 | }, | |
3023 | }, | |
3024 | }; | |
3025 | ||
02824653 GD |
3026 | static struct clk_branch gcc_usb2a_phy_sleep_clk = { |
3027 | .halt_reg = 0x04ac, | |
3028 | .clkr = { | |
3029 | .enable_reg = 0x04ac, | |
3030 | .enable_mask = BIT(0), | |
3031 | .hw.init = &(struct clk_init_data){ | |
3032 | .name = "gcc_usb2a_phy_sleep_clk", | |
3033 | .parent_names = (const char *[]){ | |
3034 | "sleep_clk_src", | |
3035 | }, | |
3036 | .num_parents = 1, | |
3037 | .ops = &clk_branch2_ops, | |
3038 | }, | |
3039 | }, | |
3040 | }; | |
3041 | ||
3042 | static struct clk_branch gcc_usb2b_phy_sleep_clk = { | |
3043 | .halt_reg = 0x04b4, | |
3044 | .clkr = { | |
3045 | .enable_reg = 0x04b4, | |
3046 | .enable_mask = BIT(0), | |
3047 | .hw.init = &(struct clk_init_data){ | |
3048 | .name = "gcc_usb2b_phy_sleep_clk", | |
3049 | .parent_names = (const char *[]){ | |
3050 | "sleep_clk_src", | |
3051 | }, | |
3052 | .num_parents = 1, | |
3053 | .ops = &clk_branch2_ops, | |
3054 | }, | |
3055 | }, | |
3056 | }; | |
3057 | ||
3058 | static struct clk_branch gcc_usb30_master_clk = { | |
3059 | .halt_reg = 0x03c8, | |
3060 | .clkr = { | |
3061 | .enable_reg = 0x03c8, | |
3062 | .enable_mask = BIT(0), | |
3063 | .hw.init = &(struct clk_init_data){ | |
3064 | .name = "gcc_usb30_master_clk", | |
3065 | .parent_names = (const char *[]){ | |
3066 | "usb30_master_clk_src", | |
3067 | }, | |
3068 | .num_parents = 1, | |
3069 | .flags = CLK_SET_RATE_PARENT, | |
3070 | .ops = &clk_branch2_ops, | |
3071 | }, | |
3072 | }, | |
3073 | }; | |
3074 | ||
3075 | static struct clk_branch gcc_usb30_sec_master_clk = { | |
3076 | .halt_reg = 0x1bc8, | |
3077 | .clkr = { | |
3078 | .enable_reg = 0x1bc8, | |
3079 | .enable_mask = BIT(0), | |
3080 | .hw.init = &(struct clk_init_data){ | |
3081 | .name = "gcc_usb30_sec_master_clk", | |
3082 | .parent_names = (const char *[]){ | |
3083 | "usb30_sec_master_clk_src", | |
3084 | }, | |
3085 | .num_parents = 1, | |
3086 | .flags = CLK_SET_RATE_PARENT, | |
3087 | .ops = &clk_branch2_ops, | |
3088 | }, | |
3089 | }, | |
3090 | }; | |
3091 | ||
3092 | static struct clk_branch gcc_usb30_mock_utmi_clk = { | |
3093 | .halt_reg = 0x03d0, | |
3094 | .clkr = { | |
3095 | .enable_reg = 0x03d0, | |
3096 | .enable_mask = BIT(0), | |
3097 | .hw.init = &(struct clk_init_data){ | |
3098 | .name = "gcc_usb30_mock_utmi_clk", | |
3099 | .parent_names = (const char *[]){ | |
3100 | "usb30_mock_utmi_clk_src", | |
3101 | }, | |
3102 | .num_parents = 1, | |
3103 | .flags = CLK_SET_RATE_PARENT, | |
3104 | .ops = &clk_branch2_ops, | |
3105 | }, | |
3106 | }, | |
3107 | }; | |
3108 | ||
3109 | static struct clk_branch gcc_usb30_sleep_clk = { | |
3110 | .halt_reg = 0x03cc, | |
3111 | .clkr = { | |
3112 | .enable_reg = 0x03cc, | |
3113 | .enable_mask = BIT(0), | |
3114 | .hw.init = &(struct clk_init_data){ | |
3115 | .name = "gcc_usb30_sleep_clk", | |
3116 | .parent_names = (const char *[]){ | |
3117 | "sleep_clk_src", | |
3118 | }, | |
3119 | .num_parents = 1, | |
3120 | .ops = &clk_branch2_ops, | |
3121 | }, | |
3122 | }, | |
3123 | }; | |
3124 | ||
3125 | static struct clk_branch gcc_usb_hs_ahb_clk = { | |
3126 | .halt_reg = 0x0488, | |
3127 | .clkr = { | |
3128 | .enable_reg = 0x0488, | |
3129 | .enable_mask = BIT(0), | |
3130 | .hw.init = &(struct clk_init_data){ | |
3131 | .name = "gcc_usb_hs_ahb_clk", | |
3132 | .parent_names = (const char *[]){ | |
3133 | "periph_noc_clk_src", | |
3134 | }, | |
3135 | .num_parents = 1, | |
3136 | .ops = &clk_branch2_ops, | |
3137 | }, | |
3138 | }, | |
3139 | }; | |
3140 | ||
3141 | static struct clk_branch gcc_usb_hs_inactivity_timers_clk = { | |
3142 | .halt_reg = 0x048c, | |
3143 | .clkr = { | |
3144 | .enable_reg = 0x048c, | |
3145 | .enable_mask = BIT(0), | |
3146 | .hw.init = &(struct clk_init_data){ | |
3147 | .name = "gcc_usb_hs_inactivity_timers_clk", | |
3148 | .parent_names = (const char *[]){ | |
3149 | "sleep_clk_src", | |
3150 | }, | |
3151 | .num_parents = 1, | |
3152 | .flags = CLK_SET_RATE_PARENT, | |
3153 | .ops = &clk_branch2_ops, | |
3154 | }, | |
3155 | }, | |
3156 | }; | |
3157 | ||
3158 | static struct clk_branch gcc_usb_hs_system_clk = { | |
3159 | .halt_reg = 0x0484, | |
3160 | .clkr = { | |
3161 | .enable_reg = 0x0484, | |
3162 | .enable_mask = BIT(0), | |
3163 | .hw.init = &(struct clk_init_data){ | |
3164 | .name = "gcc_usb_hs_system_clk", | |
3165 | .parent_names = (const char *[]){ | |
3166 | "usb_hs_system_clk_src", | |
3167 | }, | |
3168 | .num_parents = 1, | |
3169 | .flags = CLK_SET_RATE_PARENT, | |
3170 | .ops = &clk_branch2_ops, | |
3171 | }, | |
3172 | }, | |
3173 | }; | |
3174 | ||
3175 | static struct clk_branch gcc_usb_hsic_ahb_clk = { | |
3176 | .halt_reg = 0x0408, | |
3177 | .clkr = { | |
3178 | .enable_reg = 0x0408, | |
3179 | .enable_mask = BIT(0), | |
3180 | .hw.init = &(struct clk_init_data){ | |
3181 | .name = "gcc_usb_hsic_ahb_clk", | |
3182 | .parent_names = (const char *[]){ | |
3183 | "periph_noc_clk_src", | |
3184 | }, | |
3185 | .num_parents = 1, | |
3186 | .ops = &clk_branch2_ops, | |
3187 | }, | |
3188 | }, | |
3189 | }; | |
3190 | ||
3191 | static struct clk_branch gcc_usb_hsic_clk = { | |
3192 | .halt_reg = 0x0410, | |
3193 | .clkr = { | |
3194 | .enable_reg = 0x0410, | |
3195 | .enable_mask = BIT(0), | |
3196 | .hw.init = &(struct clk_init_data){ | |
3197 | .name = "gcc_usb_hsic_clk", | |
3198 | .parent_names = (const char *[]){ | |
3199 | "usb_hsic_clk_src", | |
3200 | }, | |
3201 | .num_parents = 1, | |
3202 | .flags = CLK_SET_RATE_PARENT, | |
3203 | .ops = &clk_branch2_ops, | |
3204 | }, | |
3205 | }, | |
3206 | }; | |
3207 | ||
3208 | static struct clk_branch gcc_usb_hsic_io_cal_clk = { | |
3209 | .halt_reg = 0x0414, | |
3210 | .clkr = { | |
3211 | .enable_reg = 0x0414, | |
3212 | .enable_mask = BIT(0), | |
3213 | .hw.init = &(struct clk_init_data){ | |
3214 | .name = "gcc_usb_hsic_io_cal_clk", | |
3215 | .parent_names = (const char *[]){ | |
3216 | "usb_hsic_io_cal_clk_src", | |
3217 | }, | |
3218 | .num_parents = 1, | |
3219 | .flags = CLK_SET_RATE_PARENT, | |
3220 | .ops = &clk_branch2_ops, | |
3221 | }, | |
3222 | }, | |
3223 | }; | |
3224 | ||
3225 | static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = { | |
3226 | .halt_reg = 0x0418, | |
3227 | .clkr = { | |
3228 | .enable_reg = 0x0418, | |
3229 | .enable_mask = BIT(0), | |
3230 | .hw.init = &(struct clk_init_data){ | |
3231 | .name = "gcc_usb_hsic_io_cal_sleep_clk", | |
3232 | .parent_names = (const char *[]){ | |
3233 | "sleep_clk_src", | |
3234 | }, | |
3235 | .num_parents = 1, | |
3236 | .ops = &clk_branch2_ops, | |
3237 | }, | |
3238 | }, | |
3239 | }; | |
3240 | ||
3241 | static struct clk_branch gcc_usb_hsic_system_clk = { | |
3242 | .halt_reg = 0x040c, | |
3243 | .clkr = { | |
3244 | .enable_reg = 0x040c, | |
3245 | .enable_mask = BIT(0), | |
3246 | .hw.init = &(struct clk_init_data){ | |
3247 | .name = "gcc_usb_hsic_system_clk", | |
3248 | .parent_names = (const char *[]){ | |
3249 | "usb_hsic_system_clk_src", | |
3250 | }, | |
3251 | .num_parents = 1, | |
3252 | .flags = CLK_SET_RATE_PARENT, | |
3253 | .ops = &clk_branch2_ops, | |
3254 | }, | |
3255 | }, | |
3256 | }; | |
3257 | ||
639af949 RN |
3258 | static struct gdsc usb_hs_hsic_gdsc = { |
3259 | .gdscr = 0x404, | |
3260 | .pd = { | |
3261 | .name = "usb_hs_hsic", | |
3262 | }, | |
3263 | .pwrsts = PWRSTS_OFF_ON, | |
3264 | }; | |
3265 | ||
3266 | static struct gdsc pcie0_gdsc = { | |
3267 | .gdscr = 0x1ac4, | |
3268 | .pd = { | |
3269 | .name = "pcie0", | |
3270 | }, | |
3271 | .pwrsts = PWRSTS_OFF_ON, | |
3272 | }; | |
3273 | ||
3274 | static struct gdsc pcie1_gdsc = { | |
3275 | .gdscr = 0x1b44, | |
3276 | .pd = { | |
3277 | .name = "pcie1", | |
3278 | }, | |
3279 | .pwrsts = PWRSTS_OFF_ON, | |
3280 | }; | |
3281 | ||
3282 | static struct gdsc usb30_gdsc = { | |
3283 | .gdscr = 0x1e84, | |
3284 | .pd = { | |
3285 | .name = "usb30", | |
3286 | }, | |
3287 | .pwrsts = PWRSTS_OFF_ON, | |
3288 | }; | |
3289 | ||
02824653 GD |
3290 | static struct clk_regmap *gcc_apq8084_clocks[] = { |
3291 | [GPLL0] = &gpll0.clkr, | |
3292 | [GPLL0_VOTE] = &gpll0_vote, | |
3293 | [GPLL1] = &gpll1.clkr, | |
3294 | [GPLL1_VOTE] = &gpll1_vote, | |
3295 | [GPLL4] = &gpll4.clkr, | |
3296 | [GPLL4_VOTE] = &gpll4_vote, | |
3297 | [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, | |
3298 | [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, | |
3299 | [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, | |
5424e102 | 3300 | [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, |
02824653 GD |
3301 | [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, |
3302 | [USB30_SEC_MASTER_CLK_SRC] = &usb30_sec_master_clk_src.clkr, | |
3303 | [USB_HSIC_AHB_CLK_SRC] = &usb_hsic_ahb_clk_src.clkr, | |
3304 | [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, | |
3305 | [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, | |
3306 | [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, | |
3307 | [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, | |
3308 | [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, | |
3309 | [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, | |
3310 | [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, | |
3311 | [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, | |
3312 | [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, | |
3313 | [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, | |
3314 | [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, | |
3315 | [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, | |
3316 | [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, | |
3317 | [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, | |
3318 | [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, | |
3319 | [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, | |
3320 | [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, | |
3321 | [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, | |
3322 | [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, | |
3323 | [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, | |
3324 | [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, | |
3325 | [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, | |
3326 | [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, | |
3327 | [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, | |
3328 | [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, | |
3329 | [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, | |
3330 | [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr, | |
3331 | [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr, | |
3332 | [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr, | |
3333 | [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr, | |
3334 | [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, | |
3335 | [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, | |
3336 | [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr, | |
3337 | [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr, | |
3338 | [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr, | |
3339 | [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr, | |
3340 | [CE1_CLK_SRC] = &ce1_clk_src.clkr, | |
3341 | [CE2_CLK_SRC] = &ce2_clk_src.clkr, | |
3342 | [CE3_CLK_SRC] = &ce3_clk_src.clkr, | |
3343 | [GP1_CLK_SRC] = &gp1_clk_src.clkr, | |
3344 | [GP2_CLK_SRC] = &gp2_clk_src.clkr, | |
3345 | [GP3_CLK_SRC] = &gp3_clk_src.clkr, | |
5424e102 GD |
3346 | [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr, |
3347 | [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr, | |
3348 | [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr, | |
3349 | [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr, | |
02824653 | 3350 | [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, |
5424e102 GD |
3351 | [SATA_ASIC0_CLK_SRC] = &sata_asic0_clk_src.clkr, |
3352 | [SATA_PMALIVE_CLK_SRC] = &sata_pmalive_clk_src.clkr, | |
3353 | [SATA_RX_CLK_SRC] = &sata_rx_clk_src.clkr, | |
3354 | [SATA_RX_OOB_CLK_SRC] = &sata_rx_oob_clk_src.clkr, | |
02824653 GD |
3355 | [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, |
3356 | [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, | |
3357 | [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, | |
3358 | [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr, | |
3359 | [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr, | |
3360 | [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, | |
3361 | [USB30_SEC_MOCK_UTMI_CLK_SRC] = &usb30_sec_mock_utmi_clk_src.clkr, | |
3362 | [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, | |
3363 | [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr, | |
3364 | [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr, | |
3365 | [USB_HSIC_MOCK_UTMI_CLK_SRC] = &usb_hsic_mock_utmi_clk_src.clkr, | |
3366 | [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr, | |
3367 | [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr, | |
3368 | [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, | |
3369 | [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, | |
3370 | [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, | |
3371 | [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, | |
3372 | [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, | |
3373 | [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, | |
3374 | [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, | |
3375 | [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, | |
3376 | [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, | |
3377 | [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, | |
3378 | [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, | |
3379 | [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, | |
3380 | [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, | |
3381 | [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, | |
3382 | [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, | |
3383 | [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, | |
3384 | [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, | |
3385 | [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, | |
3386 | [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, | |
3387 | [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, | |
3388 | [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, | |
3389 | [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, | |
3390 | [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, | |
3391 | [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, | |
3392 | [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, | |
3393 | [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, | |
3394 | [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, | |
3395 | [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, | |
3396 | [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr, | |
3397 | [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr, | |
3398 | [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr, | |
3399 | [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr, | |
3400 | [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, | |
3401 | [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, | |
3402 | [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr, | |
3403 | [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr, | |
3404 | [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr, | |
3405 | [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr, | |
3406 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, | |
3407 | [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, | |
3408 | [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, | |
3409 | [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, | |
3410 | [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr, | |
3411 | [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr, | |
3412 | [GCC_CE2_CLK] = &gcc_ce2_clk.clkr, | |
3413 | [GCC_CE3_AHB_CLK] = &gcc_ce3_ahb_clk.clkr, | |
3414 | [GCC_CE3_AXI_CLK] = &gcc_ce3_axi_clk.clkr, | |
3415 | [GCC_CE3_CLK] = &gcc_ce3_clk.clkr, | |
3416 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, | |
3417 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, | |
3418 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, | |
3419 | [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr, | |
5424e102 GD |
3420 | [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, |
3421 | [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, | |
3422 | [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, | |
3423 | [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, | |
3424 | [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, | |
3425 | [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, | |
3426 | [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, | |
3427 | [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, | |
3428 | [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, | |
3429 | [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, | |
02824653 GD |
3430 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, |
3431 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, | |
3432 | [GCC_PERIPH_NOC_USB_HSIC_AHB_CLK] = &gcc_periph_noc_usb_hsic_ahb_clk.clkr, | |
3433 | [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, | |
5424e102 GD |
3434 | [GCC_SATA_ASIC0_CLK] = &gcc_sata_asic0_clk.clkr, |
3435 | [GCC_SATA_AXI_CLK] = &gcc_sata_axi_clk.clkr, | |
3436 | [GCC_SATA_CFG_AHB_CLK] = &gcc_sata_cfg_ahb_clk.clkr, | |
3437 | [GCC_SATA_PMALIVE_CLK] = &gcc_sata_pmalive_clk.clkr, | |
3438 | [GCC_SATA_RX_CLK] = &gcc_sata_rx_clk.clkr, | |
3439 | [GCC_SATA_RX_OOB_CLK] = &gcc_sata_rx_oob_clk.clkr, | |
02824653 GD |
3440 | [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, |
3441 | [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, | |
3442 | [GCC_SDCC1_CDCCAL_FF_CLK] = &gcc_sdcc1_cdccal_ff_clk.clkr, | |
3443 | [GCC_SDCC1_CDCCAL_SLEEP_CLK] = &gcc_sdcc1_cdccal_sleep_clk.clkr, | |
3444 | [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, | |
3445 | [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, | |
3446 | [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, | |
3447 | [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, | |
3448 | [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, | |
3449 | [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, | |
5424e102 | 3450 | [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr, |
02824653 GD |
3451 | [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr, |
3452 | [GCC_SYS_NOC_USB3_SEC_AXI_CLK] = &gcc_sys_noc_usb3_sec_axi_clk.clkr, | |
3453 | [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr, | |
3454 | [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr, | |
3455 | [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr, | |
5424e102 GD |
3456 | [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, |
3457 | [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, | |
3458 | [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr, | |
3459 | [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, | |
3460 | [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, | |
3461 | [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr, | |
3462 | [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, | |
3463 | [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr, | |
02824653 GD |
3464 | [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, |
3465 | [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr, | |
3466 | [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, | |
3467 | [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, | |
3468 | [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, | |
3469 | [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr, | |
3470 | [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr, | |
3471 | [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr, | |
3472 | [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, | |
3473 | [GCC_USB_HS_INACTIVITY_TIMERS_CLK] = &gcc_usb_hs_inactivity_timers_clk.clkr, | |
3474 | [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, | |
3475 | [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr, | |
3476 | [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr, | |
3477 | [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr, | |
3478 | [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr, | |
3479 | [GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr, | |
3480 | [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, | |
3481 | }; | |
3482 | ||
639af949 RN |
3483 | static struct gdsc *gcc_apq8084_gdscs[] = { |
3484 | [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc, | |
3485 | [PCIE0_GDSC] = &pcie0_gdsc, | |
3486 | [PCIE1_GDSC] = &pcie1_gdsc, | |
3487 | [USB30_GDSC] = &usb30_gdsc, | |
3488 | }; | |
3489 | ||
02824653 GD |
3490 | static const struct qcom_reset_map gcc_apq8084_resets[] = { |
3491 | [GCC_SYSTEM_NOC_BCR] = { 0x0100 }, | |
3492 | [GCC_CONFIG_NOC_BCR] = { 0x0140 }, | |
3493 | [GCC_PERIPH_NOC_BCR] = { 0x0180 }, | |
3494 | [GCC_IMEM_BCR] = { 0x0200 }, | |
3495 | [GCC_MMSS_BCR] = { 0x0240 }, | |
3496 | [GCC_QDSS_BCR] = { 0x0300 }, | |
3497 | [GCC_USB_30_BCR] = { 0x03c0 }, | |
3498 | [GCC_USB3_PHY_BCR] = { 0x03fc }, | |
3499 | [GCC_USB_HS_HSIC_BCR] = { 0x0400 }, | |
3500 | [GCC_USB_HS_BCR] = { 0x0480 }, | |
3501 | [GCC_USB2A_PHY_BCR] = { 0x04a8 }, | |
3502 | [GCC_USB2B_PHY_BCR] = { 0x04b0 }, | |
3503 | [GCC_SDCC1_BCR] = { 0x04c0 }, | |
3504 | [GCC_SDCC2_BCR] = { 0x0500 }, | |
3505 | [GCC_SDCC3_BCR] = { 0x0540 }, | |
3506 | [GCC_SDCC4_BCR] = { 0x0580 }, | |
3507 | [GCC_BLSP1_BCR] = { 0x05c0 }, | |
3508 | [GCC_BLSP1_QUP1_BCR] = { 0x0640 }, | |
3509 | [GCC_BLSP1_UART1_BCR] = { 0x0680 }, | |
3510 | [GCC_BLSP1_QUP2_BCR] = { 0x06c0 }, | |
3511 | [GCC_BLSP1_UART2_BCR] = { 0x0700 }, | |
3512 | [GCC_BLSP1_QUP3_BCR] = { 0x0740 }, | |
3513 | [GCC_BLSP1_UART3_BCR] = { 0x0780 }, | |
3514 | [GCC_BLSP1_QUP4_BCR] = { 0x07c0 }, | |
3515 | [GCC_BLSP1_UART4_BCR] = { 0x0800 }, | |
3516 | [GCC_BLSP1_QUP5_BCR] = { 0x0840 }, | |
3517 | [GCC_BLSP1_UART5_BCR] = { 0x0880 }, | |
3518 | [GCC_BLSP1_QUP6_BCR] = { 0x08c0 }, | |
3519 | [GCC_BLSP1_UART6_BCR] = { 0x0900 }, | |
3520 | [GCC_BLSP2_BCR] = { 0x0940 }, | |
3521 | [GCC_BLSP2_QUP1_BCR] = { 0x0980 }, | |
3522 | [GCC_BLSP2_UART1_BCR] = { 0x09c0 }, | |
3523 | [GCC_BLSP2_QUP2_BCR] = { 0x0a00 }, | |
3524 | [GCC_BLSP2_UART2_BCR] = { 0x0a40 }, | |
3525 | [GCC_BLSP2_QUP3_BCR] = { 0x0a80 }, | |
3526 | [GCC_BLSP2_UART3_BCR] = { 0x0ac0 }, | |
3527 | [GCC_BLSP2_QUP4_BCR] = { 0x0b00 }, | |
3528 | [GCC_BLSP2_UART4_BCR] = { 0x0b40 }, | |
3529 | [GCC_BLSP2_QUP5_BCR] = { 0x0b80 }, | |
3530 | [GCC_BLSP2_UART5_BCR] = { 0x0bc0 }, | |
3531 | [GCC_BLSP2_QUP6_BCR] = { 0x0c00 }, | |
3532 | [GCC_BLSP2_UART6_BCR] = { 0x0c40 }, | |
3533 | [GCC_PDM_BCR] = { 0x0cc0 }, | |
3534 | [GCC_PRNG_BCR] = { 0x0d00 }, | |
3535 | [GCC_BAM_DMA_BCR] = { 0x0d40 }, | |
3536 | [GCC_TSIF_BCR] = { 0x0d80 }, | |
3537 | [GCC_TCSR_BCR] = { 0x0dc0 }, | |
3538 | [GCC_BOOT_ROM_BCR] = { 0x0e00 }, | |
3539 | [GCC_MSG_RAM_BCR] = { 0x0e40 }, | |
3540 | [GCC_TLMM_BCR] = { 0x0e80 }, | |
3541 | [GCC_MPM_BCR] = { 0x0ec0 }, | |
3542 | [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 }, | |
3543 | [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 }, | |
3544 | [GCC_SEC_CTRL_BCR] = { 0x0f40 }, | |
3545 | [GCC_SPMI_BCR] = { 0x0fc0 }, | |
3546 | [GCC_SPDM_BCR] = { 0x1000 }, | |
3547 | [GCC_CE1_BCR] = { 0x1040 }, | |
3548 | [GCC_CE2_BCR] = { 0x1080 }, | |
3549 | [GCC_BIMC_BCR] = { 0x1100 }, | |
3550 | [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 }, | |
3551 | [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 }, | |
3552 | [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 }, | |
3553 | [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 }, | |
3554 | [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 }, | |
3555 | [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 }, | |
3556 | [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 }, | |
3557 | [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 }, | |
3558 | [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 }, | |
3559 | [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 }, | |
3560 | [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 }, | |
3561 | [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 }, | |
3562 | [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 }, | |
3563 | [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 }, | |
3564 | [GCC_DEHR_BCR] = { 0x1300 }, | |
3565 | [GCC_RBCPR_BCR] = { 0x1380 }, | |
3566 | [GCC_MSS_RESTART] = { 0x1680 }, | |
3567 | [GCC_LPASS_RESTART] = { 0x16c0 }, | |
3568 | [GCC_WCSS_RESTART] = { 0x1700 }, | |
3569 | [GCC_VENUS_RESTART] = { 0x1740 }, | |
3570 | [GCC_COPSS_SMMU_BCR] = { 0x1a40 }, | |
3571 | [GCC_SPSS_BCR] = { 0x1a80 }, | |
3572 | [GCC_PCIE_0_BCR] = { 0x1ac0 }, | |
3573 | [GCC_PCIE_0_PHY_BCR] = { 0x1b00 }, | |
3574 | [GCC_PCIE_1_BCR] = { 0x1b40 }, | |
3575 | [GCC_PCIE_1_PHY_BCR] = { 0x1b80 }, | |
3576 | [GCC_USB_30_SEC_BCR] = { 0x1bc0 }, | |
3577 | [GCC_USB3_SEC_PHY_BCR] = { 0x1bfc }, | |
3578 | [GCC_SATA_BCR] = { 0x1c40 }, | |
3579 | [GCC_CE3_BCR] = { 0x1d00 }, | |
3580 | [GCC_UFS_BCR] = { 0x1d40 }, | |
3581 | [GCC_USB30_PHY_COM_BCR] = { 0x1e80 }, | |
3582 | }; | |
3583 | ||
3584 | static const struct regmap_config gcc_apq8084_regmap_config = { | |
3585 | .reg_bits = 32, | |
3586 | .reg_stride = 4, | |
3587 | .val_bits = 32, | |
3588 | .max_register = 0x1fc0, | |
3589 | .fast_io = true, | |
3590 | }; | |
3591 | ||
3592 | static const struct qcom_cc_desc gcc_apq8084_desc = { | |
3593 | .config = &gcc_apq8084_regmap_config, | |
3594 | .clks = gcc_apq8084_clocks, | |
3595 | .num_clks = ARRAY_SIZE(gcc_apq8084_clocks), | |
3596 | .resets = gcc_apq8084_resets, | |
3597 | .num_resets = ARRAY_SIZE(gcc_apq8084_resets), | |
639af949 RN |
3598 | .gdscs = gcc_apq8084_gdscs, |
3599 | .num_gdscs = ARRAY_SIZE(gcc_apq8084_gdscs), | |
02824653 GD |
3600 | }; |
3601 | ||
3602 | static const struct of_device_id gcc_apq8084_match_table[] = { | |
3603 | { .compatible = "qcom,gcc-apq8084" }, | |
3604 | { } | |
3605 | }; | |
3606 | MODULE_DEVICE_TABLE(of, gcc_apq8084_match_table); | |
3607 | ||
3608 | static int gcc_apq8084_probe(struct platform_device *pdev) | |
3609 | { | |
3610 | struct clk *clk; | |
3611 | struct device *dev = &pdev->dev; | |
3612 | ||
3613 | /* Temporary until RPM clocks supported */ | |
3614 | clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000); | |
3615 | if (IS_ERR(clk)) | |
3616 | return PTR_ERR(clk); | |
3617 | ||
3618 | clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL, | |
3619 | CLK_IS_ROOT, 32768); | |
3620 | if (IS_ERR(clk)) | |
3621 | return PTR_ERR(clk); | |
3622 | ||
3623 | return qcom_cc_probe(pdev, &gcc_apq8084_desc); | |
3624 | } | |
3625 | ||
02824653 GD |
3626 | static struct platform_driver gcc_apq8084_driver = { |
3627 | .probe = gcc_apq8084_probe, | |
02824653 GD |
3628 | .driver = { |
3629 | .name = "gcc-apq8084", | |
02824653 GD |
3630 | .of_match_table = gcc_apq8084_match_table, |
3631 | }, | |
3632 | }; | |
3633 | ||
3634 | static int __init gcc_apq8084_init(void) | |
3635 | { | |
3636 | return platform_driver_register(&gcc_apq8084_driver); | |
3637 | } | |
3638 | core_initcall(gcc_apq8084_init); | |
3639 | ||
3640 | static void __exit gcc_apq8084_exit(void) | |
3641 | { | |
3642 | platform_driver_unregister(&gcc_apq8084_driver); | |
3643 | } | |
3644 | module_exit(gcc_apq8084_exit); | |
3645 | ||
3646 | MODULE_DESCRIPTION("QCOM GCC APQ8084 Driver"); | |
3647 | MODULE_LICENSE("GPL v2"); | |
3648 | MODULE_ALIAS("platform:gcc-apq8084"); |