[mirror_ubuntu-zesty-kernel.git] / drivers / clk / qcom / gdsc.c

/*
 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/ktime.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include "gdsc.h"

#define PWR_ON_MASK		BIT(31)
#define EN_REST_WAIT_MASK	GENMASK_ULL(23, 20)
#define EN_FEW_WAIT_MASK	GENMASK_ULL(19, 16)
#define CLK_DIS_WAIT_MASK	GENMASK_ULL(15, 12)
#define SW_OVERRIDE_MASK	BIT(2)
#define HW_CONTROL_MASK		BIT(1)
#define SW_COLLAPSE_MASK	BIT(0)
#define GMEM_CLAMP_IO_MASK	BIT(0)

/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
#define EN_REST_WAIT_VAL	(0x2 << 20)
#define EN_FEW_WAIT_VAL		(0x8 << 16)
#define CLK_DIS_WAIT_VAL	(0x2 << 12)

#define RETAIN_MEM		BIT(14)
#define RETAIN_PERIPH		BIT(13)

#define TIMEOUT_US		100

#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)

static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
{
	u32 val;
	int ret;

	ret = regmap_read(sc->regmap, reg, &val);
	if (ret)
		return ret;

	return !!(val & PWR_ON_MASK);
}

static int gdsc_hwctrl(struct gdsc *sc, bool en)
{
	u32 val = en ? HW_CONTROL_MASK : 0;

	return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
}

static int gdsc_toggle_logic(struct gdsc *sc, bool en)
{
	int ret;
	u32 val = en ? 0 : SW_COLLAPSE_MASK;
	ktime_t start;
	unsigned int status_reg = sc->gdscr;

	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
	if (ret)
		return ret;

	/* If disabling votable gdscs, don't poll on status */
	if ((sc->flags & VOTABLE) && !en) {
		/*
		 * Add a short delay here to ensure that an enable
		 * right after it was disabled does not put it in an
		 * unknown state
		 */
		udelay(TIMEOUT_US);
		return 0;
	}

	if (sc->gds_hw_ctrl) {
		status_reg = sc->gds_hw_ctrl;
		/*
		 * The gds hw controller asserts/de-asserts the status bit soon
		 * after it receives a power on/off request from a master.
		 * The controller then takes around 8 xo cycles to start its
		 * internal state machine and update the status bit. During
		 * this time, the status bit does not reflect the true status
		 * of the core.
		 * Add a delay of 1 us between writing to the SW_COLLAPSE bit
		 * and polling the status bit.
		 */
		udelay(1);
	}

	start = ktime_get();
	do {
		if (gdsc_is_enabled(sc, status_reg) == en)
			return 0;
	} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);

	if (gdsc_is_enabled(sc, status_reg) == en)
		return 0;

	return -ETIMEDOUT;
}

static inline int gdsc_deassert_reset(struct gdsc *sc)
{
	int i;

	for (i = 0; i < sc->reset_count; i++)
		sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
	return 0;
}

static inline int gdsc_assert_reset(struct gdsc *sc)
{
	int i;

	for (i = 0; i < sc->reset_count; i++)
		sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
	return 0;
}

static inline void gdsc_force_mem_on(struct gdsc *sc)
{
	int i;
	u32 mask = RETAIN_MEM | RETAIN_PERIPH;

	for (i = 0; i < sc->cxc_count; i++)
		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
}

static inline void gdsc_clear_mem_on(struct gdsc *sc)
{
	int i;
	u32 mask = RETAIN_MEM | RETAIN_PERIPH;

	for (i = 0; i < sc->cxc_count; i++)
		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
}

static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
{
	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
			   GMEM_CLAMP_IO_MASK, 0);
}

static inline void gdsc_assert_clamp_io(struct gdsc *sc)
{
	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
			   GMEM_CLAMP_IO_MASK, 1);
}

static int gdsc_enable(struct generic_pm_domain *domain)
{
	struct gdsc *sc = domain_to_gdsc(domain);
	int ret;

	if (sc->pwrsts == PWRSTS_ON)
		return gdsc_deassert_reset(sc);

	if (sc->flags & CLAMP_IO)
		gdsc_deassert_clamp_io(sc);

	ret = gdsc_toggle_logic(sc, true);
	if (ret)
		return ret;

	if (sc->pwrsts & PWRSTS_OFF)
		gdsc_force_mem_on(sc);

	/*
	 * If clocks to this power domain were already on, they will take an
	 * additional 4 clock cycles to re-enable after the power domain is
	 * enabled. Delay to account for this. A delay is also needed to ensure
	 * clocks are not enabled within 400ns of enabling power to the
	 * memories.
	 */
	udelay(1);

	/* Turn on HW trigger mode if supported */
	if (sc->flags & HW_CTRL)
		return gdsc_hwctrl(sc, true);

	return 0;
}

static int gdsc_disable(struct generic_pm_domain *domain)
{
	struct gdsc *sc = domain_to_gdsc(domain);
	int ret;

	if (sc->pwrsts == PWRSTS_ON)
		return gdsc_assert_reset(sc);

	/* Turn off HW trigger mode if supported */
	if (sc->flags & HW_CTRL) {
		ret = gdsc_hwctrl(sc, false);
		if (ret < 0)
			return ret;
	}

	if (sc->pwrsts & PWRSTS_OFF)
		gdsc_clear_mem_on(sc);

	ret = gdsc_toggle_logic(sc, false);
	if (ret)
		return ret;

	if (sc->flags & CLAMP_IO)
		gdsc_assert_clamp_io(sc);

	return 0;
}

static int gdsc_init(struct gdsc *sc)
{
	u32 mask, val;
	int on, ret;
	unsigned int reg;

	/*
	 * Disable HW trigger: collapse/restore occur based on registers writes.
	 * Disable SW override: Use hardware state-machine for sequencing.
	 * Configure wait time between states.
	 */
	mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
	       EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
	val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
	if (ret)
		return ret;

	/* Force gdsc ON if only ON state is supported */
	if (sc->pwrsts == PWRSTS_ON) {
		ret = gdsc_toggle_logic(sc, true);
		if (ret)
			return ret;
	}

	reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
	on = gdsc_is_enabled(sc, reg);
	if (on < 0)
		return on;

	/*
	 * Votable GDSCs can be ON due to Vote from other masters.
	 * If a Votable GDSC is ON, make sure we have a Vote.
	 */
	if ((sc->flags & VOTABLE) && on)
		gdsc_enable(&sc->pd);

	if (on || (sc->pwrsts & PWRSTS_RET))
		gdsc_force_mem_on(sc);
	else
		gdsc_clear_mem_on(sc);

	sc->pd.power_off = gdsc_disable;
	sc->pd.power_on = gdsc_enable;
	pm_genpd_init(&sc->pd, NULL, !on);

	return 0;
}

int gdsc_register(struct gdsc_desc *desc,
		  struct reset_controller_dev *rcdev, struct regmap *regmap)
{
	int i, ret;
	struct genpd_onecell_data *data;
	struct device *dev = desc->dev;
	struct gdsc **scs = desc->scs;
	size_t num = desc->num;

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
				     GFP_KERNEL);
	if (!data->domains)
		return -ENOMEM;

	data->num_domains = num;
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		scs[i]->regmap = regmap;
		scs[i]->rcdev = rcdev;
		ret = gdsc_init(scs[i]);
		if (ret)
			return ret;
		data->domains[i] = &scs[i]->pd;
	}

	/* Add subdomains */
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		if (scs[i]->parent)
			pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
	}

	return of_genpd_add_provider_onecell(dev->of_node, data);
}

void gdsc_unregister(struct gdsc_desc *desc)
{
	int i;
	struct device *dev = desc->dev;
	struct gdsc **scs = desc->scs;
	size_t num = desc->num;

	/* Remove subdomains */
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		if (scs[i]->parent)
			pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
	}
	of_genpd_del_provider(dev->of_node);
}
Commit	Line	Data
45dd0e55 SB	1	/*
	2	* Copyright (c) 2015, The Linux Foundation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/bitops.h>
	15	#include <linux/delay.h>
	16	#include <linux/err.h>
	17	#include <linux/jiffies.h>
	18	#include <linux/kernel.h>
77b1067a	19	#include <linux/ktime.h>
45dd0e55 SB	20	#include <linux/pm_domain.h>
45dd0e55 SB	21	#include <linux/regmap.h>
3c53f5e2	22	#include <linux/reset-controller.h>
45dd0e55 SB	23	#include <linux/slab.h>
	24	#include "gdsc.h"
	25
	26	#define PWR_ON_MASK BIT(31)
	27	#define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
	28	#define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
	29	#define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
	30	#define SW_OVERRIDE_MASK BIT(2)
	31	#define HW_CONTROL_MASK BIT(1)
	32	#define SW_COLLAPSE_MASK BIT(0)
e7cc455f	33	#define GMEM_CLAMP_IO_MASK BIT(0)
45dd0e55 SB	34
	35	/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
	36	#define EN_REST_WAIT_VAL (0x2 << 20)
	37	#define EN_FEW_WAIT_VAL (0x8 << 16)
	38	#define CLK_DIS_WAIT_VAL (0x2 << 12)
	39
014e193c RN	40	#define RETAIN_MEM BIT(14)
	41	#define RETAIN_PERIPH BIT(13)
	42
45dd0e55 SB	43	#define TIMEOUT_US 100
	44
	45	#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
	46
77b1067a	47	static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
45dd0e55 SB	48	{
	49	u32 val;
	50	int ret;
	51
77b1067a	52	ret = regmap_read(sc->regmap, reg, &val);
45dd0e55 SB	53	if (ret)
	54	return ret;
	55
	56	return !!(val & PWR_ON_MASK);
	57	}
	58
904bb4f5 RN	59	static int gdsc_hwctrl(struct gdsc *sc, bool en)
	60	{
	61	u32 val = en ? HW_CONTROL_MASK : 0;
	62
	63	return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
	64	}
	65
45dd0e55 SB	66	static int gdsc_toggle_logic(struct gdsc *sc, bool en)
	67	{
	68	int ret;
	69	u32 val = en ? 0 : SW_COLLAPSE_MASK;
77b1067a RN	70	ktime_t start;
77b1067a RN	71	unsigned int status_reg = sc->gdscr;
45dd0e55 SB	72
	73	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
	74	if (ret)
	75	return ret;
	76
a823bb9f RN	77	/* If disabling votable gdscs, don't poll on status */
	78	if ((sc->flags & VOTABLE) && !en) {
	79	/*
	80	* Add a short delay here to ensure that an enable
	81	* right after it was disabled does not put it in an
	82	* unknown state
	83	*/
	84	udelay(TIMEOUT_US);
	85	return 0;
	86	}
	87
77b1067a RN	88	if (sc->gds_hw_ctrl) {
	89	status_reg = sc->gds_hw_ctrl;
	90	/*
	91	* The gds hw controller asserts/de-asserts the status bit soon
	92	* after it receives a power on/off request from a master.
	93	* The controller then takes around 8 xo cycles to start its
	94	* internal state machine and update the status bit. During
	95	* this time, the status bit does not reflect the true status
	96	* of the core.
	97	* Add a delay of 1 us between writing to the SW_COLLAPSE bit
	98	* and polling the status bit.
	99	*/
	100	udelay(1);
	101	}
45dd0e55	102
77b1067a RN	103	start = ktime_get();
	104	do {
	105	if (gdsc_is_enabled(sc, status_reg) == en)
45dd0e55	106	return 0;
77b1067a	107	} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
45dd0e55	108
77b1067a	109	if (gdsc_is_enabled(sc, status_reg) == en)
45dd0e55 SB	110	return 0;
	111
	112	return -ETIMEDOUT;
	113	}
	114
3c53f5e2 RN	115	static inline int gdsc_deassert_reset(struct gdsc *sc)
	116	{
	117	int i;
	118
	119	for (i = 0; i < sc->reset_count; i++)
	120	sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
	121	return 0;
	122	}
	123
	124	static inline int gdsc_assert_reset(struct gdsc *sc)
	125	{
	126	int i;
	127
	128	for (i = 0; i < sc->reset_count; i++)
	129	sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
	130	return 0;
	131	}
	132
014e193c RN	133	static inline void gdsc_force_mem_on(struct gdsc *sc)
	134	{
	135	int i;
	136	u32 mask = RETAIN_MEM \| RETAIN_PERIPH;
	137
	138	for (i = 0; i < sc->cxc_count; i++)
	139	regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
	140	}
	141
	142	static inline void gdsc_clear_mem_on(struct gdsc *sc)
	143	{
	144	int i;
	145	u32 mask = RETAIN_MEM \| RETAIN_PERIPH;
	146
	147	for (i = 0; i < sc->cxc_count; i++)
	148	regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
	149	}
	150
e7cc455f RN	151	static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
	152	{
	153	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
	154	GMEM_CLAMP_IO_MASK, 0);
	155	}
	156
	157	static inline void gdsc_assert_clamp_io(struct gdsc *sc)
	158	{
	159	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
	160	GMEM_CLAMP_IO_MASK, 1);
	161	}
	162
45dd0e55 SB	163	static int gdsc_enable(struct generic_pm_domain *domain)
	164	{
	165	struct gdsc *sc = domain_to_gdsc(domain);
	166	int ret;
	167
3c53f5e2 RN	168	if (sc->pwrsts == PWRSTS_ON)
	169	return gdsc_deassert_reset(sc);
	170
e7cc455f RN	171	if (sc->flags & CLAMP_IO)
	172	gdsc_deassert_clamp_io(sc);
	173
45dd0e55 SB	174	ret = gdsc_toggle_logic(sc, true);
	175	if (ret)
	176	return ret;
014e193c RN	177
	178	if (sc->pwrsts & PWRSTS_OFF)
	179	gdsc_force_mem_on(sc);
	180
45dd0e55 SB	181	/*
	182	* If clocks to this power domain were already on, they will take an
	183	* additional 4 clock cycles to re-enable after the power domain is
	184	* enabled. Delay to account for this. A delay is also needed to ensure
	185	* clocks are not enabled within 400ns of enabling power to the
	186	* memories.
	187	*/
	188	udelay(1);
	189
904bb4f5 RN	190	/* Turn on HW trigger mode if supported */
	191	if (sc->flags & HW_CTRL)
	192	return gdsc_hwctrl(sc, true);
	193
45dd0e55 SB	194	return 0;
	195	}
	196
	197	static int gdsc_disable(struct generic_pm_domain *domain)
	198	{
	199	struct gdsc *sc = domain_to_gdsc(domain);
e7cc455f	200	int ret;
45dd0e55	201
3c53f5e2 RN	202	if (sc->pwrsts == PWRSTS_ON)
	203	return gdsc_assert_reset(sc);
	204
904bb4f5 RN	205	/* Turn off HW trigger mode if supported */
	206	if (sc->flags & HW_CTRL) {
	207	ret = gdsc_hwctrl(sc, false);
	208	if (ret < 0)
	209	return ret;
	210	}
	211
014e193c RN	212	if (sc->pwrsts & PWRSTS_OFF)
	213	gdsc_clear_mem_on(sc);
	214
e7cc455f RN	215	ret = gdsc_toggle_logic(sc, false);
	216	if (ret)
	217	return ret;
	218
	219	if (sc->flags & CLAMP_IO)
	220	gdsc_assert_clamp_io(sc);
	221
	222	return 0;
45dd0e55 SB	223	}
	224
	225	static int gdsc_init(struct gdsc *sc)
	226	{
	227	u32 mask, val;
	228	int on, ret;
77b1067a	229	unsigned int reg;
45dd0e55 SB	230
	231	/*
	232	* Disable HW trigger: collapse/restore occur based on registers writes.
	233	* Disable SW override: Use hardware state-machine for sequencing.
	234	* Configure wait time between states.
	235	*/
	236	mask = HW_CONTROL_MASK \| SW_OVERRIDE_MASK \|
	237	EN_REST_WAIT_MASK \| EN_FEW_WAIT_MASK \| CLK_DIS_WAIT_MASK;
	238	val = EN_REST_WAIT_VAL \| EN_FEW_WAIT_VAL \| CLK_DIS_WAIT_VAL;
	239	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
	240	if (ret)
	241	return ret;
	242
3c53f5e2 RN	243	/* Force gdsc ON if only ON state is supported */
	244	if (sc->pwrsts == PWRSTS_ON) {
	245	ret = gdsc_toggle_logic(sc, true);
	246	if (ret)
	247	return ret;
	248	}
	249
77b1067a RN	250	reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
77b1067a RN	251	on = gdsc_is_enabled(sc, reg);
45dd0e55 SB	252	if (on < 0)
	253	return on;
	254
a823bb9f RN	255	/*
	256	* Votable GDSCs can be ON due to Vote from other masters.
	257	* If a Votable GDSC is ON, make sure we have a Vote.
	258	*/
	259	if ((sc->flags & VOTABLE) && on)
	260	gdsc_enable(&sc->pd);
	261
014e193c RN	262	if (on \|\| (sc->pwrsts & PWRSTS_RET))
	263	gdsc_force_mem_on(sc);
	264	else
	265	gdsc_clear_mem_on(sc);
	266
45dd0e55 SB	267	sc->pd.power_off = gdsc_disable;
	268	sc->pd.power_on = gdsc_enable;
	269	pm_genpd_init(&sc->pd, NULL, !on);
	270
	271	return 0;
	272	}
	273
c2c7f0a4	274	int gdsc_register(struct gdsc_desc *desc,
3c53f5e2	275	struct reset_controller_dev rcdev, struct regmap regmap)
45dd0e55 SB	276	{
	277	int i, ret;
	278	struct genpd_onecell_data *data;
c2c7f0a4 RN	279	struct device *dev = desc->dev;
	280	struct gdsc **scs = desc->scs;
	281	size_t num = desc->num;
45dd0e55 SB	282
	283	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	284	if (!data)
	285	return -ENOMEM;
	286
	287	data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
	288	GFP_KERNEL);
	289	if (!data->domains)
	290	return -ENOMEM;
	291
	292	data->num_domains = num;
	293	for (i = 0; i < num; i++) {
	294	if (!scs[i])
	295	continue;
	296	scs[i]->regmap = regmap;
3c53f5e2	297	scs[i]->rcdev = rcdev;
45dd0e55 SB	298	ret = gdsc_init(scs[i]);
	299	if (ret)
	300	return ret;
	301	data->domains[i] = &scs[i]->pd;
	302	}
	303
c2c7f0a4 RN	304	/* Add subdomains */
	305	for (i = 0; i < num; i++) {
	306	if (!scs[i])
	307	continue;
	308	if (scs[i]->parent)
	309	pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
	310	}
	311
45dd0e55 SB	312	return of_genpd_add_provider_onecell(dev->of_node, data);
	313	}
	314
c2c7f0a4	315	void gdsc_unregister(struct gdsc_desc *desc)
45dd0e55	316	{
c2c7f0a4 RN	317	int i;
	318	struct device *dev = desc->dev;
	319	struct gdsc **scs = desc->scs;
	320	size_t num = desc->num;
	321
	322	/* Remove subdomains */
	323	for (i = 0; i < num; i++) {
	324	if (!scs[i])
	325	continue;
	326	if (scs[i]->parent)
	327	pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
	328	}
45dd0e55 SB	329	of_genpd_del_provider(dev->of_node);
45dd0e55 SB	330	}