[mirror_ubuntu-jammy-kernel.git] / drivers / clk / qcom / gdsc.c

/*
 * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/ktime.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
#include "gdsc.h"

#define PWR_ON_MASK		BIT(31)
#define EN_REST_WAIT_MASK	GENMASK_ULL(23, 20)
#define EN_FEW_WAIT_MASK	GENMASK_ULL(19, 16)
#define CLK_DIS_WAIT_MASK	GENMASK_ULL(15, 12)
#define SW_OVERRIDE_MASK	BIT(2)
#define HW_CONTROL_MASK		BIT(1)
#define SW_COLLAPSE_MASK	BIT(0)
#define GMEM_CLAMP_IO_MASK	BIT(0)
#define GMEM_RESET_MASK		BIT(4)

/* CFG_GDSCR */
#define GDSC_POWER_UP_COMPLETE		BIT(16)
#define GDSC_POWER_DOWN_COMPLETE	BIT(15)
#define CFG_GDSCR_OFFSET		0x4

/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
#define EN_REST_WAIT_VAL	(0x2 << 20)
#define EN_FEW_WAIT_VAL		(0x8 << 16)
#define CLK_DIS_WAIT_VAL	(0x2 << 12)

#define RETAIN_MEM		BIT(14)
#define RETAIN_PERIPH		BIT(13)

#define TIMEOUT_US		500

#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)

enum gdsc_status {
	GDSC_OFF,
	GDSC_ON
};

/* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
{
	unsigned int reg;
	u32 val;
	int ret;

	if (sc->flags & POLL_CFG_GDSCR)
		reg = sc->gdscr + CFG_GDSCR_OFFSET;
	else if (sc->gds_hw_ctrl)
		reg = sc->gds_hw_ctrl;
	else
		reg = sc->gdscr;

	ret = regmap_read(sc->regmap, reg, &val);
	if (ret)
		return ret;

	if (sc->flags & POLL_CFG_GDSCR) {
		switch (status) {
		case GDSC_ON:
			return !!(val & GDSC_POWER_UP_COMPLETE);
		case GDSC_OFF:
			return !!(val & GDSC_POWER_DOWN_COMPLETE);
		}
	}

	switch (status) {
	case GDSC_ON:
		return !!(val & PWR_ON_MASK);
	case GDSC_OFF:
		return !(val & PWR_ON_MASK);
	}

	return -EINVAL;
}

static int gdsc_hwctrl(struct gdsc *sc, bool en)
{
	u32 val = en ? HW_CONTROL_MASK : 0;

	return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
}

static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
{
	ktime_t start;

	start = ktime_get();
	do {
		if (gdsc_check_status(sc, status))
			return 0;
	} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);

	if (gdsc_check_status(sc, status))
		return 0;

	return -ETIMEDOUT;
}

static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
{
	int ret;
	u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;

	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
	if (ret)
		return ret;

	/* If disabling votable gdscs, don't poll on status */
	if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
		/*
		 * Add a short delay here to ensure that an enable
		 * right after it was disabled does not put it in an
		 * unknown state
		 */
		udelay(TIMEOUT_US);
		return 0;
	}

	if (sc->gds_hw_ctrl) {
		/*
		 * The gds hw controller asserts/de-asserts the status bit soon
		 * after it receives a power on/off request from a master.
		 * The controller then takes around 8 xo cycles to start its
		 * internal state machine and update the status bit. During
		 * this time, the status bit does not reflect the true status
		 * of the core.
		 * Add a delay of 1 us between writing to the SW_COLLAPSE bit
		 * and polling the status bit.
		 */
		udelay(1);
	}

	return gdsc_poll_status(sc, status);
}

static inline int gdsc_deassert_reset(struct gdsc *sc)
{
	int i;

	for (i = 0; i < sc->reset_count; i++)
		sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
	return 0;
}

static inline int gdsc_assert_reset(struct gdsc *sc)
{
	int i;

	for (i = 0; i < sc->reset_count; i++)
		sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
	return 0;
}

static inline void gdsc_force_mem_on(struct gdsc *sc)
{
	int i;
	u32 mask = RETAIN_MEM | RETAIN_PERIPH;

	for (i = 0; i < sc->cxc_count; i++)
		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
}

static inline void gdsc_clear_mem_on(struct gdsc *sc)
{
	int i;
	u32 mask = RETAIN_MEM | RETAIN_PERIPH;

	for (i = 0; i < sc->cxc_count; i++)
		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
}

static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
{
	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
			   GMEM_CLAMP_IO_MASK, 0);
}

static inline void gdsc_assert_clamp_io(struct gdsc *sc)
{
	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
			   GMEM_CLAMP_IO_MASK, 1);
}

static inline void gdsc_assert_reset_aon(struct gdsc *sc)
{
	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
			   GMEM_RESET_MASK, 1);
	udelay(1);
	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
			   GMEM_RESET_MASK, 0);
}
static int gdsc_enable(struct generic_pm_domain *domain)
{
	struct gdsc *sc = domain_to_gdsc(domain);
	int ret;

	if (sc->pwrsts == PWRSTS_ON)
		return gdsc_deassert_reset(sc);

	if (sc->flags & SW_RESET) {
		gdsc_assert_reset(sc);
		udelay(1);
		gdsc_deassert_reset(sc);
	}

	if (sc->flags & CLAMP_IO) {
		if (sc->flags & AON_RESET)
			gdsc_assert_reset_aon(sc);
		gdsc_deassert_clamp_io(sc);
	}

	ret = gdsc_toggle_logic(sc, GDSC_ON);
	if (ret)
		return ret;

	if (sc->pwrsts & PWRSTS_OFF)
		gdsc_force_mem_on(sc);

	/*
	 * If clocks to this power domain were already on, they will take an
	 * additional 4 clock cycles to re-enable after the power domain is
	 * enabled. Delay to account for this. A delay is also needed to ensure
	 * clocks are not enabled within 400ns of enabling power to the
	 * memories.
	 */
	udelay(1);

	/* Turn on HW trigger mode if supported */
	if (sc->flags & HW_CTRL) {
		ret = gdsc_hwctrl(sc, true);
		if (ret)
			return ret;
		/*
		 * Wait for the GDSC to go through a power down and
		 * up cycle.  In case a firmware ends up polling status
		 * bits for the gdsc, it might read an 'on' status before
		 * the GDSC can finish the power cycle.
		 * We wait 1us before returning to ensure the firmware
		 * can't immediately poll the status bits.
		 */
		udelay(1);
	}

	return 0;
}

static int gdsc_disable(struct generic_pm_domain *domain)
{
	struct gdsc *sc = domain_to_gdsc(domain);
	int ret;

	if (sc->pwrsts == PWRSTS_ON)
		return gdsc_assert_reset(sc);

	/* Turn off HW trigger mode if supported */
	if (sc->flags & HW_CTRL) {
		ret = gdsc_hwctrl(sc, false);
		if (ret < 0)
			return ret;
		/*
		 * Wait for the GDSC to go through a power down and
		 * up cycle.  In case we end up polling status
		 * bits for the gdsc before the power cycle is completed
		 * it might read an 'on' status wrongly.
		 */
		udelay(1);

		ret = gdsc_poll_status(sc, GDSC_ON);
		if (ret)
			return ret;
	}

	if (sc->pwrsts & PWRSTS_OFF)
		gdsc_clear_mem_on(sc);

	ret = gdsc_toggle_logic(sc, GDSC_OFF);
	if (ret)
		return ret;

	if (sc->flags & CLAMP_IO)
		gdsc_assert_clamp_io(sc);

	return 0;
}

static int gdsc_init(struct gdsc *sc)
{
	u32 mask, val;
	int on, ret;

	/*
	 * Disable HW trigger: collapse/restore occur based on registers writes.
	 * Disable SW override: Use hardware state-machine for sequencing.
	 * Configure wait time between states.
	 */
	mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
	       EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
	val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
	if (ret)
		return ret;

	/* Force gdsc ON if only ON state is supported */
	if (sc->pwrsts == PWRSTS_ON) {
		ret = gdsc_toggle_logic(sc, GDSC_ON);
		if (ret)
			return ret;
	}

	on = gdsc_check_status(sc, GDSC_ON);
	if (on < 0)
		return on;

	/*
	 * Votable GDSCs can be ON due to Vote from other masters.
	 * If a Votable GDSC is ON, make sure we have a Vote.
	 */
	if ((sc->flags & VOTABLE) && on)
		gdsc_enable(&sc->pd);

	/* If ALWAYS_ON GDSCs are not ON, turn them ON */
	if (sc->flags & ALWAYS_ON) {
		if (!on)
			gdsc_enable(&sc->pd);
		on = true;
		sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
	}

	if (on || (sc->pwrsts & PWRSTS_RET))
		gdsc_force_mem_on(sc);
	else
		gdsc_clear_mem_on(sc);

	if (!sc->pd.power_off)
		sc->pd.power_off = gdsc_disable;
	if (!sc->pd.power_on)
		sc->pd.power_on = gdsc_enable;
	pm_genpd_init(&sc->pd, NULL, !on);

	return 0;
}

int gdsc_register(struct gdsc_desc *desc,
		  struct reset_controller_dev *rcdev, struct regmap *regmap)
{
	int i, ret;
	struct genpd_onecell_data *data;
	struct device *dev = desc->dev;
	struct gdsc **scs = desc->scs;
	size_t num = desc->num;

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
				     GFP_KERNEL);
	if (!data->domains)
		return -ENOMEM;

	data->num_domains = num;
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		scs[i]->regmap = regmap;
		scs[i]->rcdev = rcdev;
		ret = gdsc_init(scs[i]);
		if (ret)
			return ret;
		data->domains[i] = &scs[i]->pd;
	}

	/* Add subdomains */
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		if (scs[i]->parent)
			pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
	}

	return of_genpd_add_provider_onecell(dev->of_node, data);
}

void gdsc_unregister(struct gdsc_desc *desc)
{
	int i;
	struct device *dev = desc->dev;
	struct gdsc **scs = desc->scs;
	size_t num = desc->num;

	/* Remove subdomains */
	for (i = 0; i < num; i++) {
		if (!scs[i])
			continue;
		if (scs[i]->parent)
			pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
	}
	of_genpd_del_provider(dev->of_node);
}
Commit	Line	Data
45dd0e55	1	/*
44dbeebf	2	* Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
45dd0e55 SB	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/bitops.h>
	15	#include <linux/delay.h>
	16	#include <linux/err.h>
	17	#include <linux/jiffies.h>
	18	#include <linux/kernel.h>
77b1067a	19	#include <linux/ktime.h>
45dd0e55 SB	20	#include <linux/pm_domain.h>
45dd0e55 SB	21	#include <linux/regmap.h>
3c53f5e2	22	#include <linux/reset-controller.h>
45dd0e55 SB	23	#include <linux/slab.h>
	24	#include "gdsc.h"
	25
	26	#define PWR_ON_MASK BIT(31)
	27	#define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
	28	#define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
	29	#define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
	30	#define SW_OVERRIDE_MASK BIT(2)
	31	#define HW_CONTROL_MASK BIT(1)
	32	#define SW_COLLAPSE_MASK BIT(0)
e7cc455f	33	#define GMEM_CLAMP_IO_MASK BIT(0)
44dbeebf	34	#define GMEM_RESET_MASK BIT(4)
45dd0e55	35
e892e17d AN	36	/* CFG_GDSCR */
	37	#define GDSC_POWER_UP_COMPLETE BIT(16)
	38	#define GDSC_POWER_DOWN_COMPLETE BIT(15)
	39	#define CFG_GDSCR_OFFSET 0x4
45dd0e55 SB	40
	41	/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
	42	#define EN_REST_WAIT_VAL (0x2 << 20)
	43	#define EN_FEW_WAIT_VAL (0x8 << 16)
	44	#define CLK_DIS_WAIT_VAL (0x2 << 12)
	45
014e193c RN	46	#define RETAIN_MEM BIT(14)
	47	#define RETAIN_PERIPH BIT(13)
	48
9fb38cae	49	#define TIMEOUT_US 500
45dd0e55 SB	50
	51	#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
	52
88051f55 SB	53	enum gdsc_status {
	54	GDSC_OFF,
	55	GDSC_ON
	56	};
	57
	58	/* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
	59	static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
45dd0e55	60	{
e892e17d	61	unsigned int reg;
45dd0e55 SB	62	u32 val;
	63	int ret;
	64
e892e17d AN	65	if (sc->flags & POLL_CFG_GDSCR)
e892e17d AN	66	reg = sc->gdscr + CFG_GDSCR_OFFSET;
88051f55 SB	67	else if (sc->gds_hw_ctrl)
88051f55 SB	68	reg = sc->gds_hw_ctrl;
e892e17d	69	else
88051f55	70	reg = sc->gdscr;
e892e17d	71
77b1067a	72	ret = regmap_read(sc->regmap, reg, &val);
45dd0e55 SB	73	if (ret)
	74	return ret;
	75
e892e17d	76	if (sc->flags & POLL_CFG_GDSCR) {
88051f55 SB	77	switch (status) {
88051f55 SB	78	case GDSC_ON:
e892e17d	79	return !!(val & GDSC_POWER_UP_COMPLETE);
88051f55 SB	80	case GDSC_OFF:
	81	return !!(val & GDSC_POWER_DOWN_COMPLETE);
	82	}
	83	}
	84
	85	switch (status) {
	86	case GDSC_ON:
	87	return !!(val & PWR_ON_MASK);
	88	case GDSC_OFF:
	89	return !(val & PWR_ON_MASK);
e892e17d AN	90	}
e892e17d AN	91
88051f55	92	return -EINVAL;
45dd0e55 SB	93	}
45dd0e55 SB	94
904bb4f5 RN	95	static int gdsc_hwctrl(struct gdsc *sc, bool en)
	96	{
	97	u32 val = en ? HW_CONTROL_MASK : 0;
	98
	99	return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
	100	}
	101
88051f55	102	static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
843be1e7 RN	103	{
	104	ktime_t start;
	105
	106	start = ktime_get();
	107	do {
88051f55	108	if (gdsc_check_status(sc, status))
843be1e7 RN	109	return 0;
	110	} while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
	111
88051f55	112	if (gdsc_check_status(sc, status))
843be1e7 RN	113	return 0;
	114
	115	return -ETIMEDOUT;
	116	}
	117
88051f55	118	static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
45dd0e55 SB	119	{
45dd0e55 SB	120	int ret;
88051f55	121	u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
45dd0e55 SB	122
	123	ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
	124	if (ret)
	125	return ret;
	126
a823bb9f	127	/* If disabling votable gdscs, don't poll on status */
88051f55	128	if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
a823bb9f RN	129	/*
	130	* Add a short delay here to ensure that an enable
	131	* right after it was disabled does not put it in an
	132	* unknown state
	133	*/
	134	udelay(TIMEOUT_US);
	135	return 0;
	136	}
	137
77b1067a	138	if (sc->gds_hw_ctrl) {
77b1067a RN	139	/*
	140	* The gds hw controller asserts/de-asserts the status bit soon
	141	* after it receives a power on/off request from a master.
	142	* The controller then takes around 8 xo cycles to start its
	143	* internal state machine and update the status bit. During
	144	* this time, the status bit does not reflect the true status
	145	* of the core.
	146	* Add a delay of 1 us between writing to the SW_COLLAPSE bit
	147	* and polling the status bit.
	148	*/
	149	udelay(1);
	150	}
45dd0e55	151
88051f55	152	return gdsc_poll_status(sc, status);
45dd0e55 SB	153	}
45dd0e55 SB	154
3c53f5e2 RN	155	static inline int gdsc_deassert_reset(struct gdsc *sc)
	156	{
	157	int i;
	158
	159	for (i = 0; i < sc->reset_count; i++)
	160	sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
	161	return 0;
	162	}
	163
	164	static inline int gdsc_assert_reset(struct gdsc *sc)
	165	{
	166	int i;
	167
	168	for (i = 0; i < sc->reset_count; i++)
	169	sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
	170	return 0;
	171	}
	172
014e193c RN	173	static inline void gdsc_force_mem_on(struct gdsc *sc)
	174	{
	175	int i;
	176	u32 mask = RETAIN_MEM \| RETAIN_PERIPH;
	177
	178	for (i = 0; i < sc->cxc_count; i++)
	179	regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
	180	}
	181
	182	static inline void gdsc_clear_mem_on(struct gdsc *sc)
	183	{
	184	int i;
	185	u32 mask = RETAIN_MEM \| RETAIN_PERIPH;
	186
	187	for (i = 0; i < sc->cxc_count; i++)
	188	regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
	189	}
	190
e7cc455f RN	191	static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
	192	{
	193	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
	194	GMEM_CLAMP_IO_MASK, 0);
	195	}
	196
	197	static inline void gdsc_assert_clamp_io(struct gdsc *sc)
	198	{
	199	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
	200	GMEM_CLAMP_IO_MASK, 1);
	201	}
	202
44dbeebf AN	203	static inline void gdsc_assert_reset_aon(struct gdsc *sc)
	204	{
	205	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
	206	GMEM_RESET_MASK, 1);
	207	udelay(1);
	208	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
	209	GMEM_RESET_MASK, 0);
	210	}
45dd0e55 SB	211	static int gdsc_enable(struct generic_pm_domain *domain)
	212	{
	213	struct gdsc *sc = domain_to_gdsc(domain);
	214	int ret;
	215
3c53f5e2 RN	216	if (sc->pwrsts == PWRSTS_ON)
	217	return gdsc_deassert_reset(sc);
	218
44dbeebf AN	219	if (sc->flags & SW_RESET) {
	220	gdsc_assert_reset(sc);
	221	udelay(1);
	222	gdsc_deassert_reset(sc);
	223	}
	224
	225	if (sc->flags & CLAMP_IO) {
	226	if (sc->flags & AON_RESET)
	227	gdsc_assert_reset_aon(sc);
e7cc455f	228	gdsc_deassert_clamp_io(sc);
44dbeebf	229	}
e7cc455f	230
88051f55	231	ret = gdsc_toggle_logic(sc, GDSC_ON);
45dd0e55 SB	232	if (ret)
45dd0e55 SB	233	return ret;
014e193c RN	234
	235	if (sc->pwrsts & PWRSTS_OFF)
	236	gdsc_force_mem_on(sc);
	237
45dd0e55 SB	238	/*
	239	* If clocks to this power domain were already on, they will take an
	240	* additional 4 clock cycles to re-enable after the power domain is
	241	* enabled. Delay to account for this. A delay is also needed to ensure
	242	* clocks are not enabled within 400ns of enabling power to the
	243	* memories.
	244	*/
	245	udelay(1);
	246
904bb4f5	247	/* Turn on HW trigger mode if supported */
843be1e7 RN	248	if (sc->flags & HW_CTRL) {
	249	ret = gdsc_hwctrl(sc, true);
	250	if (ret)
	251	return ret;
	252	/*
	253	* Wait for the GDSC to go through a power down and
	254	* up cycle. In case a firmware ends up polling status
	255	* bits for the gdsc, it might read an 'on' status before
	256	* the GDSC can finish the power cycle.
	257	* We wait 1us before returning to ensure the firmware
	258	* can't immediately poll the status bits.
	259	*/
	260	udelay(1);
	261	}
904bb4f5	262
45dd0e55 SB	263	return 0;
	264	}
	265
	266	static int gdsc_disable(struct generic_pm_domain *domain)
	267	{
	268	struct gdsc *sc = domain_to_gdsc(domain);
e7cc455f	269	int ret;
45dd0e55	270
3c53f5e2 RN	271	if (sc->pwrsts == PWRSTS_ON)
	272	return gdsc_assert_reset(sc);
	273
904bb4f5 RN	274	/* Turn off HW trigger mode if supported */
	275	if (sc->flags & HW_CTRL) {
	276	ret = gdsc_hwctrl(sc, false);
	277	if (ret < 0)
	278	return ret;
843be1e7 RN	279	/*
	280	* Wait for the GDSC to go through a power down and
	281	* up cycle. In case we end up polling status
	282	* bits for the gdsc before the power cycle is completed
	283	* it might read an 'on' status wrongly.
	284	*/
	285	udelay(1);
	286
88051f55	287	ret = gdsc_poll_status(sc, GDSC_ON);
843be1e7 RN	288	if (ret)
843be1e7 RN	289	return ret;
904bb4f5 RN	290	}
904bb4f5 RN	291
014e193c RN	292	if (sc->pwrsts & PWRSTS_OFF)
	293	gdsc_clear_mem_on(sc);
	294
88051f55	295	ret = gdsc_toggle_logic(sc, GDSC_OFF);
e7cc455f RN	296	if (ret)
	297	return ret;
	298
	299	if (sc->flags & CLAMP_IO)
	300	gdsc_assert_clamp_io(sc);
	301
	302	return 0;
45dd0e55 SB	303	}
	304
	305	static int gdsc_init(struct gdsc *sc)
	306	{
	307	u32 mask, val;
	308	int on, ret;
	309
	310	/*
	311	* Disable HW trigger: collapse/restore occur based on registers writes.
	312	* Disable SW override: Use hardware state-machine for sequencing.
	313	* Configure wait time between states.
	314	*/
	315	mask = HW_CONTROL_MASK \| SW_OVERRIDE_MASK \|
	316	EN_REST_WAIT_MASK \| EN_FEW_WAIT_MASK \| CLK_DIS_WAIT_MASK;
	317	val = EN_REST_WAIT_VAL \| EN_FEW_WAIT_VAL \| CLK_DIS_WAIT_VAL;
	318	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
	319	if (ret)
	320	return ret;
	321
3c53f5e2 RN	322	/* Force gdsc ON if only ON state is supported */
3c53f5e2 RN	323	if (sc->pwrsts == PWRSTS_ON) {
88051f55	324	ret = gdsc_toggle_logic(sc, GDSC_ON);
3c53f5e2 RN	325	if (ret)
	326	return ret;
	327	}
	328
88051f55	329	on = gdsc_check_status(sc, GDSC_ON);
45dd0e55 SB	330	if (on < 0)
	331	return on;
	332
a823bb9f RN	333	/*
	334	* Votable GDSCs can be ON due to Vote from other masters.
	335	* If a Votable GDSC is ON, make sure we have a Vote.
	336	*/
	337	if ((sc->flags & VOTABLE) && on)
	338	gdsc_enable(&sc->pd);
	339
fb55bea1 RN	340	/* If ALWAYS_ON GDSCs are not ON, turn them ON */
	341	if (sc->flags & ALWAYS_ON) {
	342	if (!on)
	343	gdsc_enable(&sc->pd);
	344	on = true;
	345	sc->pd.flags \|= GENPD_FLAG_ALWAYS_ON;
	346	}
	347
014e193c RN	348	if (on \|\| (sc->pwrsts & PWRSTS_RET))
	349	gdsc_force_mem_on(sc);
	350	else
	351	gdsc_clear_mem_on(sc);
	352
7895861a JC	353	if (!sc->pd.power_off)
	354	sc->pd.power_off = gdsc_disable;
	355	if (!sc->pd.power_on)
	356	sc->pd.power_on = gdsc_enable;
45dd0e55 SB	357	pm_genpd_init(&sc->pd, NULL, !on);
	358
	359	return 0;
	360	}
	361
c2c7f0a4	362	int gdsc_register(struct gdsc_desc *desc,
3c53f5e2	363	struct reset_controller_dev rcdev, struct regmap regmap)
45dd0e55 SB	364	{
	365	int i, ret;
	366	struct genpd_onecell_data *data;
c2c7f0a4 RN	367	struct device *dev = desc->dev;
	368	struct gdsc **scs = desc->scs;
	369	size_t num = desc->num;
45dd0e55 SB	370
	371	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	372	if (!data)
	373	return -ENOMEM;
	374
	375	data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
	376	GFP_KERNEL);
	377	if (!data->domains)
	378	return -ENOMEM;
	379
	380	data->num_domains = num;
	381	for (i = 0; i < num; i++) {
	382	if (!scs[i])
	383	continue;
	384	scs[i]->regmap = regmap;
3c53f5e2	385	scs[i]->rcdev = rcdev;
45dd0e55 SB	386	ret = gdsc_init(scs[i]);
	387	if (ret)
	388	return ret;
	389	data->domains[i] = &scs[i]->pd;
	390	}
	391
c2c7f0a4 RN	392	/* Add subdomains */
	393	for (i = 0; i < num; i++) {
	394	if (!scs[i])
	395	continue;
	396	if (scs[i]->parent)
	397	pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
	398	}
	399
45dd0e55 SB	400	return of_genpd_add_provider_onecell(dev->of_node, data);
	401	}
	402
c2c7f0a4	403	void gdsc_unregister(struct gdsc_desc *desc)
45dd0e55	404	{
c2c7f0a4 RN	405	int i;
	406	struct device *dev = desc->dev;
	407	struct gdsc **scs = desc->scs;
	408	size_t num = desc->num;
	409
	410	/* Remove subdomains */
	411	for (i = 0; i < num; i++) {
	412	if (!scs[i])
	413	continue;
	414	if (scs[i]->parent)
	415	pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
	416	}
45dd0e55 SB	417	of_genpd_del_provider(dev->of_node);
45dd0e55 SB	418	}