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1 | /* |
2 | * Copyright (c) 2015, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 and | |
6 | * only version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #ifndef __QCOM_GDSC_H__ | |
15 | #define __QCOM_GDSC_H__ | |
16 | ||
17 | #include <linux/err.h> | |
18 | #include <linux/pm_domain.h> | |
19 | ||
20 | struct regmap; | |
3c53f5e2 | 21 | struct reset_controller_dev; |
45dd0e55 SB |
22 | |
23 | /** | |
24 | * struct gdsc - Globally Distributed Switch Controller | |
25 | * @pd: generic power domain | |
26 | * @regmap: regmap for MMIO accesses | |
27 | * @gdscr: gsdc control register | |
77b1067a | 28 | * @gds_hw_ctrl: gds_hw_ctrl register |
014e193c RN |
29 | * @cxcs: offsets of branch registers to toggle mem/periph bits in |
30 | * @cxc_count: number of @cxcs | |
31 | * @pwrsts: Possible powerdomain power states | |
3c53f5e2 RN |
32 | * @resets: ids of resets associated with this gdsc |
33 | * @reset_count: number of @resets | |
34 | * @rcdev: reset controller | |
45dd0e55 SB |
35 | */ |
36 | struct gdsc { | |
37 | struct generic_pm_domain pd; | |
c2c7f0a4 | 38 | struct generic_pm_domain *parent; |
45dd0e55 SB |
39 | struct regmap *regmap; |
40 | unsigned int gdscr; | |
77b1067a | 41 | unsigned int gds_hw_ctrl; |
e7cc455f | 42 | unsigned int clamp_io_ctrl; |
014e193c RN |
43 | unsigned int *cxcs; |
44 | unsigned int cxc_count; | |
45 | const u8 pwrsts; | |
a823bb9f RN |
46 | /* Powerdomain allowable state bitfields */ |
47 | #define PWRSTS_OFF BIT(0) | |
48 | #define PWRSTS_RET BIT(1) | |
49 | #define PWRSTS_ON BIT(2) | |
50 | #define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON) | |
51 | #define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON) | |
52 | const u8 flags; | |
53 | #define VOTABLE BIT(0) | |
e7cc455f | 54 | #define CLAMP_IO BIT(1) |
3c53f5e2 RN |
55 | struct reset_controller_dev *rcdev; |
56 | unsigned int *resets; | |
57 | unsigned int reset_count; | |
45dd0e55 SB |
58 | }; |
59 | ||
c2c7f0a4 RN |
60 | struct gdsc_desc { |
61 | struct device *dev; | |
62 | struct gdsc **scs; | |
63 | size_t num; | |
64 | }; | |
65 | ||
45dd0e55 | 66 | #ifdef CONFIG_QCOM_GDSC |
c2c7f0a4 RN |
67 | int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *, |
68 | struct regmap *); | |
69 | void gdsc_unregister(struct gdsc_desc *desc); | |
45dd0e55 | 70 | #else |
c2c7f0a4 | 71 | static inline int gdsc_register(struct gdsc_desc *desc, |
3c53f5e2 | 72 | struct reset_controller_dev *rcdev, |
45dd0e55 SB |
73 | struct regmap *r) |
74 | { | |
75 | return -ENOSYS; | |
76 | } | |
77 | ||
c2c7f0a4 | 78 | static inline void gdsc_unregister(struct gdsc_desc *desc) {}; |
45dd0e55 SB |
79 | #endif /* CONFIG_QCOM_GDSC */ |
80 | #endif /* __QCOM_GDSC_H__ */ |