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b82875ee SB |
1 | /* |
2 | * Copyright (c) 2014, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/clk-provider.h> | |
22 | #include <linux/regmap.h> | |
23 | ||
24 | #include <dt-bindings/clock/qcom,lcc-msm8960.h> | |
25 | ||
26 | #include "common.h" | |
27 | #include "clk-regmap.h" | |
28 | #include "clk-pll.h" | |
29 | #include "clk-rcg.h" | |
30 | #include "clk-branch.h" | |
31 | #include "clk-regmap-divider.h" | |
32 | #include "clk-regmap-mux.h" | |
33 | ||
34 | static struct clk_pll pll4 = { | |
35 | .l_reg = 0x4, | |
36 | .m_reg = 0x8, | |
37 | .n_reg = 0xc, | |
38 | .config_reg = 0x14, | |
39 | .mode_reg = 0x0, | |
40 | .status_reg = 0x18, | |
41 | .status_bit = 16, | |
42 | .clkr.hw.init = &(struct clk_init_data){ | |
43 | .name = "pll4", | |
44 | .parent_names = (const char *[]){ "pxo" }, | |
45 | .num_parents = 1, | |
46 | .ops = &clk_pll_ops, | |
47 | }, | |
48 | }; | |
49 | ||
293d2e97 GD |
50 | enum { |
51 | P_PXO, | |
52 | P_PLL4, | |
53 | }; | |
b82875ee | 54 | |
293d2e97 GD |
55 | static const struct parent_map lcc_pxo_pll4_map[] = { |
56 | { P_PXO, 0 }, | |
57 | { P_PLL4, 2 } | |
b82875ee SB |
58 | }; |
59 | ||
adb11a40 | 60 | static const char * const lcc_pxo_pll4[] = { |
b82875ee SB |
61 | "pxo", |
62 | "pll4_vote", | |
63 | }; | |
64 | ||
65 | static struct freq_tbl clk_tbl_aif_osr_492[] = { | |
66 | { 512000, P_PLL4, 4, 1, 240 }, | |
67 | { 768000, P_PLL4, 4, 1, 160 }, | |
68 | { 1024000, P_PLL4, 4, 1, 120 }, | |
69 | { 1536000, P_PLL4, 4, 1, 80 }, | |
70 | { 2048000, P_PLL4, 4, 1, 60 }, | |
71 | { 3072000, P_PLL4, 4, 1, 40 }, | |
72 | { 4096000, P_PLL4, 4, 1, 30 }, | |
73 | { 6144000, P_PLL4, 4, 1, 20 }, | |
74 | { 8192000, P_PLL4, 4, 1, 15 }, | |
75 | { 12288000, P_PLL4, 4, 1, 10 }, | |
76 | { 24576000, P_PLL4, 4, 1, 5 }, | |
77 | { 27000000, P_PXO, 1, 0, 0 }, | |
78 | { } | |
79 | }; | |
80 | ||
81 | static struct freq_tbl clk_tbl_aif_osr_393[] = { | |
82 | { 512000, P_PLL4, 4, 1, 192 }, | |
83 | { 768000, P_PLL4, 4, 1, 128 }, | |
84 | { 1024000, P_PLL4, 4, 1, 96 }, | |
85 | { 1536000, P_PLL4, 4, 1, 64 }, | |
86 | { 2048000, P_PLL4, 4, 1, 48 }, | |
87 | { 3072000, P_PLL4, 4, 1, 32 }, | |
88 | { 4096000, P_PLL4, 4, 1, 24 }, | |
89 | { 6144000, P_PLL4, 4, 1, 16 }, | |
90 | { 8192000, P_PLL4, 4, 1, 12 }, | |
91 | { 12288000, P_PLL4, 4, 1, 8 }, | |
92 | { 24576000, P_PLL4, 4, 1, 4 }, | |
93 | { 27000000, P_PXO, 1, 0, 0 }, | |
94 | { } | |
95 | }; | |
96 | ||
97 | static struct clk_rcg mi2s_osr_src = { | |
98 | .ns_reg = 0x48, | |
99 | .md_reg = 0x4c, | |
100 | .mn = { | |
101 | .mnctr_en_bit = 8, | |
102 | .mnctr_reset_bit = 7, | |
103 | .mnctr_mode_shift = 5, | |
104 | .n_val_shift = 24, | |
105 | .m_val_shift = 8, | |
106 | .width = 8, | |
107 | }, | |
108 | .p = { | |
109 | .pre_div_shift = 3, | |
110 | .pre_div_width = 2, | |
111 | }, | |
112 | .s = { | |
113 | .src_sel_shift = 0, | |
114 | .parent_map = lcc_pxo_pll4_map, | |
115 | }, | |
116 | .freq_tbl = clk_tbl_aif_osr_393, | |
117 | .clkr = { | |
118 | .enable_reg = 0x48, | |
119 | .enable_mask = BIT(9), | |
120 | .hw.init = &(struct clk_init_data){ | |
121 | .name = "mi2s_osr_src", | |
122 | .parent_names = lcc_pxo_pll4, | |
123 | .num_parents = 2, | |
124 | .ops = &clk_rcg_ops, | |
125 | .flags = CLK_SET_RATE_GATE, | |
126 | }, | |
127 | }, | |
128 | }; | |
129 | ||
adb11a40 | 130 | static const char * const lcc_mi2s_parents[] = { |
b82875ee SB |
131 | "mi2s_osr_src", |
132 | }; | |
133 | ||
134 | static struct clk_branch mi2s_osr_clk = { | |
135 | .halt_reg = 0x50, | |
136 | .halt_bit = 1, | |
137 | .halt_check = BRANCH_HALT_ENABLE, | |
138 | .clkr = { | |
139 | .enable_reg = 0x48, | |
140 | .enable_mask = BIT(17), | |
141 | .hw.init = &(struct clk_init_data){ | |
142 | .name = "mi2s_osr_clk", | |
143 | .parent_names = lcc_mi2s_parents, | |
144 | .num_parents = 1, | |
145 | .ops = &clk_branch_ops, | |
146 | .flags = CLK_SET_RATE_PARENT, | |
147 | }, | |
148 | }, | |
149 | }; | |
150 | ||
151 | static struct clk_regmap_div mi2s_div_clk = { | |
152 | .reg = 0x48, | |
153 | .shift = 10, | |
154 | .width = 4, | |
155 | .clkr = { | |
156 | .enable_reg = 0x48, | |
157 | .enable_mask = BIT(15), | |
158 | .hw.init = &(struct clk_init_data){ | |
159 | .name = "mi2s_div_clk", | |
160 | .parent_names = lcc_mi2s_parents, | |
161 | .num_parents = 1, | |
162 | .ops = &clk_regmap_div_ops, | |
163 | }, | |
164 | }, | |
165 | }; | |
166 | ||
167 | static struct clk_branch mi2s_bit_div_clk = { | |
168 | .halt_reg = 0x50, | |
169 | .halt_bit = 0, | |
170 | .halt_check = BRANCH_HALT_ENABLE, | |
171 | .clkr = { | |
172 | .enable_reg = 0x48, | |
173 | .enable_mask = BIT(15), | |
174 | .hw.init = &(struct clk_init_data){ | |
175 | .name = "mi2s_bit_div_clk", | |
176 | .parent_names = (const char *[]){ "mi2s_div_clk" }, | |
177 | .num_parents = 1, | |
178 | .ops = &clk_branch_ops, | |
179 | .flags = CLK_SET_RATE_PARENT, | |
180 | }, | |
181 | }, | |
182 | }; | |
183 | ||
184 | static struct clk_regmap_mux mi2s_bit_clk = { | |
185 | .reg = 0x48, | |
186 | .shift = 14, | |
187 | .width = 1, | |
188 | .clkr = { | |
189 | .hw.init = &(struct clk_init_data){ | |
190 | .name = "mi2s_bit_clk", | |
191 | .parent_names = (const char *[]){ | |
192 | "mi2s_bit_div_clk", | |
193 | "mi2s_codec_clk", | |
194 | }, | |
195 | .num_parents = 2, | |
196 | .ops = &clk_regmap_mux_closest_ops, | |
197 | .flags = CLK_SET_RATE_PARENT, | |
198 | }, | |
199 | }, | |
200 | }; | |
201 | ||
202 | #define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \ | |
203 | static struct clk_rcg prefix##_osr_src = { \ | |
204 | .ns_reg = _ns, \ | |
205 | .md_reg = _md, \ | |
206 | .mn = { \ | |
207 | .mnctr_en_bit = 8, \ | |
208 | .mnctr_reset_bit = 7, \ | |
209 | .mnctr_mode_shift = 5, \ | |
210 | .n_val_shift = 24, \ | |
211 | .m_val_shift = 8, \ | |
212 | .width = 8, \ | |
213 | }, \ | |
214 | .p = { \ | |
215 | .pre_div_shift = 3, \ | |
216 | .pre_div_width = 2, \ | |
217 | }, \ | |
218 | .s = { \ | |
219 | .src_sel_shift = 0, \ | |
220 | .parent_map = lcc_pxo_pll4_map, \ | |
221 | }, \ | |
222 | .freq_tbl = clk_tbl_aif_osr_393, \ | |
223 | .clkr = { \ | |
224 | .enable_reg = _ns, \ | |
225 | .enable_mask = BIT(9), \ | |
226 | .hw.init = &(struct clk_init_data){ \ | |
227 | .name = #prefix "_osr_src", \ | |
228 | .parent_names = lcc_pxo_pll4, \ | |
229 | .num_parents = 2, \ | |
230 | .ops = &clk_rcg_ops, \ | |
231 | .flags = CLK_SET_RATE_GATE, \ | |
232 | }, \ | |
233 | }, \ | |
234 | }; \ | |
235 | \ | |
adb11a40 | 236 | static const char * const lcc_##prefix##_parents[] = { \ |
b82875ee SB |
237 | #prefix "_osr_src", \ |
238 | }; \ | |
239 | \ | |
240 | static struct clk_branch prefix##_osr_clk = { \ | |
241 | .halt_reg = hr, \ | |
242 | .halt_bit = 1, \ | |
243 | .halt_check = BRANCH_HALT_ENABLE, \ | |
244 | .clkr = { \ | |
245 | .enable_reg = _ns, \ | |
246 | .enable_mask = BIT(21), \ | |
247 | .hw.init = &(struct clk_init_data){ \ | |
248 | .name = #prefix "_osr_clk", \ | |
249 | .parent_names = lcc_##prefix##_parents, \ | |
250 | .num_parents = 1, \ | |
251 | .ops = &clk_branch_ops, \ | |
252 | .flags = CLK_SET_RATE_PARENT, \ | |
253 | }, \ | |
254 | }, \ | |
255 | }; \ | |
256 | \ | |
257 | static struct clk_regmap_div prefix##_div_clk = { \ | |
258 | .reg = _ns, \ | |
259 | .shift = 10, \ | |
260 | .width = 8, \ | |
261 | .clkr = { \ | |
262 | .hw.init = &(struct clk_init_data){ \ | |
263 | .name = #prefix "_div_clk", \ | |
264 | .parent_names = lcc_##prefix##_parents, \ | |
265 | .num_parents = 1, \ | |
266 | .ops = &clk_regmap_div_ops, \ | |
267 | }, \ | |
268 | }, \ | |
269 | }; \ | |
270 | \ | |
271 | static struct clk_branch prefix##_bit_div_clk = { \ | |
272 | .halt_reg = hr, \ | |
273 | .halt_bit = 0, \ | |
274 | .halt_check = BRANCH_HALT_ENABLE, \ | |
275 | .clkr = { \ | |
276 | .enable_reg = _ns, \ | |
277 | .enable_mask = BIT(19), \ | |
278 | .hw.init = &(struct clk_init_data){ \ | |
279 | .name = #prefix "_bit_div_clk", \ | |
280 | .parent_names = (const char *[]){ \ | |
281 | #prefix "_div_clk" \ | |
282 | }, \ | |
283 | .num_parents = 1, \ | |
284 | .ops = &clk_branch_ops, \ | |
285 | .flags = CLK_SET_RATE_PARENT, \ | |
286 | }, \ | |
287 | }, \ | |
288 | }; \ | |
289 | \ | |
290 | static struct clk_regmap_mux prefix##_bit_clk = { \ | |
291 | .reg = _ns, \ | |
292 | .shift = 18, \ | |
293 | .width = 1, \ | |
294 | .clkr = { \ | |
295 | .hw.init = &(struct clk_init_data){ \ | |
296 | .name = #prefix "_bit_clk", \ | |
297 | .parent_names = (const char *[]){ \ | |
298 | #prefix "_bit_div_clk", \ | |
299 | #prefix "_codec_clk", \ | |
300 | }, \ | |
301 | .num_parents = 2, \ | |
302 | .ops = &clk_regmap_mux_closest_ops, \ | |
303 | .flags = CLK_SET_RATE_PARENT, \ | |
304 | }, \ | |
305 | }, \ | |
306 | } | |
307 | ||
308 | CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68); | |
309 | CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80); | |
310 | CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74); | |
311 | CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c); | |
312 | ||
313 | static struct freq_tbl clk_tbl_pcm_492[] = { | |
314 | { 256000, P_PLL4, 4, 1, 480 }, | |
315 | { 512000, P_PLL4, 4, 1, 240 }, | |
316 | { 768000, P_PLL4, 4, 1, 160 }, | |
317 | { 1024000, P_PLL4, 4, 1, 120 }, | |
318 | { 1536000, P_PLL4, 4, 1, 80 }, | |
319 | { 2048000, P_PLL4, 4, 1, 60 }, | |
320 | { 3072000, P_PLL4, 4, 1, 40 }, | |
321 | { 4096000, P_PLL4, 4, 1, 30 }, | |
322 | { 6144000, P_PLL4, 4, 1, 20 }, | |
323 | { 8192000, P_PLL4, 4, 1, 15 }, | |
324 | { 12288000, P_PLL4, 4, 1, 10 }, | |
325 | { 24576000, P_PLL4, 4, 1, 5 }, | |
326 | { 27000000, P_PXO, 1, 0, 0 }, | |
327 | { } | |
328 | }; | |
329 | ||
330 | static struct freq_tbl clk_tbl_pcm_393[] = { | |
331 | { 256000, P_PLL4, 4, 1, 384 }, | |
332 | { 512000, P_PLL4, 4, 1, 192 }, | |
333 | { 768000, P_PLL4, 4, 1, 128 }, | |
334 | { 1024000, P_PLL4, 4, 1, 96 }, | |
335 | { 1536000, P_PLL4, 4, 1, 64 }, | |
336 | { 2048000, P_PLL4, 4, 1, 48 }, | |
337 | { 3072000, P_PLL4, 4, 1, 32 }, | |
338 | { 4096000, P_PLL4, 4, 1, 24 }, | |
339 | { 6144000, P_PLL4, 4, 1, 16 }, | |
340 | { 8192000, P_PLL4, 4, 1, 12 }, | |
341 | { 12288000, P_PLL4, 4, 1, 8 }, | |
342 | { 24576000, P_PLL4, 4, 1, 4 }, | |
343 | { 27000000, P_PXO, 1, 0, 0 }, | |
344 | { } | |
345 | }; | |
346 | ||
347 | static struct clk_rcg pcm_src = { | |
348 | .ns_reg = 0x54, | |
349 | .md_reg = 0x58, | |
350 | .mn = { | |
351 | .mnctr_en_bit = 8, | |
352 | .mnctr_reset_bit = 7, | |
353 | .mnctr_mode_shift = 5, | |
354 | .n_val_shift = 16, | |
355 | .m_val_shift = 16, | |
356 | .width = 16, | |
357 | }, | |
358 | .p = { | |
359 | .pre_div_shift = 3, | |
360 | .pre_div_width = 2, | |
361 | }, | |
362 | .s = { | |
363 | .src_sel_shift = 0, | |
364 | .parent_map = lcc_pxo_pll4_map, | |
365 | }, | |
366 | .freq_tbl = clk_tbl_pcm_393, | |
367 | .clkr = { | |
368 | .enable_reg = 0x54, | |
369 | .enable_mask = BIT(9), | |
370 | .hw.init = &(struct clk_init_data){ | |
371 | .name = "pcm_src", | |
372 | .parent_names = lcc_pxo_pll4, | |
373 | .num_parents = 2, | |
374 | .ops = &clk_rcg_ops, | |
375 | .flags = CLK_SET_RATE_GATE, | |
376 | }, | |
377 | }, | |
378 | }; | |
379 | ||
380 | static struct clk_branch pcm_clk_out = { | |
381 | .halt_reg = 0x5c, | |
382 | .halt_bit = 0, | |
383 | .halt_check = BRANCH_HALT_ENABLE, | |
384 | .clkr = { | |
385 | .enable_reg = 0x54, | |
386 | .enable_mask = BIT(11), | |
387 | .hw.init = &(struct clk_init_data){ | |
388 | .name = "pcm_clk_out", | |
389 | .parent_names = (const char *[]){ "pcm_src" }, | |
390 | .num_parents = 1, | |
391 | .ops = &clk_branch_ops, | |
392 | .flags = CLK_SET_RATE_PARENT, | |
393 | }, | |
394 | }, | |
395 | }; | |
396 | ||
397 | static struct clk_regmap_mux pcm_clk = { | |
398 | .reg = 0x54, | |
399 | .shift = 10, | |
400 | .width = 1, | |
401 | .clkr = { | |
402 | .hw.init = &(struct clk_init_data){ | |
403 | .name = "pcm_clk", | |
404 | .parent_names = (const char *[]){ | |
405 | "pcm_clk_out", | |
406 | "pcm_codec_clk", | |
407 | }, | |
408 | .num_parents = 2, | |
409 | .ops = &clk_regmap_mux_closest_ops, | |
410 | .flags = CLK_SET_RATE_PARENT, | |
411 | }, | |
412 | }, | |
413 | }; | |
414 | ||
415 | static struct clk_rcg slimbus_src = { | |
416 | .ns_reg = 0xcc, | |
417 | .md_reg = 0xd0, | |
418 | .mn = { | |
419 | .mnctr_en_bit = 8, | |
420 | .mnctr_reset_bit = 7, | |
421 | .mnctr_mode_shift = 5, | |
7dd47b8e SB |
422 | .n_val_shift = 24, |
423 | .m_val_shift = 8, | |
b82875ee SB |
424 | .width = 8, |
425 | }, | |
426 | .p = { | |
427 | .pre_div_shift = 3, | |
428 | .pre_div_width = 2, | |
429 | }, | |
430 | .s = { | |
431 | .src_sel_shift = 0, | |
432 | .parent_map = lcc_pxo_pll4_map, | |
433 | }, | |
434 | .freq_tbl = clk_tbl_aif_osr_393, | |
435 | .clkr = { | |
436 | .enable_reg = 0xcc, | |
437 | .enable_mask = BIT(9), | |
438 | .hw.init = &(struct clk_init_data){ | |
439 | .name = "slimbus_src", | |
440 | .parent_names = lcc_pxo_pll4, | |
441 | .num_parents = 2, | |
442 | .ops = &clk_rcg_ops, | |
443 | .flags = CLK_SET_RATE_GATE, | |
444 | }, | |
445 | }, | |
446 | }; | |
447 | ||
adb11a40 | 448 | static const char * const lcc_slimbus_parents[] = { |
b82875ee SB |
449 | "slimbus_src", |
450 | }; | |
451 | ||
452 | static struct clk_branch audio_slimbus_clk = { | |
453 | .halt_reg = 0xd4, | |
454 | .halt_bit = 0, | |
455 | .halt_check = BRANCH_HALT_ENABLE, | |
456 | .clkr = { | |
457 | .enable_reg = 0xcc, | |
458 | .enable_mask = BIT(10), | |
459 | .hw.init = &(struct clk_init_data){ | |
460 | .name = "audio_slimbus_clk", | |
461 | .parent_names = lcc_slimbus_parents, | |
462 | .num_parents = 1, | |
463 | .ops = &clk_branch_ops, | |
464 | .flags = CLK_SET_RATE_PARENT, | |
465 | }, | |
466 | }, | |
467 | }; | |
468 | ||
469 | static struct clk_branch sps_slimbus_clk = { | |
470 | .halt_reg = 0xd4, | |
471 | .halt_bit = 1, | |
472 | .halt_check = BRANCH_HALT_ENABLE, | |
473 | .clkr = { | |
474 | .enable_reg = 0xcc, | |
475 | .enable_mask = BIT(12), | |
476 | .hw.init = &(struct clk_init_data){ | |
477 | .name = "sps_slimbus_clk", | |
478 | .parent_names = lcc_slimbus_parents, | |
479 | .num_parents = 1, | |
480 | .ops = &clk_branch_ops, | |
481 | .flags = CLK_SET_RATE_PARENT, | |
482 | }, | |
483 | }, | |
484 | }; | |
485 | ||
486 | static struct clk_regmap *lcc_msm8960_clks[] = { | |
487 | [PLL4] = &pll4.clkr, | |
488 | [MI2S_OSR_SRC] = &mi2s_osr_src.clkr, | |
489 | [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr, | |
490 | [MI2S_DIV_CLK] = &mi2s_div_clk.clkr, | |
491 | [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr, | |
492 | [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr, | |
493 | [PCM_SRC] = &pcm_src.clkr, | |
494 | [PCM_CLK_OUT] = &pcm_clk_out.clkr, | |
495 | [PCM_CLK] = &pcm_clk.clkr, | |
496 | [SLIMBUS_SRC] = &slimbus_src.clkr, | |
497 | [AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr, | |
498 | [SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr, | |
499 | [CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr, | |
500 | [CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr, | |
501 | [CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr, | |
502 | [CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr, | |
503 | [CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr, | |
504 | [SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr, | |
505 | [SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr, | |
506 | [SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr, | |
507 | [SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr, | |
508 | [SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr, | |
509 | [CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr, | |
510 | [CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr, | |
511 | [CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr, | |
512 | [CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr, | |
513 | [CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr, | |
514 | [SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr, | |
515 | [SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr, | |
516 | [SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr, | |
517 | [SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr, | |
518 | [SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr, | |
519 | }; | |
520 | ||
521 | static const struct regmap_config lcc_msm8960_regmap_config = { | |
522 | .reg_bits = 32, | |
523 | .reg_stride = 4, | |
524 | .val_bits = 32, | |
525 | .max_register = 0xfc, | |
526 | .fast_io = true, | |
527 | }; | |
528 | ||
529 | static const struct qcom_cc_desc lcc_msm8960_desc = { | |
530 | .config = &lcc_msm8960_regmap_config, | |
531 | .clks = lcc_msm8960_clks, | |
532 | .num_clks = ARRAY_SIZE(lcc_msm8960_clks), | |
533 | }; | |
534 | ||
535 | static const struct of_device_id lcc_msm8960_match_table[] = { | |
536 | { .compatible = "qcom,lcc-msm8960" }, | |
537 | { .compatible = "qcom,lcc-apq8064" }, | |
538 | { } | |
539 | }; | |
540 | MODULE_DEVICE_TABLE(of, lcc_msm8960_match_table); | |
541 | ||
542 | static int lcc_msm8960_probe(struct platform_device *pdev) | |
543 | { | |
544 | u32 val; | |
545 | struct regmap *regmap; | |
546 | ||
547 | regmap = qcom_cc_map(pdev, &lcc_msm8960_desc); | |
548 | if (IS_ERR(regmap)) | |
549 | return PTR_ERR(regmap); | |
550 | ||
551 | /* Use the correct frequency plan depending on speed of PLL4 */ | |
84b919fd | 552 | regmap_read(regmap, 0x4, &val); |
b82875ee SB |
553 | if (val == 0x12) { |
554 | slimbus_src.freq_tbl = clk_tbl_aif_osr_492; | |
555 | mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492; | |
556 | codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492; | |
557 | spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492; | |
558 | codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492; | |
559 | spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492; | |
560 | pcm_src.freq_tbl = clk_tbl_pcm_492; | |
561 | } | |
562 | /* Enable PLL4 source on the LPASS Primary PLL Mux */ | |
563 | regmap_write(regmap, 0xc4, 0x1); | |
564 | ||
565 | return qcom_cc_really_probe(pdev, &lcc_msm8960_desc, regmap); | |
566 | } | |
567 | ||
b82875ee SB |
568 | static struct platform_driver lcc_msm8960_driver = { |
569 | .probe = lcc_msm8960_probe, | |
b82875ee SB |
570 | .driver = { |
571 | .name = "lcc-msm8960", | |
b82875ee SB |
572 | .of_match_table = lcc_msm8960_match_table, |
573 | }, | |
574 | }; | |
575 | module_platform_driver(lcc_msm8960_driver); | |
576 | ||
577 | MODULE_DESCRIPTION("QCOM LCC MSM8960 Driver"); | |
578 | MODULE_LICENSE("GPL v2"); | |
579 | MODULE_ALIAS("platform:lcc-msm8960"); |