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d8b21201 SB |
1 | /* |
2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/clk-provider.h> | |
22 | #include <linux/regmap.h> | |
23 | #include <linux/reset-controller.h> | |
24 | ||
25 | #include <dt-bindings/clock/qcom,mmcc-msm8974.h> | |
26 | #include <dt-bindings/reset/qcom,mmcc-msm8974.h> | |
27 | ||
49fc825f | 28 | #include "common.h" |
d8b21201 SB |
29 | #include "clk-regmap.h" |
30 | #include "clk-pll.h" | |
31 | #include "clk-rcg.h" | |
32 | #include "clk-branch.h" | |
33 | #include "reset.h" | |
8108b23c | 34 | #include "gdsc.h" |
d8b21201 | 35 | |
293d2e97 GD |
36 | enum { |
37 | P_XO, | |
38 | P_MMPLL0, | |
39 | P_EDPLINK, | |
40 | P_MMPLL1, | |
41 | P_HDMIPLL, | |
42 | P_GPLL0, | |
43 | P_EDPVCO, | |
44 | P_GPLL1, | |
45 | P_DSI0PLL, | |
46 | P_DSI0PLL_BYTE, | |
47 | P_MMPLL2, | |
48 | P_MMPLL3, | |
49 | P_DSI1PLL, | |
50 | P_DSI1PLL_BYTE, | |
51 | }; | |
52 | ||
53 | static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { | |
54 | { P_XO, 0 }, | |
55 | { P_MMPLL0, 1 }, | |
56 | { P_MMPLL1, 2 }, | |
57 | { P_GPLL0, 5 } | |
d8b21201 SB |
58 | }; |
59 | ||
adb11a40 | 60 | static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = { |
d8b21201 SB |
61 | "xo", |
62 | "mmpll0_vote", | |
63 | "mmpll1_vote", | |
64 | "mmss_gpll0_vote", | |
65 | }; | |
66 | ||
293d2e97 GD |
67 | static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { |
68 | { P_XO, 0 }, | |
69 | { P_MMPLL0, 1 }, | |
70 | { P_HDMIPLL, 4 }, | |
71 | { P_GPLL0, 5 }, | |
72 | { P_DSI0PLL, 2 }, | |
73 | { P_DSI1PLL, 3 } | |
d8b21201 SB |
74 | }; |
75 | ||
adb11a40 | 76 | static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { |
d8b21201 SB |
77 | "xo", |
78 | "mmpll0_vote", | |
79 | "hdmipll", | |
80 | "mmss_gpll0_vote", | |
81 | "dsi0pll", | |
82 | "dsi1pll", | |
83 | }; | |
84 | ||
293d2e97 GD |
85 | static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = { |
86 | { P_XO, 0 }, | |
87 | { P_MMPLL0, 1 }, | |
88 | { P_MMPLL1, 2 }, | |
89 | { P_GPLL0, 5 }, | |
90 | { P_MMPLL2, 3 } | |
d8b21201 SB |
91 | }; |
92 | ||
adb11a40 | 93 | static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = { |
d8b21201 SB |
94 | "xo", |
95 | "mmpll0_vote", | |
96 | "mmpll1_vote", | |
97 | "mmss_gpll0_vote", | |
98 | "mmpll2", | |
99 | }; | |
100 | ||
293d2e97 GD |
101 | static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = { |
102 | { P_XO, 0 }, | |
103 | { P_MMPLL0, 1 }, | |
104 | { P_MMPLL1, 2 }, | |
105 | { P_GPLL0, 5 }, | |
106 | { P_MMPLL3, 3 } | |
d8b21201 SB |
107 | }; |
108 | ||
adb11a40 | 109 | static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = { |
d8b21201 SB |
110 | "xo", |
111 | "mmpll0_vote", | |
112 | "mmpll1_vote", | |
113 | "mmss_gpll0_vote", | |
114 | "mmpll3", | |
115 | }; | |
116 | ||
293d2e97 GD |
117 | static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = { |
118 | { P_XO, 0 }, | |
119 | { P_MMPLL0, 1 }, | |
120 | { P_MMPLL1, 2 }, | |
121 | { P_GPLL0, 5 }, | |
122 | { P_GPLL1, 4 } | |
d8b21201 SB |
123 | }; |
124 | ||
adb11a40 | 125 | static const char * const mmcc_xo_mmpll0_1_gpll1_0[] = { |
d8b21201 SB |
126 | "xo", |
127 | "mmpll0_vote", | |
128 | "mmpll1_vote", | |
129 | "mmss_gpll0_vote", | |
130 | "gpll1_vote", | |
131 | }; | |
132 | ||
293d2e97 GD |
133 | static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = { |
134 | { P_XO, 0 }, | |
135 | { P_EDPLINK, 4 }, | |
136 | { P_HDMIPLL, 3 }, | |
137 | { P_EDPVCO, 5 }, | |
138 | { P_DSI0PLL, 1 }, | |
139 | { P_DSI1PLL, 2 } | |
d8b21201 SB |
140 | }; |
141 | ||
adb11a40 | 142 | static const char * const mmcc_xo_dsi_hdmi_edp[] = { |
d8b21201 SB |
143 | "xo", |
144 | "edp_link_clk", | |
145 | "hdmipll", | |
146 | "edp_vco_div", | |
147 | "dsi0pll", | |
148 | "dsi1pll", | |
149 | }; | |
150 | ||
293d2e97 GD |
151 | static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { |
152 | { P_XO, 0 }, | |
153 | { P_EDPLINK, 4 }, | |
154 | { P_HDMIPLL, 3 }, | |
155 | { P_GPLL0, 5 }, | |
156 | { P_DSI0PLL, 1 }, | |
157 | { P_DSI1PLL, 2 } | |
d8b21201 SB |
158 | }; |
159 | ||
adb11a40 | 160 | static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = { |
d8b21201 SB |
161 | "xo", |
162 | "edp_link_clk", | |
163 | "hdmipll", | |
164 | "gpll0_vote", | |
165 | "dsi0pll", | |
166 | "dsi1pll", | |
167 | }; | |
168 | ||
293d2e97 GD |
169 | static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { |
170 | { P_XO, 0 }, | |
171 | { P_EDPLINK, 4 }, | |
172 | { P_HDMIPLL, 3 }, | |
173 | { P_GPLL0, 5 }, | |
174 | { P_DSI0PLL_BYTE, 1 }, | |
175 | { P_DSI1PLL_BYTE, 2 } | |
b7b7cc70 SB |
176 | }; |
177 | ||
adb11a40 | 178 | static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { |
b7b7cc70 SB |
179 | "xo", |
180 | "edp_link_clk", | |
181 | "hdmipll", | |
182 | "gpll0_vote", | |
183 | "dsi0pllbyte", | |
184 | "dsi1pllbyte", | |
185 | }; | |
186 | ||
d8b21201 SB |
187 | #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } |
188 | ||
189 | static struct clk_pll mmpll0 = { | |
190 | .l_reg = 0x0004, | |
191 | .m_reg = 0x0008, | |
192 | .n_reg = 0x000c, | |
193 | .config_reg = 0x0014, | |
194 | .mode_reg = 0x0000, | |
195 | .status_reg = 0x001c, | |
437ae6a1 | 196 | .status_bit = 17, |
d8b21201 SB |
197 | .clkr.hw.init = &(struct clk_init_data){ |
198 | .name = "mmpll0", | |
199 | .parent_names = (const char *[]){ "xo" }, | |
200 | .num_parents = 1, | |
201 | .ops = &clk_pll_ops, | |
202 | }, | |
203 | }; | |
204 | ||
205 | static struct clk_regmap mmpll0_vote = { | |
206 | .enable_reg = 0x0100, | |
207 | .enable_mask = BIT(0), | |
208 | .hw.init = &(struct clk_init_data){ | |
209 | .name = "mmpll0_vote", | |
210 | .parent_names = (const char *[]){ "mmpll0" }, | |
211 | .num_parents = 1, | |
212 | .ops = &clk_pll_vote_ops, | |
213 | }, | |
214 | }; | |
215 | ||
216 | static struct clk_pll mmpll1 = { | |
217 | .l_reg = 0x0044, | |
218 | .m_reg = 0x0048, | |
219 | .n_reg = 0x004c, | |
437ae6a1 | 220 | .config_reg = 0x0050, |
d8b21201 SB |
221 | .mode_reg = 0x0040, |
222 | .status_reg = 0x005c, | |
437ae6a1 | 223 | .status_bit = 17, |
d8b21201 SB |
224 | .clkr.hw.init = &(struct clk_init_data){ |
225 | .name = "mmpll1", | |
226 | .parent_names = (const char *[]){ "xo" }, | |
227 | .num_parents = 1, | |
228 | .ops = &clk_pll_ops, | |
229 | }, | |
230 | }; | |
231 | ||
232 | static struct clk_regmap mmpll1_vote = { | |
233 | .enable_reg = 0x0100, | |
234 | .enable_mask = BIT(1), | |
235 | .hw.init = &(struct clk_init_data){ | |
236 | .name = "mmpll1_vote", | |
237 | .parent_names = (const char *[]){ "mmpll1" }, | |
238 | .num_parents = 1, | |
239 | .ops = &clk_pll_vote_ops, | |
240 | }, | |
241 | }; | |
242 | ||
243 | static struct clk_pll mmpll2 = { | |
244 | .l_reg = 0x4104, | |
245 | .m_reg = 0x4108, | |
246 | .n_reg = 0x410c, | |
437ae6a1 | 247 | .config_reg = 0x4110, |
d8b21201 SB |
248 | .mode_reg = 0x4100, |
249 | .status_reg = 0x411c, | |
250 | .clkr.hw.init = &(struct clk_init_data){ | |
251 | .name = "mmpll2", | |
252 | .parent_names = (const char *[]){ "xo" }, | |
253 | .num_parents = 1, | |
254 | .ops = &clk_pll_ops, | |
255 | }, | |
256 | }; | |
257 | ||
258 | static struct clk_pll mmpll3 = { | |
259 | .l_reg = 0x0084, | |
260 | .m_reg = 0x0088, | |
261 | .n_reg = 0x008c, | |
437ae6a1 | 262 | .config_reg = 0x0090, |
d8b21201 SB |
263 | .mode_reg = 0x0080, |
264 | .status_reg = 0x009c, | |
437ae6a1 | 265 | .status_bit = 17, |
d8b21201 SB |
266 | .clkr.hw.init = &(struct clk_init_data){ |
267 | .name = "mmpll3", | |
268 | .parent_names = (const char *[]){ "xo" }, | |
269 | .num_parents = 1, | |
270 | .ops = &clk_pll_ops, | |
271 | }, | |
272 | }; | |
273 | ||
274 | static struct clk_rcg2 mmss_ahb_clk_src = { | |
275 | .cmd_rcgr = 0x5000, | |
276 | .hid_width = 5, | |
277 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
278 | .clkr.hw.init = &(struct clk_init_data){ | |
279 | .name = "mmss_ahb_clk_src", | |
280 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
281 | .num_parents = 4, | |
282 | .ops = &clk_rcg2_ops, | |
283 | }, | |
284 | }; | |
285 | ||
286 | static struct freq_tbl ftbl_mmss_axi_clk[] = { | |
287 | F( 19200000, P_XO, 1, 0, 0), | |
288 | F( 37500000, P_GPLL0, 16, 0, 0), | |
289 | F( 50000000, P_GPLL0, 12, 0, 0), | |
290 | F( 75000000, P_GPLL0, 8, 0, 0), | |
291 | F(100000000, P_GPLL0, 6, 0, 0), | |
292 | F(150000000, P_GPLL0, 4, 0, 0), | |
293 | F(291750000, P_MMPLL1, 4, 0, 0), | |
294 | F(400000000, P_MMPLL0, 2, 0, 0), | |
295 | F(466800000, P_MMPLL1, 2.5, 0, 0), | |
296 | }; | |
297 | ||
298 | static struct clk_rcg2 mmss_axi_clk_src = { | |
299 | .cmd_rcgr = 0x5040, | |
300 | .hid_width = 5, | |
301 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
302 | .freq_tbl = ftbl_mmss_axi_clk, | |
303 | .clkr.hw.init = &(struct clk_init_data){ | |
304 | .name = "mmss_axi_clk_src", | |
305 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
306 | .num_parents = 4, | |
307 | .ops = &clk_rcg2_ops, | |
308 | }, | |
309 | }; | |
310 | ||
311 | static struct freq_tbl ftbl_ocmemnoc_clk[] = { | |
312 | F( 19200000, P_XO, 1, 0, 0), | |
313 | F( 37500000, P_GPLL0, 16, 0, 0), | |
314 | F( 50000000, P_GPLL0, 12, 0, 0), | |
315 | F( 75000000, P_GPLL0, 8, 0, 0), | |
316 | F(100000000, P_GPLL0, 6, 0, 0), | |
317 | F(150000000, P_GPLL0, 4, 0, 0), | |
318 | F(291750000, P_MMPLL1, 4, 0, 0), | |
319 | F(400000000, P_MMPLL0, 2, 0, 0), | |
320 | }; | |
321 | ||
322 | static struct clk_rcg2 ocmemnoc_clk_src = { | |
323 | .cmd_rcgr = 0x5090, | |
324 | .hid_width = 5, | |
325 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
326 | .freq_tbl = ftbl_ocmemnoc_clk, | |
327 | .clkr.hw.init = &(struct clk_init_data){ | |
328 | .name = "ocmemnoc_clk_src", | |
329 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
330 | .num_parents = 4, | |
331 | .ops = &clk_rcg2_ops, | |
332 | }, | |
333 | }; | |
334 | ||
335 | static struct freq_tbl ftbl_camss_csi0_3_clk[] = { | |
336 | F(100000000, P_GPLL0, 6, 0, 0), | |
337 | F(200000000, P_MMPLL0, 4, 0, 0), | |
338 | { } | |
339 | }; | |
340 | ||
341 | static struct clk_rcg2 csi0_clk_src = { | |
342 | .cmd_rcgr = 0x3090, | |
343 | .hid_width = 5, | |
344 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
345 | .freq_tbl = ftbl_camss_csi0_3_clk, | |
346 | .clkr.hw.init = &(struct clk_init_data){ | |
347 | .name = "csi0_clk_src", | |
348 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
349 | .num_parents = 4, | |
350 | .ops = &clk_rcg2_ops, | |
351 | }, | |
352 | }; | |
353 | ||
354 | static struct clk_rcg2 csi1_clk_src = { | |
355 | .cmd_rcgr = 0x3100, | |
356 | .hid_width = 5, | |
357 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
358 | .freq_tbl = ftbl_camss_csi0_3_clk, | |
359 | .clkr.hw.init = &(struct clk_init_data){ | |
360 | .name = "csi1_clk_src", | |
361 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
362 | .num_parents = 4, | |
363 | .ops = &clk_rcg2_ops, | |
364 | }, | |
365 | }; | |
366 | ||
367 | static struct clk_rcg2 csi2_clk_src = { | |
368 | .cmd_rcgr = 0x3160, | |
369 | .hid_width = 5, | |
370 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
371 | .freq_tbl = ftbl_camss_csi0_3_clk, | |
372 | .clkr.hw.init = &(struct clk_init_data){ | |
373 | .name = "csi2_clk_src", | |
374 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
375 | .num_parents = 4, | |
376 | .ops = &clk_rcg2_ops, | |
377 | }, | |
378 | }; | |
379 | ||
380 | static struct clk_rcg2 csi3_clk_src = { | |
381 | .cmd_rcgr = 0x31c0, | |
382 | .hid_width = 5, | |
383 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
384 | .freq_tbl = ftbl_camss_csi0_3_clk, | |
385 | .clkr.hw.init = &(struct clk_init_data){ | |
386 | .name = "csi3_clk_src", | |
387 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
388 | .num_parents = 4, | |
389 | .ops = &clk_rcg2_ops, | |
390 | }, | |
391 | }; | |
392 | ||
393 | static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = { | |
394 | F(37500000, P_GPLL0, 16, 0, 0), | |
395 | F(50000000, P_GPLL0, 12, 0, 0), | |
396 | F(60000000, P_GPLL0, 10, 0, 0), | |
397 | F(80000000, P_GPLL0, 7.5, 0, 0), | |
398 | F(100000000, P_GPLL0, 6, 0, 0), | |
399 | F(109090000, P_GPLL0, 5.5, 0, 0), | |
400 | F(133330000, P_GPLL0, 4.5, 0, 0), | |
401 | F(200000000, P_GPLL0, 3, 0, 0), | |
402 | F(228570000, P_MMPLL0, 3.5, 0, 0), | |
403 | F(266670000, P_MMPLL0, 3, 0, 0), | |
404 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
405 | F(400000000, P_MMPLL0, 2, 0, 0), | |
406 | F(465000000, P_MMPLL3, 2, 0, 0), | |
407 | { } | |
408 | }; | |
409 | ||
410 | static struct clk_rcg2 vfe0_clk_src = { | |
411 | .cmd_rcgr = 0x3600, | |
412 | .hid_width = 5, | |
413 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
414 | .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, | |
415 | .clkr.hw.init = &(struct clk_init_data){ | |
416 | .name = "vfe0_clk_src", | |
417 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
418 | .num_parents = 4, | |
419 | .ops = &clk_rcg2_ops, | |
420 | }, | |
421 | }; | |
422 | ||
423 | static struct clk_rcg2 vfe1_clk_src = { | |
424 | .cmd_rcgr = 0x3620, | |
425 | .hid_width = 5, | |
426 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
427 | .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, | |
428 | .clkr.hw.init = &(struct clk_init_data){ | |
429 | .name = "vfe1_clk_src", | |
430 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
431 | .num_parents = 4, | |
432 | .ops = &clk_rcg2_ops, | |
433 | }, | |
434 | }; | |
435 | ||
436 | static struct freq_tbl ftbl_mdss_mdp_clk[] = { | |
437 | F(37500000, P_GPLL0, 16, 0, 0), | |
438 | F(60000000, P_GPLL0, 10, 0, 0), | |
439 | F(75000000, P_GPLL0, 8, 0, 0), | |
440 | F(85710000, P_GPLL0, 7, 0, 0), | |
441 | F(100000000, P_GPLL0, 6, 0, 0), | |
442 | F(133330000, P_MMPLL0, 6, 0, 0), | |
443 | F(160000000, P_MMPLL0, 5, 0, 0), | |
444 | F(200000000, P_MMPLL0, 4, 0, 0), | |
445 | F(228570000, P_MMPLL0, 3.5, 0, 0), | |
446 | F(240000000, P_GPLL0, 2.5, 0, 0), | |
447 | F(266670000, P_MMPLL0, 3, 0, 0), | |
448 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
449 | { } | |
450 | }; | |
451 | ||
452 | static struct clk_rcg2 mdp_clk_src = { | |
453 | .cmd_rcgr = 0x2040, | |
454 | .hid_width = 5, | |
455 | .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map, | |
456 | .freq_tbl = ftbl_mdss_mdp_clk, | |
457 | .clkr.hw.init = &(struct clk_init_data){ | |
458 | .name = "mdp_clk_src", | |
459 | .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0, | |
460 | .num_parents = 6, | |
461 | .ops = &clk_rcg2_ops, | |
462 | }, | |
463 | }; | |
464 | ||
465 | static struct clk_rcg2 gfx3d_clk_src = { | |
466 | .cmd_rcgr = 0x4000, | |
467 | .hid_width = 5, | |
468 | .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map, | |
469 | .clkr.hw.init = &(struct clk_init_data){ | |
470 | .name = "gfx3d_clk_src", | |
471 | .parent_names = mmcc_xo_mmpll0_1_2_gpll0, | |
472 | .num_parents = 5, | |
473 | .ops = &clk_rcg2_ops, | |
474 | }, | |
475 | }; | |
476 | ||
477 | static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = { | |
478 | F(75000000, P_GPLL0, 8, 0, 0), | |
479 | F(133330000, P_GPLL0, 4.5, 0, 0), | |
480 | F(200000000, P_GPLL0, 3, 0, 0), | |
481 | F(228570000, P_MMPLL0, 3.5, 0, 0), | |
482 | F(266670000, P_MMPLL0, 3, 0, 0), | |
483 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
484 | { } | |
485 | }; | |
486 | ||
487 | static struct clk_rcg2 jpeg0_clk_src = { | |
488 | .cmd_rcgr = 0x3500, | |
489 | .hid_width = 5, | |
490 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
491 | .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, | |
492 | .clkr.hw.init = &(struct clk_init_data){ | |
493 | .name = "jpeg0_clk_src", | |
494 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
495 | .num_parents = 4, | |
496 | .ops = &clk_rcg2_ops, | |
497 | }, | |
498 | }; | |
499 | ||
500 | static struct clk_rcg2 jpeg1_clk_src = { | |
501 | .cmd_rcgr = 0x3520, | |
502 | .hid_width = 5, | |
503 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
504 | .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, | |
505 | .clkr.hw.init = &(struct clk_init_data){ | |
506 | .name = "jpeg1_clk_src", | |
507 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
508 | .num_parents = 4, | |
509 | .ops = &clk_rcg2_ops, | |
510 | }, | |
511 | }; | |
512 | ||
513 | static struct clk_rcg2 jpeg2_clk_src = { | |
514 | .cmd_rcgr = 0x3540, | |
515 | .hid_width = 5, | |
516 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
517 | .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, | |
518 | .clkr.hw.init = &(struct clk_init_data){ | |
519 | .name = "jpeg2_clk_src", | |
520 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
521 | .num_parents = 4, | |
522 | .ops = &clk_rcg2_ops, | |
523 | }, | |
524 | }; | |
525 | ||
d8b21201 SB |
526 | static struct clk_rcg2 pclk0_clk_src = { |
527 | .cmd_rcgr = 0x2000, | |
528 | .mnd_width = 8, | |
529 | .hid_width = 5, | |
530 | .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, | |
d8b21201 SB |
531 | .clkr.hw.init = &(struct clk_init_data){ |
532 | .name = "pclk0_clk_src", | |
533 | .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, | |
534 | .num_parents = 6, | |
b7b7cc70 SB |
535 | .ops = &clk_pixel_ops, |
536 | .flags = CLK_SET_RATE_PARENT, | |
d8b21201 SB |
537 | }, |
538 | }; | |
539 | ||
540 | static struct clk_rcg2 pclk1_clk_src = { | |
541 | .cmd_rcgr = 0x2020, | |
542 | .mnd_width = 8, | |
543 | .hid_width = 5, | |
544 | .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, | |
d8b21201 SB |
545 | .clkr.hw.init = &(struct clk_init_data){ |
546 | .name = "pclk1_clk_src", | |
547 | .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, | |
548 | .num_parents = 6, | |
b7b7cc70 SB |
549 | .ops = &clk_pixel_ops, |
550 | .flags = CLK_SET_RATE_PARENT, | |
d8b21201 SB |
551 | }, |
552 | }; | |
553 | ||
554 | static struct freq_tbl ftbl_venus0_vcodec0_clk[] = { | |
555 | F(50000000, P_GPLL0, 12, 0, 0), | |
556 | F(100000000, P_GPLL0, 6, 0, 0), | |
557 | F(133330000, P_MMPLL0, 6, 0, 0), | |
558 | F(200000000, P_MMPLL0, 4, 0, 0), | |
559 | F(266670000, P_MMPLL0, 3, 0, 0), | |
560 | F(465000000, P_MMPLL3, 2, 0, 0), | |
561 | { } | |
562 | }; | |
563 | ||
564 | static struct clk_rcg2 vcodec0_clk_src = { | |
565 | .cmd_rcgr = 0x1000, | |
566 | .mnd_width = 8, | |
567 | .hid_width = 5, | |
568 | .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map, | |
569 | .freq_tbl = ftbl_venus0_vcodec0_clk, | |
570 | .clkr.hw.init = &(struct clk_init_data){ | |
571 | .name = "vcodec0_clk_src", | |
572 | .parent_names = mmcc_xo_mmpll0_1_3_gpll0, | |
573 | .num_parents = 5, | |
574 | .ops = &clk_rcg2_ops, | |
575 | }, | |
576 | }; | |
577 | ||
578 | static struct freq_tbl ftbl_camss_cci_cci_clk[] = { | |
579 | F(19200000, P_XO, 1, 0, 0), | |
580 | { } | |
581 | }; | |
582 | ||
583 | static struct clk_rcg2 cci_clk_src = { | |
584 | .cmd_rcgr = 0x3300, | |
585 | .hid_width = 5, | |
586 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
587 | .freq_tbl = ftbl_camss_cci_cci_clk, | |
588 | .clkr.hw.init = &(struct clk_init_data){ | |
589 | .name = "cci_clk_src", | |
590 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
591 | .num_parents = 4, | |
592 | .ops = &clk_rcg2_ops, | |
593 | }, | |
594 | }; | |
595 | ||
596 | static struct freq_tbl ftbl_camss_gp0_1_clk[] = { | |
597 | F(10000, P_XO, 16, 1, 120), | |
598 | F(24000, P_XO, 16, 1, 50), | |
599 | F(6000000, P_GPLL0, 10, 1, 10), | |
600 | F(12000000, P_GPLL0, 10, 1, 5), | |
601 | F(13000000, P_GPLL0, 4, 13, 150), | |
602 | F(24000000, P_GPLL0, 5, 1, 5), | |
603 | { } | |
604 | }; | |
605 | ||
606 | static struct clk_rcg2 camss_gp0_clk_src = { | |
607 | .cmd_rcgr = 0x3420, | |
608 | .mnd_width = 8, | |
609 | .hid_width = 5, | |
610 | .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map, | |
611 | .freq_tbl = ftbl_camss_gp0_1_clk, | |
612 | .clkr.hw.init = &(struct clk_init_data){ | |
613 | .name = "camss_gp0_clk_src", | |
614 | .parent_names = mmcc_xo_mmpll0_1_gpll1_0, | |
615 | .num_parents = 5, | |
616 | .ops = &clk_rcg2_ops, | |
617 | }, | |
618 | }; | |
619 | ||
620 | static struct clk_rcg2 camss_gp1_clk_src = { | |
621 | .cmd_rcgr = 0x3450, | |
622 | .mnd_width = 8, | |
623 | .hid_width = 5, | |
624 | .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map, | |
625 | .freq_tbl = ftbl_camss_gp0_1_clk, | |
626 | .clkr.hw.init = &(struct clk_init_data){ | |
627 | .name = "camss_gp1_clk_src", | |
628 | .parent_names = mmcc_xo_mmpll0_1_gpll1_0, | |
629 | .num_parents = 5, | |
630 | .ops = &clk_rcg2_ops, | |
631 | }, | |
632 | }; | |
633 | ||
634 | static struct freq_tbl ftbl_camss_mclk0_3_clk[] = { | |
635 | F(4800000, P_XO, 4, 0, 0), | |
636 | F(6000000, P_GPLL0, 10, 1, 10), | |
637 | F(8000000, P_GPLL0, 15, 1, 5), | |
638 | F(9600000, P_XO, 2, 0, 0), | |
639 | F(16000000, P_GPLL0, 12.5, 1, 3), | |
640 | F(19200000, P_XO, 1, 0, 0), | |
641 | F(24000000, P_GPLL0, 5, 1, 5), | |
642 | F(32000000, P_MMPLL0, 5, 1, 5), | |
643 | F(48000000, P_GPLL0, 12.5, 0, 0), | |
644 | F(64000000, P_MMPLL0, 12.5, 0, 0), | |
645 | F(66670000, P_GPLL0, 9, 0, 0), | |
646 | { } | |
647 | }; | |
648 | ||
649 | static struct clk_rcg2 mclk0_clk_src = { | |
650 | .cmd_rcgr = 0x3360, | |
651 | .hid_width = 5, | |
652 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
653 | .freq_tbl = ftbl_camss_mclk0_3_clk, | |
654 | .clkr.hw.init = &(struct clk_init_data){ | |
655 | .name = "mclk0_clk_src", | |
656 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
657 | .num_parents = 4, | |
658 | .ops = &clk_rcg2_ops, | |
659 | }, | |
660 | }; | |
661 | ||
662 | static struct clk_rcg2 mclk1_clk_src = { | |
663 | .cmd_rcgr = 0x3390, | |
664 | .hid_width = 5, | |
665 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
666 | .freq_tbl = ftbl_camss_mclk0_3_clk, | |
667 | .clkr.hw.init = &(struct clk_init_data){ | |
668 | .name = "mclk1_clk_src", | |
669 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
670 | .num_parents = 4, | |
671 | .ops = &clk_rcg2_ops, | |
672 | }, | |
673 | }; | |
674 | ||
675 | static struct clk_rcg2 mclk2_clk_src = { | |
676 | .cmd_rcgr = 0x33c0, | |
677 | .hid_width = 5, | |
678 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
679 | .freq_tbl = ftbl_camss_mclk0_3_clk, | |
680 | .clkr.hw.init = &(struct clk_init_data){ | |
681 | .name = "mclk2_clk_src", | |
682 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
683 | .num_parents = 4, | |
684 | .ops = &clk_rcg2_ops, | |
685 | }, | |
686 | }; | |
687 | ||
688 | static struct clk_rcg2 mclk3_clk_src = { | |
689 | .cmd_rcgr = 0x33f0, | |
690 | .hid_width = 5, | |
691 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
692 | .freq_tbl = ftbl_camss_mclk0_3_clk, | |
693 | .clkr.hw.init = &(struct clk_init_data){ | |
694 | .name = "mclk3_clk_src", | |
695 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
696 | .num_parents = 4, | |
697 | .ops = &clk_rcg2_ops, | |
698 | }, | |
699 | }; | |
700 | ||
701 | static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = { | |
702 | F(100000000, P_GPLL0, 6, 0, 0), | |
703 | F(200000000, P_MMPLL0, 4, 0, 0), | |
704 | { } | |
705 | }; | |
706 | ||
707 | static struct clk_rcg2 csi0phytimer_clk_src = { | |
708 | .cmd_rcgr = 0x3000, | |
709 | .hid_width = 5, | |
710 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
711 | .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, | |
712 | .clkr.hw.init = &(struct clk_init_data){ | |
713 | .name = "csi0phytimer_clk_src", | |
714 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
715 | .num_parents = 4, | |
716 | .ops = &clk_rcg2_ops, | |
717 | }, | |
718 | }; | |
719 | ||
720 | static struct clk_rcg2 csi1phytimer_clk_src = { | |
721 | .cmd_rcgr = 0x3030, | |
722 | .hid_width = 5, | |
723 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
724 | .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, | |
725 | .clkr.hw.init = &(struct clk_init_data){ | |
726 | .name = "csi1phytimer_clk_src", | |
727 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
728 | .num_parents = 4, | |
729 | .ops = &clk_rcg2_ops, | |
730 | }, | |
731 | }; | |
732 | ||
733 | static struct clk_rcg2 csi2phytimer_clk_src = { | |
734 | .cmd_rcgr = 0x3060, | |
735 | .hid_width = 5, | |
736 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
737 | .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, | |
738 | .clkr.hw.init = &(struct clk_init_data){ | |
739 | .name = "csi2phytimer_clk_src", | |
740 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
741 | .num_parents = 4, | |
742 | .ops = &clk_rcg2_ops, | |
743 | }, | |
744 | }; | |
745 | ||
746 | static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = { | |
747 | F(133330000, P_GPLL0, 4.5, 0, 0), | |
748 | F(266670000, P_MMPLL0, 3, 0, 0), | |
749 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
750 | F(400000000, P_MMPLL0, 2, 0, 0), | |
751 | F(465000000, P_MMPLL3, 2, 0, 0), | |
752 | { } | |
753 | }; | |
754 | ||
755 | static struct clk_rcg2 cpp_clk_src = { | |
756 | .cmd_rcgr = 0x3640, | |
757 | .hid_width = 5, | |
758 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
759 | .freq_tbl = ftbl_camss_vfe_cpp_clk, | |
760 | .clkr.hw.init = &(struct clk_init_data){ | |
761 | .name = "cpp_clk_src", | |
762 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
763 | .num_parents = 4, | |
764 | .ops = &clk_rcg2_ops, | |
765 | }, | |
766 | }; | |
767 | ||
b7b7cc70 SB |
768 | static struct freq_tbl byte_freq_tbl[] = { |
769 | { .src = P_DSI0PLL_BYTE }, | |
d8b21201 SB |
770 | { } |
771 | }; | |
772 | ||
773 | static struct clk_rcg2 byte0_clk_src = { | |
774 | .cmd_rcgr = 0x2120, | |
775 | .hid_width = 5, | |
b7b7cc70 SB |
776 | .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, |
777 | .freq_tbl = byte_freq_tbl, | |
d8b21201 SB |
778 | .clkr.hw.init = &(struct clk_init_data){ |
779 | .name = "byte0_clk_src", | |
b7b7cc70 | 780 | .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, |
d8b21201 | 781 | .num_parents = 6, |
8ee9c7de | 782 | .ops = &clk_byte2_ops, |
b7b7cc70 | 783 | .flags = CLK_SET_RATE_PARENT, |
d8b21201 SB |
784 | }, |
785 | }; | |
786 | ||
787 | static struct clk_rcg2 byte1_clk_src = { | |
788 | .cmd_rcgr = 0x2140, | |
789 | .hid_width = 5, | |
b7b7cc70 SB |
790 | .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, |
791 | .freq_tbl = byte_freq_tbl, | |
d8b21201 SB |
792 | .clkr.hw.init = &(struct clk_init_data){ |
793 | .name = "byte1_clk_src", | |
b7b7cc70 | 794 | .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, |
d8b21201 | 795 | .num_parents = 6, |
8ee9c7de | 796 | .ops = &clk_byte2_ops, |
b7b7cc70 | 797 | .flags = CLK_SET_RATE_PARENT, |
d8b21201 SB |
798 | }, |
799 | }; | |
800 | ||
801 | static struct freq_tbl ftbl_mdss_edpaux_clk[] = { | |
802 | F(19200000, P_XO, 1, 0, 0), | |
803 | { } | |
804 | }; | |
805 | ||
806 | static struct clk_rcg2 edpaux_clk_src = { | |
807 | .cmd_rcgr = 0x20e0, | |
808 | .hid_width = 5, | |
809 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
810 | .freq_tbl = ftbl_mdss_edpaux_clk, | |
811 | .clkr.hw.init = &(struct clk_init_data){ | |
812 | .name = "edpaux_clk_src", | |
813 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
814 | .num_parents = 4, | |
815 | .ops = &clk_rcg2_ops, | |
816 | }, | |
817 | }; | |
818 | ||
819 | static struct freq_tbl ftbl_mdss_edplink_clk[] = { | |
820 | F(135000000, P_EDPLINK, 2, 0, 0), | |
821 | F(270000000, P_EDPLINK, 11, 0, 0), | |
822 | { } | |
823 | }; | |
824 | ||
825 | static struct clk_rcg2 edplink_clk_src = { | |
826 | .cmd_rcgr = 0x20c0, | |
827 | .hid_width = 5, | |
828 | .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, | |
829 | .freq_tbl = ftbl_mdss_edplink_clk, | |
830 | .clkr.hw.init = &(struct clk_init_data){ | |
831 | .name = "edplink_clk_src", | |
832 | .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, | |
833 | .num_parents = 6, | |
834 | .ops = &clk_rcg2_ops, | |
b7b7cc70 | 835 | .flags = CLK_SET_RATE_PARENT, |
d8b21201 SB |
836 | }, |
837 | }; | |
838 | ||
b7b7cc70 SB |
839 | static struct freq_tbl edp_pixel_freq_tbl[] = { |
840 | { .src = P_EDPVCO }, | |
d8b21201 SB |
841 | { } |
842 | }; | |
843 | ||
844 | static struct clk_rcg2 edppixel_clk_src = { | |
845 | .cmd_rcgr = 0x20a0, | |
846 | .mnd_width = 8, | |
847 | .hid_width = 5, | |
848 | .parent_map = mmcc_xo_dsi_hdmi_edp_map, | |
b7b7cc70 | 849 | .freq_tbl = edp_pixel_freq_tbl, |
d8b21201 SB |
850 | .clkr.hw.init = &(struct clk_init_data){ |
851 | .name = "edppixel_clk_src", | |
852 | .parent_names = mmcc_xo_dsi_hdmi_edp, | |
853 | .num_parents = 6, | |
b7b7cc70 | 854 | .ops = &clk_edp_pixel_ops, |
d8b21201 SB |
855 | }, |
856 | }; | |
857 | ||
858 | static struct freq_tbl ftbl_mdss_esc0_1_clk[] = { | |
859 | F(19200000, P_XO, 1, 0, 0), | |
860 | { } | |
861 | }; | |
862 | ||
863 | static struct clk_rcg2 esc0_clk_src = { | |
864 | .cmd_rcgr = 0x2160, | |
865 | .hid_width = 5, | |
b7b7cc70 | 866 | .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, |
d8b21201 SB |
867 | .freq_tbl = ftbl_mdss_esc0_1_clk, |
868 | .clkr.hw.init = &(struct clk_init_data){ | |
869 | .name = "esc0_clk_src", | |
b7b7cc70 | 870 | .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, |
d8b21201 SB |
871 | .num_parents = 6, |
872 | .ops = &clk_rcg2_ops, | |
873 | }, | |
874 | }; | |
875 | ||
876 | static struct clk_rcg2 esc1_clk_src = { | |
877 | .cmd_rcgr = 0x2180, | |
878 | .hid_width = 5, | |
b7b7cc70 | 879 | .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, |
d8b21201 SB |
880 | .freq_tbl = ftbl_mdss_esc0_1_clk, |
881 | .clkr.hw.init = &(struct clk_init_data){ | |
882 | .name = "esc1_clk_src", | |
b7b7cc70 | 883 | .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, |
d8b21201 SB |
884 | .num_parents = 6, |
885 | .ops = &clk_rcg2_ops, | |
886 | }, | |
887 | }; | |
888 | ||
b7b7cc70 SB |
889 | static struct freq_tbl extpclk_freq_tbl[] = { |
890 | { .src = P_HDMIPLL }, | |
d8b21201 SB |
891 | { } |
892 | }; | |
893 | ||
894 | static struct clk_rcg2 extpclk_clk_src = { | |
895 | .cmd_rcgr = 0x2060, | |
896 | .hid_width = 5, | |
897 | .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, | |
b7b7cc70 | 898 | .freq_tbl = extpclk_freq_tbl, |
d8b21201 SB |
899 | .clkr.hw.init = &(struct clk_init_data){ |
900 | .name = "extpclk_clk_src", | |
901 | .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, | |
902 | .num_parents = 6, | |
b7b7cc70 SB |
903 | .ops = &clk_byte_ops, |
904 | .flags = CLK_SET_RATE_PARENT, | |
d8b21201 SB |
905 | }, |
906 | }; | |
907 | ||
908 | static struct freq_tbl ftbl_mdss_hdmi_clk[] = { | |
909 | F(19200000, P_XO, 1, 0, 0), | |
910 | { } | |
911 | }; | |
912 | ||
913 | static struct clk_rcg2 hdmi_clk_src = { | |
914 | .cmd_rcgr = 0x2100, | |
915 | .hid_width = 5, | |
916 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
917 | .freq_tbl = ftbl_mdss_hdmi_clk, | |
918 | .clkr.hw.init = &(struct clk_init_data){ | |
919 | .name = "hdmi_clk_src", | |
920 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
921 | .num_parents = 4, | |
922 | .ops = &clk_rcg2_ops, | |
923 | }, | |
924 | }; | |
925 | ||
926 | static struct freq_tbl ftbl_mdss_vsync_clk[] = { | |
927 | F(19200000, P_XO, 1, 0, 0), | |
928 | { } | |
929 | }; | |
930 | ||
931 | static struct clk_rcg2 vsync_clk_src = { | |
932 | .cmd_rcgr = 0x2080, | |
933 | .hid_width = 5, | |
934 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
935 | .freq_tbl = ftbl_mdss_vsync_clk, | |
936 | .clkr.hw.init = &(struct clk_init_data){ | |
937 | .name = "vsync_clk_src", | |
938 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
939 | .num_parents = 4, | |
940 | .ops = &clk_rcg2_ops, | |
941 | }, | |
942 | }; | |
943 | ||
944 | static struct clk_branch camss_cci_cci_ahb_clk = { | |
945 | .halt_reg = 0x3348, | |
946 | .clkr = { | |
947 | .enable_reg = 0x3348, | |
948 | .enable_mask = BIT(0), | |
949 | .hw.init = &(struct clk_init_data){ | |
950 | .name = "camss_cci_cci_ahb_clk", | |
951 | .parent_names = (const char *[]){ | |
952 | "mmss_ahb_clk_src", | |
953 | }, | |
954 | .num_parents = 1, | |
955 | .ops = &clk_branch2_ops, | |
956 | }, | |
957 | }, | |
958 | }; | |
959 | ||
960 | static struct clk_branch camss_cci_cci_clk = { | |
961 | .halt_reg = 0x3344, | |
962 | .clkr = { | |
963 | .enable_reg = 0x3344, | |
964 | .enable_mask = BIT(0), | |
965 | .hw.init = &(struct clk_init_data){ | |
966 | .name = "camss_cci_cci_clk", | |
967 | .parent_names = (const char *[]){ | |
968 | "cci_clk_src", | |
969 | }, | |
970 | .num_parents = 1, | |
971 | .flags = CLK_SET_RATE_PARENT, | |
972 | .ops = &clk_branch2_ops, | |
973 | }, | |
974 | }, | |
975 | }; | |
976 | ||
977 | static struct clk_branch camss_csi0_ahb_clk = { | |
978 | .halt_reg = 0x30bc, | |
979 | .clkr = { | |
980 | .enable_reg = 0x30bc, | |
981 | .enable_mask = BIT(0), | |
982 | .hw.init = &(struct clk_init_data){ | |
983 | .name = "camss_csi0_ahb_clk", | |
984 | .parent_names = (const char *[]){ | |
985 | "mmss_ahb_clk_src", | |
986 | }, | |
987 | .num_parents = 1, | |
988 | .ops = &clk_branch2_ops, | |
989 | }, | |
990 | }, | |
991 | }; | |
992 | ||
993 | static struct clk_branch camss_csi0_clk = { | |
994 | .halt_reg = 0x30b4, | |
995 | .clkr = { | |
996 | .enable_reg = 0x30b4, | |
997 | .enable_mask = BIT(0), | |
998 | .hw.init = &(struct clk_init_data){ | |
999 | .name = "camss_csi0_clk", | |
1000 | .parent_names = (const char *[]){ | |
1001 | "csi0_clk_src", | |
1002 | }, | |
1003 | .num_parents = 1, | |
1004 | .flags = CLK_SET_RATE_PARENT, | |
1005 | .ops = &clk_branch2_ops, | |
1006 | }, | |
1007 | }, | |
1008 | }; | |
1009 | ||
1010 | static struct clk_branch camss_csi0phy_clk = { | |
1011 | .halt_reg = 0x30c4, | |
1012 | .clkr = { | |
1013 | .enable_reg = 0x30c4, | |
1014 | .enable_mask = BIT(0), | |
1015 | .hw.init = &(struct clk_init_data){ | |
1016 | .name = "camss_csi0phy_clk", | |
1017 | .parent_names = (const char *[]){ | |
1018 | "csi0_clk_src", | |
1019 | }, | |
1020 | .num_parents = 1, | |
1021 | .flags = CLK_SET_RATE_PARENT, | |
1022 | .ops = &clk_branch2_ops, | |
1023 | }, | |
1024 | }, | |
1025 | }; | |
1026 | ||
1027 | static struct clk_branch camss_csi0pix_clk = { | |
1028 | .halt_reg = 0x30e4, | |
1029 | .clkr = { | |
1030 | .enable_reg = 0x30e4, | |
1031 | .enable_mask = BIT(0), | |
1032 | .hw.init = &(struct clk_init_data){ | |
1033 | .name = "camss_csi0pix_clk", | |
1034 | .parent_names = (const char *[]){ | |
1035 | "csi0_clk_src", | |
1036 | }, | |
1037 | .num_parents = 1, | |
1038 | .flags = CLK_SET_RATE_PARENT, | |
1039 | .ops = &clk_branch2_ops, | |
1040 | }, | |
1041 | }, | |
1042 | }; | |
1043 | ||
1044 | static struct clk_branch camss_csi0rdi_clk = { | |
1045 | .halt_reg = 0x30d4, | |
1046 | .clkr = { | |
1047 | .enable_reg = 0x30d4, | |
1048 | .enable_mask = BIT(0), | |
1049 | .hw.init = &(struct clk_init_data){ | |
1050 | .name = "camss_csi0rdi_clk", | |
1051 | .parent_names = (const char *[]){ | |
1052 | "csi0_clk_src", | |
1053 | }, | |
1054 | .num_parents = 1, | |
1055 | .flags = CLK_SET_RATE_PARENT, | |
1056 | .ops = &clk_branch2_ops, | |
1057 | }, | |
1058 | }, | |
1059 | }; | |
1060 | ||
1061 | static struct clk_branch camss_csi1_ahb_clk = { | |
1062 | .halt_reg = 0x3128, | |
1063 | .clkr = { | |
1064 | .enable_reg = 0x3128, | |
1065 | .enable_mask = BIT(0), | |
1066 | .hw.init = &(struct clk_init_data){ | |
1067 | .name = "camss_csi1_ahb_clk", | |
1068 | .parent_names = (const char *[]){ | |
1069 | "mmss_ahb_clk_src", | |
1070 | }, | |
1071 | .num_parents = 1, | |
1072 | .ops = &clk_branch2_ops, | |
1073 | }, | |
1074 | }, | |
1075 | }; | |
1076 | ||
1077 | static struct clk_branch camss_csi1_clk = { | |
1078 | .halt_reg = 0x3124, | |
1079 | .clkr = { | |
1080 | .enable_reg = 0x3124, | |
1081 | .enable_mask = BIT(0), | |
1082 | .hw.init = &(struct clk_init_data){ | |
1083 | .name = "camss_csi1_clk", | |
1084 | .parent_names = (const char *[]){ | |
1085 | "csi1_clk_src", | |
1086 | }, | |
1087 | .num_parents = 1, | |
1088 | .flags = CLK_SET_RATE_PARENT, | |
1089 | .ops = &clk_branch2_ops, | |
1090 | }, | |
1091 | }, | |
1092 | }; | |
1093 | ||
1094 | static struct clk_branch camss_csi1phy_clk = { | |
1095 | .halt_reg = 0x3134, | |
1096 | .clkr = { | |
1097 | .enable_reg = 0x3134, | |
1098 | .enable_mask = BIT(0), | |
1099 | .hw.init = &(struct clk_init_data){ | |
1100 | .name = "camss_csi1phy_clk", | |
1101 | .parent_names = (const char *[]){ | |
1102 | "csi1_clk_src", | |
1103 | }, | |
1104 | .num_parents = 1, | |
1105 | .flags = CLK_SET_RATE_PARENT, | |
1106 | .ops = &clk_branch2_ops, | |
1107 | }, | |
1108 | }, | |
1109 | }; | |
1110 | ||
1111 | static struct clk_branch camss_csi1pix_clk = { | |
1112 | .halt_reg = 0x3154, | |
1113 | .clkr = { | |
1114 | .enable_reg = 0x3154, | |
1115 | .enable_mask = BIT(0), | |
1116 | .hw.init = &(struct clk_init_data){ | |
1117 | .name = "camss_csi1pix_clk", | |
1118 | .parent_names = (const char *[]){ | |
1119 | "csi1_clk_src", | |
1120 | }, | |
1121 | .num_parents = 1, | |
1122 | .flags = CLK_SET_RATE_PARENT, | |
1123 | .ops = &clk_branch2_ops, | |
1124 | }, | |
1125 | }, | |
1126 | }; | |
1127 | ||
1128 | static struct clk_branch camss_csi1rdi_clk = { | |
1129 | .halt_reg = 0x3144, | |
1130 | .clkr = { | |
1131 | .enable_reg = 0x3144, | |
1132 | .enable_mask = BIT(0), | |
1133 | .hw.init = &(struct clk_init_data){ | |
1134 | .name = "camss_csi1rdi_clk", | |
1135 | .parent_names = (const char *[]){ | |
1136 | "csi1_clk_src", | |
1137 | }, | |
1138 | .num_parents = 1, | |
1139 | .flags = CLK_SET_RATE_PARENT, | |
1140 | .ops = &clk_branch2_ops, | |
1141 | }, | |
1142 | }, | |
1143 | }; | |
1144 | ||
1145 | static struct clk_branch camss_csi2_ahb_clk = { | |
1146 | .halt_reg = 0x3188, | |
1147 | .clkr = { | |
1148 | .enable_reg = 0x3188, | |
1149 | .enable_mask = BIT(0), | |
1150 | .hw.init = &(struct clk_init_data){ | |
1151 | .name = "camss_csi2_ahb_clk", | |
1152 | .parent_names = (const char *[]){ | |
1153 | "mmss_ahb_clk_src", | |
1154 | }, | |
1155 | .num_parents = 1, | |
1156 | .ops = &clk_branch2_ops, | |
1157 | }, | |
1158 | }, | |
1159 | }; | |
1160 | ||
1161 | static struct clk_branch camss_csi2_clk = { | |
1162 | .halt_reg = 0x3184, | |
1163 | .clkr = { | |
1164 | .enable_reg = 0x3184, | |
1165 | .enable_mask = BIT(0), | |
1166 | .hw.init = &(struct clk_init_data){ | |
1167 | .name = "camss_csi2_clk", | |
1168 | .parent_names = (const char *[]){ | |
1169 | "csi2_clk_src", | |
1170 | }, | |
1171 | .num_parents = 1, | |
1172 | .flags = CLK_SET_RATE_PARENT, | |
1173 | .ops = &clk_branch2_ops, | |
1174 | }, | |
1175 | }, | |
1176 | }; | |
1177 | ||
1178 | static struct clk_branch camss_csi2phy_clk = { | |
1179 | .halt_reg = 0x3194, | |
1180 | .clkr = { | |
1181 | .enable_reg = 0x3194, | |
1182 | .enable_mask = BIT(0), | |
1183 | .hw.init = &(struct clk_init_data){ | |
1184 | .name = "camss_csi2phy_clk", | |
1185 | .parent_names = (const char *[]){ | |
1186 | "csi2_clk_src", | |
1187 | }, | |
1188 | .num_parents = 1, | |
1189 | .flags = CLK_SET_RATE_PARENT, | |
1190 | .ops = &clk_branch2_ops, | |
1191 | }, | |
1192 | }, | |
1193 | }; | |
1194 | ||
1195 | static struct clk_branch camss_csi2pix_clk = { | |
1196 | .halt_reg = 0x31b4, | |
1197 | .clkr = { | |
1198 | .enable_reg = 0x31b4, | |
1199 | .enable_mask = BIT(0), | |
1200 | .hw.init = &(struct clk_init_data){ | |
1201 | .name = "camss_csi2pix_clk", | |
1202 | .parent_names = (const char *[]){ | |
1203 | "csi2_clk_src", | |
1204 | }, | |
1205 | .num_parents = 1, | |
1206 | .flags = CLK_SET_RATE_PARENT, | |
1207 | .ops = &clk_branch2_ops, | |
1208 | }, | |
1209 | }, | |
1210 | }; | |
1211 | ||
1212 | static struct clk_branch camss_csi2rdi_clk = { | |
1213 | .halt_reg = 0x31a4, | |
1214 | .clkr = { | |
1215 | .enable_reg = 0x31a4, | |
1216 | .enable_mask = BIT(0), | |
1217 | .hw.init = &(struct clk_init_data){ | |
1218 | .name = "camss_csi2rdi_clk", | |
1219 | .parent_names = (const char *[]){ | |
1220 | "csi2_clk_src", | |
1221 | }, | |
1222 | .num_parents = 1, | |
1223 | .flags = CLK_SET_RATE_PARENT, | |
1224 | .ops = &clk_branch2_ops, | |
1225 | }, | |
1226 | }, | |
1227 | }; | |
1228 | ||
1229 | static struct clk_branch camss_csi3_ahb_clk = { | |
1230 | .halt_reg = 0x31e8, | |
1231 | .clkr = { | |
1232 | .enable_reg = 0x31e8, | |
1233 | .enable_mask = BIT(0), | |
1234 | .hw.init = &(struct clk_init_data){ | |
1235 | .name = "camss_csi3_ahb_clk", | |
1236 | .parent_names = (const char *[]){ | |
1237 | "mmss_ahb_clk_src", | |
1238 | }, | |
1239 | .num_parents = 1, | |
1240 | .ops = &clk_branch2_ops, | |
1241 | }, | |
1242 | }, | |
1243 | }; | |
1244 | ||
1245 | static struct clk_branch camss_csi3_clk = { | |
1246 | .halt_reg = 0x31e4, | |
1247 | .clkr = { | |
1248 | .enable_reg = 0x31e4, | |
1249 | .enable_mask = BIT(0), | |
1250 | .hw.init = &(struct clk_init_data){ | |
1251 | .name = "camss_csi3_clk", | |
1252 | .parent_names = (const char *[]){ | |
1253 | "csi3_clk_src", | |
1254 | }, | |
1255 | .num_parents = 1, | |
1256 | .flags = CLK_SET_RATE_PARENT, | |
1257 | .ops = &clk_branch2_ops, | |
1258 | }, | |
1259 | }, | |
1260 | }; | |
1261 | ||
1262 | static struct clk_branch camss_csi3phy_clk = { | |
1263 | .halt_reg = 0x31f4, | |
1264 | .clkr = { | |
1265 | .enable_reg = 0x31f4, | |
1266 | .enable_mask = BIT(0), | |
1267 | .hw.init = &(struct clk_init_data){ | |
1268 | .name = "camss_csi3phy_clk", | |
1269 | .parent_names = (const char *[]){ | |
1270 | "csi3_clk_src", | |
1271 | }, | |
1272 | .num_parents = 1, | |
1273 | .flags = CLK_SET_RATE_PARENT, | |
1274 | .ops = &clk_branch2_ops, | |
1275 | }, | |
1276 | }, | |
1277 | }; | |
1278 | ||
1279 | static struct clk_branch camss_csi3pix_clk = { | |
1280 | .halt_reg = 0x3214, | |
1281 | .clkr = { | |
1282 | .enable_reg = 0x3214, | |
1283 | .enable_mask = BIT(0), | |
1284 | .hw.init = &(struct clk_init_data){ | |
1285 | .name = "camss_csi3pix_clk", | |
1286 | .parent_names = (const char *[]){ | |
1287 | "csi3_clk_src", | |
1288 | }, | |
1289 | .num_parents = 1, | |
1290 | .flags = CLK_SET_RATE_PARENT, | |
1291 | .ops = &clk_branch2_ops, | |
1292 | }, | |
1293 | }, | |
1294 | }; | |
1295 | ||
1296 | static struct clk_branch camss_csi3rdi_clk = { | |
1297 | .halt_reg = 0x3204, | |
1298 | .clkr = { | |
1299 | .enable_reg = 0x3204, | |
1300 | .enable_mask = BIT(0), | |
1301 | .hw.init = &(struct clk_init_data){ | |
1302 | .name = "camss_csi3rdi_clk", | |
1303 | .parent_names = (const char *[]){ | |
1304 | "csi3_clk_src", | |
1305 | }, | |
1306 | .num_parents = 1, | |
1307 | .flags = CLK_SET_RATE_PARENT, | |
1308 | .ops = &clk_branch2_ops, | |
1309 | }, | |
1310 | }, | |
1311 | }; | |
1312 | ||
1313 | static struct clk_branch camss_csi_vfe0_clk = { | |
1314 | .halt_reg = 0x3704, | |
1315 | .clkr = { | |
1316 | .enable_reg = 0x3704, | |
1317 | .enable_mask = BIT(0), | |
1318 | .hw.init = &(struct clk_init_data){ | |
1319 | .name = "camss_csi_vfe0_clk", | |
1320 | .parent_names = (const char *[]){ | |
1321 | "vfe0_clk_src", | |
1322 | }, | |
1323 | .num_parents = 1, | |
1324 | .flags = CLK_SET_RATE_PARENT, | |
1325 | .ops = &clk_branch2_ops, | |
1326 | }, | |
1327 | }, | |
1328 | }; | |
1329 | ||
1330 | static struct clk_branch camss_csi_vfe1_clk = { | |
1331 | .halt_reg = 0x3714, | |
1332 | .clkr = { | |
1333 | .enable_reg = 0x3714, | |
1334 | .enable_mask = BIT(0), | |
1335 | .hw.init = &(struct clk_init_data){ | |
1336 | .name = "camss_csi_vfe1_clk", | |
1337 | .parent_names = (const char *[]){ | |
1338 | "vfe1_clk_src", | |
1339 | }, | |
1340 | .num_parents = 1, | |
1341 | .flags = CLK_SET_RATE_PARENT, | |
1342 | .ops = &clk_branch2_ops, | |
1343 | }, | |
1344 | }, | |
1345 | }; | |
1346 | ||
1347 | static struct clk_branch camss_gp0_clk = { | |
1348 | .halt_reg = 0x3444, | |
1349 | .clkr = { | |
1350 | .enable_reg = 0x3444, | |
1351 | .enable_mask = BIT(0), | |
1352 | .hw.init = &(struct clk_init_data){ | |
1353 | .name = "camss_gp0_clk", | |
1354 | .parent_names = (const char *[]){ | |
1355 | "camss_gp0_clk_src", | |
1356 | }, | |
1357 | .num_parents = 1, | |
1358 | .flags = CLK_SET_RATE_PARENT, | |
1359 | .ops = &clk_branch2_ops, | |
1360 | }, | |
1361 | }, | |
1362 | }; | |
1363 | ||
1364 | static struct clk_branch camss_gp1_clk = { | |
1365 | .halt_reg = 0x3474, | |
1366 | .clkr = { | |
1367 | .enable_reg = 0x3474, | |
1368 | .enable_mask = BIT(0), | |
1369 | .hw.init = &(struct clk_init_data){ | |
1370 | .name = "camss_gp1_clk", | |
1371 | .parent_names = (const char *[]){ | |
1372 | "camss_gp1_clk_src", | |
1373 | }, | |
1374 | .num_parents = 1, | |
1375 | .flags = CLK_SET_RATE_PARENT, | |
1376 | .ops = &clk_branch2_ops, | |
1377 | }, | |
1378 | }, | |
1379 | }; | |
1380 | ||
1381 | static struct clk_branch camss_ispif_ahb_clk = { | |
1382 | .halt_reg = 0x3224, | |
1383 | .clkr = { | |
1384 | .enable_reg = 0x3224, | |
1385 | .enable_mask = BIT(0), | |
1386 | .hw.init = &(struct clk_init_data){ | |
1387 | .name = "camss_ispif_ahb_clk", | |
1388 | .parent_names = (const char *[]){ | |
1389 | "mmss_ahb_clk_src", | |
1390 | }, | |
1391 | .num_parents = 1, | |
1392 | .ops = &clk_branch2_ops, | |
1393 | }, | |
1394 | }, | |
1395 | }; | |
1396 | ||
1397 | static struct clk_branch camss_jpeg_jpeg0_clk = { | |
1398 | .halt_reg = 0x35a8, | |
1399 | .clkr = { | |
1400 | .enable_reg = 0x35a8, | |
1401 | .enable_mask = BIT(0), | |
1402 | .hw.init = &(struct clk_init_data){ | |
1403 | .name = "camss_jpeg_jpeg0_clk", | |
1404 | .parent_names = (const char *[]){ | |
1405 | "jpeg0_clk_src", | |
1406 | }, | |
1407 | .num_parents = 1, | |
1408 | .flags = CLK_SET_RATE_PARENT, | |
1409 | .ops = &clk_branch2_ops, | |
1410 | }, | |
1411 | }, | |
1412 | }; | |
1413 | ||
1414 | static struct clk_branch camss_jpeg_jpeg1_clk = { | |
1415 | .halt_reg = 0x35ac, | |
1416 | .clkr = { | |
1417 | .enable_reg = 0x35ac, | |
1418 | .enable_mask = BIT(0), | |
1419 | .hw.init = &(struct clk_init_data){ | |
1420 | .name = "camss_jpeg_jpeg1_clk", | |
1421 | .parent_names = (const char *[]){ | |
1422 | "jpeg1_clk_src", | |
1423 | }, | |
1424 | .num_parents = 1, | |
1425 | .flags = CLK_SET_RATE_PARENT, | |
1426 | .ops = &clk_branch2_ops, | |
1427 | }, | |
1428 | }, | |
1429 | }; | |
1430 | ||
1431 | static struct clk_branch camss_jpeg_jpeg2_clk = { | |
1432 | .halt_reg = 0x35b0, | |
1433 | .clkr = { | |
1434 | .enable_reg = 0x35b0, | |
1435 | .enable_mask = BIT(0), | |
1436 | .hw.init = &(struct clk_init_data){ | |
1437 | .name = "camss_jpeg_jpeg2_clk", | |
1438 | .parent_names = (const char *[]){ | |
1439 | "jpeg2_clk_src", | |
1440 | }, | |
1441 | .num_parents = 1, | |
1442 | .flags = CLK_SET_RATE_PARENT, | |
1443 | .ops = &clk_branch2_ops, | |
1444 | }, | |
1445 | }, | |
1446 | }; | |
1447 | ||
1448 | static struct clk_branch camss_jpeg_jpeg_ahb_clk = { | |
1449 | .halt_reg = 0x35b4, | |
1450 | .clkr = { | |
1451 | .enable_reg = 0x35b4, | |
1452 | .enable_mask = BIT(0), | |
1453 | .hw.init = &(struct clk_init_data){ | |
1454 | .name = "camss_jpeg_jpeg_ahb_clk", | |
1455 | .parent_names = (const char *[]){ | |
1456 | "mmss_ahb_clk_src", | |
1457 | }, | |
1458 | .num_parents = 1, | |
1459 | .ops = &clk_branch2_ops, | |
1460 | }, | |
1461 | }, | |
1462 | }; | |
1463 | ||
1464 | static struct clk_branch camss_jpeg_jpeg_axi_clk = { | |
1465 | .halt_reg = 0x35b8, | |
1466 | .clkr = { | |
1467 | .enable_reg = 0x35b8, | |
1468 | .enable_mask = BIT(0), | |
1469 | .hw.init = &(struct clk_init_data){ | |
1470 | .name = "camss_jpeg_jpeg_axi_clk", | |
1471 | .parent_names = (const char *[]){ | |
1472 | "mmss_axi_clk_src", | |
1473 | }, | |
1474 | .num_parents = 1, | |
1475 | .ops = &clk_branch2_ops, | |
1476 | }, | |
1477 | }, | |
1478 | }; | |
1479 | ||
1480 | static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = { | |
1481 | .halt_reg = 0x35bc, | |
1482 | .clkr = { | |
1483 | .enable_reg = 0x35bc, | |
1484 | .enable_mask = BIT(0), | |
1485 | .hw.init = &(struct clk_init_data){ | |
1486 | .name = "camss_jpeg_jpeg_ocmemnoc_clk", | |
1487 | .parent_names = (const char *[]){ | |
1488 | "ocmemnoc_clk_src", | |
1489 | }, | |
1490 | .num_parents = 1, | |
1491 | .flags = CLK_SET_RATE_PARENT, | |
1492 | .ops = &clk_branch2_ops, | |
1493 | }, | |
1494 | }, | |
1495 | }; | |
1496 | ||
1497 | static struct clk_branch camss_mclk0_clk = { | |
1498 | .halt_reg = 0x3384, | |
1499 | .clkr = { | |
1500 | .enable_reg = 0x3384, | |
1501 | .enable_mask = BIT(0), | |
1502 | .hw.init = &(struct clk_init_data){ | |
1503 | .name = "camss_mclk0_clk", | |
1504 | .parent_names = (const char *[]){ | |
1505 | "mclk0_clk_src", | |
1506 | }, | |
1507 | .num_parents = 1, | |
1508 | .flags = CLK_SET_RATE_PARENT, | |
1509 | .ops = &clk_branch2_ops, | |
1510 | }, | |
1511 | }, | |
1512 | }; | |
1513 | ||
1514 | static struct clk_branch camss_mclk1_clk = { | |
1515 | .halt_reg = 0x33b4, | |
1516 | .clkr = { | |
1517 | .enable_reg = 0x33b4, | |
1518 | .enable_mask = BIT(0), | |
1519 | .hw.init = &(struct clk_init_data){ | |
1520 | .name = "camss_mclk1_clk", | |
1521 | .parent_names = (const char *[]){ | |
1522 | "mclk1_clk_src", | |
1523 | }, | |
1524 | .num_parents = 1, | |
1525 | .flags = CLK_SET_RATE_PARENT, | |
1526 | .ops = &clk_branch2_ops, | |
1527 | }, | |
1528 | }, | |
1529 | }; | |
1530 | ||
1531 | static struct clk_branch camss_mclk2_clk = { | |
1532 | .halt_reg = 0x33e4, | |
1533 | .clkr = { | |
1534 | .enable_reg = 0x33e4, | |
1535 | .enable_mask = BIT(0), | |
1536 | .hw.init = &(struct clk_init_data){ | |
1537 | .name = "camss_mclk2_clk", | |
1538 | .parent_names = (const char *[]){ | |
1539 | "mclk2_clk_src", | |
1540 | }, | |
1541 | .num_parents = 1, | |
1542 | .flags = CLK_SET_RATE_PARENT, | |
1543 | .ops = &clk_branch2_ops, | |
1544 | }, | |
1545 | }, | |
1546 | }; | |
1547 | ||
1548 | static struct clk_branch camss_mclk3_clk = { | |
1549 | .halt_reg = 0x3414, | |
1550 | .clkr = { | |
1551 | .enable_reg = 0x3414, | |
1552 | .enable_mask = BIT(0), | |
1553 | .hw.init = &(struct clk_init_data){ | |
1554 | .name = "camss_mclk3_clk", | |
1555 | .parent_names = (const char *[]){ | |
1556 | "mclk3_clk_src", | |
1557 | }, | |
1558 | .num_parents = 1, | |
1559 | .flags = CLK_SET_RATE_PARENT, | |
1560 | .ops = &clk_branch2_ops, | |
1561 | }, | |
1562 | }, | |
1563 | }; | |
1564 | ||
1565 | static struct clk_branch camss_micro_ahb_clk = { | |
1566 | .halt_reg = 0x3494, | |
1567 | .clkr = { | |
1568 | .enable_reg = 0x3494, | |
1569 | .enable_mask = BIT(0), | |
1570 | .hw.init = &(struct clk_init_data){ | |
1571 | .name = "camss_micro_ahb_clk", | |
1572 | .parent_names = (const char *[]){ | |
1573 | "mmss_ahb_clk_src", | |
1574 | }, | |
1575 | .num_parents = 1, | |
1576 | .ops = &clk_branch2_ops, | |
1577 | }, | |
1578 | }, | |
1579 | }; | |
1580 | ||
1581 | static struct clk_branch camss_phy0_csi0phytimer_clk = { | |
1582 | .halt_reg = 0x3024, | |
1583 | .clkr = { | |
1584 | .enable_reg = 0x3024, | |
1585 | .enable_mask = BIT(0), | |
1586 | .hw.init = &(struct clk_init_data){ | |
1587 | .name = "camss_phy0_csi0phytimer_clk", | |
1588 | .parent_names = (const char *[]){ | |
1589 | "csi0phytimer_clk_src", | |
1590 | }, | |
1591 | .num_parents = 1, | |
1592 | .flags = CLK_SET_RATE_PARENT, | |
1593 | .ops = &clk_branch2_ops, | |
1594 | }, | |
1595 | }, | |
1596 | }; | |
1597 | ||
1598 | static struct clk_branch camss_phy1_csi1phytimer_clk = { | |
1599 | .halt_reg = 0x3054, | |
1600 | .clkr = { | |
1601 | .enable_reg = 0x3054, | |
1602 | .enable_mask = BIT(0), | |
1603 | .hw.init = &(struct clk_init_data){ | |
1604 | .name = "camss_phy1_csi1phytimer_clk", | |
1605 | .parent_names = (const char *[]){ | |
1606 | "csi1phytimer_clk_src", | |
1607 | }, | |
1608 | .num_parents = 1, | |
1609 | .flags = CLK_SET_RATE_PARENT, | |
1610 | .ops = &clk_branch2_ops, | |
1611 | }, | |
1612 | }, | |
1613 | }; | |
1614 | ||
1615 | static struct clk_branch camss_phy2_csi2phytimer_clk = { | |
1616 | .halt_reg = 0x3084, | |
1617 | .clkr = { | |
1618 | .enable_reg = 0x3084, | |
1619 | .enable_mask = BIT(0), | |
1620 | .hw.init = &(struct clk_init_data){ | |
1621 | .name = "camss_phy2_csi2phytimer_clk", | |
1622 | .parent_names = (const char *[]){ | |
1623 | "csi2phytimer_clk_src", | |
1624 | }, | |
1625 | .num_parents = 1, | |
1626 | .flags = CLK_SET_RATE_PARENT, | |
1627 | .ops = &clk_branch2_ops, | |
1628 | }, | |
1629 | }, | |
1630 | }; | |
1631 | ||
1632 | static struct clk_branch camss_top_ahb_clk = { | |
1633 | .halt_reg = 0x3484, | |
1634 | .clkr = { | |
1635 | .enable_reg = 0x3484, | |
1636 | .enable_mask = BIT(0), | |
1637 | .hw.init = &(struct clk_init_data){ | |
1638 | .name = "camss_top_ahb_clk", | |
1639 | .parent_names = (const char *[]){ | |
1640 | "mmss_ahb_clk_src", | |
1641 | }, | |
1642 | .num_parents = 1, | |
1643 | .ops = &clk_branch2_ops, | |
1644 | }, | |
1645 | }, | |
1646 | }; | |
1647 | ||
1648 | static struct clk_branch camss_vfe_cpp_ahb_clk = { | |
1649 | .halt_reg = 0x36b4, | |
1650 | .clkr = { | |
1651 | .enable_reg = 0x36b4, | |
1652 | .enable_mask = BIT(0), | |
1653 | .hw.init = &(struct clk_init_data){ | |
1654 | .name = "camss_vfe_cpp_ahb_clk", | |
1655 | .parent_names = (const char *[]){ | |
1656 | "mmss_ahb_clk_src", | |
1657 | }, | |
1658 | .num_parents = 1, | |
1659 | .ops = &clk_branch2_ops, | |
1660 | }, | |
1661 | }, | |
1662 | }; | |
1663 | ||
1664 | static struct clk_branch camss_vfe_cpp_clk = { | |
1665 | .halt_reg = 0x36b0, | |
1666 | .clkr = { | |
1667 | .enable_reg = 0x36b0, | |
1668 | .enable_mask = BIT(0), | |
1669 | .hw.init = &(struct clk_init_data){ | |
1670 | .name = "camss_vfe_cpp_clk", | |
1671 | .parent_names = (const char *[]){ | |
1672 | "cpp_clk_src", | |
1673 | }, | |
1674 | .num_parents = 1, | |
1675 | .flags = CLK_SET_RATE_PARENT, | |
1676 | .ops = &clk_branch2_ops, | |
1677 | }, | |
1678 | }, | |
1679 | }; | |
1680 | ||
1681 | static struct clk_branch camss_vfe_vfe0_clk = { | |
1682 | .halt_reg = 0x36a8, | |
1683 | .clkr = { | |
1684 | .enable_reg = 0x36a8, | |
1685 | .enable_mask = BIT(0), | |
1686 | .hw.init = &(struct clk_init_data){ | |
1687 | .name = "camss_vfe_vfe0_clk", | |
1688 | .parent_names = (const char *[]){ | |
1689 | "vfe0_clk_src", | |
1690 | }, | |
1691 | .num_parents = 1, | |
1692 | .flags = CLK_SET_RATE_PARENT, | |
1693 | .ops = &clk_branch2_ops, | |
1694 | }, | |
1695 | }, | |
1696 | }; | |
1697 | ||
1698 | static struct clk_branch camss_vfe_vfe1_clk = { | |
1699 | .halt_reg = 0x36ac, | |
1700 | .clkr = { | |
1701 | .enable_reg = 0x36ac, | |
1702 | .enable_mask = BIT(0), | |
1703 | .hw.init = &(struct clk_init_data){ | |
1704 | .name = "camss_vfe_vfe1_clk", | |
1705 | .parent_names = (const char *[]){ | |
1706 | "vfe1_clk_src", | |
1707 | }, | |
1708 | .num_parents = 1, | |
1709 | .flags = CLK_SET_RATE_PARENT, | |
1710 | .ops = &clk_branch2_ops, | |
1711 | }, | |
1712 | }, | |
1713 | }; | |
1714 | ||
1715 | static struct clk_branch camss_vfe_vfe_ahb_clk = { | |
1716 | .halt_reg = 0x36b8, | |
1717 | .clkr = { | |
1718 | .enable_reg = 0x36b8, | |
1719 | .enable_mask = BIT(0), | |
1720 | .hw.init = &(struct clk_init_data){ | |
1721 | .name = "camss_vfe_vfe_ahb_clk", | |
1722 | .parent_names = (const char *[]){ | |
1723 | "mmss_ahb_clk_src", | |
1724 | }, | |
1725 | .num_parents = 1, | |
1726 | .ops = &clk_branch2_ops, | |
1727 | }, | |
1728 | }, | |
1729 | }; | |
1730 | ||
1731 | static struct clk_branch camss_vfe_vfe_axi_clk = { | |
1732 | .halt_reg = 0x36bc, | |
1733 | .clkr = { | |
1734 | .enable_reg = 0x36bc, | |
1735 | .enable_mask = BIT(0), | |
1736 | .hw.init = &(struct clk_init_data){ | |
1737 | .name = "camss_vfe_vfe_axi_clk", | |
1738 | .parent_names = (const char *[]){ | |
1739 | "mmss_axi_clk_src", | |
1740 | }, | |
1741 | .num_parents = 1, | |
1742 | .ops = &clk_branch2_ops, | |
1743 | }, | |
1744 | }, | |
1745 | }; | |
1746 | ||
1747 | static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = { | |
1748 | .halt_reg = 0x36c0, | |
1749 | .clkr = { | |
1750 | .enable_reg = 0x36c0, | |
1751 | .enable_mask = BIT(0), | |
1752 | .hw.init = &(struct clk_init_data){ | |
1753 | .name = "camss_vfe_vfe_ocmemnoc_clk", | |
1754 | .parent_names = (const char *[]){ | |
1755 | "ocmemnoc_clk_src", | |
1756 | }, | |
1757 | .num_parents = 1, | |
1758 | .flags = CLK_SET_RATE_PARENT, | |
1759 | .ops = &clk_branch2_ops, | |
1760 | }, | |
1761 | }, | |
1762 | }; | |
1763 | ||
1764 | static struct clk_branch mdss_ahb_clk = { | |
1765 | .halt_reg = 0x2308, | |
1766 | .clkr = { | |
1767 | .enable_reg = 0x2308, | |
1768 | .enable_mask = BIT(0), | |
1769 | .hw.init = &(struct clk_init_data){ | |
1770 | .name = "mdss_ahb_clk", | |
1771 | .parent_names = (const char *[]){ | |
1772 | "mmss_ahb_clk_src", | |
1773 | }, | |
1774 | .num_parents = 1, | |
1775 | .ops = &clk_branch2_ops, | |
1776 | }, | |
1777 | }, | |
1778 | }; | |
1779 | ||
1780 | static struct clk_branch mdss_axi_clk = { | |
1781 | .halt_reg = 0x2310, | |
1782 | .clkr = { | |
1783 | .enable_reg = 0x2310, | |
1784 | .enable_mask = BIT(0), | |
1785 | .hw.init = &(struct clk_init_data){ | |
1786 | .name = "mdss_axi_clk", | |
1787 | .parent_names = (const char *[]){ | |
1788 | "mmss_axi_clk_src", | |
1789 | }, | |
1790 | .num_parents = 1, | |
1791 | .flags = CLK_SET_RATE_PARENT, | |
1792 | .ops = &clk_branch2_ops, | |
1793 | }, | |
1794 | }, | |
1795 | }; | |
1796 | ||
1797 | static struct clk_branch mdss_byte0_clk = { | |
1798 | .halt_reg = 0x233c, | |
1799 | .clkr = { | |
1800 | .enable_reg = 0x233c, | |
1801 | .enable_mask = BIT(0), | |
1802 | .hw.init = &(struct clk_init_data){ | |
1803 | .name = "mdss_byte0_clk", | |
1804 | .parent_names = (const char *[]){ | |
1805 | "byte0_clk_src", | |
1806 | }, | |
1807 | .num_parents = 1, | |
1808 | .flags = CLK_SET_RATE_PARENT, | |
1809 | .ops = &clk_branch2_ops, | |
1810 | }, | |
1811 | }, | |
1812 | }; | |
1813 | ||
1814 | static struct clk_branch mdss_byte1_clk = { | |
1815 | .halt_reg = 0x2340, | |
1816 | .clkr = { | |
1817 | .enable_reg = 0x2340, | |
1818 | .enable_mask = BIT(0), | |
1819 | .hw.init = &(struct clk_init_data){ | |
1820 | .name = "mdss_byte1_clk", | |
1821 | .parent_names = (const char *[]){ | |
1822 | "byte1_clk_src", | |
1823 | }, | |
1824 | .num_parents = 1, | |
1825 | .flags = CLK_SET_RATE_PARENT, | |
1826 | .ops = &clk_branch2_ops, | |
1827 | }, | |
1828 | }, | |
1829 | }; | |
1830 | ||
1831 | static struct clk_branch mdss_edpaux_clk = { | |
1832 | .halt_reg = 0x2334, | |
1833 | .clkr = { | |
1834 | .enable_reg = 0x2334, | |
1835 | .enable_mask = BIT(0), | |
1836 | .hw.init = &(struct clk_init_data){ | |
1837 | .name = "mdss_edpaux_clk", | |
1838 | .parent_names = (const char *[]){ | |
1839 | "edpaux_clk_src", | |
1840 | }, | |
1841 | .num_parents = 1, | |
1842 | .flags = CLK_SET_RATE_PARENT, | |
1843 | .ops = &clk_branch2_ops, | |
1844 | }, | |
1845 | }, | |
1846 | }; | |
1847 | ||
1848 | static struct clk_branch mdss_edplink_clk = { | |
1849 | .halt_reg = 0x2330, | |
1850 | .clkr = { | |
1851 | .enable_reg = 0x2330, | |
1852 | .enable_mask = BIT(0), | |
1853 | .hw.init = &(struct clk_init_data){ | |
1854 | .name = "mdss_edplink_clk", | |
1855 | .parent_names = (const char *[]){ | |
1856 | "edplink_clk_src", | |
1857 | }, | |
1858 | .num_parents = 1, | |
1859 | .flags = CLK_SET_RATE_PARENT, | |
1860 | .ops = &clk_branch2_ops, | |
1861 | }, | |
1862 | }, | |
1863 | }; | |
1864 | ||
1865 | static struct clk_branch mdss_edppixel_clk = { | |
1866 | .halt_reg = 0x232c, | |
1867 | .clkr = { | |
1868 | .enable_reg = 0x232c, | |
1869 | .enable_mask = BIT(0), | |
1870 | .hw.init = &(struct clk_init_data){ | |
1871 | .name = "mdss_edppixel_clk", | |
1872 | .parent_names = (const char *[]){ | |
1873 | "edppixel_clk_src", | |
1874 | }, | |
1875 | .num_parents = 1, | |
1876 | .flags = CLK_SET_RATE_PARENT, | |
1877 | .ops = &clk_branch2_ops, | |
1878 | }, | |
1879 | }, | |
1880 | }; | |
1881 | ||
1882 | static struct clk_branch mdss_esc0_clk = { | |
1883 | .halt_reg = 0x2344, | |
1884 | .clkr = { | |
1885 | .enable_reg = 0x2344, | |
1886 | .enable_mask = BIT(0), | |
1887 | .hw.init = &(struct clk_init_data){ | |
1888 | .name = "mdss_esc0_clk", | |
1889 | .parent_names = (const char *[]){ | |
1890 | "esc0_clk_src", | |
1891 | }, | |
1892 | .num_parents = 1, | |
1893 | .flags = CLK_SET_RATE_PARENT, | |
1894 | .ops = &clk_branch2_ops, | |
1895 | }, | |
1896 | }, | |
1897 | }; | |
1898 | ||
1899 | static struct clk_branch mdss_esc1_clk = { | |
1900 | .halt_reg = 0x2348, | |
1901 | .clkr = { | |
1902 | .enable_reg = 0x2348, | |
1903 | .enable_mask = BIT(0), | |
1904 | .hw.init = &(struct clk_init_data){ | |
1905 | .name = "mdss_esc1_clk", | |
1906 | .parent_names = (const char *[]){ | |
1907 | "esc1_clk_src", | |
1908 | }, | |
1909 | .num_parents = 1, | |
1910 | .flags = CLK_SET_RATE_PARENT, | |
1911 | .ops = &clk_branch2_ops, | |
1912 | }, | |
1913 | }, | |
1914 | }; | |
1915 | ||
1916 | static struct clk_branch mdss_extpclk_clk = { | |
1917 | .halt_reg = 0x2324, | |
1918 | .clkr = { | |
1919 | .enable_reg = 0x2324, | |
1920 | .enable_mask = BIT(0), | |
1921 | .hw.init = &(struct clk_init_data){ | |
1922 | .name = "mdss_extpclk_clk", | |
1923 | .parent_names = (const char *[]){ | |
1924 | "extpclk_clk_src", | |
1925 | }, | |
1926 | .num_parents = 1, | |
1927 | .flags = CLK_SET_RATE_PARENT, | |
1928 | .ops = &clk_branch2_ops, | |
1929 | }, | |
1930 | }, | |
1931 | }; | |
1932 | ||
1933 | static struct clk_branch mdss_hdmi_ahb_clk = { | |
1934 | .halt_reg = 0x230c, | |
1935 | .clkr = { | |
1936 | .enable_reg = 0x230c, | |
1937 | .enable_mask = BIT(0), | |
1938 | .hw.init = &(struct clk_init_data){ | |
1939 | .name = "mdss_hdmi_ahb_clk", | |
1940 | .parent_names = (const char *[]){ | |
1941 | "mmss_ahb_clk_src", | |
1942 | }, | |
1943 | .num_parents = 1, | |
1944 | .ops = &clk_branch2_ops, | |
1945 | }, | |
1946 | }, | |
1947 | }; | |
1948 | ||
1949 | static struct clk_branch mdss_hdmi_clk = { | |
1950 | .halt_reg = 0x2338, | |
1951 | .clkr = { | |
1952 | .enable_reg = 0x2338, | |
1953 | .enable_mask = BIT(0), | |
1954 | .hw.init = &(struct clk_init_data){ | |
1955 | .name = "mdss_hdmi_clk", | |
1956 | .parent_names = (const char *[]){ | |
1957 | "hdmi_clk_src", | |
1958 | }, | |
1959 | .num_parents = 1, | |
1960 | .flags = CLK_SET_RATE_PARENT, | |
1961 | .ops = &clk_branch2_ops, | |
1962 | }, | |
1963 | }, | |
1964 | }; | |
1965 | ||
1966 | static struct clk_branch mdss_mdp_clk = { | |
1967 | .halt_reg = 0x231c, | |
1968 | .clkr = { | |
1969 | .enable_reg = 0x231c, | |
1970 | .enable_mask = BIT(0), | |
1971 | .hw.init = &(struct clk_init_data){ | |
1972 | .name = "mdss_mdp_clk", | |
1973 | .parent_names = (const char *[]){ | |
1974 | "mdp_clk_src", | |
1975 | }, | |
1976 | .num_parents = 1, | |
1977 | .flags = CLK_SET_RATE_PARENT, | |
1978 | .ops = &clk_branch2_ops, | |
1979 | }, | |
1980 | }, | |
1981 | }; | |
1982 | ||
1983 | static struct clk_branch mdss_mdp_lut_clk = { | |
1984 | .halt_reg = 0x2320, | |
1985 | .clkr = { | |
1986 | .enable_reg = 0x2320, | |
1987 | .enable_mask = BIT(0), | |
1988 | .hw.init = &(struct clk_init_data){ | |
1989 | .name = "mdss_mdp_lut_clk", | |
1990 | .parent_names = (const char *[]){ | |
1991 | "mdp_clk_src", | |
1992 | }, | |
1993 | .num_parents = 1, | |
1994 | .flags = CLK_SET_RATE_PARENT, | |
1995 | .ops = &clk_branch2_ops, | |
1996 | }, | |
1997 | }, | |
1998 | }; | |
1999 | ||
2000 | static struct clk_branch mdss_pclk0_clk = { | |
2001 | .halt_reg = 0x2314, | |
2002 | .clkr = { | |
2003 | .enable_reg = 0x2314, | |
2004 | .enable_mask = BIT(0), | |
2005 | .hw.init = &(struct clk_init_data){ | |
2006 | .name = "mdss_pclk0_clk", | |
2007 | .parent_names = (const char *[]){ | |
2008 | "pclk0_clk_src", | |
2009 | }, | |
2010 | .num_parents = 1, | |
2011 | .flags = CLK_SET_RATE_PARENT, | |
2012 | .ops = &clk_branch2_ops, | |
2013 | }, | |
2014 | }, | |
2015 | }; | |
2016 | ||
2017 | static struct clk_branch mdss_pclk1_clk = { | |
2018 | .halt_reg = 0x2318, | |
2019 | .clkr = { | |
2020 | .enable_reg = 0x2318, | |
2021 | .enable_mask = BIT(0), | |
2022 | .hw.init = &(struct clk_init_data){ | |
2023 | .name = "mdss_pclk1_clk", | |
2024 | .parent_names = (const char *[]){ | |
2025 | "pclk1_clk_src", | |
2026 | }, | |
2027 | .num_parents = 1, | |
2028 | .flags = CLK_SET_RATE_PARENT, | |
2029 | .ops = &clk_branch2_ops, | |
2030 | }, | |
2031 | }, | |
2032 | }; | |
2033 | ||
2034 | static struct clk_branch mdss_vsync_clk = { | |
2035 | .halt_reg = 0x2328, | |
2036 | .clkr = { | |
2037 | .enable_reg = 0x2328, | |
2038 | .enable_mask = BIT(0), | |
2039 | .hw.init = &(struct clk_init_data){ | |
2040 | .name = "mdss_vsync_clk", | |
2041 | .parent_names = (const char *[]){ | |
2042 | "vsync_clk_src", | |
2043 | }, | |
2044 | .num_parents = 1, | |
2045 | .flags = CLK_SET_RATE_PARENT, | |
2046 | .ops = &clk_branch2_ops, | |
2047 | }, | |
2048 | }, | |
2049 | }; | |
2050 | ||
2051 | static struct clk_branch mmss_misc_ahb_clk = { | |
2052 | .halt_reg = 0x502c, | |
2053 | .clkr = { | |
2054 | .enable_reg = 0x502c, | |
2055 | .enable_mask = BIT(0), | |
2056 | .hw.init = &(struct clk_init_data){ | |
2057 | .name = "mmss_misc_ahb_clk", | |
2058 | .parent_names = (const char *[]){ | |
2059 | "mmss_ahb_clk_src", | |
2060 | }, | |
2061 | .num_parents = 1, | |
2062 | .ops = &clk_branch2_ops, | |
2063 | }, | |
2064 | }, | |
2065 | }; | |
2066 | ||
2067 | static struct clk_branch mmss_mmssnoc_ahb_clk = { | |
2068 | .halt_reg = 0x5024, | |
2069 | .clkr = { | |
2070 | .enable_reg = 0x5024, | |
2071 | .enable_mask = BIT(0), | |
2072 | .hw.init = &(struct clk_init_data){ | |
2073 | .name = "mmss_mmssnoc_ahb_clk", | |
2074 | .parent_names = (const char *[]){ | |
2075 | "mmss_ahb_clk_src", | |
2076 | }, | |
2077 | .num_parents = 1, | |
2078 | .ops = &clk_branch2_ops, | |
2079 | .flags = CLK_IGNORE_UNUSED, | |
2080 | }, | |
2081 | }, | |
2082 | }; | |
2083 | ||
2084 | static struct clk_branch mmss_mmssnoc_bto_ahb_clk = { | |
2085 | .halt_reg = 0x5028, | |
2086 | .clkr = { | |
2087 | .enable_reg = 0x5028, | |
2088 | .enable_mask = BIT(0), | |
2089 | .hw.init = &(struct clk_init_data){ | |
2090 | .name = "mmss_mmssnoc_bto_ahb_clk", | |
2091 | .parent_names = (const char *[]){ | |
2092 | "mmss_ahb_clk_src", | |
2093 | }, | |
2094 | .num_parents = 1, | |
2095 | .ops = &clk_branch2_ops, | |
2096 | .flags = CLK_IGNORE_UNUSED, | |
2097 | }, | |
2098 | }, | |
2099 | }; | |
2100 | ||
2101 | static struct clk_branch mmss_mmssnoc_axi_clk = { | |
2102 | .halt_reg = 0x506c, | |
2103 | .clkr = { | |
2104 | .enable_reg = 0x506c, | |
2105 | .enable_mask = BIT(0), | |
2106 | .hw.init = &(struct clk_init_data){ | |
2107 | .name = "mmss_mmssnoc_axi_clk", | |
2108 | .parent_names = (const char *[]){ | |
2109 | "mmss_axi_clk_src", | |
2110 | }, | |
2111 | .num_parents = 1, | |
2112 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2113 | .ops = &clk_branch2_ops, | |
2114 | }, | |
2115 | }, | |
2116 | }; | |
2117 | ||
2118 | static struct clk_branch mmss_s0_axi_clk = { | |
2119 | .halt_reg = 0x5064, | |
2120 | .clkr = { | |
2121 | .enable_reg = 0x5064, | |
2122 | .enable_mask = BIT(0), | |
2123 | .hw.init = &(struct clk_init_data){ | |
2124 | .name = "mmss_s0_axi_clk", | |
2125 | .parent_names = (const char *[]){ | |
2126 | "mmss_axi_clk_src", | |
2127 | }, | |
2128 | .num_parents = 1, | |
2129 | .ops = &clk_branch2_ops, | |
2130 | .flags = CLK_IGNORE_UNUSED, | |
2131 | }, | |
2132 | }, | |
2133 | }; | |
2134 | ||
2135 | static struct clk_branch ocmemcx_ahb_clk = { | |
2136 | .halt_reg = 0x405c, | |
2137 | .clkr = { | |
2138 | .enable_reg = 0x405c, | |
2139 | .enable_mask = BIT(0), | |
2140 | .hw.init = &(struct clk_init_data){ | |
2141 | .name = "ocmemcx_ahb_clk", | |
2142 | .parent_names = (const char *[]){ | |
2143 | "mmss_ahb_clk_src", | |
2144 | }, | |
2145 | .num_parents = 1, | |
2146 | .ops = &clk_branch2_ops, | |
2147 | }, | |
2148 | }, | |
2149 | }; | |
2150 | ||
2151 | static struct clk_branch ocmemcx_ocmemnoc_clk = { | |
2152 | .halt_reg = 0x4058, | |
2153 | .clkr = { | |
2154 | .enable_reg = 0x4058, | |
2155 | .enable_mask = BIT(0), | |
2156 | .hw.init = &(struct clk_init_data){ | |
2157 | .name = "ocmemcx_ocmemnoc_clk", | |
2158 | .parent_names = (const char *[]){ | |
2159 | "ocmemnoc_clk_src", | |
2160 | }, | |
2161 | .num_parents = 1, | |
2162 | .flags = CLK_SET_RATE_PARENT, | |
2163 | .ops = &clk_branch2_ops, | |
2164 | }, | |
2165 | }, | |
2166 | }; | |
2167 | ||
2168 | static struct clk_branch oxili_ocmemgx_clk = { | |
2169 | .halt_reg = 0x402c, | |
2170 | .clkr = { | |
2171 | .enable_reg = 0x402c, | |
2172 | .enable_mask = BIT(0), | |
2173 | .hw.init = &(struct clk_init_data){ | |
2174 | .name = "oxili_ocmemgx_clk", | |
2175 | .parent_names = (const char *[]){ | |
2176 | "gfx3d_clk_src", | |
2177 | }, | |
2178 | .num_parents = 1, | |
2179 | .flags = CLK_SET_RATE_PARENT, | |
2180 | .ops = &clk_branch2_ops, | |
2181 | }, | |
2182 | }, | |
2183 | }; | |
2184 | ||
2185 | static struct clk_branch ocmemnoc_clk = { | |
2186 | .halt_reg = 0x50b4, | |
2187 | .clkr = { | |
2188 | .enable_reg = 0x50b4, | |
2189 | .enable_mask = BIT(0), | |
2190 | .hw.init = &(struct clk_init_data){ | |
2191 | .name = "ocmemnoc_clk", | |
2192 | .parent_names = (const char *[]){ | |
2193 | "ocmemnoc_clk_src", | |
2194 | }, | |
2195 | .num_parents = 1, | |
2196 | .flags = CLK_SET_RATE_PARENT, | |
2197 | .ops = &clk_branch2_ops, | |
2198 | }, | |
2199 | }, | |
2200 | }; | |
2201 | ||
2202 | static struct clk_branch oxili_gfx3d_clk = { | |
2203 | .halt_reg = 0x4028, | |
2204 | .clkr = { | |
2205 | .enable_reg = 0x4028, | |
2206 | .enable_mask = BIT(0), | |
2207 | .hw.init = &(struct clk_init_data){ | |
2208 | .name = "oxili_gfx3d_clk", | |
2209 | .parent_names = (const char *[]){ | |
2210 | "gfx3d_clk_src", | |
2211 | }, | |
2212 | .num_parents = 1, | |
2213 | .flags = CLK_SET_RATE_PARENT, | |
2214 | .ops = &clk_branch2_ops, | |
2215 | }, | |
2216 | }, | |
2217 | }; | |
2218 | ||
2219 | static struct clk_branch oxilicx_ahb_clk = { | |
2220 | .halt_reg = 0x403c, | |
2221 | .clkr = { | |
2222 | .enable_reg = 0x403c, | |
2223 | .enable_mask = BIT(0), | |
2224 | .hw.init = &(struct clk_init_data){ | |
2225 | .name = "oxilicx_ahb_clk", | |
2226 | .parent_names = (const char *[]){ | |
2227 | "mmss_ahb_clk_src", | |
2228 | }, | |
2229 | .num_parents = 1, | |
2230 | .ops = &clk_branch2_ops, | |
2231 | }, | |
2232 | }, | |
2233 | }; | |
2234 | ||
2235 | static struct clk_branch oxilicx_axi_clk = { | |
2236 | .halt_reg = 0x4038, | |
2237 | .clkr = { | |
2238 | .enable_reg = 0x4038, | |
2239 | .enable_mask = BIT(0), | |
2240 | .hw.init = &(struct clk_init_data){ | |
2241 | .name = "oxilicx_axi_clk", | |
2242 | .parent_names = (const char *[]){ | |
2243 | "mmss_axi_clk_src", | |
2244 | }, | |
2245 | .num_parents = 1, | |
2246 | .ops = &clk_branch2_ops, | |
2247 | }, | |
2248 | }, | |
2249 | }; | |
2250 | ||
2251 | static struct clk_branch venus0_ahb_clk = { | |
2252 | .halt_reg = 0x1030, | |
2253 | .clkr = { | |
2254 | .enable_reg = 0x1030, | |
2255 | .enable_mask = BIT(0), | |
2256 | .hw.init = &(struct clk_init_data){ | |
2257 | .name = "venus0_ahb_clk", | |
2258 | .parent_names = (const char *[]){ | |
2259 | "mmss_ahb_clk_src", | |
2260 | }, | |
2261 | .num_parents = 1, | |
2262 | .ops = &clk_branch2_ops, | |
2263 | }, | |
2264 | }, | |
2265 | }; | |
2266 | ||
2267 | static struct clk_branch venus0_axi_clk = { | |
2268 | .halt_reg = 0x1034, | |
2269 | .clkr = { | |
2270 | .enable_reg = 0x1034, | |
2271 | .enable_mask = BIT(0), | |
2272 | .hw.init = &(struct clk_init_data){ | |
2273 | .name = "venus0_axi_clk", | |
2274 | .parent_names = (const char *[]){ | |
2275 | "mmss_axi_clk_src", | |
2276 | }, | |
2277 | .num_parents = 1, | |
2278 | .ops = &clk_branch2_ops, | |
2279 | }, | |
2280 | }, | |
2281 | }; | |
2282 | ||
2283 | static struct clk_branch venus0_ocmemnoc_clk = { | |
2284 | .halt_reg = 0x1038, | |
2285 | .clkr = { | |
2286 | .enable_reg = 0x1038, | |
2287 | .enable_mask = BIT(0), | |
2288 | .hw.init = &(struct clk_init_data){ | |
2289 | .name = "venus0_ocmemnoc_clk", | |
2290 | .parent_names = (const char *[]){ | |
2291 | "ocmemnoc_clk_src", | |
2292 | }, | |
2293 | .num_parents = 1, | |
2294 | .flags = CLK_SET_RATE_PARENT, | |
2295 | .ops = &clk_branch2_ops, | |
2296 | }, | |
2297 | }, | |
2298 | }; | |
2299 | ||
2300 | static struct clk_branch venus0_vcodec0_clk = { | |
2301 | .halt_reg = 0x1028, | |
2302 | .clkr = { | |
2303 | .enable_reg = 0x1028, | |
2304 | .enable_mask = BIT(0), | |
2305 | .hw.init = &(struct clk_init_data){ | |
2306 | .name = "venus0_vcodec0_clk", | |
2307 | .parent_names = (const char *[]){ | |
2308 | "vcodec0_clk_src", | |
2309 | }, | |
2310 | .num_parents = 1, | |
2311 | .flags = CLK_SET_RATE_PARENT, | |
2312 | .ops = &clk_branch2_ops, | |
2313 | }, | |
2314 | }, | |
2315 | }; | |
2316 | ||
2317 | static const struct pll_config mmpll1_config = { | |
2318 | .l = 60, | |
2319 | .m = 25, | |
2320 | .n = 32, | |
2321 | .vco_val = 0x0, | |
2322 | .vco_mask = 0x3 << 20, | |
2323 | .pre_div_val = 0x0, | |
437ae6a1 | 2324 | .pre_div_mask = 0x7 << 12, |
d8b21201 SB |
2325 | .post_div_val = 0x0, |
2326 | .post_div_mask = 0x3 << 8, | |
2327 | .mn_ena_mask = BIT(24), | |
2328 | .main_output_mask = BIT(0), | |
2329 | }; | |
2330 | ||
2331 | static struct pll_config mmpll3_config = { | |
2332 | .l = 48, | |
2333 | .m = 7, | |
2334 | .n = 16, | |
2335 | .vco_val = 0x0, | |
2336 | .vco_mask = 0x3 << 20, | |
2337 | .pre_div_val = 0x0, | |
437ae6a1 | 2338 | .pre_div_mask = 0x7 << 12, |
d8b21201 SB |
2339 | .post_div_val = 0x0, |
2340 | .post_div_mask = 0x3 << 8, | |
2341 | .mn_ena_mask = BIT(24), | |
2342 | .main_output_mask = BIT(0), | |
2343 | .aux_output_mask = BIT(1), | |
2344 | }; | |
2345 | ||
8108b23c SB |
2346 | static struct gdsc venus0_gdsc = { |
2347 | .gdscr = 0x1024, | |
2348 | .cxcs = (unsigned int []){ 0x1028 }, | |
2349 | .cxc_count = 1, | |
2350 | .resets = (unsigned int []){ VENUS0_RESET }, | |
2351 | .reset_count = 1, | |
2352 | .pd = { | |
2353 | .name = "venus0", | |
2354 | }, | |
2355 | .pwrsts = PWRSTS_ON, | |
2356 | }; | |
2357 | ||
2358 | static struct gdsc mdss_gdsc = { | |
2359 | .gdscr = 0x2304, | |
2360 | .cxcs = (unsigned int []){ 0x231c, 0x2320 }, | |
2361 | .cxc_count = 2, | |
2362 | .pd = { | |
2363 | .name = "mdss", | |
2364 | }, | |
2365 | .pwrsts = PWRSTS_RET_ON, | |
2366 | }; | |
2367 | ||
2368 | static struct gdsc camss_jpeg_gdsc = { | |
2369 | .gdscr = 0x35a4, | |
2370 | .cxcs = (unsigned int []){ 0x35a8, 0x35ac, 0x35b0 }, | |
2371 | .cxc_count = 3, | |
2372 | .pd = { | |
2373 | .name = "camss_jpeg", | |
2374 | }, | |
2375 | .pwrsts = PWRSTS_OFF_ON, | |
2376 | }; | |
2377 | ||
2378 | static struct gdsc camss_vfe_gdsc = { | |
2379 | .gdscr = 0x36a4, | |
2380 | .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x3704, 0x3714, 0x36b0 }, | |
2381 | .cxc_count = 5, | |
2382 | .pd = { | |
2383 | .name = "camss_vfe", | |
2384 | }, | |
2385 | .pwrsts = PWRSTS_OFF_ON, | |
2386 | }; | |
2387 | ||
2388 | static struct gdsc oxili_gdsc = { | |
2389 | .gdscr = 0x4024, | |
2390 | .cxcs = (unsigned int []){ 0x4028 }, | |
2391 | .cxc_count = 1, | |
2392 | .pd = { | |
2393 | .name = "oxili", | |
2394 | }, | |
2395 | .pwrsts = PWRSTS_OFF_ON, | |
2396 | }; | |
2397 | ||
2398 | static struct gdsc oxilicx_gdsc = { | |
2399 | .gdscr = 0x4034, | |
2400 | .pd = { | |
2401 | .name = "oxilicx", | |
2402 | }, | |
7208d1d9 | 2403 | .parent = &oxili_gdsc.pd, |
8108b23c SB |
2404 | .pwrsts = PWRSTS_OFF_ON, |
2405 | }; | |
2406 | ||
d8b21201 SB |
2407 | static struct clk_regmap *mmcc_msm8974_clocks[] = { |
2408 | [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr, | |
2409 | [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr, | |
2410 | [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr, | |
2411 | [MMPLL0] = &mmpll0.clkr, | |
2412 | [MMPLL0_VOTE] = &mmpll0_vote, | |
2413 | [MMPLL1] = &mmpll1.clkr, | |
2414 | [MMPLL1_VOTE] = &mmpll1_vote, | |
2415 | [MMPLL2] = &mmpll2.clkr, | |
2416 | [MMPLL3] = &mmpll3.clkr, | |
2417 | [CSI0_CLK_SRC] = &csi0_clk_src.clkr, | |
2418 | [CSI1_CLK_SRC] = &csi1_clk_src.clkr, | |
2419 | [CSI2_CLK_SRC] = &csi2_clk_src.clkr, | |
2420 | [CSI3_CLK_SRC] = &csi3_clk_src.clkr, | |
2421 | [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, | |
2422 | [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, | |
2423 | [MDP_CLK_SRC] = &mdp_clk_src.clkr, | |
2424 | [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, | |
2425 | [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, | |
2426 | [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr, | |
2427 | [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, | |
2428 | [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, | |
2429 | [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, | |
2430 | [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, | |
2431 | [CCI_CLK_SRC] = &cci_clk_src.clkr, | |
2432 | [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, | |
2433 | [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, | |
2434 | [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, | |
2435 | [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, | |
2436 | [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, | |
2437 | [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, | |
2438 | [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, | |
2439 | [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, | |
2440 | [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, | |
2441 | [CPP_CLK_SRC] = &cpp_clk_src.clkr, | |
2442 | [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, | |
2443 | [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, | |
2444 | [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr, | |
2445 | [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr, | |
2446 | [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr, | |
2447 | [ESC0_CLK_SRC] = &esc0_clk_src.clkr, | |
2448 | [ESC1_CLK_SRC] = &esc1_clk_src.clkr, | |
2449 | [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, | |
2450 | [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, | |
2451 | [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, | |
2452 | [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr, | |
2453 | [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr, | |
2454 | [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, | |
2455 | [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, | |
2456 | [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, | |
2457 | [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, | |
2458 | [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, | |
2459 | [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, | |
2460 | [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, | |
2461 | [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, | |
2462 | [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, | |
2463 | [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, | |
2464 | [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, | |
2465 | [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, | |
2466 | [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, | |
2467 | [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, | |
2468 | [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, | |
2469 | [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, | |
2470 | [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, | |
2471 | [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, | |
2472 | [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, | |
2473 | [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, | |
2474 | [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, | |
2475 | [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, | |
2476 | [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, | |
2477 | [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, | |
2478 | [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, | |
2479 | [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr, | |
2480 | [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr, | |
2481 | [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr, | |
2482 | [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr, | |
2483 | [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr, | |
2484 | [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr, | |
2485 | [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, | |
2486 | [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, | |
2487 | [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, | |
2488 | [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, | |
2489 | [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, | |
2490 | [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr, | |
2491 | [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr, | |
2492 | [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr, | |
2493 | [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, | |
2494 | [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr, | |
2495 | [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr, | |
2496 | [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr, | |
2497 | [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr, | |
2498 | [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr, | |
2499 | [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr, | |
2500 | [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr, | |
2501 | [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, | |
2502 | [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, | |
2503 | [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, | |
2504 | [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, | |
2505 | [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr, | |
2506 | [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr, | |
2507 | [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr, | |
2508 | [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, | |
2509 | [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, | |
2510 | [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, | |
2511 | [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, | |
2512 | [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, | |
2513 | [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, | |
2514 | [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr, | |
2515 | [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, | |
2516 | [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, | |
2517 | [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, | |
2518 | [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, | |
2519 | [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr, | |
2520 | [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr, | |
2521 | [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr, | |
2522 | [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr, | |
2523 | [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr, | |
2524 | [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr, | |
2525 | [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr, | |
2526 | [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr, | |
2527 | [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr, | |
2528 | [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr, | |
2529 | [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr, | |
2530 | [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr, | |
2531 | [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr, | |
2532 | [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr, | |
2533 | [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr, | |
2534 | }; | |
2535 | ||
2536 | static const struct qcom_reset_map mmcc_msm8974_resets[] = { | |
2537 | [SPDM_RESET] = { 0x0200 }, | |
2538 | [SPDM_RM_RESET] = { 0x0300 }, | |
2539 | [VENUS0_RESET] = { 0x1020 }, | |
2540 | [MDSS_RESET] = { 0x2300 }, | |
2541 | [CAMSS_PHY0_RESET] = { 0x3020 }, | |
2542 | [CAMSS_PHY1_RESET] = { 0x3050 }, | |
2543 | [CAMSS_PHY2_RESET] = { 0x3080 }, | |
2544 | [CAMSS_CSI0_RESET] = { 0x30b0 }, | |
2545 | [CAMSS_CSI0PHY_RESET] = { 0x30c0 }, | |
2546 | [CAMSS_CSI0RDI_RESET] = { 0x30d0 }, | |
2547 | [CAMSS_CSI0PIX_RESET] = { 0x30e0 }, | |
2548 | [CAMSS_CSI1_RESET] = { 0x3120 }, | |
2549 | [CAMSS_CSI1PHY_RESET] = { 0x3130 }, | |
2550 | [CAMSS_CSI1RDI_RESET] = { 0x3140 }, | |
2551 | [CAMSS_CSI1PIX_RESET] = { 0x3150 }, | |
2552 | [CAMSS_CSI2_RESET] = { 0x3180 }, | |
2553 | [CAMSS_CSI2PHY_RESET] = { 0x3190 }, | |
2554 | [CAMSS_CSI2RDI_RESET] = { 0x31a0 }, | |
2555 | [CAMSS_CSI2PIX_RESET] = { 0x31b0 }, | |
2556 | [CAMSS_CSI3_RESET] = { 0x31e0 }, | |
2557 | [CAMSS_CSI3PHY_RESET] = { 0x31f0 }, | |
2558 | [CAMSS_CSI3RDI_RESET] = { 0x3200 }, | |
2559 | [CAMSS_CSI3PIX_RESET] = { 0x3210 }, | |
2560 | [CAMSS_ISPIF_RESET] = { 0x3220 }, | |
2561 | [CAMSS_CCI_RESET] = { 0x3340 }, | |
2562 | [CAMSS_MCLK0_RESET] = { 0x3380 }, | |
2563 | [CAMSS_MCLK1_RESET] = { 0x33b0 }, | |
2564 | [CAMSS_MCLK2_RESET] = { 0x33e0 }, | |
2565 | [CAMSS_MCLK3_RESET] = { 0x3410 }, | |
2566 | [CAMSS_GP0_RESET] = { 0x3440 }, | |
2567 | [CAMSS_GP1_RESET] = { 0x3470 }, | |
2568 | [CAMSS_TOP_RESET] = { 0x3480 }, | |
2569 | [CAMSS_MICRO_RESET] = { 0x3490 }, | |
2570 | [CAMSS_JPEG_RESET] = { 0x35a0 }, | |
2571 | [CAMSS_VFE_RESET] = { 0x36a0 }, | |
2572 | [CAMSS_CSI_VFE0_RESET] = { 0x3700 }, | |
2573 | [CAMSS_CSI_VFE1_RESET] = { 0x3710 }, | |
2574 | [OXILI_RESET] = { 0x4020 }, | |
2575 | [OXILICX_RESET] = { 0x4030 }, | |
2576 | [OCMEMCX_RESET] = { 0x4050 }, | |
2577 | [MMSS_RBCRP_RESET] = { 0x4080 }, | |
2578 | [MMSSNOCAHB_RESET] = { 0x5020 }, | |
2579 | [MMSSNOCAXI_RESET] = { 0x5060 }, | |
2580 | [OCMEMNOC_RESET] = { 0x50b0 }, | |
2581 | }; | |
2582 | ||
8108b23c SB |
2583 | static struct gdsc *mmcc_msm8974_gdscs[] = { |
2584 | [VENUS0_GDSC] = &venus0_gdsc, | |
2585 | [MDSS_GDSC] = &mdss_gdsc, | |
2586 | [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc, | |
2587 | [CAMSS_VFE_GDSC] = &camss_vfe_gdsc, | |
2588 | [OXILI_GDSC] = &oxili_gdsc, | |
2589 | [OXILICX_GDSC] = &oxilicx_gdsc, | |
2590 | }; | |
2591 | ||
d8b21201 SB |
2592 | static const struct regmap_config mmcc_msm8974_regmap_config = { |
2593 | .reg_bits = 32, | |
2594 | .reg_stride = 4, | |
2595 | .val_bits = 32, | |
2596 | .max_register = 0x5104, | |
2597 | .fast_io = true, | |
2598 | }; | |
2599 | ||
49fc825f SB |
2600 | static const struct qcom_cc_desc mmcc_msm8974_desc = { |
2601 | .config = &mmcc_msm8974_regmap_config, | |
2602 | .clks = mmcc_msm8974_clocks, | |
2603 | .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks), | |
2604 | .resets = mmcc_msm8974_resets, | |
2605 | .num_resets = ARRAY_SIZE(mmcc_msm8974_resets), | |
8108b23c SB |
2606 | .gdscs = mmcc_msm8974_gdscs, |
2607 | .num_gdscs = ARRAY_SIZE(mmcc_msm8974_gdscs), | |
49fc825f SB |
2608 | }; |
2609 | ||
d8b21201 SB |
2610 | static const struct of_device_id mmcc_msm8974_match_table[] = { |
2611 | { .compatible = "qcom,mmcc-msm8974" }, | |
2612 | { } | |
2613 | }; | |
2614 | MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table); | |
2615 | ||
d8b21201 SB |
2616 | static int mmcc_msm8974_probe(struct platform_device *pdev) |
2617 | { | |
d8b21201 | 2618 | struct regmap *regmap; |
d8b21201 | 2619 | |
5b6b7490 SB |
2620 | regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc); |
2621 | if (IS_ERR(regmap)) | |
2622 | return PTR_ERR(regmap); | |
d8b21201 | 2623 | |
49fc825f SB |
2624 | clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true); |
2625 | clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false); | |
d8b21201 | 2626 | |
7208d1d9 | 2627 | return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap); |
d8b21201 SB |
2628 | } |
2629 | ||
2630 | static struct platform_driver mmcc_msm8974_driver = { | |
2631 | .probe = mmcc_msm8974_probe, | |
d8b21201 SB |
2632 | .driver = { |
2633 | .name = "mmcc-msm8974", | |
d8b21201 SB |
2634 | .of_match_table = mmcc_msm8974_match_table, |
2635 | }, | |
2636 | }; | |
2637 | module_platform_driver(mmcc_msm8974_driver); | |
2638 | ||
2639 | MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver"); | |
2640 | MODULE_LICENSE("GPL v2"); | |
2641 | MODULE_ALIAS("platform:mmcc-msm8974"); |