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d8b21201 SB |
1 | /* |
2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/bitops.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/clk-provider.h> | |
22 | #include <linux/regmap.h> | |
23 | #include <linux/reset-controller.h> | |
24 | ||
25 | #include <dt-bindings/clock/qcom,mmcc-msm8974.h> | |
26 | #include <dt-bindings/reset/qcom,mmcc-msm8974.h> | |
27 | ||
49fc825f | 28 | #include "common.h" |
d8b21201 SB |
29 | #include "clk-regmap.h" |
30 | #include "clk-pll.h" | |
31 | #include "clk-rcg.h" | |
32 | #include "clk-branch.h" | |
33 | #include "reset.h" | |
34 | ||
35 | #define P_XO 0 | |
36 | #define P_MMPLL0 1 | |
37 | #define P_EDPLINK 1 | |
38 | #define P_MMPLL1 2 | |
39 | #define P_HDMIPLL 2 | |
40 | #define P_GPLL0 3 | |
41 | #define P_EDPVCO 3 | |
42 | #define P_GPLL1 4 | |
43 | #define P_DSI0PLL 4 | |
b7b7cc70 | 44 | #define P_DSI0PLL_BYTE 4 |
d8b21201 SB |
45 | #define P_MMPLL2 4 |
46 | #define P_MMPLL3 4 | |
47 | #define P_DSI1PLL 5 | |
b7b7cc70 | 48 | #define P_DSI1PLL_BYTE 5 |
d8b21201 SB |
49 | |
50 | static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { | |
51 | [P_XO] = 0, | |
52 | [P_MMPLL0] = 1, | |
53 | [P_MMPLL1] = 2, | |
54 | [P_GPLL0] = 5, | |
55 | }; | |
56 | ||
57 | static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = { | |
58 | "xo", | |
59 | "mmpll0_vote", | |
60 | "mmpll1_vote", | |
61 | "mmss_gpll0_vote", | |
62 | }; | |
63 | ||
64 | static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { | |
65 | [P_XO] = 0, | |
66 | [P_MMPLL0] = 1, | |
67 | [P_HDMIPLL] = 4, | |
68 | [P_GPLL0] = 5, | |
69 | [P_DSI0PLL] = 2, | |
70 | [P_DSI1PLL] = 3, | |
71 | }; | |
72 | ||
73 | static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { | |
74 | "xo", | |
75 | "mmpll0_vote", | |
76 | "hdmipll", | |
77 | "mmss_gpll0_vote", | |
78 | "dsi0pll", | |
79 | "dsi1pll", | |
80 | }; | |
81 | ||
82 | static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = { | |
83 | [P_XO] = 0, | |
84 | [P_MMPLL0] = 1, | |
85 | [P_MMPLL1] = 2, | |
86 | [P_GPLL0] = 5, | |
87 | [P_MMPLL2] = 3, | |
88 | }; | |
89 | ||
90 | static const char *mmcc_xo_mmpll0_1_2_gpll0[] = { | |
91 | "xo", | |
92 | "mmpll0_vote", | |
93 | "mmpll1_vote", | |
94 | "mmss_gpll0_vote", | |
95 | "mmpll2", | |
96 | }; | |
97 | ||
98 | static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = { | |
99 | [P_XO] = 0, | |
100 | [P_MMPLL0] = 1, | |
101 | [P_MMPLL1] = 2, | |
102 | [P_GPLL0] = 5, | |
103 | [P_MMPLL3] = 3, | |
104 | }; | |
105 | ||
106 | static const char *mmcc_xo_mmpll0_1_3_gpll0[] = { | |
107 | "xo", | |
108 | "mmpll0_vote", | |
109 | "mmpll1_vote", | |
110 | "mmss_gpll0_vote", | |
111 | "mmpll3", | |
112 | }; | |
113 | ||
114 | static const u8 mmcc_xo_mmpll0_1_gpll1_0_map[] = { | |
115 | [P_XO] = 0, | |
116 | [P_MMPLL0] = 1, | |
117 | [P_MMPLL1] = 2, | |
118 | [P_GPLL0] = 5, | |
119 | [P_GPLL1] = 4, | |
120 | }; | |
121 | ||
122 | static const char *mmcc_xo_mmpll0_1_gpll1_0[] = { | |
123 | "xo", | |
124 | "mmpll0_vote", | |
125 | "mmpll1_vote", | |
126 | "mmss_gpll0_vote", | |
127 | "gpll1_vote", | |
128 | }; | |
129 | ||
130 | static const u8 mmcc_xo_dsi_hdmi_edp_map[] = { | |
131 | [P_XO] = 0, | |
132 | [P_EDPLINK] = 4, | |
133 | [P_HDMIPLL] = 3, | |
134 | [P_EDPVCO] = 5, | |
135 | [P_DSI0PLL] = 1, | |
136 | [P_DSI1PLL] = 2, | |
137 | }; | |
138 | ||
139 | static const char *mmcc_xo_dsi_hdmi_edp[] = { | |
140 | "xo", | |
141 | "edp_link_clk", | |
142 | "hdmipll", | |
143 | "edp_vco_div", | |
144 | "dsi0pll", | |
145 | "dsi1pll", | |
146 | }; | |
147 | ||
148 | static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { | |
149 | [P_XO] = 0, | |
150 | [P_EDPLINK] = 4, | |
151 | [P_HDMIPLL] = 3, | |
152 | [P_GPLL0] = 5, | |
153 | [P_DSI0PLL] = 1, | |
154 | [P_DSI1PLL] = 2, | |
155 | }; | |
156 | ||
157 | static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = { | |
158 | "xo", | |
159 | "edp_link_clk", | |
160 | "hdmipll", | |
161 | "gpll0_vote", | |
162 | "dsi0pll", | |
163 | "dsi1pll", | |
164 | }; | |
165 | ||
b7b7cc70 SB |
166 | static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { |
167 | [P_XO] = 0, | |
168 | [P_EDPLINK] = 4, | |
169 | [P_HDMIPLL] = 3, | |
170 | [P_GPLL0] = 5, | |
171 | [P_DSI0PLL_BYTE] = 1, | |
172 | [P_DSI1PLL_BYTE] = 2, | |
173 | }; | |
174 | ||
175 | static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { | |
176 | "xo", | |
177 | "edp_link_clk", | |
178 | "hdmipll", | |
179 | "gpll0_vote", | |
180 | "dsi0pllbyte", | |
181 | "dsi1pllbyte", | |
182 | }; | |
183 | ||
d8b21201 SB |
184 | #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } |
185 | ||
186 | static struct clk_pll mmpll0 = { | |
187 | .l_reg = 0x0004, | |
188 | .m_reg = 0x0008, | |
189 | .n_reg = 0x000c, | |
190 | .config_reg = 0x0014, | |
191 | .mode_reg = 0x0000, | |
192 | .status_reg = 0x001c, | |
437ae6a1 | 193 | .status_bit = 17, |
d8b21201 SB |
194 | .clkr.hw.init = &(struct clk_init_data){ |
195 | .name = "mmpll0", | |
196 | .parent_names = (const char *[]){ "xo" }, | |
197 | .num_parents = 1, | |
198 | .ops = &clk_pll_ops, | |
199 | }, | |
200 | }; | |
201 | ||
202 | static struct clk_regmap mmpll0_vote = { | |
203 | .enable_reg = 0x0100, | |
204 | .enable_mask = BIT(0), | |
205 | .hw.init = &(struct clk_init_data){ | |
206 | .name = "mmpll0_vote", | |
207 | .parent_names = (const char *[]){ "mmpll0" }, | |
208 | .num_parents = 1, | |
209 | .ops = &clk_pll_vote_ops, | |
210 | }, | |
211 | }; | |
212 | ||
213 | static struct clk_pll mmpll1 = { | |
214 | .l_reg = 0x0044, | |
215 | .m_reg = 0x0048, | |
216 | .n_reg = 0x004c, | |
437ae6a1 | 217 | .config_reg = 0x0050, |
d8b21201 SB |
218 | .mode_reg = 0x0040, |
219 | .status_reg = 0x005c, | |
437ae6a1 | 220 | .status_bit = 17, |
d8b21201 SB |
221 | .clkr.hw.init = &(struct clk_init_data){ |
222 | .name = "mmpll1", | |
223 | .parent_names = (const char *[]){ "xo" }, | |
224 | .num_parents = 1, | |
225 | .ops = &clk_pll_ops, | |
226 | }, | |
227 | }; | |
228 | ||
229 | static struct clk_regmap mmpll1_vote = { | |
230 | .enable_reg = 0x0100, | |
231 | .enable_mask = BIT(1), | |
232 | .hw.init = &(struct clk_init_data){ | |
233 | .name = "mmpll1_vote", | |
234 | .parent_names = (const char *[]){ "mmpll1" }, | |
235 | .num_parents = 1, | |
236 | .ops = &clk_pll_vote_ops, | |
237 | }, | |
238 | }; | |
239 | ||
240 | static struct clk_pll mmpll2 = { | |
241 | .l_reg = 0x4104, | |
242 | .m_reg = 0x4108, | |
243 | .n_reg = 0x410c, | |
437ae6a1 | 244 | .config_reg = 0x4110, |
d8b21201 SB |
245 | .mode_reg = 0x4100, |
246 | .status_reg = 0x411c, | |
247 | .clkr.hw.init = &(struct clk_init_data){ | |
248 | .name = "mmpll2", | |
249 | .parent_names = (const char *[]){ "xo" }, | |
250 | .num_parents = 1, | |
251 | .ops = &clk_pll_ops, | |
252 | }, | |
253 | }; | |
254 | ||
255 | static struct clk_pll mmpll3 = { | |
256 | .l_reg = 0x0084, | |
257 | .m_reg = 0x0088, | |
258 | .n_reg = 0x008c, | |
437ae6a1 | 259 | .config_reg = 0x0090, |
d8b21201 SB |
260 | .mode_reg = 0x0080, |
261 | .status_reg = 0x009c, | |
437ae6a1 | 262 | .status_bit = 17, |
d8b21201 SB |
263 | .clkr.hw.init = &(struct clk_init_data){ |
264 | .name = "mmpll3", | |
265 | .parent_names = (const char *[]){ "xo" }, | |
266 | .num_parents = 1, | |
267 | .ops = &clk_pll_ops, | |
268 | }, | |
269 | }; | |
270 | ||
271 | static struct clk_rcg2 mmss_ahb_clk_src = { | |
272 | .cmd_rcgr = 0x5000, | |
273 | .hid_width = 5, | |
274 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
275 | .clkr.hw.init = &(struct clk_init_data){ | |
276 | .name = "mmss_ahb_clk_src", | |
277 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
278 | .num_parents = 4, | |
279 | .ops = &clk_rcg2_ops, | |
280 | }, | |
281 | }; | |
282 | ||
283 | static struct freq_tbl ftbl_mmss_axi_clk[] = { | |
284 | F( 19200000, P_XO, 1, 0, 0), | |
285 | F( 37500000, P_GPLL0, 16, 0, 0), | |
286 | F( 50000000, P_GPLL0, 12, 0, 0), | |
287 | F( 75000000, P_GPLL0, 8, 0, 0), | |
288 | F(100000000, P_GPLL0, 6, 0, 0), | |
289 | F(150000000, P_GPLL0, 4, 0, 0), | |
290 | F(291750000, P_MMPLL1, 4, 0, 0), | |
291 | F(400000000, P_MMPLL0, 2, 0, 0), | |
292 | F(466800000, P_MMPLL1, 2.5, 0, 0), | |
293 | }; | |
294 | ||
295 | static struct clk_rcg2 mmss_axi_clk_src = { | |
296 | .cmd_rcgr = 0x5040, | |
297 | .hid_width = 5, | |
298 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
299 | .freq_tbl = ftbl_mmss_axi_clk, | |
300 | .clkr.hw.init = &(struct clk_init_data){ | |
301 | .name = "mmss_axi_clk_src", | |
302 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
303 | .num_parents = 4, | |
304 | .ops = &clk_rcg2_ops, | |
305 | }, | |
306 | }; | |
307 | ||
308 | static struct freq_tbl ftbl_ocmemnoc_clk[] = { | |
309 | F( 19200000, P_XO, 1, 0, 0), | |
310 | F( 37500000, P_GPLL0, 16, 0, 0), | |
311 | F( 50000000, P_GPLL0, 12, 0, 0), | |
312 | F( 75000000, P_GPLL0, 8, 0, 0), | |
313 | F(100000000, P_GPLL0, 6, 0, 0), | |
314 | F(150000000, P_GPLL0, 4, 0, 0), | |
315 | F(291750000, P_MMPLL1, 4, 0, 0), | |
316 | F(400000000, P_MMPLL0, 2, 0, 0), | |
317 | }; | |
318 | ||
319 | static struct clk_rcg2 ocmemnoc_clk_src = { | |
320 | .cmd_rcgr = 0x5090, | |
321 | .hid_width = 5, | |
322 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
323 | .freq_tbl = ftbl_ocmemnoc_clk, | |
324 | .clkr.hw.init = &(struct clk_init_data){ | |
325 | .name = "ocmemnoc_clk_src", | |
326 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
327 | .num_parents = 4, | |
328 | .ops = &clk_rcg2_ops, | |
329 | }, | |
330 | }; | |
331 | ||
332 | static struct freq_tbl ftbl_camss_csi0_3_clk[] = { | |
333 | F(100000000, P_GPLL0, 6, 0, 0), | |
334 | F(200000000, P_MMPLL0, 4, 0, 0), | |
335 | { } | |
336 | }; | |
337 | ||
338 | static struct clk_rcg2 csi0_clk_src = { | |
339 | .cmd_rcgr = 0x3090, | |
340 | .hid_width = 5, | |
341 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
342 | .freq_tbl = ftbl_camss_csi0_3_clk, | |
343 | .clkr.hw.init = &(struct clk_init_data){ | |
344 | .name = "csi0_clk_src", | |
345 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
346 | .num_parents = 4, | |
347 | .ops = &clk_rcg2_ops, | |
348 | }, | |
349 | }; | |
350 | ||
351 | static struct clk_rcg2 csi1_clk_src = { | |
352 | .cmd_rcgr = 0x3100, | |
353 | .hid_width = 5, | |
354 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
355 | .freq_tbl = ftbl_camss_csi0_3_clk, | |
356 | .clkr.hw.init = &(struct clk_init_data){ | |
357 | .name = "csi1_clk_src", | |
358 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
359 | .num_parents = 4, | |
360 | .ops = &clk_rcg2_ops, | |
361 | }, | |
362 | }; | |
363 | ||
364 | static struct clk_rcg2 csi2_clk_src = { | |
365 | .cmd_rcgr = 0x3160, | |
366 | .hid_width = 5, | |
367 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
368 | .freq_tbl = ftbl_camss_csi0_3_clk, | |
369 | .clkr.hw.init = &(struct clk_init_data){ | |
370 | .name = "csi2_clk_src", | |
371 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
372 | .num_parents = 4, | |
373 | .ops = &clk_rcg2_ops, | |
374 | }, | |
375 | }; | |
376 | ||
377 | static struct clk_rcg2 csi3_clk_src = { | |
378 | .cmd_rcgr = 0x31c0, | |
379 | .hid_width = 5, | |
380 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
381 | .freq_tbl = ftbl_camss_csi0_3_clk, | |
382 | .clkr.hw.init = &(struct clk_init_data){ | |
383 | .name = "csi3_clk_src", | |
384 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
385 | .num_parents = 4, | |
386 | .ops = &clk_rcg2_ops, | |
387 | }, | |
388 | }; | |
389 | ||
390 | static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = { | |
391 | F(37500000, P_GPLL0, 16, 0, 0), | |
392 | F(50000000, P_GPLL0, 12, 0, 0), | |
393 | F(60000000, P_GPLL0, 10, 0, 0), | |
394 | F(80000000, P_GPLL0, 7.5, 0, 0), | |
395 | F(100000000, P_GPLL0, 6, 0, 0), | |
396 | F(109090000, P_GPLL0, 5.5, 0, 0), | |
397 | F(133330000, P_GPLL0, 4.5, 0, 0), | |
398 | F(200000000, P_GPLL0, 3, 0, 0), | |
399 | F(228570000, P_MMPLL0, 3.5, 0, 0), | |
400 | F(266670000, P_MMPLL0, 3, 0, 0), | |
401 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
402 | F(400000000, P_MMPLL0, 2, 0, 0), | |
403 | F(465000000, P_MMPLL3, 2, 0, 0), | |
404 | { } | |
405 | }; | |
406 | ||
407 | static struct clk_rcg2 vfe0_clk_src = { | |
408 | .cmd_rcgr = 0x3600, | |
409 | .hid_width = 5, | |
410 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
411 | .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, | |
412 | .clkr.hw.init = &(struct clk_init_data){ | |
413 | .name = "vfe0_clk_src", | |
414 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
415 | .num_parents = 4, | |
416 | .ops = &clk_rcg2_ops, | |
417 | }, | |
418 | }; | |
419 | ||
420 | static struct clk_rcg2 vfe1_clk_src = { | |
421 | .cmd_rcgr = 0x3620, | |
422 | .hid_width = 5, | |
423 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
424 | .freq_tbl = ftbl_camss_vfe_vfe0_1_clk, | |
425 | .clkr.hw.init = &(struct clk_init_data){ | |
426 | .name = "vfe1_clk_src", | |
427 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
428 | .num_parents = 4, | |
429 | .ops = &clk_rcg2_ops, | |
430 | }, | |
431 | }; | |
432 | ||
433 | static struct freq_tbl ftbl_mdss_mdp_clk[] = { | |
434 | F(37500000, P_GPLL0, 16, 0, 0), | |
435 | F(60000000, P_GPLL0, 10, 0, 0), | |
436 | F(75000000, P_GPLL0, 8, 0, 0), | |
437 | F(85710000, P_GPLL0, 7, 0, 0), | |
438 | F(100000000, P_GPLL0, 6, 0, 0), | |
439 | F(133330000, P_MMPLL0, 6, 0, 0), | |
440 | F(160000000, P_MMPLL0, 5, 0, 0), | |
441 | F(200000000, P_MMPLL0, 4, 0, 0), | |
442 | F(228570000, P_MMPLL0, 3.5, 0, 0), | |
443 | F(240000000, P_GPLL0, 2.5, 0, 0), | |
444 | F(266670000, P_MMPLL0, 3, 0, 0), | |
445 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
446 | { } | |
447 | }; | |
448 | ||
449 | static struct clk_rcg2 mdp_clk_src = { | |
450 | .cmd_rcgr = 0x2040, | |
451 | .hid_width = 5, | |
452 | .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map, | |
453 | .freq_tbl = ftbl_mdss_mdp_clk, | |
454 | .clkr.hw.init = &(struct clk_init_data){ | |
455 | .name = "mdp_clk_src", | |
456 | .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0, | |
457 | .num_parents = 6, | |
458 | .ops = &clk_rcg2_ops, | |
459 | }, | |
460 | }; | |
461 | ||
462 | static struct clk_rcg2 gfx3d_clk_src = { | |
463 | .cmd_rcgr = 0x4000, | |
464 | .hid_width = 5, | |
465 | .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map, | |
466 | .clkr.hw.init = &(struct clk_init_data){ | |
467 | .name = "gfx3d_clk_src", | |
468 | .parent_names = mmcc_xo_mmpll0_1_2_gpll0, | |
469 | .num_parents = 5, | |
470 | .ops = &clk_rcg2_ops, | |
471 | }, | |
472 | }; | |
473 | ||
474 | static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = { | |
475 | F(75000000, P_GPLL0, 8, 0, 0), | |
476 | F(133330000, P_GPLL0, 4.5, 0, 0), | |
477 | F(200000000, P_GPLL0, 3, 0, 0), | |
478 | F(228570000, P_MMPLL0, 3.5, 0, 0), | |
479 | F(266670000, P_MMPLL0, 3, 0, 0), | |
480 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
481 | { } | |
482 | }; | |
483 | ||
484 | static struct clk_rcg2 jpeg0_clk_src = { | |
485 | .cmd_rcgr = 0x3500, | |
486 | .hid_width = 5, | |
487 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
488 | .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, | |
489 | .clkr.hw.init = &(struct clk_init_data){ | |
490 | .name = "jpeg0_clk_src", | |
491 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
492 | .num_parents = 4, | |
493 | .ops = &clk_rcg2_ops, | |
494 | }, | |
495 | }; | |
496 | ||
497 | static struct clk_rcg2 jpeg1_clk_src = { | |
498 | .cmd_rcgr = 0x3520, | |
499 | .hid_width = 5, | |
500 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
501 | .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, | |
502 | .clkr.hw.init = &(struct clk_init_data){ | |
503 | .name = "jpeg1_clk_src", | |
504 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
505 | .num_parents = 4, | |
506 | .ops = &clk_rcg2_ops, | |
507 | }, | |
508 | }; | |
509 | ||
510 | static struct clk_rcg2 jpeg2_clk_src = { | |
511 | .cmd_rcgr = 0x3540, | |
512 | .hid_width = 5, | |
513 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
514 | .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk, | |
515 | .clkr.hw.init = &(struct clk_init_data){ | |
516 | .name = "jpeg2_clk_src", | |
517 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
518 | .num_parents = 4, | |
519 | .ops = &clk_rcg2_ops, | |
520 | }, | |
521 | }; | |
522 | ||
b7b7cc70 SB |
523 | static struct freq_tbl pixel_freq_tbl[] = { |
524 | { .src = P_DSI0PLL }, | |
d8b21201 SB |
525 | { } |
526 | }; | |
527 | ||
528 | static struct clk_rcg2 pclk0_clk_src = { | |
529 | .cmd_rcgr = 0x2000, | |
530 | .mnd_width = 8, | |
531 | .hid_width = 5, | |
532 | .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, | |
b7b7cc70 | 533 | .freq_tbl = pixel_freq_tbl, |
d8b21201 SB |
534 | .clkr.hw.init = &(struct clk_init_data){ |
535 | .name = "pclk0_clk_src", | |
536 | .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, | |
537 | .num_parents = 6, | |
b7b7cc70 SB |
538 | .ops = &clk_pixel_ops, |
539 | .flags = CLK_SET_RATE_PARENT, | |
d8b21201 SB |
540 | }, |
541 | }; | |
542 | ||
543 | static struct clk_rcg2 pclk1_clk_src = { | |
544 | .cmd_rcgr = 0x2020, | |
545 | .mnd_width = 8, | |
546 | .hid_width = 5, | |
547 | .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, | |
b7b7cc70 | 548 | .freq_tbl = pixel_freq_tbl, |
d8b21201 SB |
549 | .clkr.hw.init = &(struct clk_init_data){ |
550 | .name = "pclk1_clk_src", | |
551 | .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, | |
552 | .num_parents = 6, | |
b7b7cc70 SB |
553 | .ops = &clk_pixel_ops, |
554 | .flags = CLK_SET_RATE_PARENT, | |
d8b21201 SB |
555 | }, |
556 | }; | |
557 | ||
558 | static struct freq_tbl ftbl_venus0_vcodec0_clk[] = { | |
559 | F(50000000, P_GPLL0, 12, 0, 0), | |
560 | F(100000000, P_GPLL0, 6, 0, 0), | |
561 | F(133330000, P_MMPLL0, 6, 0, 0), | |
562 | F(200000000, P_MMPLL0, 4, 0, 0), | |
563 | F(266670000, P_MMPLL0, 3, 0, 0), | |
564 | F(465000000, P_MMPLL3, 2, 0, 0), | |
565 | { } | |
566 | }; | |
567 | ||
568 | static struct clk_rcg2 vcodec0_clk_src = { | |
569 | .cmd_rcgr = 0x1000, | |
570 | .mnd_width = 8, | |
571 | .hid_width = 5, | |
572 | .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map, | |
573 | .freq_tbl = ftbl_venus0_vcodec0_clk, | |
574 | .clkr.hw.init = &(struct clk_init_data){ | |
575 | .name = "vcodec0_clk_src", | |
576 | .parent_names = mmcc_xo_mmpll0_1_3_gpll0, | |
577 | .num_parents = 5, | |
578 | .ops = &clk_rcg2_ops, | |
579 | }, | |
580 | }; | |
581 | ||
582 | static struct freq_tbl ftbl_camss_cci_cci_clk[] = { | |
583 | F(19200000, P_XO, 1, 0, 0), | |
584 | { } | |
585 | }; | |
586 | ||
587 | static struct clk_rcg2 cci_clk_src = { | |
588 | .cmd_rcgr = 0x3300, | |
589 | .hid_width = 5, | |
590 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
591 | .freq_tbl = ftbl_camss_cci_cci_clk, | |
592 | .clkr.hw.init = &(struct clk_init_data){ | |
593 | .name = "cci_clk_src", | |
594 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
595 | .num_parents = 4, | |
596 | .ops = &clk_rcg2_ops, | |
597 | }, | |
598 | }; | |
599 | ||
600 | static struct freq_tbl ftbl_camss_gp0_1_clk[] = { | |
601 | F(10000, P_XO, 16, 1, 120), | |
602 | F(24000, P_XO, 16, 1, 50), | |
603 | F(6000000, P_GPLL0, 10, 1, 10), | |
604 | F(12000000, P_GPLL0, 10, 1, 5), | |
605 | F(13000000, P_GPLL0, 4, 13, 150), | |
606 | F(24000000, P_GPLL0, 5, 1, 5), | |
607 | { } | |
608 | }; | |
609 | ||
610 | static struct clk_rcg2 camss_gp0_clk_src = { | |
611 | .cmd_rcgr = 0x3420, | |
612 | .mnd_width = 8, | |
613 | .hid_width = 5, | |
614 | .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map, | |
615 | .freq_tbl = ftbl_camss_gp0_1_clk, | |
616 | .clkr.hw.init = &(struct clk_init_data){ | |
617 | .name = "camss_gp0_clk_src", | |
618 | .parent_names = mmcc_xo_mmpll0_1_gpll1_0, | |
619 | .num_parents = 5, | |
620 | .ops = &clk_rcg2_ops, | |
621 | }, | |
622 | }; | |
623 | ||
624 | static struct clk_rcg2 camss_gp1_clk_src = { | |
625 | .cmd_rcgr = 0x3450, | |
626 | .mnd_width = 8, | |
627 | .hid_width = 5, | |
628 | .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map, | |
629 | .freq_tbl = ftbl_camss_gp0_1_clk, | |
630 | .clkr.hw.init = &(struct clk_init_data){ | |
631 | .name = "camss_gp1_clk_src", | |
632 | .parent_names = mmcc_xo_mmpll0_1_gpll1_0, | |
633 | .num_parents = 5, | |
634 | .ops = &clk_rcg2_ops, | |
635 | }, | |
636 | }; | |
637 | ||
638 | static struct freq_tbl ftbl_camss_mclk0_3_clk[] = { | |
639 | F(4800000, P_XO, 4, 0, 0), | |
640 | F(6000000, P_GPLL0, 10, 1, 10), | |
641 | F(8000000, P_GPLL0, 15, 1, 5), | |
642 | F(9600000, P_XO, 2, 0, 0), | |
643 | F(16000000, P_GPLL0, 12.5, 1, 3), | |
644 | F(19200000, P_XO, 1, 0, 0), | |
645 | F(24000000, P_GPLL0, 5, 1, 5), | |
646 | F(32000000, P_MMPLL0, 5, 1, 5), | |
647 | F(48000000, P_GPLL0, 12.5, 0, 0), | |
648 | F(64000000, P_MMPLL0, 12.5, 0, 0), | |
649 | F(66670000, P_GPLL0, 9, 0, 0), | |
650 | { } | |
651 | }; | |
652 | ||
653 | static struct clk_rcg2 mclk0_clk_src = { | |
654 | .cmd_rcgr = 0x3360, | |
655 | .hid_width = 5, | |
656 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
657 | .freq_tbl = ftbl_camss_mclk0_3_clk, | |
658 | .clkr.hw.init = &(struct clk_init_data){ | |
659 | .name = "mclk0_clk_src", | |
660 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
661 | .num_parents = 4, | |
662 | .ops = &clk_rcg2_ops, | |
663 | }, | |
664 | }; | |
665 | ||
666 | static struct clk_rcg2 mclk1_clk_src = { | |
667 | .cmd_rcgr = 0x3390, | |
668 | .hid_width = 5, | |
669 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
670 | .freq_tbl = ftbl_camss_mclk0_3_clk, | |
671 | .clkr.hw.init = &(struct clk_init_data){ | |
672 | .name = "mclk1_clk_src", | |
673 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
674 | .num_parents = 4, | |
675 | .ops = &clk_rcg2_ops, | |
676 | }, | |
677 | }; | |
678 | ||
679 | static struct clk_rcg2 mclk2_clk_src = { | |
680 | .cmd_rcgr = 0x33c0, | |
681 | .hid_width = 5, | |
682 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
683 | .freq_tbl = ftbl_camss_mclk0_3_clk, | |
684 | .clkr.hw.init = &(struct clk_init_data){ | |
685 | .name = "mclk2_clk_src", | |
686 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
687 | .num_parents = 4, | |
688 | .ops = &clk_rcg2_ops, | |
689 | }, | |
690 | }; | |
691 | ||
692 | static struct clk_rcg2 mclk3_clk_src = { | |
693 | .cmd_rcgr = 0x33f0, | |
694 | .hid_width = 5, | |
695 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
696 | .freq_tbl = ftbl_camss_mclk0_3_clk, | |
697 | .clkr.hw.init = &(struct clk_init_data){ | |
698 | .name = "mclk3_clk_src", | |
699 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
700 | .num_parents = 4, | |
701 | .ops = &clk_rcg2_ops, | |
702 | }, | |
703 | }; | |
704 | ||
705 | static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = { | |
706 | F(100000000, P_GPLL0, 6, 0, 0), | |
707 | F(200000000, P_MMPLL0, 4, 0, 0), | |
708 | { } | |
709 | }; | |
710 | ||
711 | static struct clk_rcg2 csi0phytimer_clk_src = { | |
712 | .cmd_rcgr = 0x3000, | |
713 | .hid_width = 5, | |
714 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
715 | .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, | |
716 | .clkr.hw.init = &(struct clk_init_data){ | |
717 | .name = "csi0phytimer_clk_src", | |
718 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
719 | .num_parents = 4, | |
720 | .ops = &clk_rcg2_ops, | |
721 | }, | |
722 | }; | |
723 | ||
724 | static struct clk_rcg2 csi1phytimer_clk_src = { | |
725 | .cmd_rcgr = 0x3030, | |
726 | .hid_width = 5, | |
727 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
728 | .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, | |
729 | .clkr.hw.init = &(struct clk_init_data){ | |
730 | .name = "csi1phytimer_clk_src", | |
731 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
732 | .num_parents = 4, | |
733 | .ops = &clk_rcg2_ops, | |
734 | }, | |
735 | }; | |
736 | ||
737 | static struct clk_rcg2 csi2phytimer_clk_src = { | |
738 | .cmd_rcgr = 0x3060, | |
739 | .hid_width = 5, | |
740 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
741 | .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk, | |
742 | .clkr.hw.init = &(struct clk_init_data){ | |
743 | .name = "csi2phytimer_clk_src", | |
744 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
745 | .num_parents = 4, | |
746 | .ops = &clk_rcg2_ops, | |
747 | }, | |
748 | }; | |
749 | ||
750 | static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = { | |
751 | F(133330000, P_GPLL0, 4.5, 0, 0), | |
752 | F(266670000, P_MMPLL0, 3, 0, 0), | |
753 | F(320000000, P_MMPLL0, 2.5, 0, 0), | |
754 | F(400000000, P_MMPLL0, 2, 0, 0), | |
755 | F(465000000, P_MMPLL3, 2, 0, 0), | |
756 | { } | |
757 | }; | |
758 | ||
759 | static struct clk_rcg2 cpp_clk_src = { | |
760 | .cmd_rcgr = 0x3640, | |
761 | .hid_width = 5, | |
762 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
763 | .freq_tbl = ftbl_camss_vfe_cpp_clk, | |
764 | .clkr.hw.init = &(struct clk_init_data){ | |
765 | .name = "cpp_clk_src", | |
766 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
767 | .num_parents = 4, | |
768 | .ops = &clk_rcg2_ops, | |
769 | }, | |
770 | }; | |
771 | ||
b7b7cc70 SB |
772 | static struct freq_tbl byte_freq_tbl[] = { |
773 | { .src = P_DSI0PLL_BYTE }, | |
d8b21201 SB |
774 | { } |
775 | }; | |
776 | ||
777 | static struct clk_rcg2 byte0_clk_src = { | |
778 | .cmd_rcgr = 0x2120, | |
779 | .hid_width = 5, | |
b7b7cc70 SB |
780 | .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, |
781 | .freq_tbl = byte_freq_tbl, | |
d8b21201 SB |
782 | .clkr.hw.init = &(struct clk_init_data){ |
783 | .name = "byte0_clk_src", | |
b7b7cc70 | 784 | .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, |
d8b21201 | 785 | .num_parents = 6, |
b7b7cc70 SB |
786 | .ops = &clk_byte_ops, |
787 | .flags = CLK_SET_RATE_PARENT, | |
d8b21201 SB |
788 | }, |
789 | }; | |
790 | ||
791 | static struct clk_rcg2 byte1_clk_src = { | |
792 | .cmd_rcgr = 0x2140, | |
793 | .hid_width = 5, | |
b7b7cc70 SB |
794 | .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, |
795 | .freq_tbl = byte_freq_tbl, | |
d8b21201 SB |
796 | .clkr.hw.init = &(struct clk_init_data){ |
797 | .name = "byte1_clk_src", | |
b7b7cc70 | 798 | .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, |
d8b21201 | 799 | .num_parents = 6, |
b7b7cc70 SB |
800 | .ops = &clk_byte_ops, |
801 | .flags = CLK_SET_RATE_PARENT, | |
d8b21201 SB |
802 | }, |
803 | }; | |
804 | ||
805 | static struct freq_tbl ftbl_mdss_edpaux_clk[] = { | |
806 | F(19200000, P_XO, 1, 0, 0), | |
807 | { } | |
808 | }; | |
809 | ||
810 | static struct clk_rcg2 edpaux_clk_src = { | |
811 | .cmd_rcgr = 0x20e0, | |
812 | .hid_width = 5, | |
813 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
814 | .freq_tbl = ftbl_mdss_edpaux_clk, | |
815 | .clkr.hw.init = &(struct clk_init_data){ | |
816 | .name = "edpaux_clk_src", | |
817 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
818 | .num_parents = 4, | |
819 | .ops = &clk_rcg2_ops, | |
820 | }, | |
821 | }; | |
822 | ||
823 | static struct freq_tbl ftbl_mdss_edplink_clk[] = { | |
824 | F(135000000, P_EDPLINK, 2, 0, 0), | |
825 | F(270000000, P_EDPLINK, 11, 0, 0), | |
826 | { } | |
827 | }; | |
828 | ||
829 | static struct clk_rcg2 edplink_clk_src = { | |
830 | .cmd_rcgr = 0x20c0, | |
831 | .hid_width = 5, | |
832 | .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, | |
833 | .freq_tbl = ftbl_mdss_edplink_clk, | |
834 | .clkr.hw.init = &(struct clk_init_data){ | |
835 | .name = "edplink_clk_src", | |
836 | .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, | |
837 | .num_parents = 6, | |
838 | .ops = &clk_rcg2_ops, | |
b7b7cc70 | 839 | .flags = CLK_SET_RATE_PARENT, |
d8b21201 SB |
840 | }, |
841 | }; | |
842 | ||
b7b7cc70 SB |
843 | static struct freq_tbl edp_pixel_freq_tbl[] = { |
844 | { .src = P_EDPVCO }, | |
d8b21201 SB |
845 | { } |
846 | }; | |
847 | ||
848 | static struct clk_rcg2 edppixel_clk_src = { | |
849 | .cmd_rcgr = 0x20a0, | |
850 | .mnd_width = 8, | |
851 | .hid_width = 5, | |
852 | .parent_map = mmcc_xo_dsi_hdmi_edp_map, | |
b7b7cc70 | 853 | .freq_tbl = edp_pixel_freq_tbl, |
d8b21201 SB |
854 | .clkr.hw.init = &(struct clk_init_data){ |
855 | .name = "edppixel_clk_src", | |
856 | .parent_names = mmcc_xo_dsi_hdmi_edp, | |
857 | .num_parents = 6, | |
b7b7cc70 | 858 | .ops = &clk_edp_pixel_ops, |
d8b21201 SB |
859 | }, |
860 | }; | |
861 | ||
862 | static struct freq_tbl ftbl_mdss_esc0_1_clk[] = { | |
863 | F(19200000, P_XO, 1, 0, 0), | |
864 | { } | |
865 | }; | |
866 | ||
867 | static struct clk_rcg2 esc0_clk_src = { | |
868 | .cmd_rcgr = 0x2160, | |
869 | .hid_width = 5, | |
b7b7cc70 | 870 | .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, |
d8b21201 SB |
871 | .freq_tbl = ftbl_mdss_esc0_1_clk, |
872 | .clkr.hw.init = &(struct clk_init_data){ | |
873 | .name = "esc0_clk_src", | |
b7b7cc70 | 874 | .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, |
d8b21201 SB |
875 | .num_parents = 6, |
876 | .ops = &clk_rcg2_ops, | |
877 | }, | |
878 | }; | |
879 | ||
880 | static struct clk_rcg2 esc1_clk_src = { | |
881 | .cmd_rcgr = 0x2180, | |
882 | .hid_width = 5, | |
b7b7cc70 | 883 | .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map, |
d8b21201 SB |
884 | .freq_tbl = ftbl_mdss_esc0_1_clk, |
885 | .clkr.hw.init = &(struct clk_init_data){ | |
886 | .name = "esc1_clk_src", | |
b7b7cc70 | 887 | .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, |
d8b21201 SB |
888 | .num_parents = 6, |
889 | .ops = &clk_rcg2_ops, | |
890 | }, | |
891 | }; | |
892 | ||
b7b7cc70 SB |
893 | static struct freq_tbl extpclk_freq_tbl[] = { |
894 | { .src = P_HDMIPLL }, | |
d8b21201 SB |
895 | { } |
896 | }; | |
897 | ||
898 | static struct clk_rcg2 extpclk_clk_src = { | |
899 | .cmd_rcgr = 0x2060, | |
900 | .hid_width = 5, | |
901 | .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map, | |
b7b7cc70 | 902 | .freq_tbl = extpclk_freq_tbl, |
d8b21201 SB |
903 | .clkr.hw.init = &(struct clk_init_data){ |
904 | .name = "extpclk_clk_src", | |
905 | .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, | |
906 | .num_parents = 6, | |
b7b7cc70 SB |
907 | .ops = &clk_byte_ops, |
908 | .flags = CLK_SET_RATE_PARENT, | |
d8b21201 SB |
909 | }, |
910 | }; | |
911 | ||
912 | static struct freq_tbl ftbl_mdss_hdmi_clk[] = { | |
913 | F(19200000, P_XO, 1, 0, 0), | |
914 | { } | |
915 | }; | |
916 | ||
917 | static struct clk_rcg2 hdmi_clk_src = { | |
918 | .cmd_rcgr = 0x2100, | |
919 | .hid_width = 5, | |
920 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
921 | .freq_tbl = ftbl_mdss_hdmi_clk, | |
922 | .clkr.hw.init = &(struct clk_init_data){ | |
923 | .name = "hdmi_clk_src", | |
924 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
925 | .num_parents = 4, | |
926 | .ops = &clk_rcg2_ops, | |
927 | }, | |
928 | }; | |
929 | ||
930 | static struct freq_tbl ftbl_mdss_vsync_clk[] = { | |
931 | F(19200000, P_XO, 1, 0, 0), | |
932 | { } | |
933 | }; | |
934 | ||
935 | static struct clk_rcg2 vsync_clk_src = { | |
936 | .cmd_rcgr = 0x2080, | |
937 | .hid_width = 5, | |
938 | .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map, | |
939 | .freq_tbl = ftbl_mdss_vsync_clk, | |
940 | .clkr.hw.init = &(struct clk_init_data){ | |
941 | .name = "vsync_clk_src", | |
942 | .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, | |
943 | .num_parents = 4, | |
944 | .ops = &clk_rcg2_ops, | |
945 | }, | |
946 | }; | |
947 | ||
948 | static struct clk_branch camss_cci_cci_ahb_clk = { | |
949 | .halt_reg = 0x3348, | |
950 | .clkr = { | |
951 | .enable_reg = 0x3348, | |
952 | .enable_mask = BIT(0), | |
953 | .hw.init = &(struct clk_init_data){ | |
954 | .name = "camss_cci_cci_ahb_clk", | |
955 | .parent_names = (const char *[]){ | |
956 | "mmss_ahb_clk_src", | |
957 | }, | |
958 | .num_parents = 1, | |
959 | .ops = &clk_branch2_ops, | |
960 | }, | |
961 | }, | |
962 | }; | |
963 | ||
964 | static struct clk_branch camss_cci_cci_clk = { | |
965 | .halt_reg = 0x3344, | |
966 | .clkr = { | |
967 | .enable_reg = 0x3344, | |
968 | .enable_mask = BIT(0), | |
969 | .hw.init = &(struct clk_init_data){ | |
970 | .name = "camss_cci_cci_clk", | |
971 | .parent_names = (const char *[]){ | |
972 | "cci_clk_src", | |
973 | }, | |
974 | .num_parents = 1, | |
975 | .flags = CLK_SET_RATE_PARENT, | |
976 | .ops = &clk_branch2_ops, | |
977 | }, | |
978 | }, | |
979 | }; | |
980 | ||
981 | static struct clk_branch camss_csi0_ahb_clk = { | |
982 | .halt_reg = 0x30bc, | |
983 | .clkr = { | |
984 | .enable_reg = 0x30bc, | |
985 | .enable_mask = BIT(0), | |
986 | .hw.init = &(struct clk_init_data){ | |
987 | .name = "camss_csi0_ahb_clk", | |
988 | .parent_names = (const char *[]){ | |
989 | "mmss_ahb_clk_src", | |
990 | }, | |
991 | .num_parents = 1, | |
992 | .ops = &clk_branch2_ops, | |
993 | }, | |
994 | }, | |
995 | }; | |
996 | ||
997 | static struct clk_branch camss_csi0_clk = { | |
998 | .halt_reg = 0x30b4, | |
999 | .clkr = { | |
1000 | .enable_reg = 0x30b4, | |
1001 | .enable_mask = BIT(0), | |
1002 | .hw.init = &(struct clk_init_data){ | |
1003 | .name = "camss_csi0_clk", | |
1004 | .parent_names = (const char *[]){ | |
1005 | "csi0_clk_src", | |
1006 | }, | |
1007 | .num_parents = 1, | |
1008 | .flags = CLK_SET_RATE_PARENT, | |
1009 | .ops = &clk_branch2_ops, | |
1010 | }, | |
1011 | }, | |
1012 | }; | |
1013 | ||
1014 | static struct clk_branch camss_csi0phy_clk = { | |
1015 | .halt_reg = 0x30c4, | |
1016 | .clkr = { | |
1017 | .enable_reg = 0x30c4, | |
1018 | .enable_mask = BIT(0), | |
1019 | .hw.init = &(struct clk_init_data){ | |
1020 | .name = "camss_csi0phy_clk", | |
1021 | .parent_names = (const char *[]){ | |
1022 | "csi0_clk_src", | |
1023 | }, | |
1024 | .num_parents = 1, | |
1025 | .flags = CLK_SET_RATE_PARENT, | |
1026 | .ops = &clk_branch2_ops, | |
1027 | }, | |
1028 | }, | |
1029 | }; | |
1030 | ||
1031 | static struct clk_branch camss_csi0pix_clk = { | |
1032 | .halt_reg = 0x30e4, | |
1033 | .clkr = { | |
1034 | .enable_reg = 0x30e4, | |
1035 | .enable_mask = BIT(0), | |
1036 | .hw.init = &(struct clk_init_data){ | |
1037 | .name = "camss_csi0pix_clk", | |
1038 | .parent_names = (const char *[]){ | |
1039 | "csi0_clk_src", | |
1040 | }, | |
1041 | .num_parents = 1, | |
1042 | .flags = CLK_SET_RATE_PARENT, | |
1043 | .ops = &clk_branch2_ops, | |
1044 | }, | |
1045 | }, | |
1046 | }; | |
1047 | ||
1048 | static struct clk_branch camss_csi0rdi_clk = { | |
1049 | .halt_reg = 0x30d4, | |
1050 | .clkr = { | |
1051 | .enable_reg = 0x30d4, | |
1052 | .enable_mask = BIT(0), | |
1053 | .hw.init = &(struct clk_init_data){ | |
1054 | .name = "camss_csi0rdi_clk", | |
1055 | .parent_names = (const char *[]){ | |
1056 | "csi0_clk_src", | |
1057 | }, | |
1058 | .num_parents = 1, | |
1059 | .flags = CLK_SET_RATE_PARENT, | |
1060 | .ops = &clk_branch2_ops, | |
1061 | }, | |
1062 | }, | |
1063 | }; | |
1064 | ||
1065 | static struct clk_branch camss_csi1_ahb_clk = { | |
1066 | .halt_reg = 0x3128, | |
1067 | .clkr = { | |
1068 | .enable_reg = 0x3128, | |
1069 | .enable_mask = BIT(0), | |
1070 | .hw.init = &(struct clk_init_data){ | |
1071 | .name = "camss_csi1_ahb_clk", | |
1072 | .parent_names = (const char *[]){ | |
1073 | "mmss_ahb_clk_src", | |
1074 | }, | |
1075 | .num_parents = 1, | |
1076 | .ops = &clk_branch2_ops, | |
1077 | }, | |
1078 | }, | |
1079 | }; | |
1080 | ||
1081 | static struct clk_branch camss_csi1_clk = { | |
1082 | .halt_reg = 0x3124, | |
1083 | .clkr = { | |
1084 | .enable_reg = 0x3124, | |
1085 | .enable_mask = BIT(0), | |
1086 | .hw.init = &(struct clk_init_data){ | |
1087 | .name = "camss_csi1_clk", | |
1088 | .parent_names = (const char *[]){ | |
1089 | "csi1_clk_src", | |
1090 | }, | |
1091 | .num_parents = 1, | |
1092 | .flags = CLK_SET_RATE_PARENT, | |
1093 | .ops = &clk_branch2_ops, | |
1094 | }, | |
1095 | }, | |
1096 | }; | |
1097 | ||
1098 | static struct clk_branch camss_csi1phy_clk = { | |
1099 | .halt_reg = 0x3134, | |
1100 | .clkr = { | |
1101 | .enable_reg = 0x3134, | |
1102 | .enable_mask = BIT(0), | |
1103 | .hw.init = &(struct clk_init_data){ | |
1104 | .name = "camss_csi1phy_clk", | |
1105 | .parent_names = (const char *[]){ | |
1106 | "csi1_clk_src", | |
1107 | }, | |
1108 | .num_parents = 1, | |
1109 | .flags = CLK_SET_RATE_PARENT, | |
1110 | .ops = &clk_branch2_ops, | |
1111 | }, | |
1112 | }, | |
1113 | }; | |
1114 | ||
1115 | static struct clk_branch camss_csi1pix_clk = { | |
1116 | .halt_reg = 0x3154, | |
1117 | .clkr = { | |
1118 | .enable_reg = 0x3154, | |
1119 | .enable_mask = BIT(0), | |
1120 | .hw.init = &(struct clk_init_data){ | |
1121 | .name = "camss_csi1pix_clk", | |
1122 | .parent_names = (const char *[]){ | |
1123 | "csi1_clk_src", | |
1124 | }, | |
1125 | .num_parents = 1, | |
1126 | .flags = CLK_SET_RATE_PARENT, | |
1127 | .ops = &clk_branch2_ops, | |
1128 | }, | |
1129 | }, | |
1130 | }; | |
1131 | ||
1132 | static struct clk_branch camss_csi1rdi_clk = { | |
1133 | .halt_reg = 0x3144, | |
1134 | .clkr = { | |
1135 | .enable_reg = 0x3144, | |
1136 | .enable_mask = BIT(0), | |
1137 | .hw.init = &(struct clk_init_data){ | |
1138 | .name = "camss_csi1rdi_clk", | |
1139 | .parent_names = (const char *[]){ | |
1140 | "csi1_clk_src", | |
1141 | }, | |
1142 | .num_parents = 1, | |
1143 | .flags = CLK_SET_RATE_PARENT, | |
1144 | .ops = &clk_branch2_ops, | |
1145 | }, | |
1146 | }, | |
1147 | }; | |
1148 | ||
1149 | static struct clk_branch camss_csi2_ahb_clk = { | |
1150 | .halt_reg = 0x3188, | |
1151 | .clkr = { | |
1152 | .enable_reg = 0x3188, | |
1153 | .enable_mask = BIT(0), | |
1154 | .hw.init = &(struct clk_init_data){ | |
1155 | .name = "camss_csi2_ahb_clk", | |
1156 | .parent_names = (const char *[]){ | |
1157 | "mmss_ahb_clk_src", | |
1158 | }, | |
1159 | .num_parents = 1, | |
1160 | .ops = &clk_branch2_ops, | |
1161 | }, | |
1162 | }, | |
1163 | }; | |
1164 | ||
1165 | static struct clk_branch camss_csi2_clk = { | |
1166 | .halt_reg = 0x3184, | |
1167 | .clkr = { | |
1168 | .enable_reg = 0x3184, | |
1169 | .enable_mask = BIT(0), | |
1170 | .hw.init = &(struct clk_init_data){ | |
1171 | .name = "camss_csi2_clk", | |
1172 | .parent_names = (const char *[]){ | |
1173 | "csi2_clk_src", | |
1174 | }, | |
1175 | .num_parents = 1, | |
1176 | .flags = CLK_SET_RATE_PARENT, | |
1177 | .ops = &clk_branch2_ops, | |
1178 | }, | |
1179 | }, | |
1180 | }; | |
1181 | ||
1182 | static struct clk_branch camss_csi2phy_clk = { | |
1183 | .halt_reg = 0x3194, | |
1184 | .clkr = { | |
1185 | .enable_reg = 0x3194, | |
1186 | .enable_mask = BIT(0), | |
1187 | .hw.init = &(struct clk_init_data){ | |
1188 | .name = "camss_csi2phy_clk", | |
1189 | .parent_names = (const char *[]){ | |
1190 | "csi2_clk_src", | |
1191 | }, | |
1192 | .num_parents = 1, | |
1193 | .flags = CLK_SET_RATE_PARENT, | |
1194 | .ops = &clk_branch2_ops, | |
1195 | }, | |
1196 | }, | |
1197 | }; | |
1198 | ||
1199 | static struct clk_branch camss_csi2pix_clk = { | |
1200 | .halt_reg = 0x31b4, | |
1201 | .clkr = { | |
1202 | .enable_reg = 0x31b4, | |
1203 | .enable_mask = BIT(0), | |
1204 | .hw.init = &(struct clk_init_data){ | |
1205 | .name = "camss_csi2pix_clk", | |
1206 | .parent_names = (const char *[]){ | |
1207 | "csi2_clk_src", | |
1208 | }, | |
1209 | .num_parents = 1, | |
1210 | .flags = CLK_SET_RATE_PARENT, | |
1211 | .ops = &clk_branch2_ops, | |
1212 | }, | |
1213 | }, | |
1214 | }; | |
1215 | ||
1216 | static struct clk_branch camss_csi2rdi_clk = { | |
1217 | .halt_reg = 0x31a4, | |
1218 | .clkr = { | |
1219 | .enable_reg = 0x31a4, | |
1220 | .enable_mask = BIT(0), | |
1221 | .hw.init = &(struct clk_init_data){ | |
1222 | .name = "camss_csi2rdi_clk", | |
1223 | .parent_names = (const char *[]){ | |
1224 | "csi2_clk_src", | |
1225 | }, | |
1226 | .num_parents = 1, | |
1227 | .flags = CLK_SET_RATE_PARENT, | |
1228 | .ops = &clk_branch2_ops, | |
1229 | }, | |
1230 | }, | |
1231 | }; | |
1232 | ||
1233 | static struct clk_branch camss_csi3_ahb_clk = { | |
1234 | .halt_reg = 0x31e8, | |
1235 | .clkr = { | |
1236 | .enable_reg = 0x31e8, | |
1237 | .enable_mask = BIT(0), | |
1238 | .hw.init = &(struct clk_init_data){ | |
1239 | .name = "camss_csi3_ahb_clk", | |
1240 | .parent_names = (const char *[]){ | |
1241 | "mmss_ahb_clk_src", | |
1242 | }, | |
1243 | .num_parents = 1, | |
1244 | .ops = &clk_branch2_ops, | |
1245 | }, | |
1246 | }, | |
1247 | }; | |
1248 | ||
1249 | static struct clk_branch camss_csi3_clk = { | |
1250 | .halt_reg = 0x31e4, | |
1251 | .clkr = { | |
1252 | .enable_reg = 0x31e4, | |
1253 | .enable_mask = BIT(0), | |
1254 | .hw.init = &(struct clk_init_data){ | |
1255 | .name = "camss_csi3_clk", | |
1256 | .parent_names = (const char *[]){ | |
1257 | "csi3_clk_src", | |
1258 | }, | |
1259 | .num_parents = 1, | |
1260 | .flags = CLK_SET_RATE_PARENT, | |
1261 | .ops = &clk_branch2_ops, | |
1262 | }, | |
1263 | }, | |
1264 | }; | |
1265 | ||
1266 | static struct clk_branch camss_csi3phy_clk = { | |
1267 | .halt_reg = 0x31f4, | |
1268 | .clkr = { | |
1269 | .enable_reg = 0x31f4, | |
1270 | .enable_mask = BIT(0), | |
1271 | .hw.init = &(struct clk_init_data){ | |
1272 | .name = "camss_csi3phy_clk", | |
1273 | .parent_names = (const char *[]){ | |
1274 | "csi3_clk_src", | |
1275 | }, | |
1276 | .num_parents = 1, | |
1277 | .flags = CLK_SET_RATE_PARENT, | |
1278 | .ops = &clk_branch2_ops, | |
1279 | }, | |
1280 | }, | |
1281 | }; | |
1282 | ||
1283 | static struct clk_branch camss_csi3pix_clk = { | |
1284 | .halt_reg = 0x3214, | |
1285 | .clkr = { | |
1286 | .enable_reg = 0x3214, | |
1287 | .enable_mask = BIT(0), | |
1288 | .hw.init = &(struct clk_init_data){ | |
1289 | .name = "camss_csi3pix_clk", | |
1290 | .parent_names = (const char *[]){ | |
1291 | "csi3_clk_src", | |
1292 | }, | |
1293 | .num_parents = 1, | |
1294 | .flags = CLK_SET_RATE_PARENT, | |
1295 | .ops = &clk_branch2_ops, | |
1296 | }, | |
1297 | }, | |
1298 | }; | |
1299 | ||
1300 | static struct clk_branch camss_csi3rdi_clk = { | |
1301 | .halt_reg = 0x3204, | |
1302 | .clkr = { | |
1303 | .enable_reg = 0x3204, | |
1304 | .enable_mask = BIT(0), | |
1305 | .hw.init = &(struct clk_init_data){ | |
1306 | .name = "camss_csi3rdi_clk", | |
1307 | .parent_names = (const char *[]){ | |
1308 | "csi3_clk_src", | |
1309 | }, | |
1310 | .num_parents = 1, | |
1311 | .flags = CLK_SET_RATE_PARENT, | |
1312 | .ops = &clk_branch2_ops, | |
1313 | }, | |
1314 | }, | |
1315 | }; | |
1316 | ||
1317 | static struct clk_branch camss_csi_vfe0_clk = { | |
1318 | .halt_reg = 0x3704, | |
1319 | .clkr = { | |
1320 | .enable_reg = 0x3704, | |
1321 | .enable_mask = BIT(0), | |
1322 | .hw.init = &(struct clk_init_data){ | |
1323 | .name = "camss_csi_vfe0_clk", | |
1324 | .parent_names = (const char *[]){ | |
1325 | "vfe0_clk_src", | |
1326 | }, | |
1327 | .num_parents = 1, | |
1328 | .flags = CLK_SET_RATE_PARENT, | |
1329 | .ops = &clk_branch2_ops, | |
1330 | }, | |
1331 | }, | |
1332 | }; | |
1333 | ||
1334 | static struct clk_branch camss_csi_vfe1_clk = { | |
1335 | .halt_reg = 0x3714, | |
1336 | .clkr = { | |
1337 | .enable_reg = 0x3714, | |
1338 | .enable_mask = BIT(0), | |
1339 | .hw.init = &(struct clk_init_data){ | |
1340 | .name = "camss_csi_vfe1_clk", | |
1341 | .parent_names = (const char *[]){ | |
1342 | "vfe1_clk_src", | |
1343 | }, | |
1344 | .num_parents = 1, | |
1345 | .flags = CLK_SET_RATE_PARENT, | |
1346 | .ops = &clk_branch2_ops, | |
1347 | }, | |
1348 | }, | |
1349 | }; | |
1350 | ||
1351 | static struct clk_branch camss_gp0_clk = { | |
1352 | .halt_reg = 0x3444, | |
1353 | .clkr = { | |
1354 | .enable_reg = 0x3444, | |
1355 | .enable_mask = BIT(0), | |
1356 | .hw.init = &(struct clk_init_data){ | |
1357 | .name = "camss_gp0_clk", | |
1358 | .parent_names = (const char *[]){ | |
1359 | "camss_gp0_clk_src", | |
1360 | }, | |
1361 | .num_parents = 1, | |
1362 | .flags = CLK_SET_RATE_PARENT, | |
1363 | .ops = &clk_branch2_ops, | |
1364 | }, | |
1365 | }, | |
1366 | }; | |
1367 | ||
1368 | static struct clk_branch camss_gp1_clk = { | |
1369 | .halt_reg = 0x3474, | |
1370 | .clkr = { | |
1371 | .enable_reg = 0x3474, | |
1372 | .enable_mask = BIT(0), | |
1373 | .hw.init = &(struct clk_init_data){ | |
1374 | .name = "camss_gp1_clk", | |
1375 | .parent_names = (const char *[]){ | |
1376 | "camss_gp1_clk_src", | |
1377 | }, | |
1378 | .num_parents = 1, | |
1379 | .flags = CLK_SET_RATE_PARENT, | |
1380 | .ops = &clk_branch2_ops, | |
1381 | }, | |
1382 | }, | |
1383 | }; | |
1384 | ||
1385 | static struct clk_branch camss_ispif_ahb_clk = { | |
1386 | .halt_reg = 0x3224, | |
1387 | .clkr = { | |
1388 | .enable_reg = 0x3224, | |
1389 | .enable_mask = BIT(0), | |
1390 | .hw.init = &(struct clk_init_data){ | |
1391 | .name = "camss_ispif_ahb_clk", | |
1392 | .parent_names = (const char *[]){ | |
1393 | "mmss_ahb_clk_src", | |
1394 | }, | |
1395 | .num_parents = 1, | |
1396 | .ops = &clk_branch2_ops, | |
1397 | }, | |
1398 | }, | |
1399 | }; | |
1400 | ||
1401 | static struct clk_branch camss_jpeg_jpeg0_clk = { | |
1402 | .halt_reg = 0x35a8, | |
1403 | .clkr = { | |
1404 | .enable_reg = 0x35a8, | |
1405 | .enable_mask = BIT(0), | |
1406 | .hw.init = &(struct clk_init_data){ | |
1407 | .name = "camss_jpeg_jpeg0_clk", | |
1408 | .parent_names = (const char *[]){ | |
1409 | "jpeg0_clk_src", | |
1410 | }, | |
1411 | .num_parents = 1, | |
1412 | .flags = CLK_SET_RATE_PARENT, | |
1413 | .ops = &clk_branch2_ops, | |
1414 | }, | |
1415 | }, | |
1416 | }; | |
1417 | ||
1418 | static struct clk_branch camss_jpeg_jpeg1_clk = { | |
1419 | .halt_reg = 0x35ac, | |
1420 | .clkr = { | |
1421 | .enable_reg = 0x35ac, | |
1422 | .enable_mask = BIT(0), | |
1423 | .hw.init = &(struct clk_init_data){ | |
1424 | .name = "camss_jpeg_jpeg1_clk", | |
1425 | .parent_names = (const char *[]){ | |
1426 | "jpeg1_clk_src", | |
1427 | }, | |
1428 | .num_parents = 1, | |
1429 | .flags = CLK_SET_RATE_PARENT, | |
1430 | .ops = &clk_branch2_ops, | |
1431 | }, | |
1432 | }, | |
1433 | }; | |
1434 | ||
1435 | static struct clk_branch camss_jpeg_jpeg2_clk = { | |
1436 | .halt_reg = 0x35b0, | |
1437 | .clkr = { | |
1438 | .enable_reg = 0x35b0, | |
1439 | .enable_mask = BIT(0), | |
1440 | .hw.init = &(struct clk_init_data){ | |
1441 | .name = "camss_jpeg_jpeg2_clk", | |
1442 | .parent_names = (const char *[]){ | |
1443 | "jpeg2_clk_src", | |
1444 | }, | |
1445 | .num_parents = 1, | |
1446 | .flags = CLK_SET_RATE_PARENT, | |
1447 | .ops = &clk_branch2_ops, | |
1448 | }, | |
1449 | }, | |
1450 | }; | |
1451 | ||
1452 | static struct clk_branch camss_jpeg_jpeg_ahb_clk = { | |
1453 | .halt_reg = 0x35b4, | |
1454 | .clkr = { | |
1455 | .enable_reg = 0x35b4, | |
1456 | .enable_mask = BIT(0), | |
1457 | .hw.init = &(struct clk_init_data){ | |
1458 | .name = "camss_jpeg_jpeg_ahb_clk", | |
1459 | .parent_names = (const char *[]){ | |
1460 | "mmss_ahb_clk_src", | |
1461 | }, | |
1462 | .num_parents = 1, | |
1463 | .ops = &clk_branch2_ops, | |
1464 | }, | |
1465 | }, | |
1466 | }; | |
1467 | ||
1468 | static struct clk_branch camss_jpeg_jpeg_axi_clk = { | |
1469 | .halt_reg = 0x35b8, | |
1470 | .clkr = { | |
1471 | .enable_reg = 0x35b8, | |
1472 | .enable_mask = BIT(0), | |
1473 | .hw.init = &(struct clk_init_data){ | |
1474 | .name = "camss_jpeg_jpeg_axi_clk", | |
1475 | .parent_names = (const char *[]){ | |
1476 | "mmss_axi_clk_src", | |
1477 | }, | |
1478 | .num_parents = 1, | |
1479 | .ops = &clk_branch2_ops, | |
1480 | }, | |
1481 | }, | |
1482 | }; | |
1483 | ||
1484 | static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = { | |
1485 | .halt_reg = 0x35bc, | |
1486 | .clkr = { | |
1487 | .enable_reg = 0x35bc, | |
1488 | .enable_mask = BIT(0), | |
1489 | .hw.init = &(struct clk_init_data){ | |
1490 | .name = "camss_jpeg_jpeg_ocmemnoc_clk", | |
1491 | .parent_names = (const char *[]){ | |
1492 | "ocmemnoc_clk_src", | |
1493 | }, | |
1494 | .num_parents = 1, | |
1495 | .flags = CLK_SET_RATE_PARENT, | |
1496 | .ops = &clk_branch2_ops, | |
1497 | }, | |
1498 | }, | |
1499 | }; | |
1500 | ||
1501 | static struct clk_branch camss_mclk0_clk = { | |
1502 | .halt_reg = 0x3384, | |
1503 | .clkr = { | |
1504 | .enable_reg = 0x3384, | |
1505 | .enable_mask = BIT(0), | |
1506 | .hw.init = &(struct clk_init_data){ | |
1507 | .name = "camss_mclk0_clk", | |
1508 | .parent_names = (const char *[]){ | |
1509 | "mclk0_clk_src", | |
1510 | }, | |
1511 | .num_parents = 1, | |
1512 | .flags = CLK_SET_RATE_PARENT, | |
1513 | .ops = &clk_branch2_ops, | |
1514 | }, | |
1515 | }, | |
1516 | }; | |
1517 | ||
1518 | static struct clk_branch camss_mclk1_clk = { | |
1519 | .halt_reg = 0x33b4, | |
1520 | .clkr = { | |
1521 | .enable_reg = 0x33b4, | |
1522 | .enable_mask = BIT(0), | |
1523 | .hw.init = &(struct clk_init_data){ | |
1524 | .name = "camss_mclk1_clk", | |
1525 | .parent_names = (const char *[]){ | |
1526 | "mclk1_clk_src", | |
1527 | }, | |
1528 | .num_parents = 1, | |
1529 | .flags = CLK_SET_RATE_PARENT, | |
1530 | .ops = &clk_branch2_ops, | |
1531 | }, | |
1532 | }, | |
1533 | }; | |
1534 | ||
1535 | static struct clk_branch camss_mclk2_clk = { | |
1536 | .halt_reg = 0x33e4, | |
1537 | .clkr = { | |
1538 | .enable_reg = 0x33e4, | |
1539 | .enable_mask = BIT(0), | |
1540 | .hw.init = &(struct clk_init_data){ | |
1541 | .name = "camss_mclk2_clk", | |
1542 | .parent_names = (const char *[]){ | |
1543 | "mclk2_clk_src", | |
1544 | }, | |
1545 | .num_parents = 1, | |
1546 | .flags = CLK_SET_RATE_PARENT, | |
1547 | .ops = &clk_branch2_ops, | |
1548 | }, | |
1549 | }, | |
1550 | }; | |
1551 | ||
1552 | static struct clk_branch camss_mclk3_clk = { | |
1553 | .halt_reg = 0x3414, | |
1554 | .clkr = { | |
1555 | .enable_reg = 0x3414, | |
1556 | .enable_mask = BIT(0), | |
1557 | .hw.init = &(struct clk_init_data){ | |
1558 | .name = "camss_mclk3_clk", | |
1559 | .parent_names = (const char *[]){ | |
1560 | "mclk3_clk_src", | |
1561 | }, | |
1562 | .num_parents = 1, | |
1563 | .flags = CLK_SET_RATE_PARENT, | |
1564 | .ops = &clk_branch2_ops, | |
1565 | }, | |
1566 | }, | |
1567 | }; | |
1568 | ||
1569 | static struct clk_branch camss_micro_ahb_clk = { | |
1570 | .halt_reg = 0x3494, | |
1571 | .clkr = { | |
1572 | .enable_reg = 0x3494, | |
1573 | .enable_mask = BIT(0), | |
1574 | .hw.init = &(struct clk_init_data){ | |
1575 | .name = "camss_micro_ahb_clk", | |
1576 | .parent_names = (const char *[]){ | |
1577 | "mmss_ahb_clk_src", | |
1578 | }, | |
1579 | .num_parents = 1, | |
1580 | .ops = &clk_branch2_ops, | |
1581 | }, | |
1582 | }, | |
1583 | }; | |
1584 | ||
1585 | static struct clk_branch camss_phy0_csi0phytimer_clk = { | |
1586 | .halt_reg = 0x3024, | |
1587 | .clkr = { | |
1588 | .enable_reg = 0x3024, | |
1589 | .enable_mask = BIT(0), | |
1590 | .hw.init = &(struct clk_init_data){ | |
1591 | .name = "camss_phy0_csi0phytimer_clk", | |
1592 | .parent_names = (const char *[]){ | |
1593 | "csi0phytimer_clk_src", | |
1594 | }, | |
1595 | .num_parents = 1, | |
1596 | .flags = CLK_SET_RATE_PARENT, | |
1597 | .ops = &clk_branch2_ops, | |
1598 | }, | |
1599 | }, | |
1600 | }; | |
1601 | ||
1602 | static struct clk_branch camss_phy1_csi1phytimer_clk = { | |
1603 | .halt_reg = 0x3054, | |
1604 | .clkr = { | |
1605 | .enable_reg = 0x3054, | |
1606 | .enable_mask = BIT(0), | |
1607 | .hw.init = &(struct clk_init_data){ | |
1608 | .name = "camss_phy1_csi1phytimer_clk", | |
1609 | .parent_names = (const char *[]){ | |
1610 | "csi1phytimer_clk_src", | |
1611 | }, | |
1612 | .num_parents = 1, | |
1613 | .flags = CLK_SET_RATE_PARENT, | |
1614 | .ops = &clk_branch2_ops, | |
1615 | }, | |
1616 | }, | |
1617 | }; | |
1618 | ||
1619 | static struct clk_branch camss_phy2_csi2phytimer_clk = { | |
1620 | .halt_reg = 0x3084, | |
1621 | .clkr = { | |
1622 | .enable_reg = 0x3084, | |
1623 | .enable_mask = BIT(0), | |
1624 | .hw.init = &(struct clk_init_data){ | |
1625 | .name = "camss_phy2_csi2phytimer_clk", | |
1626 | .parent_names = (const char *[]){ | |
1627 | "csi2phytimer_clk_src", | |
1628 | }, | |
1629 | .num_parents = 1, | |
1630 | .flags = CLK_SET_RATE_PARENT, | |
1631 | .ops = &clk_branch2_ops, | |
1632 | }, | |
1633 | }, | |
1634 | }; | |
1635 | ||
1636 | static struct clk_branch camss_top_ahb_clk = { | |
1637 | .halt_reg = 0x3484, | |
1638 | .clkr = { | |
1639 | .enable_reg = 0x3484, | |
1640 | .enable_mask = BIT(0), | |
1641 | .hw.init = &(struct clk_init_data){ | |
1642 | .name = "camss_top_ahb_clk", | |
1643 | .parent_names = (const char *[]){ | |
1644 | "mmss_ahb_clk_src", | |
1645 | }, | |
1646 | .num_parents = 1, | |
1647 | .ops = &clk_branch2_ops, | |
1648 | }, | |
1649 | }, | |
1650 | }; | |
1651 | ||
1652 | static struct clk_branch camss_vfe_cpp_ahb_clk = { | |
1653 | .halt_reg = 0x36b4, | |
1654 | .clkr = { | |
1655 | .enable_reg = 0x36b4, | |
1656 | .enable_mask = BIT(0), | |
1657 | .hw.init = &(struct clk_init_data){ | |
1658 | .name = "camss_vfe_cpp_ahb_clk", | |
1659 | .parent_names = (const char *[]){ | |
1660 | "mmss_ahb_clk_src", | |
1661 | }, | |
1662 | .num_parents = 1, | |
1663 | .ops = &clk_branch2_ops, | |
1664 | }, | |
1665 | }, | |
1666 | }; | |
1667 | ||
1668 | static struct clk_branch camss_vfe_cpp_clk = { | |
1669 | .halt_reg = 0x36b0, | |
1670 | .clkr = { | |
1671 | .enable_reg = 0x36b0, | |
1672 | .enable_mask = BIT(0), | |
1673 | .hw.init = &(struct clk_init_data){ | |
1674 | .name = "camss_vfe_cpp_clk", | |
1675 | .parent_names = (const char *[]){ | |
1676 | "cpp_clk_src", | |
1677 | }, | |
1678 | .num_parents = 1, | |
1679 | .flags = CLK_SET_RATE_PARENT, | |
1680 | .ops = &clk_branch2_ops, | |
1681 | }, | |
1682 | }, | |
1683 | }; | |
1684 | ||
1685 | static struct clk_branch camss_vfe_vfe0_clk = { | |
1686 | .halt_reg = 0x36a8, | |
1687 | .clkr = { | |
1688 | .enable_reg = 0x36a8, | |
1689 | .enable_mask = BIT(0), | |
1690 | .hw.init = &(struct clk_init_data){ | |
1691 | .name = "camss_vfe_vfe0_clk", | |
1692 | .parent_names = (const char *[]){ | |
1693 | "vfe0_clk_src", | |
1694 | }, | |
1695 | .num_parents = 1, | |
1696 | .flags = CLK_SET_RATE_PARENT, | |
1697 | .ops = &clk_branch2_ops, | |
1698 | }, | |
1699 | }, | |
1700 | }; | |
1701 | ||
1702 | static struct clk_branch camss_vfe_vfe1_clk = { | |
1703 | .halt_reg = 0x36ac, | |
1704 | .clkr = { | |
1705 | .enable_reg = 0x36ac, | |
1706 | .enable_mask = BIT(0), | |
1707 | .hw.init = &(struct clk_init_data){ | |
1708 | .name = "camss_vfe_vfe1_clk", | |
1709 | .parent_names = (const char *[]){ | |
1710 | "vfe1_clk_src", | |
1711 | }, | |
1712 | .num_parents = 1, | |
1713 | .flags = CLK_SET_RATE_PARENT, | |
1714 | .ops = &clk_branch2_ops, | |
1715 | }, | |
1716 | }, | |
1717 | }; | |
1718 | ||
1719 | static struct clk_branch camss_vfe_vfe_ahb_clk = { | |
1720 | .halt_reg = 0x36b8, | |
1721 | .clkr = { | |
1722 | .enable_reg = 0x36b8, | |
1723 | .enable_mask = BIT(0), | |
1724 | .hw.init = &(struct clk_init_data){ | |
1725 | .name = "camss_vfe_vfe_ahb_clk", | |
1726 | .parent_names = (const char *[]){ | |
1727 | "mmss_ahb_clk_src", | |
1728 | }, | |
1729 | .num_parents = 1, | |
1730 | .ops = &clk_branch2_ops, | |
1731 | }, | |
1732 | }, | |
1733 | }; | |
1734 | ||
1735 | static struct clk_branch camss_vfe_vfe_axi_clk = { | |
1736 | .halt_reg = 0x36bc, | |
1737 | .clkr = { | |
1738 | .enable_reg = 0x36bc, | |
1739 | .enable_mask = BIT(0), | |
1740 | .hw.init = &(struct clk_init_data){ | |
1741 | .name = "camss_vfe_vfe_axi_clk", | |
1742 | .parent_names = (const char *[]){ | |
1743 | "mmss_axi_clk_src", | |
1744 | }, | |
1745 | .num_parents = 1, | |
1746 | .ops = &clk_branch2_ops, | |
1747 | }, | |
1748 | }, | |
1749 | }; | |
1750 | ||
1751 | static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = { | |
1752 | .halt_reg = 0x36c0, | |
1753 | .clkr = { | |
1754 | .enable_reg = 0x36c0, | |
1755 | .enable_mask = BIT(0), | |
1756 | .hw.init = &(struct clk_init_data){ | |
1757 | .name = "camss_vfe_vfe_ocmemnoc_clk", | |
1758 | .parent_names = (const char *[]){ | |
1759 | "ocmemnoc_clk_src", | |
1760 | }, | |
1761 | .num_parents = 1, | |
1762 | .flags = CLK_SET_RATE_PARENT, | |
1763 | .ops = &clk_branch2_ops, | |
1764 | }, | |
1765 | }, | |
1766 | }; | |
1767 | ||
1768 | static struct clk_branch mdss_ahb_clk = { | |
1769 | .halt_reg = 0x2308, | |
1770 | .clkr = { | |
1771 | .enable_reg = 0x2308, | |
1772 | .enable_mask = BIT(0), | |
1773 | .hw.init = &(struct clk_init_data){ | |
1774 | .name = "mdss_ahb_clk", | |
1775 | .parent_names = (const char *[]){ | |
1776 | "mmss_ahb_clk_src", | |
1777 | }, | |
1778 | .num_parents = 1, | |
1779 | .ops = &clk_branch2_ops, | |
1780 | }, | |
1781 | }, | |
1782 | }; | |
1783 | ||
1784 | static struct clk_branch mdss_axi_clk = { | |
1785 | .halt_reg = 0x2310, | |
1786 | .clkr = { | |
1787 | .enable_reg = 0x2310, | |
1788 | .enable_mask = BIT(0), | |
1789 | .hw.init = &(struct clk_init_data){ | |
1790 | .name = "mdss_axi_clk", | |
1791 | .parent_names = (const char *[]){ | |
1792 | "mmss_axi_clk_src", | |
1793 | }, | |
1794 | .num_parents = 1, | |
1795 | .flags = CLK_SET_RATE_PARENT, | |
1796 | .ops = &clk_branch2_ops, | |
1797 | }, | |
1798 | }, | |
1799 | }; | |
1800 | ||
1801 | static struct clk_branch mdss_byte0_clk = { | |
1802 | .halt_reg = 0x233c, | |
1803 | .clkr = { | |
1804 | .enable_reg = 0x233c, | |
1805 | .enable_mask = BIT(0), | |
1806 | .hw.init = &(struct clk_init_data){ | |
1807 | .name = "mdss_byte0_clk", | |
1808 | .parent_names = (const char *[]){ | |
1809 | "byte0_clk_src", | |
1810 | }, | |
1811 | .num_parents = 1, | |
1812 | .flags = CLK_SET_RATE_PARENT, | |
1813 | .ops = &clk_branch2_ops, | |
1814 | }, | |
1815 | }, | |
1816 | }; | |
1817 | ||
1818 | static struct clk_branch mdss_byte1_clk = { | |
1819 | .halt_reg = 0x2340, | |
1820 | .clkr = { | |
1821 | .enable_reg = 0x2340, | |
1822 | .enable_mask = BIT(0), | |
1823 | .hw.init = &(struct clk_init_data){ | |
1824 | .name = "mdss_byte1_clk", | |
1825 | .parent_names = (const char *[]){ | |
1826 | "byte1_clk_src", | |
1827 | }, | |
1828 | .num_parents = 1, | |
1829 | .flags = CLK_SET_RATE_PARENT, | |
1830 | .ops = &clk_branch2_ops, | |
1831 | }, | |
1832 | }, | |
1833 | }; | |
1834 | ||
1835 | static struct clk_branch mdss_edpaux_clk = { | |
1836 | .halt_reg = 0x2334, | |
1837 | .clkr = { | |
1838 | .enable_reg = 0x2334, | |
1839 | .enable_mask = BIT(0), | |
1840 | .hw.init = &(struct clk_init_data){ | |
1841 | .name = "mdss_edpaux_clk", | |
1842 | .parent_names = (const char *[]){ | |
1843 | "edpaux_clk_src", | |
1844 | }, | |
1845 | .num_parents = 1, | |
1846 | .flags = CLK_SET_RATE_PARENT, | |
1847 | .ops = &clk_branch2_ops, | |
1848 | }, | |
1849 | }, | |
1850 | }; | |
1851 | ||
1852 | static struct clk_branch mdss_edplink_clk = { | |
1853 | .halt_reg = 0x2330, | |
1854 | .clkr = { | |
1855 | .enable_reg = 0x2330, | |
1856 | .enable_mask = BIT(0), | |
1857 | .hw.init = &(struct clk_init_data){ | |
1858 | .name = "mdss_edplink_clk", | |
1859 | .parent_names = (const char *[]){ | |
1860 | "edplink_clk_src", | |
1861 | }, | |
1862 | .num_parents = 1, | |
1863 | .flags = CLK_SET_RATE_PARENT, | |
1864 | .ops = &clk_branch2_ops, | |
1865 | }, | |
1866 | }, | |
1867 | }; | |
1868 | ||
1869 | static struct clk_branch mdss_edppixel_clk = { | |
1870 | .halt_reg = 0x232c, | |
1871 | .clkr = { | |
1872 | .enable_reg = 0x232c, | |
1873 | .enable_mask = BIT(0), | |
1874 | .hw.init = &(struct clk_init_data){ | |
1875 | .name = "mdss_edppixel_clk", | |
1876 | .parent_names = (const char *[]){ | |
1877 | "edppixel_clk_src", | |
1878 | }, | |
1879 | .num_parents = 1, | |
1880 | .flags = CLK_SET_RATE_PARENT, | |
1881 | .ops = &clk_branch2_ops, | |
1882 | }, | |
1883 | }, | |
1884 | }; | |
1885 | ||
1886 | static struct clk_branch mdss_esc0_clk = { | |
1887 | .halt_reg = 0x2344, | |
1888 | .clkr = { | |
1889 | .enable_reg = 0x2344, | |
1890 | .enable_mask = BIT(0), | |
1891 | .hw.init = &(struct clk_init_data){ | |
1892 | .name = "mdss_esc0_clk", | |
1893 | .parent_names = (const char *[]){ | |
1894 | "esc0_clk_src", | |
1895 | }, | |
1896 | .num_parents = 1, | |
1897 | .flags = CLK_SET_RATE_PARENT, | |
1898 | .ops = &clk_branch2_ops, | |
1899 | }, | |
1900 | }, | |
1901 | }; | |
1902 | ||
1903 | static struct clk_branch mdss_esc1_clk = { | |
1904 | .halt_reg = 0x2348, | |
1905 | .clkr = { | |
1906 | .enable_reg = 0x2348, | |
1907 | .enable_mask = BIT(0), | |
1908 | .hw.init = &(struct clk_init_data){ | |
1909 | .name = "mdss_esc1_clk", | |
1910 | .parent_names = (const char *[]){ | |
1911 | "esc1_clk_src", | |
1912 | }, | |
1913 | .num_parents = 1, | |
1914 | .flags = CLK_SET_RATE_PARENT, | |
1915 | .ops = &clk_branch2_ops, | |
1916 | }, | |
1917 | }, | |
1918 | }; | |
1919 | ||
1920 | static struct clk_branch mdss_extpclk_clk = { | |
1921 | .halt_reg = 0x2324, | |
1922 | .clkr = { | |
1923 | .enable_reg = 0x2324, | |
1924 | .enable_mask = BIT(0), | |
1925 | .hw.init = &(struct clk_init_data){ | |
1926 | .name = "mdss_extpclk_clk", | |
1927 | .parent_names = (const char *[]){ | |
1928 | "extpclk_clk_src", | |
1929 | }, | |
1930 | .num_parents = 1, | |
1931 | .flags = CLK_SET_RATE_PARENT, | |
1932 | .ops = &clk_branch2_ops, | |
1933 | }, | |
1934 | }, | |
1935 | }; | |
1936 | ||
1937 | static struct clk_branch mdss_hdmi_ahb_clk = { | |
1938 | .halt_reg = 0x230c, | |
1939 | .clkr = { | |
1940 | .enable_reg = 0x230c, | |
1941 | .enable_mask = BIT(0), | |
1942 | .hw.init = &(struct clk_init_data){ | |
1943 | .name = "mdss_hdmi_ahb_clk", | |
1944 | .parent_names = (const char *[]){ | |
1945 | "mmss_ahb_clk_src", | |
1946 | }, | |
1947 | .num_parents = 1, | |
1948 | .ops = &clk_branch2_ops, | |
1949 | }, | |
1950 | }, | |
1951 | }; | |
1952 | ||
1953 | static struct clk_branch mdss_hdmi_clk = { | |
1954 | .halt_reg = 0x2338, | |
1955 | .clkr = { | |
1956 | .enable_reg = 0x2338, | |
1957 | .enable_mask = BIT(0), | |
1958 | .hw.init = &(struct clk_init_data){ | |
1959 | .name = "mdss_hdmi_clk", | |
1960 | .parent_names = (const char *[]){ | |
1961 | "hdmi_clk_src", | |
1962 | }, | |
1963 | .num_parents = 1, | |
1964 | .flags = CLK_SET_RATE_PARENT, | |
1965 | .ops = &clk_branch2_ops, | |
1966 | }, | |
1967 | }, | |
1968 | }; | |
1969 | ||
1970 | static struct clk_branch mdss_mdp_clk = { | |
1971 | .halt_reg = 0x231c, | |
1972 | .clkr = { | |
1973 | .enable_reg = 0x231c, | |
1974 | .enable_mask = BIT(0), | |
1975 | .hw.init = &(struct clk_init_data){ | |
1976 | .name = "mdss_mdp_clk", | |
1977 | .parent_names = (const char *[]){ | |
1978 | "mdp_clk_src", | |
1979 | }, | |
1980 | .num_parents = 1, | |
1981 | .flags = CLK_SET_RATE_PARENT, | |
1982 | .ops = &clk_branch2_ops, | |
1983 | }, | |
1984 | }, | |
1985 | }; | |
1986 | ||
1987 | static struct clk_branch mdss_mdp_lut_clk = { | |
1988 | .halt_reg = 0x2320, | |
1989 | .clkr = { | |
1990 | .enable_reg = 0x2320, | |
1991 | .enable_mask = BIT(0), | |
1992 | .hw.init = &(struct clk_init_data){ | |
1993 | .name = "mdss_mdp_lut_clk", | |
1994 | .parent_names = (const char *[]){ | |
1995 | "mdp_clk_src", | |
1996 | }, | |
1997 | .num_parents = 1, | |
1998 | .flags = CLK_SET_RATE_PARENT, | |
1999 | .ops = &clk_branch2_ops, | |
2000 | }, | |
2001 | }, | |
2002 | }; | |
2003 | ||
2004 | static struct clk_branch mdss_pclk0_clk = { | |
2005 | .halt_reg = 0x2314, | |
2006 | .clkr = { | |
2007 | .enable_reg = 0x2314, | |
2008 | .enable_mask = BIT(0), | |
2009 | .hw.init = &(struct clk_init_data){ | |
2010 | .name = "mdss_pclk0_clk", | |
2011 | .parent_names = (const char *[]){ | |
2012 | "pclk0_clk_src", | |
2013 | }, | |
2014 | .num_parents = 1, | |
2015 | .flags = CLK_SET_RATE_PARENT, | |
2016 | .ops = &clk_branch2_ops, | |
2017 | }, | |
2018 | }, | |
2019 | }; | |
2020 | ||
2021 | static struct clk_branch mdss_pclk1_clk = { | |
2022 | .halt_reg = 0x2318, | |
2023 | .clkr = { | |
2024 | .enable_reg = 0x2318, | |
2025 | .enable_mask = BIT(0), | |
2026 | .hw.init = &(struct clk_init_data){ | |
2027 | .name = "mdss_pclk1_clk", | |
2028 | .parent_names = (const char *[]){ | |
2029 | "pclk1_clk_src", | |
2030 | }, | |
2031 | .num_parents = 1, | |
2032 | .flags = CLK_SET_RATE_PARENT, | |
2033 | .ops = &clk_branch2_ops, | |
2034 | }, | |
2035 | }, | |
2036 | }; | |
2037 | ||
2038 | static struct clk_branch mdss_vsync_clk = { | |
2039 | .halt_reg = 0x2328, | |
2040 | .clkr = { | |
2041 | .enable_reg = 0x2328, | |
2042 | .enable_mask = BIT(0), | |
2043 | .hw.init = &(struct clk_init_data){ | |
2044 | .name = "mdss_vsync_clk", | |
2045 | .parent_names = (const char *[]){ | |
2046 | "vsync_clk_src", | |
2047 | }, | |
2048 | .num_parents = 1, | |
2049 | .flags = CLK_SET_RATE_PARENT, | |
2050 | .ops = &clk_branch2_ops, | |
2051 | }, | |
2052 | }, | |
2053 | }; | |
2054 | ||
2055 | static struct clk_branch mmss_misc_ahb_clk = { | |
2056 | .halt_reg = 0x502c, | |
2057 | .clkr = { | |
2058 | .enable_reg = 0x502c, | |
2059 | .enable_mask = BIT(0), | |
2060 | .hw.init = &(struct clk_init_data){ | |
2061 | .name = "mmss_misc_ahb_clk", | |
2062 | .parent_names = (const char *[]){ | |
2063 | "mmss_ahb_clk_src", | |
2064 | }, | |
2065 | .num_parents = 1, | |
2066 | .ops = &clk_branch2_ops, | |
2067 | }, | |
2068 | }, | |
2069 | }; | |
2070 | ||
2071 | static struct clk_branch mmss_mmssnoc_ahb_clk = { | |
2072 | .halt_reg = 0x5024, | |
2073 | .clkr = { | |
2074 | .enable_reg = 0x5024, | |
2075 | .enable_mask = BIT(0), | |
2076 | .hw.init = &(struct clk_init_data){ | |
2077 | .name = "mmss_mmssnoc_ahb_clk", | |
2078 | .parent_names = (const char *[]){ | |
2079 | "mmss_ahb_clk_src", | |
2080 | }, | |
2081 | .num_parents = 1, | |
2082 | .ops = &clk_branch2_ops, | |
2083 | .flags = CLK_IGNORE_UNUSED, | |
2084 | }, | |
2085 | }, | |
2086 | }; | |
2087 | ||
2088 | static struct clk_branch mmss_mmssnoc_bto_ahb_clk = { | |
2089 | .halt_reg = 0x5028, | |
2090 | .clkr = { | |
2091 | .enable_reg = 0x5028, | |
2092 | .enable_mask = BIT(0), | |
2093 | .hw.init = &(struct clk_init_data){ | |
2094 | .name = "mmss_mmssnoc_bto_ahb_clk", | |
2095 | .parent_names = (const char *[]){ | |
2096 | "mmss_ahb_clk_src", | |
2097 | }, | |
2098 | .num_parents = 1, | |
2099 | .ops = &clk_branch2_ops, | |
2100 | .flags = CLK_IGNORE_UNUSED, | |
2101 | }, | |
2102 | }, | |
2103 | }; | |
2104 | ||
2105 | static struct clk_branch mmss_mmssnoc_axi_clk = { | |
2106 | .halt_reg = 0x506c, | |
2107 | .clkr = { | |
2108 | .enable_reg = 0x506c, | |
2109 | .enable_mask = BIT(0), | |
2110 | .hw.init = &(struct clk_init_data){ | |
2111 | .name = "mmss_mmssnoc_axi_clk", | |
2112 | .parent_names = (const char *[]){ | |
2113 | "mmss_axi_clk_src", | |
2114 | }, | |
2115 | .num_parents = 1, | |
2116 | .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, | |
2117 | .ops = &clk_branch2_ops, | |
2118 | }, | |
2119 | }, | |
2120 | }; | |
2121 | ||
2122 | static struct clk_branch mmss_s0_axi_clk = { | |
2123 | .halt_reg = 0x5064, | |
2124 | .clkr = { | |
2125 | .enable_reg = 0x5064, | |
2126 | .enable_mask = BIT(0), | |
2127 | .hw.init = &(struct clk_init_data){ | |
2128 | .name = "mmss_s0_axi_clk", | |
2129 | .parent_names = (const char *[]){ | |
2130 | "mmss_axi_clk_src", | |
2131 | }, | |
2132 | .num_parents = 1, | |
2133 | .ops = &clk_branch2_ops, | |
2134 | .flags = CLK_IGNORE_UNUSED, | |
2135 | }, | |
2136 | }, | |
2137 | }; | |
2138 | ||
2139 | static struct clk_branch ocmemcx_ahb_clk = { | |
2140 | .halt_reg = 0x405c, | |
2141 | .clkr = { | |
2142 | .enable_reg = 0x405c, | |
2143 | .enable_mask = BIT(0), | |
2144 | .hw.init = &(struct clk_init_data){ | |
2145 | .name = "ocmemcx_ahb_clk", | |
2146 | .parent_names = (const char *[]){ | |
2147 | "mmss_ahb_clk_src", | |
2148 | }, | |
2149 | .num_parents = 1, | |
2150 | .ops = &clk_branch2_ops, | |
2151 | }, | |
2152 | }, | |
2153 | }; | |
2154 | ||
2155 | static struct clk_branch ocmemcx_ocmemnoc_clk = { | |
2156 | .halt_reg = 0x4058, | |
2157 | .clkr = { | |
2158 | .enable_reg = 0x4058, | |
2159 | .enable_mask = BIT(0), | |
2160 | .hw.init = &(struct clk_init_data){ | |
2161 | .name = "ocmemcx_ocmemnoc_clk", | |
2162 | .parent_names = (const char *[]){ | |
2163 | "ocmemnoc_clk_src", | |
2164 | }, | |
2165 | .num_parents = 1, | |
2166 | .flags = CLK_SET_RATE_PARENT, | |
2167 | .ops = &clk_branch2_ops, | |
2168 | }, | |
2169 | }, | |
2170 | }; | |
2171 | ||
2172 | static struct clk_branch oxili_ocmemgx_clk = { | |
2173 | .halt_reg = 0x402c, | |
2174 | .clkr = { | |
2175 | .enable_reg = 0x402c, | |
2176 | .enable_mask = BIT(0), | |
2177 | .hw.init = &(struct clk_init_data){ | |
2178 | .name = "oxili_ocmemgx_clk", | |
2179 | .parent_names = (const char *[]){ | |
2180 | "gfx3d_clk_src", | |
2181 | }, | |
2182 | .num_parents = 1, | |
2183 | .flags = CLK_SET_RATE_PARENT, | |
2184 | .ops = &clk_branch2_ops, | |
2185 | }, | |
2186 | }, | |
2187 | }; | |
2188 | ||
2189 | static struct clk_branch ocmemnoc_clk = { | |
2190 | .halt_reg = 0x50b4, | |
2191 | .clkr = { | |
2192 | .enable_reg = 0x50b4, | |
2193 | .enable_mask = BIT(0), | |
2194 | .hw.init = &(struct clk_init_data){ | |
2195 | .name = "ocmemnoc_clk", | |
2196 | .parent_names = (const char *[]){ | |
2197 | "ocmemnoc_clk_src", | |
2198 | }, | |
2199 | .num_parents = 1, | |
2200 | .flags = CLK_SET_RATE_PARENT, | |
2201 | .ops = &clk_branch2_ops, | |
2202 | }, | |
2203 | }, | |
2204 | }; | |
2205 | ||
2206 | static struct clk_branch oxili_gfx3d_clk = { | |
2207 | .halt_reg = 0x4028, | |
2208 | .clkr = { | |
2209 | .enable_reg = 0x4028, | |
2210 | .enable_mask = BIT(0), | |
2211 | .hw.init = &(struct clk_init_data){ | |
2212 | .name = "oxili_gfx3d_clk", | |
2213 | .parent_names = (const char *[]){ | |
2214 | "gfx3d_clk_src", | |
2215 | }, | |
2216 | .num_parents = 1, | |
2217 | .flags = CLK_SET_RATE_PARENT, | |
2218 | .ops = &clk_branch2_ops, | |
2219 | }, | |
2220 | }, | |
2221 | }; | |
2222 | ||
2223 | static struct clk_branch oxilicx_ahb_clk = { | |
2224 | .halt_reg = 0x403c, | |
2225 | .clkr = { | |
2226 | .enable_reg = 0x403c, | |
2227 | .enable_mask = BIT(0), | |
2228 | .hw.init = &(struct clk_init_data){ | |
2229 | .name = "oxilicx_ahb_clk", | |
2230 | .parent_names = (const char *[]){ | |
2231 | "mmss_ahb_clk_src", | |
2232 | }, | |
2233 | .num_parents = 1, | |
2234 | .ops = &clk_branch2_ops, | |
2235 | }, | |
2236 | }, | |
2237 | }; | |
2238 | ||
2239 | static struct clk_branch oxilicx_axi_clk = { | |
2240 | .halt_reg = 0x4038, | |
2241 | .clkr = { | |
2242 | .enable_reg = 0x4038, | |
2243 | .enable_mask = BIT(0), | |
2244 | .hw.init = &(struct clk_init_data){ | |
2245 | .name = "oxilicx_axi_clk", | |
2246 | .parent_names = (const char *[]){ | |
2247 | "mmss_axi_clk_src", | |
2248 | }, | |
2249 | .num_parents = 1, | |
2250 | .ops = &clk_branch2_ops, | |
2251 | }, | |
2252 | }, | |
2253 | }; | |
2254 | ||
2255 | static struct clk_branch venus0_ahb_clk = { | |
2256 | .halt_reg = 0x1030, | |
2257 | .clkr = { | |
2258 | .enable_reg = 0x1030, | |
2259 | .enable_mask = BIT(0), | |
2260 | .hw.init = &(struct clk_init_data){ | |
2261 | .name = "venus0_ahb_clk", | |
2262 | .parent_names = (const char *[]){ | |
2263 | "mmss_ahb_clk_src", | |
2264 | }, | |
2265 | .num_parents = 1, | |
2266 | .ops = &clk_branch2_ops, | |
2267 | }, | |
2268 | }, | |
2269 | }; | |
2270 | ||
2271 | static struct clk_branch venus0_axi_clk = { | |
2272 | .halt_reg = 0x1034, | |
2273 | .clkr = { | |
2274 | .enable_reg = 0x1034, | |
2275 | .enable_mask = BIT(0), | |
2276 | .hw.init = &(struct clk_init_data){ | |
2277 | .name = "venus0_axi_clk", | |
2278 | .parent_names = (const char *[]){ | |
2279 | "mmss_axi_clk_src", | |
2280 | }, | |
2281 | .num_parents = 1, | |
2282 | .ops = &clk_branch2_ops, | |
2283 | }, | |
2284 | }, | |
2285 | }; | |
2286 | ||
2287 | static struct clk_branch venus0_ocmemnoc_clk = { | |
2288 | .halt_reg = 0x1038, | |
2289 | .clkr = { | |
2290 | .enable_reg = 0x1038, | |
2291 | .enable_mask = BIT(0), | |
2292 | .hw.init = &(struct clk_init_data){ | |
2293 | .name = "venus0_ocmemnoc_clk", | |
2294 | .parent_names = (const char *[]){ | |
2295 | "ocmemnoc_clk_src", | |
2296 | }, | |
2297 | .num_parents = 1, | |
2298 | .flags = CLK_SET_RATE_PARENT, | |
2299 | .ops = &clk_branch2_ops, | |
2300 | }, | |
2301 | }, | |
2302 | }; | |
2303 | ||
2304 | static struct clk_branch venus0_vcodec0_clk = { | |
2305 | .halt_reg = 0x1028, | |
2306 | .clkr = { | |
2307 | .enable_reg = 0x1028, | |
2308 | .enable_mask = BIT(0), | |
2309 | .hw.init = &(struct clk_init_data){ | |
2310 | .name = "venus0_vcodec0_clk", | |
2311 | .parent_names = (const char *[]){ | |
2312 | "vcodec0_clk_src", | |
2313 | }, | |
2314 | .num_parents = 1, | |
2315 | .flags = CLK_SET_RATE_PARENT, | |
2316 | .ops = &clk_branch2_ops, | |
2317 | }, | |
2318 | }, | |
2319 | }; | |
2320 | ||
2321 | static const struct pll_config mmpll1_config = { | |
2322 | .l = 60, | |
2323 | .m = 25, | |
2324 | .n = 32, | |
2325 | .vco_val = 0x0, | |
2326 | .vco_mask = 0x3 << 20, | |
2327 | .pre_div_val = 0x0, | |
437ae6a1 | 2328 | .pre_div_mask = 0x7 << 12, |
d8b21201 SB |
2329 | .post_div_val = 0x0, |
2330 | .post_div_mask = 0x3 << 8, | |
2331 | .mn_ena_mask = BIT(24), | |
2332 | .main_output_mask = BIT(0), | |
2333 | }; | |
2334 | ||
2335 | static struct pll_config mmpll3_config = { | |
2336 | .l = 48, | |
2337 | .m = 7, | |
2338 | .n = 16, | |
2339 | .vco_val = 0x0, | |
2340 | .vco_mask = 0x3 << 20, | |
2341 | .pre_div_val = 0x0, | |
437ae6a1 | 2342 | .pre_div_mask = 0x7 << 12, |
d8b21201 SB |
2343 | .post_div_val = 0x0, |
2344 | .post_div_mask = 0x3 << 8, | |
2345 | .mn_ena_mask = BIT(24), | |
2346 | .main_output_mask = BIT(0), | |
2347 | .aux_output_mask = BIT(1), | |
2348 | }; | |
2349 | ||
2350 | static struct clk_regmap *mmcc_msm8974_clocks[] = { | |
2351 | [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr, | |
2352 | [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr, | |
2353 | [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr, | |
2354 | [MMPLL0] = &mmpll0.clkr, | |
2355 | [MMPLL0_VOTE] = &mmpll0_vote, | |
2356 | [MMPLL1] = &mmpll1.clkr, | |
2357 | [MMPLL1_VOTE] = &mmpll1_vote, | |
2358 | [MMPLL2] = &mmpll2.clkr, | |
2359 | [MMPLL3] = &mmpll3.clkr, | |
2360 | [CSI0_CLK_SRC] = &csi0_clk_src.clkr, | |
2361 | [CSI1_CLK_SRC] = &csi1_clk_src.clkr, | |
2362 | [CSI2_CLK_SRC] = &csi2_clk_src.clkr, | |
2363 | [CSI3_CLK_SRC] = &csi3_clk_src.clkr, | |
2364 | [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, | |
2365 | [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, | |
2366 | [MDP_CLK_SRC] = &mdp_clk_src.clkr, | |
2367 | [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, | |
2368 | [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, | |
2369 | [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr, | |
2370 | [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, | |
2371 | [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, | |
2372 | [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, | |
2373 | [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, | |
2374 | [CCI_CLK_SRC] = &cci_clk_src.clkr, | |
2375 | [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, | |
2376 | [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, | |
2377 | [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, | |
2378 | [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, | |
2379 | [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, | |
2380 | [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, | |
2381 | [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, | |
2382 | [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, | |
2383 | [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, | |
2384 | [CPP_CLK_SRC] = &cpp_clk_src.clkr, | |
2385 | [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, | |
2386 | [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, | |
2387 | [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr, | |
2388 | [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr, | |
2389 | [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr, | |
2390 | [ESC0_CLK_SRC] = &esc0_clk_src.clkr, | |
2391 | [ESC1_CLK_SRC] = &esc1_clk_src.clkr, | |
2392 | [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr, | |
2393 | [HDMI_CLK_SRC] = &hdmi_clk_src.clkr, | |
2394 | [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, | |
2395 | [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr, | |
2396 | [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr, | |
2397 | [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr, | |
2398 | [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr, | |
2399 | [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr, | |
2400 | [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr, | |
2401 | [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr, | |
2402 | [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr, | |
2403 | [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr, | |
2404 | [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr, | |
2405 | [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr, | |
2406 | [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr, | |
2407 | [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr, | |
2408 | [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr, | |
2409 | [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr, | |
2410 | [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr, | |
2411 | [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr, | |
2412 | [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr, | |
2413 | [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr, | |
2414 | [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr, | |
2415 | [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr, | |
2416 | [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr, | |
2417 | [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr, | |
2418 | [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr, | |
2419 | [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr, | |
2420 | [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr, | |
2421 | [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr, | |
2422 | [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr, | |
2423 | [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr, | |
2424 | [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr, | |
2425 | [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr, | |
2426 | [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr, | |
2427 | [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr, | |
2428 | [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr, | |
2429 | [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr, | |
2430 | [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr, | |
2431 | [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr, | |
2432 | [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr, | |
2433 | [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr, | |
2434 | [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr, | |
2435 | [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr, | |
2436 | [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr, | |
2437 | [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr, | |
2438 | [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr, | |
2439 | [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr, | |
2440 | [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr, | |
2441 | [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr, | |
2442 | [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr, | |
2443 | [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr, | |
2444 | [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr, | |
2445 | [MDSS_AXI_CLK] = &mdss_axi_clk.clkr, | |
2446 | [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr, | |
2447 | [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr, | |
2448 | [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr, | |
2449 | [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr, | |
2450 | [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr, | |
2451 | [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr, | |
2452 | [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr, | |
2453 | [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr, | |
2454 | [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr, | |
2455 | [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr, | |
2456 | [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr, | |
2457 | [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr, | |
2458 | [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr, | |
2459 | [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr, | |
2460 | [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr, | |
2461 | [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, | |
2462 | [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr, | |
2463 | [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr, | |
2464 | [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr, | |
2465 | [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr, | |
2466 | [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr, | |
2467 | [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr, | |
2468 | [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr, | |
2469 | [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr, | |
2470 | [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr, | |
2471 | [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr, | |
2472 | [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr, | |
2473 | [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr, | |
2474 | [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr, | |
2475 | [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr, | |
2476 | [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr, | |
2477 | }; | |
2478 | ||
2479 | static const struct qcom_reset_map mmcc_msm8974_resets[] = { | |
2480 | [SPDM_RESET] = { 0x0200 }, | |
2481 | [SPDM_RM_RESET] = { 0x0300 }, | |
2482 | [VENUS0_RESET] = { 0x1020 }, | |
2483 | [MDSS_RESET] = { 0x2300 }, | |
2484 | [CAMSS_PHY0_RESET] = { 0x3020 }, | |
2485 | [CAMSS_PHY1_RESET] = { 0x3050 }, | |
2486 | [CAMSS_PHY2_RESET] = { 0x3080 }, | |
2487 | [CAMSS_CSI0_RESET] = { 0x30b0 }, | |
2488 | [CAMSS_CSI0PHY_RESET] = { 0x30c0 }, | |
2489 | [CAMSS_CSI0RDI_RESET] = { 0x30d0 }, | |
2490 | [CAMSS_CSI0PIX_RESET] = { 0x30e0 }, | |
2491 | [CAMSS_CSI1_RESET] = { 0x3120 }, | |
2492 | [CAMSS_CSI1PHY_RESET] = { 0x3130 }, | |
2493 | [CAMSS_CSI1RDI_RESET] = { 0x3140 }, | |
2494 | [CAMSS_CSI1PIX_RESET] = { 0x3150 }, | |
2495 | [CAMSS_CSI2_RESET] = { 0x3180 }, | |
2496 | [CAMSS_CSI2PHY_RESET] = { 0x3190 }, | |
2497 | [CAMSS_CSI2RDI_RESET] = { 0x31a0 }, | |
2498 | [CAMSS_CSI2PIX_RESET] = { 0x31b0 }, | |
2499 | [CAMSS_CSI3_RESET] = { 0x31e0 }, | |
2500 | [CAMSS_CSI3PHY_RESET] = { 0x31f0 }, | |
2501 | [CAMSS_CSI3RDI_RESET] = { 0x3200 }, | |
2502 | [CAMSS_CSI3PIX_RESET] = { 0x3210 }, | |
2503 | [CAMSS_ISPIF_RESET] = { 0x3220 }, | |
2504 | [CAMSS_CCI_RESET] = { 0x3340 }, | |
2505 | [CAMSS_MCLK0_RESET] = { 0x3380 }, | |
2506 | [CAMSS_MCLK1_RESET] = { 0x33b0 }, | |
2507 | [CAMSS_MCLK2_RESET] = { 0x33e0 }, | |
2508 | [CAMSS_MCLK3_RESET] = { 0x3410 }, | |
2509 | [CAMSS_GP0_RESET] = { 0x3440 }, | |
2510 | [CAMSS_GP1_RESET] = { 0x3470 }, | |
2511 | [CAMSS_TOP_RESET] = { 0x3480 }, | |
2512 | [CAMSS_MICRO_RESET] = { 0x3490 }, | |
2513 | [CAMSS_JPEG_RESET] = { 0x35a0 }, | |
2514 | [CAMSS_VFE_RESET] = { 0x36a0 }, | |
2515 | [CAMSS_CSI_VFE0_RESET] = { 0x3700 }, | |
2516 | [CAMSS_CSI_VFE1_RESET] = { 0x3710 }, | |
2517 | [OXILI_RESET] = { 0x4020 }, | |
2518 | [OXILICX_RESET] = { 0x4030 }, | |
2519 | [OCMEMCX_RESET] = { 0x4050 }, | |
2520 | [MMSS_RBCRP_RESET] = { 0x4080 }, | |
2521 | [MMSSNOCAHB_RESET] = { 0x5020 }, | |
2522 | [MMSSNOCAXI_RESET] = { 0x5060 }, | |
2523 | [OCMEMNOC_RESET] = { 0x50b0 }, | |
2524 | }; | |
2525 | ||
2526 | static const struct regmap_config mmcc_msm8974_regmap_config = { | |
2527 | .reg_bits = 32, | |
2528 | .reg_stride = 4, | |
2529 | .val_bits = 32, | |
2530 | .max_register = 0x5104, | |
2531 | .fast_io = true, | |
2532 | }; | |
2533 | ||
49fc825f SB |
2534 | static const struct qcom_cc_desc mmcc_msm8974_desc = { |
2535 | .config = &mmcc_msm8974_regmap_config, | |
2536 | .clks = mmcc_msm8974_clocks, | |
2537 | .num_clks = ARRAY_SIZE(mmcc_msm8974_clocks), | |
2538 | .resets = mmcc_msm8974_resets, | |
2539 | .num_resets = ARRAY_SIZE(mmcc_msm8974_resets), | |
2540 | }; | |
2541 | ||
d8b21201 SB |
2542 | static const struct of_device_id mmcc_msm8974_match_table[] = { |
2543 | { .compatible = "qcom,mmcc-msm8974" }, | |
2544 | { } | |
2545 | }; | |
2546 | MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table); | |
2547 | ||
d8b21201 SB |
2548 | static int mmcc_msm8974_probe(struct platform_device *pdev) |
2549 | { | |
49fc825f | 2550 | int ret; |
d8b21201 | 2551 | struct regmap *regmap; |
d8b21201 | 2552 | |
49fc825f | 2553 | ret = qcom_cc_probe(pdev, &mmcc_msm8974_desc); |
d8b21201 SB |
2554 | if (ret) |
2555 | return ret; | |
2556 | ||
49fc825f SB |
2557 | regmap = dev_get_regmap(&pdev->dev, NULL); |
2558 | clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true); | |
2559 | clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false); | |
d8b21201 | 2560 | |
49fc825f | 2561 | return 0; |
d8b21201 SB |
2562 | } |
2563 | ||
2564 | static int mmcc_msm8974_remove(struct platform_device *pdev) | |
2565 | { | |
49fc825f | 2566 | qcom_cc_remove(pdev); |
d8b21201 SB |
2567 | return 0; |
2568 | } | |
2569 | ||
2570 | static struct platform_driver mmcc_msm8974_driver = { | |
2571 | .probe = mmcc_msm8974_probe, | |
2572 | .remove = mmcc_msm8974_remove, | |
2573 | .driver = { | |
2574 | .name = "mmcc-msm8974", | |
2575 | .owner = THIS_MODULE, | |
2576 | .of_match_table = mmcc_msm8974_match_table, | |
2577 | }, | |
2578 | }; | |
2579 | module_platform_driver(mmcc_msm8974_driver); | |
2580 | ||
2581 | MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver"); | |
2582 | MODULE_LICENSE("GPL v2"); | |
2583 | MODULE_ALIAS("platform:mmcc-msm8974"); |