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Commit | Line | Data |
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80978a4b GU |
1 | config CLK_RENESAS |
2 | bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS | |
3 | default y if ARCH_RENESAS | |
4 | select CLK_EMEV2 if ARCH_EMEV2 | |
5 | select CLK_RZA1 if ARCH_R7S72100 | |
6 | select CLK_R8A73A4 if ARCH_R8A73A4 | |
7 | select CLK_R8A7740 if ARCH_R8A7740 | |
8 | select CLK_R8A7743 if ARCH_R8A7743 | |
9 | select CLK_R8A7745 if ARCH_R8A7745 | |
10 | select CLK_R8A7778 if ARCH_R8A7778 | |
11 | select CLK_R8A7779 if ARCH_R8A7779 | |
12 | select CLK_R8A7790 if ARCH_R8A7790 | |
13 | select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793 | |
14 | select CLK_R8A7792 if ARCH_R8A7792 | |
15 | select CLK_R8A7794 if ARCH_R8A7794 | |
16 | select CLK_R8A7795 if ARCH_R8A7795 | |
17 | select CLK_R8A7796 if ARCH_R8A7796 | |
18 | select CLK_SH73A0 if ARCH_SH73A0 | |
19 | ||
20 | if CLK_RENESAS | |
21 | ||
d4e59f10 GU |
22 | config CLK_RENESAS_LEGACY |
23 | bool "Legacy DT clock support" | |
2d75588a | 24 | depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792 || CLK_R8A7794 |
d4e59f10 GU |
25 | default y |
26 | help | |
27 | Enable backward compatibility with old device trees describing a | |
28 | hierarchical representation of the various CPG and MSTP clocks. | |
29 | ||
30 | Say Y if you want your kernel to work with old DTBs. | |
31 | ||
80978a4b GU |
32 | # SoC |
33 | config CLK_EMEV2 | |
34 | bool "Emma Mobile EV2 clock support" if COMPILE_TEST | |
35 | ||
36 | config CLK_RZA1 | |
37 | bool | |
38 | select CLK_RENESAS_CPG_MSTP | |
39 | ||
40 | config CLK_R8A73A4 | |
41 | bool | |
42 | select CLK_RENESAS_CPG_MSTP | |
43 | select CLK_RENESAS_DIV6 | |
44 | ||
45 | config CLK_R8A7740 | |
46 | bool | |
47 | select CLK_RENESAS_CPG_MSTP | |
48 | select CLK_RENESAS_DIV6 | |
49 | ||
50 | config CLK_R8A7743 | |
51 | bool | |
52 | select CLK_RCAR_GEN2_CPG | |
53 | ||
54 | config CLK_R8A7745 | |
55 | bool | |
56 | select CLK_RCAR_GEN2_CPG | |
57 | ||
58 | config CLK_R8A7778 | |
59 | bool | |
60 | select CLK_RENESAS_CPG_MSTP | |
61 | ||
62 | config CLK_R8A7779 | |
63 | bool | |
64 | select CLK_RENESAS_CPG_MSTP | |
65 | ||
66 | config CLK_R8A7790 | |
67 | bool | |
d4e59f10 GU |
68 | select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY |
69 | select CLK_RCAR_GEN2_CPG | |
80978a4b GU |
70 | select CLK_RENESAS_DIV6 |
71 | ||
72 | config CLK_R8A7791 | |
73 | bool | |
6449ab81 GU |
74 | select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY |
75 | select CLK_RCAR_GEN2_CPG | |
80978a4b GU |
76 | select CLK_RENESAS_DIV6 |
77 | ||
78 | config CLK_R8A7792 | |
79 | bool | |
fd3c2f38 GU |
80 | select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY |
81 | select CLK_RCAR_GEN2_CPG | |
80978a4b GU |
82 | |
83 | config CLK_R8A7794 | |
84 | bool | |
2d75588a GU |
85 | select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY |
86 | select CLK_RCAR_GEN2_CPG | |
80978a4b GU |
87 | select CLK_RENESAS_DIV6 |
88 | ||
89 | config CLK_R8A7795 | |
90 | bool | |
91 | select CLK_RCAR_GEN3_CPG | |
92 | ||
93 | config CLK_R8A7796 | |
94 | bool | |
95 | select CLK_RCAR_GEN3_CPG | |
96 | ||
97 | config CLK_SH73A0 | |
98 | bool | |
99 | select CLK_RENESAS_CPG_MSTP | |
100 | select CLK_RENESAS_DIV6 | |
101 | ||
102 | ||
103 | # Family | |
104 | config CLK_RCAR_GEN2 | |
105 | bool | |
106 | select CLK_RENESAS_CPG_MSTP | |
107 | select CLK_RENESAS_DIV6 | |
108 | ||
109 | config CLK_RCAR_GEN2_CPG | |
110 | bool | |
111 | select CLK_RENESAS_CPG_MSSR | |
112 | ||
113 | config CLK_RCAR_GEN3_CPG | |
114 | bool | |
115 | select CLK_RENESAS_CPG_MSSR | |
116 | ||
117 | ||
118 | # Generic | |
a5bd7f7a GU |
119 | config CLK_RENESAS_CPG_MSSR |
120 | bool | |
80978a4b | 121 | select CLK_RENESAS_DIV6 |
a5bd7f7a GU |
122 | |
123 | config CLK_RENESAS_CPG_MSTP | |
124 | bool | |
80978a4b GU |
125 | |
126 | config CLK_RENESAS_DIV6 | |
127 | bool "DIV6 clock support" if COMPILE_TEST | |
128 | ||
129 | endif # CLK_RENESAS |