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10cdfe9f LP |
1 | /* |
2 | * rcar_gen2 Core CPG Clocks | |
3 | * | |
4 | * Copyright (C) 2013 Ideas On Board SPRL | |
5 | * | |
6 | * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | */ | |
12 | ||
13 | #include <linux/clk-provider.h> | |
09c32427 | 14 | #include <linux/clk/renesas.h> |
10cdfe9f LP |
15 | #include <linux/init.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/math64.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/of_address.h> | |
5a1cfafa | 20 | #include <linux/slab.h> |
10cdfe9f | 21 | #include <linux/spinlock.h> |
f84c9c3c | 22 | #include <linux/soc/renesas/rcar-rst.h> |
10cdfe9f LP |
23 | |
24 | struct rcar_gen2_cpg { | |
25 | struct clk_onecell_data data; | |
26 | spinlock_t lock; | |
27 | void __iomem *reg; | |
28 | }; | |
29 | ||
d9120198 BC |
30 | #define CPG_FRQCRB 0x00000004 |
31 | #define CPG_FRQCRB_KICK BIT(31) | |
10cdfe9f LP |
32 | #define CPG_SDCKCR 0x00000074 |
33 | #define CPG_PLL0CR 0x000000d8 | |
34 | #define CPG_FRQCRC 0x000000e0 | |
35 | #define CPG_FRQCRC_ZFC_MASK (0x1f << 8) | |
36 | #define CPG_FRQCRC_ZFC_SHIFT 8 | |
14842761 | 37 | #define CPG_ADSPCKCR 0x0000025c |
90cf0e2b | 38 | #define CPG_RCANCKCR 0x00000270 |
10cdfe9f LP |
39 | |
40 | /* ----------------------------------------------------------------------------- | |
41 | * Z Clock | |
42 | * | |
43 | * Traits of this clock: | |
44 | * prepare - clk_prepare only ensures that parents are prepared | |
45 | * enable - clk_enable only ensures that parents are enabled | |
46 | * rate - rate is adjustable. clk->rate = parent->rate * mult / 32 | |
47 | * parent - fixed parent. No clk_set_parent support | |
48 | */ | |
49 | ||
50 | struct cpg_z_clk { | |
51 | struct clk_hw hw; | |
52 | void __iomem *reg; | |
d9120198 | 53 | void __iomem *kick_reg; |
10cdfe9f LP |
54 | }; |
55 | ||
56 | #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) | |
57 | ||
58 | static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, | |
59 | unsigned long parent_rate) | |
60 | { | |
61 | struct cpg_z_clk *zclk = to_z_clk(hw); | |
62 | unsigned int mult; | |
63 | unsigned int val; | |
64 | ||
65 | val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) | |
66 | >> CPG_FRQCRC_ZFC_SHIFT; | |
67 | mult = 32 - val; | |
68 | ||
69 | return div_u64((u64)parent_rate * mult, 32); | |
70 | } | |
71 | ||
72 | static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate, | |
73 | unsigned long *parent_rate) | |
74 | { | |
75 | unsigned long prate = *parent_rate; | |
76 | unsigned int mult; | |
77 | ||
78 | if (!prate) | |
79 | prate = 1; | |
80 | ||
81 | mult = div_u64((u64)rate * 32, prate); | |
82 | mult = clamp(mult, 1U, 32U); | |
83 | ||
84 | return *parent_rate / 32 * mult; | |
85 | } | |
86 | ||
87 | static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, | |
88 | unsigned long parent_rate) | |
89 | { | |
90 | struct cpg_z_clk *zclk = to_z_clk(hw); | |
91 | unsigned int mult; | |
d9120198 BC |
92 | u32 val, kick; |
93 | unsigned int i; | |
10cdfe9f LP |
94 | |
95 | mult = div_u64((u64)rate * 32, parent_rate); | |
96 | mult = clamp(mult, 1U, 32U); | |
97 | ||
d9120198 BC |
98 | if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK) |
99 | return -EBUSY; | |
100 | ||
10cdfe9f LP |
101 | val = clk_readl(zclk->reg); |
102 | val &= ~CPG_FRQCRC_ZFC_MASK; | |
103 | val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT; | |
104 | clk_writel(val, zclk->reg); | |
105 | ||
d9120198 BC |
106 | /* |
107 | * Set KICK bit in FRQCRB to update hardware setting and wait for | |
108 | * clock change completion. | |
109 | */ | |
110 | kick = clk_readl(zclk->kick_reg); | |
111 | kick |= CPG_FRQCRB_KICK; | |
112 | clk_writel(kick, zclk->kick_reg); | |
113 | ||
114 | /* | |
115 | * Note: There is no HW information about the worst case latency. | |
116 | * | |
117 | * Using experimental measurements, it seems that no more than | |
118 | * ~10 iterations are needed, independently of the CPU rate. | |
96cb6933 | 119 | * Since this value might be dependent on external xtal rate, pll1 |
d9120198 BC |
120 | * rate or even the other emulation clocks rate, use 1000 as a |
121 | * "super" safe value. | |
122 | */ | |
123 | for (i = 1000; i; i--) { | |
124 | if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) | |
125 | return 0; | |
126 | ||
127 | cpu_relax(); | |
128 | } | |
129 | ||
130 | return -ETIMEDOUT; | |
10cdfe9f LP |
131 | } |
132 | ||
133 | static const struct clk_ops cpg_z_clk_ops = { | |
134 | .recalc_rate = cpg_z_clk_recalc_rate, | |
135 | .round_rate = cpg_z_clk_round_rate, | |
136 | .set_rate = cpg_z_clk_set_rate, | |
137 | }; | |
138 | ||
139 | static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg) | |
140 | { | |
141 | static const char *parent_name = "pll0"; | |
142 | struct clk_init_data init; | |
143 | struct cpg_z_clk *zclk; | |
144 | struct clk *clk; | |
145 | ||
146 | zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); | |
147 | if (!zclk) | |
148 | return ERR_PTR(-ENOMEM); | |
149 | ||
150 | init.name = "z"; | |
151 | init.ops = &cpg_z_clk_ops; | |
152 | init.flags = 0; | |
153 | init.parent_names = &parent_name; | |
154 | init.num_parents = 1; | |
155 | ||
156 | zclk->reg = cpg->reg + CPG_FRQCRC; | |
d9120198 | 157 | zclk->kick_reg = cpg->reg + CPG_FRQCRB; |
10cdfe9f LP |
158 | zclk->hw.init = &init; |
159 | ||
160 | clk = clk_register(NULL, &zclk->hw); | |
161 | if (IS_ERR(clk)) | |
162 | kfree(zclk); | |
163 | ||
164 | return clk; | |
165 | } | |
166 | ||
90cf0e2b SS |
167 | static struct clk * __init cpg_rcan_clk_register(struct rcar_gen2_cpg *cpg, |
168 | struct device_node *np) | |
169 | { | |
170 | const char *parent_name = of_clk_get_parent_name(np, 1); | |
171 | struct clk_fixed_factor *fixed; | |
172 | struct clk_gate *gate; | |
173 | struct clk *clk; | |
174 | ||
175 | fixed = kzalloc(sizeof(*fixed), GFP_KERNEL); | |
176 | if (!fixed) | |
177 | return ERR_PTR(-ENOMEM); | |
178 | ||
179 | fixed->mult = 1; | |
180 | fixed->div = 6; | |
181 | ||
182 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); | |
183 | if (!gate) { | |
184 | kfree(fixed); | |
185 | return ERR_PTR(-ENOMEM); | |
186 | } | |
187 | ||
188 | gate->reg = cpg->reg + CPG_RCANCKCR; | |
189 | gate->bit_idx = 8; | |
190 | gate->flags = CLK_GATE_SET_TO_DISABLE; | |
191 | gate->lock = &cpg->lock; | |
192 | ||
193 | clk = clk_register_composite(NULL, "rcan", &parent_name, 1, NULL, NULL, | |
194 | &fixed->hw, &clk_fixed_factor_ops, | |
195 | &gate->hw, &clk_gate_ops, 0); | |
196 | if (IS_ERR(clk)) { | |
197 | kfree(gate); | |
198 | kfree(fixed); | |
199 | } | |
200 | ||
201 | return clk; | |
202 | } | |
203 | ||
14842761 SS |
204 | /* ADSP divisors */ |
205 | static const struct clk_div_table cpg_adsp_div_table[] = { | |
206 | { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, | |
207 | { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 }, | |
208 | { 10, 36 }, { 11, 48 }, { 0, 0 }, | |
209 | }; | |
210 | ||
211 | static struct clk * __init cpg_adsp_clk_register(struct rcar_gen2_cpg *cpg) | |
212 | { | |
213 | const char *parent_name = "pll1"; | |
214 | struct clk_divider *div; | |
215 | struct clk_gate *gate; | |
216 | struct clk *clk; | |
217 | ||
218 | div = kzalloc(sizeof(*div), GFP_KERNEL); | |
219 | if (!div) | |
220 | return ERR_PTR(-ENOMEM); | |
221 | ||
222 | div->reg = cpg->reg + CPG_ADSPCKCR; | |
223 | div->width = 4; | |
224 | div->table = cpg_adsp_div_table; | |
225 | div->lock = &cpg->lock; | |
226 | ||
227 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); | |
228 | if (!gate) { | |
229 | kfree(div); | |
230 | return ERR_PTR(-ENOMEM); | |
231 | } | |
232 | ||
233 | gate->reg = cpg->reg + CPG_ADSPCKCR; | |
234 | gate->bit_idx = 8; | |
235 | gate->flags = CLK_GATE_SET_TO_DISABLE; | |
236 | gate->lock = &cpg->lock; | |
237 | ||
238 | clk = clk_register_composite(NULL, "adsp", &parent_name, 1, NULL, NULL, | |
239 | &div->hw, &clk_divider_ops, | |
240 | &gate->hw, &clk_gate_ops, 0); | |
241 | if (IS_ERR(clk)) { | |
242 | kfree(gate); | |
243 | kfree(div); | |
244 | } | |
245 | ||
246 | return clk; | |
247 | } | |
248 | ||
10cdfe9f LP |
249 | /* ----------------------------------------------------------------------------- |
250 | * CPG Clock Data | |
251 | */ | |
252 | ||
253 | /* | |
254 | * MD EXTAL PLL0 PLL1 PLL3 | |
255 | * 14 13 19 (MHz) *1 *1 | |
256 | *--------------------------------------------------- | |
257 | * 0 0 0 15 x 1 x172/2 x208/2 x106 | |
258 | * 0 0 1 15 x 1 x172/2 x208/2 x88 | |
259 | * 0 1 0 20 x 1 x130/2 x156/2 x80 | |
260 | * 0 1 1 20 x 1 x130/2 x156/2 x66 | |
261 | * 1 0 0 26 / 2 x200/2 x240/2 x122 | |
262 | * 1 0 1 26 / 2 x200/2 x240/2 x102 | |
263 | * 1 1 0 30 / 2 x172/2 x208/2 x106 | |
264 | * 1 1 1 30 / 2 x172/2 x208/2 x88 | |
265 | * | |
96cb6933 | 266 | * *1 : Table 7.6 indicates VCO output (PLLx = VCO/2) |
10cdfe9f LP |
267 | */ |
268 | #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ | |
269 | (((md) & BIT(13)) >> 12) | \ | |
270 | (((md) & BIT(19)) >> 19)) | |
271 | struct cpg_pll_config { | |
272 | unsigned int extal_div; | |
273 | unsigned int pll1_mult; | |
274 | unsigned int pll3_mult; | |
b7c563c4 | 275 | unsigned int pll0_mult; /* For R-Car V2H and E2 only */ |
10cdfe9f LP |
276 | }; |
277 | ||
278 | static const struct cpg_pll_config cpg_pll_configs[8] __initconst = { | |
b7c563c4 GU |
279 | { 1, 208, 106, 200 }, { 1, 208, 88, 200 }, |
280 | { 1, 156, 80, 150 }, { 1, 156, 66, 150 }, | |
281 | { 2, 240, 122, 230 }, { 2, 240, 102, 230 }, | |
282 | { 2, 208, 106, 200 }, { 2, 208, 88, 200 }, | |
10cdfe9f LP |
283 | }; |
284 | ||
285 | /* SDHI divisors */ | |
286 | static const struct clk_div_table cpg_sdh_div_table[] = { | |
287 | { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, | |
288 | { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, | |
289 | { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 }, | |
290 | }; | |
291 | ||
292 | static const struct clk_div_table cpg_sd01_div_table[] = { | |
4abe2408 | 293 | { 4, 8 }, |
10cdfe9f LP |
294 | { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 }, |
295 | { 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 }, | |
296 | }; | |
297 | ||
298 | /* ----------------------------------------------------------------------------- | |
299 | * Initialization | |
300 | */ | |
301 | ||
302 | static u32 cpg_mode __initdata; | |
303 | ||
b7c563c4 GU |
304 | static const char * const pll0_mult_match[] = { |
305 | "renesas,r8a7792-cpg-clocks", | |
306 | "renesas,r8a7794-cpg-clocks", | |
307 | NULL | |
308 | }; | |
309 | ||
10cdfe9f LP |
310 | static struct clk * __init |
311 | rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg, | |
312 | const struct cpg_pll_config *config, | |
313 | const char *name) | |
314 | { | |
315 | const struct clk_div_table *table = NULL; | |
995a9190 | 316 | const char *parent_name; |
10cdfe9f LP |
317 | unsigned int shift; |
318 | unsigned int mult = 1; | |
319 | unsigned int div = 1; | |
320 | ||
321 | if (!strcmp(name, "main")) { | |
322 | parent_name = of_clk_get_parent_name(np, 0); | |
323 | div = config->extal_div; | |
324 | } else if (!strcmp(name, "pll0")) { | |
325 | /* PLL0 is a configurable multiplier clock. Register it as a | |
326 | * fixed factor clock for now as there's no generic multiplier | |
327 | * clock implementation and we currently have no need to change | |
328 | * the multiplier value. | |
329 | */ | |
b7c563c4 GU |
330 | if (of_device_compatible_match(np, pll0_mult_match)) { |
331 | /* R-Car V2H and E2 do not have PLL0CR */ | |
332 | mult = config->pll0_mult; | |
333 | div = 3; | |
334 | } else { | |
335 | u32 value = clk_readl(cpg->reg + CPG_PLL0CR); | |
336 | mult = ((value >> 24) & ((1 << 7) - 1)) + 1; | |
337 | } | |
995a9190 | 338 | parent_name = "main"; |
10cdfe9f | 339 | } else if (!strcmp(name, "pll1")) { |
995a9190 | 340 | parent_name = "main"; |
10cdfe9f LP |
341 | mult = config->pll1_mult / 2; |
342 | } else if (!strcmp(name, "pll3")) { | |
995a9190 | 343 | parent_name = "main"; |
10cdfe9f LP |
344 | mult = config->pll3_mult; |
345 | } else if (!strcmp(name, "lb")) { | |
365b0186 | 346 | parent_name = "pll1"; |
10cdfe9f LP |
347 | div = cpg_mode & BIT(18) ? 36 : 24; |
348 | } else if (!strcmp(name, "qspi")) { | |
995a9190 | 349 | parent_name = "pll1_div2"; |
10cdfe9f | 350 | div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) |
8510e726 | 351 | ? 8 : 10; |
10cdfe9f | 352 | } else if (!strcmp(name, "sdh")) { |
365b0186 | 353 | parent_name = "pll1"; |
10cdfe9f LP |
354 | table = cpg_sdh_div_table; |
355 | shift = 8; | |
356 | } else if (!strcmp(name, "sd0")) { | |
365b0186 | 357 | parent_name = "pll1"; |
10cdfe9f LP |
358 | table = cpg_sd01_div_table; |
359 | shift = 4; | |
360 | } else if (!strcmp(name, "sd1")) { | |
365b0186 | 361 | parent_name = "pll1"; |
10cdfe9f LP |
362 | table = cpg_sd01_div_table; |
363 | shift = 0; | |
364 | } else if (!strcmp(name, "z")) { | |
365 | return cpg_z_clk_register(cpg); | |
90cf0e2b SS |
366 | } else if (!strcmp(name, "rcan")) { |
367 | return cpg_rcan_clk_register(cpg, np); | |
14842761 SS |
368 | } else if (!strcmp(name, "adsp")) { |
369 | return cpg_adsp_clk_register(cpg); | |
10cdfe9f LP |
370 | } else { |
371 | return ERR_PTR(-EINVAL); | |
372 | } | |
373 | ||
374 | if (!table) | |
375 | return clk_register_fixed_factor(NULL, name, parent_name, 0, | |
376 | mult, div); | |
377 | else | |
378 | return clk_register_divider_table(NULL, name, parent_name, 0, | |
379 | cpg->reg + CPG_SDCKCR, shift, | |
380 | 4, 0, table, &cpg->lock); | |
381 | } | |
382 | ||
f84c9c3c GU |
383 | /* |
384 | * Reset register definitions. | |
385 | */ | |
386 | #define MODEMR 0xe6160060 | |
387 | ||
388 | static u32 __init rcar_gen2_read_mode_pins(void) | |
389 | { | |
390 | void __iomem *modemr = ioremap_nocache(MODEMR, 4); | |
391 | u32 mode; | |
392 | ||
393 | BUG_ON(!modemr); | |
394 | mode = ioread32(modemr); | |
395 | iounmap(modemr); | |
396 | ||
397 | return mode; | |
398 | } | |
399 | ||
10cdfe9f LP |
400 | static void __init rcar_gen2_cpg_clocks_init(struct device_node *np) |
401 | { | |
402 | const struct cpg_pll_config *config; | |
403 | struct rcar_gen2_cpg *cpg; | |
404 | struct clk **clks; | |
405 | unsigned int i; | |
406 | int num_clks; | |
407 | ||
f84c9c3c GU |
408 | if (rcar_rst_read_mode_pins(&cpg_mode)) { |
409 | /* Backward-compatibility with old DT */ | |
16673931 | 410 | pr_warn("%pOF: failed to obtain mode pins from RST\n", np); |
f84c9c3c GU |
411 | cpg_mode = rcar_gen2_read_mode_pins(); |
412 | } | |
413 | ||
10cdfe9f LP |
414 | num_clks = of_property_count_strings(np, "clock-output-names"); |
415 | if (num_clks < 0) { | |
416 | pr_err("%s: failed to count clocks\n", __func__); | |
417 | return; | |
418 | } | |
419 | ||
420 | cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); | |
421 | clks = kzalloc(num_clks * sizeof(*clks), GFP_KERNEL); | |
422 | if (cpg == NULL || clks == NULL) { | |
423 | /* We're leaking memory on purpose, there's no point in cleaning | |
424 | * up as the system won't boot anyway. | |
425 | */ | |
426 | pr_err("%s: failed to allocate cpg\n", __func__); | |
427 | return; | |
428 | } | |
429 | ||
430 | spin_lock_init(&cpg->lock); | |
431 | ||
432 | cpg->data.clks = clks; | |
433 | cpg->data.clk_num = num_clks; | |
434 | ||
435 | cpg->reg = of_iomap(np, 0); | |
436 | if (WARN_ON(cpg->reg == NULL)) | |
437 | return; | |
438 | ||
439 | config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; | |
440 | ||
441 | for (i = 0; i < num_clks; ++i) { | |
442 | const char *name; | |
443 | struct clk *clk; | |
444 | ||
445 | of_property_read_string_index(np, "clock-output-names", i, | |
446 | &name); | |
447 | ||
448 | clk = rcar_gen2_cpg_register_clock(np, cpg, config, name); | |
449 | if (IS_ERR(clk)) | |
450 | pr_err("%s: failed to register %s %s clock (%ld)\n", | |
451 | __func__, np->name, name, PTR_ERR(clk)); | |
452 | else | |
453 | cpg->data.clks[i] = clk; | |
454 | } | |
455 | ||
456 | of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); | |
63e05d93 GU |
457 | |
458 | cpg_mstp_add_clk_domain(np); | |
10cdfe9f LP |
459 | } |
460 | CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks", | |
461 | rcar_gen2_cpg_clocks_init); |