[mirror_ubuntu-jammy-kernel.git] / drivers / clk / renesas / r9a07g044-cpg.c

// SPDX-License-Identifier: GPL-2.0
/*
 * RZ/G2L CPG driver
 *
 * Copyright (C) 2021 Renesas Electronics Corp.
 */

#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/kernel.h>

#include <dt-bindings/clock/r9a07g044-cpg.h>

#include "rzg2l-cpg.h"

enum clk_ids {
	/* Core Clock Outputs exported to DT */
	LAST_DT_CORE_CLK = R9A07G044_OSCCLK,

	/* External Input Clocks */
	CLK_EXTAL,

	/* Internal Core Clocks */
	CLK_OSC_DIV1000,
	CLK_PLL1,
	CLK_PLL2,
	CLK_PLL2_DIV2,
	CLK_PLL2_DIV16,
	CLK_PLL2_DIV20,
	CLK_PLL3,
	CLK_PLL3_DIV2,
	CLK_PLL3_DIV2_4,
	CLK_PLL3_DIV2_4_2,
	CLK_PLL3_DIV4,
	CLK_PLL4,
	CLK_PLL5,
	CLK_PLL5_DIV2,
	CLK_PLL6,
	CLK_P1_DIV2,

	/* Module Clocks */
	MOD_CLK_BASE,
};

/* Divider tables */
static const struct clk_div_table dtable_1_32[] = {
	{0, 1},
	{1, 2},
	{2, 4},
	{3, 8},
	{4, 32},
	{0, 0},
};

static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
	/* External Clock Inputs */
	DEF_INPUT("extal", CLK_EXTAL),

	/* Internal Core Clocks */
	DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
	DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
	DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
	DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),

	DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
	DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),
	DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),

	DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
	DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
	DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
	DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),

	/* Core output clk */
	DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
	DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
		dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
	DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
	DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
		DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
	DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
	DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
		DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
};

static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
	DEF_MOD("gic",		R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
				0x514, 0),
	DEF_MOD("ia55_pclk",	R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
				0x518, 0),
	DEF_MOD("ia55_clk",	R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
				0x518, 1),
	DEF_MOD("dmac_aclk",	R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
				0x52c, 0),
	DEF_MOD("dmac_pclk",	R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
				0x52c, 1),
	DEF_MOD("ssi0_pclk",	R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
				0x570, 0),
	DEF_MOD("ssi0_sfr",	R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
				0x570, 1),
	DEF_MOD("ssi1_pclk",	R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
				0x570, 2),
	DEF_MOD("ssi1_sfr",	R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
				0x570, 3),
	DEF_MOD("ssi2_pclk",	R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
				0x570, 4),
	DEF_MOD("ssi2_sfr",	R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
				0x570, 5),
	DEF_MOD("ssi3_pclk",	R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
				0x570, 6),
	DEF_MOD("ssi3_sfr",	R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
				0x570, 7),
	DEF_MOD("usb0_host",	R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
				0x578, 0),
	DEF_MOD("usb1_host",	R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
				0x578, 1),
	DEF_MOD("usb0_func",	R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
				0x578, 2),
	DEF_MOD("usb_pclk",	R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
				0x578, 3),
	DEF_MOD("i2c0",		R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
				0x580, 0),
	DEF_MOD("i2c1",		R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
				0x580, 1),
	DEF_MOD("i2c2",		R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
				0x580, 2),
	DEF_MOD("i2c3",		R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
				0x580, 3),
	DEF_MOD("scif0",	R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
				0x584, 0),
	DEF_MOD("scif1",	R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
				0x584, 1),
	DEF_MOD("scif2",	R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
				0x584, 2),
	DEF_MOD("scif3",	R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
				0x584, 3),
	DEF_MOD("scif4",	R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
				0x584, 4),
	DEF_MOD("sci0",		R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
				0x588, 0),
	DEF_MOD("gpio",		R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
				0x598, 0),
};

static struct rzg2l_reset r9a07g044_resets[] = {
	DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
	DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
	DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
	DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
	DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
	DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
	DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
	DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
	DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
	DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
	DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
	DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
	DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
	DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
	DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
	DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
	DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
	DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
	DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
	DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
	DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
	DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
	DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
	DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
	DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
	DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
};

static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
	MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
};

const struct rzg2l_cpg_info r9a07g044_cpg_info = {
	/* Core Clocks */
	.core_clks = r9a07g044_core_clks,
	.num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
	.last_dt_core_clk = LAST_DT_CORE_CLK,
	.num_total_core_clks = MOD_CLK_BASE,

	/* Critical Module Clocks */
	.crit_mod_clks = r9a07g044_crit_mod_clks,
	.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),

	/* Module Clocks */
	.mod_clks = r9a07g044_mod_clks,
	.num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
	.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,

	/* Resets */
	.resets = r9a07g044_resets,
	.num_resets = ARRAY_SIZE(r9a07g044_resets),
};
Commit	Line	Data
17f0ff3d LP	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* RZ/G2L CPG driver
	4	*
	5	* Copyright (C) 2021 Renesas Electronics Corp.
	6	*/
	7
	8	#include <linux/clk-provider.h>
	9	#include <linux/device.h>
	10	#include <linux/init.h>
	11	#include <linux/kernel.h>
	12
	13	#include <dt-bindings/clock/r9a07g044-cpg.h>
	14
0aae437a	15	#include "rzg2l-cpg.h"
17f0ff3d LP	16
	17	enum clk_ids {
	18	/* Core Clock Outputs exported to DT */
	19	LAST_DT_CORE_CLK = R9A07G044_OSCCLK,
	20
	21	/* External Input Clocks */
	22	CLK_EXTAL,
	23
	24	/* Internal Core Clocks */
	25	CLK_OSC_DIV1000,
	26	CLK_PLL1,
	27	CLK_PLL2,
	28	CLK_PLL2_DIV2,
	29	CLK_PLL2_DIV16,
	30	CLK_PLL2_DIV20,
	31	CLK_PLL3,
	32	CLK_PLL3_DIV2,
fd8c3f6c	33	CLK_PLL3_DIV2_4,
668756f7	34	CLK_PLL3_DIV2_4_2,
17f0ff3d	35	CLK_PLL3_DIV4,
17f0ff3d LP	36	CLK_PLL4,
	37	CLK_PLL5,
	38	CLK_PLL5_DIV2,
	39	CLK_PLL6,
eb829e54	40	CLK_P1_DIV2,
17f0ff3d LP	41
	42	/* Module Clocks */
	43	MOD_CLK_BASE,
	44	};
	45
	46	/* Divider tables */
e93c1373	47	static const struct clk_div_table dtable_1_32[] = {
17f0ff3d LP	48	{0, 1},
	49	{1, 2},
	50	{2, 4},
	51	{3, 8},
	52	{4, 32},
e93c1373	53	{0, 0},
17f0ff3d LP	54	};
	55
	56	static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
	57	/* External Clock Inputs */
	58	DEF_INPUT("extal", CLK_EXTAL),
	59
	60	/* Internal Core Clocks */
	61	DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
	62	DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
	63	DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
	64	DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
	65	DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),
	66
	67	DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
	68	DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),
	69	DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
	70
	71	DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
fd8c3f6c	72	DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
668756f7	73	DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
17f0ff3d	74	DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
17f0ff3d LP	75
	76	/* Core output clk */
	77	DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
	78	DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
e93c1373	79	dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
17f0ff3d	80	DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
fd8c3f6c	81	DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
e93c1373	82	DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
eb829e54	83	DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
668756f7 BD	84	DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
668756f7 BD	85	DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
17f0ff3d LP	86	};
	87
	88	static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
c3e67ad6 BD	89	DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
	90	0x514, 0),
	91	DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
	92	0x518, 0),
	93	DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
	94	0x518, 1),
eb829e54 BD	95	DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
	96	0x52c, 0),
	97	DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
	98	0x52c, 1),
d520af34 BD	99	DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
	100	0x570, 0),
	101	DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
	102	0x570, 1),
	103	DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
	104	0x570, 2),
	105	DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
	106	0x570, 3),
	107	DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
	108	0x570, 4),
	109	DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
	110	0x570, 5),
	111	DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
	112	0x570, 6),
	113	DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
	114	0x570, 7),
03fa6e4b BD	115	DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
	116	0x578, 0),
	117	DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
	118	0x578, 1),
	119	DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
	120	0x578, 2),
	121	DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
	122	0x578, 3),
1962dd36 BD	123	DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
	124	0x580, 0),
	125	DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
	126	0x580, 1),
	127	DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
	128	0x580, 2),
	129	DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
	130	0x580, 3),
c3e67ad6 BD	131	DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
	132	0x584, 0),
	133	DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
	134	0x584, 1),
	135	DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
	136	0x584, 2),
	137	DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
	138	0x584, 3),
	139	DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
	140	0x584, 4),
	141	DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
	142	0x588, 0),
d85b82f0 LP	143	DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
d85b82f0 LP	144	0x598, 0),
c3e67ad6 BD	145	};
	146
	147	static struct rzg2l_reset r9a07g044_resets[] = {
	148	DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
	149	DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
	150	DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
eb829e54 BD	151	DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
eb829e54 BD	152	DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
d520af34 BD	153	DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
	154	DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
	155	DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
	156	DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
03fa6e4b BD	157	DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
	158	DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
	159	DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
	160	DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
1962dd36 BD	161	DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
	162	DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
	163	DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
	164	DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
c3e67ad6 BD	165	DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
	166	DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
	167	DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
	168	DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
	169	DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
	170	DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
d85b82f0 LP	171	DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
	172	DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
	173	DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
17f0ff3d LP	174	};
	175
	176	static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
c3e67ad6	177	MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
17f0ff3d LP	178	};
	179
	180	const struct rzg2l_cpg_info r9a07g044_cpg_info = {
	181	/* Core Clocks */
	182	.core_clks = r9a07g044_core_clks,
	183	.num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
	184	.last_dt_core_clk = LAST_DT_CORE_CLK,
	185	.num_total_core_clks = MOD_CLK_BASE,
	186
	187	/* Critical Module Clocks */
	188	.crit_mod_clks = r9a07g044_crit_mod_clks,
	189	.num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
	190
	191	/* Module Clocks */
	192	.mod_clks = r9a07g044_mod_clks,
	193	.num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
c3e67ad6 BD	194	.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
	195
	196	/* Resets */
	197	.resets = r9a07g044_resets,
	198	.num_resets = ARRAY_SIZE(r9a07g044_resets),
17f0ff3d	199	};