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2c14736c HS |
1 | /* |
2 | * Copyright (c) 2014 MundoReader S.L. | |
3 | * Author: Heiko Stuebner <heiko@sntech.de> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
f684ff8b | 16 | #include <linux/clk.h> |
2c14736c HS |
17 | #include <linux/clk-provider.h> |
18 | #include <linux/of.h> | |
19 | #include <linux/of_address.h> | |
20 | #include <dt-bindings/clock/rk3188-cru-common.h> | |
21 | #include "clk.h" | |
22 | ||
11ff376f | 23 | #define RK3066_GRF_SOC_STATUS 0x15c |
2c14736c HS |
24 | #define RK3188_GRF_SOC_STATUS 0xac |
25 | ||
26 | enum rk3188_plls { | |
27 | apll, cpll, dpll, gpll, | |
28 | }; | |
29 | ||
9b030bc9 | 30 | static struct rockchip_pll_rate_table rk3188_pll_rates[] = { |
2c14736c HS |
31 | RK3066_PLL_RATE(2208000000, 1, 92, 1), |
32 | RK3066_PLL_RATE(2184000000, 1, 91, 1), | |
33 | RK3066_PLL_RATE(2160000000, 1, 90, 1), | |
34 | RK3066_PLL_RATE(2136000000, 1, 89, 1), | |
35 | RK3066_PLL_RATE(2112000000, 1, 88, 1), | |
36 | RK3066_PLL_RATE(2088000000, 1, 87, 1), | |
37 | RK3066_PLL_RATE(2064000000, 1, 86, 1), | |
38 | RK3066_PLL_RATE(2040000000, 1, 85, 1), | |
39 | RK3066_PLL_RATE(2016000000, 1, 84, 1), | |
40 | RK3066_PLL_RATE(1992000000, 1, 83, 1), | |
41 | RK3066_PLL_RATE(1968000000, 1, 82, 1), | |
42 | RK3066_PLL_RATE(1944000000, 1, 81, 1), | |
43 | RK3066_PLL_RATE(1920000000, 1, 80, 1), | |
44 | RK3066_PLL_RATE(1896000000, 1, 79, 1), | |
45 | RK3066_PLL_RATE(1872000000, 1, 78, 1), | |
46 | RK3066_PLL_RATE(1848000000, 1, 77, 1), | |
47 | RK3066_PLL_RATE(1824000000, 1, 76, 1), | |
48 | RK3066_PLL_RATE(1800000000, 1, 75, 1), | |
49 | RK3066_PLL_RATE(1776000000, 1, 74, 1), | |
50 | RK3066_PLL_RATE(1752000000, 1, 73, 1), | |
51 | RK3066_PLL_RATE(1728000000, 1, 72, 1), | |
52 | RK3066_PLL_RATE(1704000000, 1, 71, 1), | |
53 | RK3066_PLL_RATE(1680000000, 1, 70, 1), | |
54 | RK3066_PLL_RATE(1656000000, 1, 69, 1), | |
55 | RK3066_PLL_RATE(1632000000, 1, 68, 1), | |
56 | RK3066_PLL_RATE(1608000000, 1, 67, 1), | |
57 | RK3066_PLL_RATE(1560000000, 1, 65, 1), | |
58 | RK3066_PLL_RATE(1512000000, 1, 63, 1), | |
59 | RK3066_PLL_RATE(1488000000, 1, 62, 1), | |
60 | RK3066_PLL_RATE(1464000000, 1, 61, 1), | |
61 | RK3066_PLL_RATE(1440000000, 1, 60, 1), | |
62 | RK3066_PLL_RATE(1416000000, 1, 59, 1), | |
63 | RK3066_PLL_RATE(1392000000, 1, 58, 1), | |
64 | RK3066_PLL_RATE(1368000000, 1, 57, 1), | |
65 | RK3066_PLL_RATE(1344000000, 1, 56, 1), | |
66 | RK3066_PLL_RATE(1320000000, 1, 55, 1), | |
67 | RK3066_PLL_RATE(1296000000, 1, 54, 1), | |
68 | RK3066_PLL_RATE(1272000000, 1, 53, 1), | |
69 | RK3066_PLL_RATE(1248000000, 1, 52, 1), | |
70 | RK3066_PLL_RATE(1224000000, 1, 51, 1), | |
71 | RK3066_PLL_RATE(1200000000, 1, 50, 1), | |
72 | RK3066_PLL_RATE(1188000000, 2, 99, 1), | |
73 | RK3066_PLL_RATE(1176000000, 1, 49, 1), | |
74 | RK3066_PLL_RATE(1128000000, 1, 47, 1), | |
75 | RK3066_PLL_RATE(1104000000, 1, 46, 1), | |
76 | RK3066_PLL_RATE(1008000000, 1, 84, 2), | |
77 | RK3066_PLL_RATE( 912000000, 1, 76, 2), | |
78 | RK3066_PLL_RATE( 891000000, 8, 594, 2), | |
79 | RK3066_PLL_RATE( 888000000, 1, 74, 2), | |
80 | RK3066_PLL_RATE( 816000000, 1, 68, 2), | |
81 | RK3066_PLL_RATE( 798000000, 2, 133, 2), | |
82 | RK3066_PLL_RATE( 792000000, 1, 66, 2), | |
83 | RK3066_PLL_RATE( 768000000, 1, 64, 2), | |
84 | RK3066_PLL_RATE( 742500000, 8, 495, 2), | |
85 | RK3066_PLL_RATE( 696000000, 1, 58, 2), | |
86 | RK3066_PLL_RATE( 600000000, 1, 50, 2), | |
87 | RK3066_PLL_RATE( 594000000, 2, 198, 4), | |
88 | RK3066_PLL_RATE( 552000000, 1, 46, 2), | |
89 | RK3066_PLL_RATE( 504000000, 1, 84, 4), | |
90 | RK3066_PLL_RATE( 456000000, 1, 76, 4), | |
91 | RK3066_PLL_RATE( 408000000, 1, 68, 4), | |
92 | RK3066_PLL_RATE( 384000000, 2, 128, 4), | |
93 | RK3066_PLL_RATE( 360000000, 1, 60, 4), | |
94 | RK3066_PLL_RATE( 312000000, 1, 52, 4), | |
95 | RK3066_PLL_RATE( 300000000, 1, 50, 4), | |
96 | RK3066_PLL_RATE( 297000000, 2, 198, 8), | |
97 | RK3066_PLL_RATE( 252000000, 1, 84, 8), | |
98 | RK3066_PLL_RATE( 216000000, 1, 72, 8), | |
99 | RK3066_PLL_RATE( 148500000, 2, 99, 8), | |
100 | RK3066_PLL_RATE( 126000000, 1, 84, 16), | |
101 | RK3066_PLL_RATE( 48000000, 1, 64, 32), | |
102 | { /* sentinel */ }, | |
103 | }; | |
104 | ||
0e5bdb3f HS |
105 | #define RK3066_DIV_CORE_PERIPH_MASK 0x3 |
106 | #define RK3066_DIV_CORE_PERIPH_SHIFT 6 | |
107 | #define RK3066_DIV_ACLK_CORE_MASK 0x7 | |
108 | #define RK3066_DIV_ACLK_CORE_SHIFT 0 | |
109 | #define RK3066_DIV_ACLK_HCLK_MASK 0x3 | |
110 | #define RK3066_DIV_ACLK_HCLK_SHIFT 8 | |
111 | #define RK3066_DIV_ACLK_PCLK_MASK 0x3 | |
112 | #define RK3066_DIV_ACLK_PCLK_SHIFT 12 | |
113 | #define RK3066_DIV_AHB2APB_MASK 0x3 | |
114 | #define RK3066_DIV_AHB2APB_SHIFT 14 | |
115 | ||
116 | #define RK3066_CLKSEL0(_core_peri) \ | |
117 | { \ | |
118 | .reg = RK2928_CLKSEL_CON(0), \ | |
119 | .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \ | |
120 | RK3066_DIV_CORE_PERIPH_SHIFT) \ | |
121 | } | |
122 | #define RK3066_CLKSEL1(_aclk_core, _aclk_hclk, _aclk_pclk, _ahb2apb) \ | |
123 | { \ | |
124 | .reg = RK2928_CLKSEL_CON(1), \ | |
125 | .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \ | |
126 | RK3066_DIV_ACLK_CORE_SHIFT) | \ | |
127 | HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \ | |
128 | RK3066_DIV_ACLK_HCLK_SHIFT) | \ | |
129 | HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \ | |
130 | RK3066_DIV_ACLK_PCLK_SHIFT) | \ | |
131 | HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \ | |
132 | RK3066_DIV_AHB2APB_SHIFT), \ | |
133 | } | |
134 | ||
135 | #define RK3066_CPUCLK_RATE(_prate, _core_peri, _acore, _ahclk, _apclk, _h2p) \ | |
136 | { \ | |
137 | .prate = _prate, \ | |
138 | .divs = { \ | |
139 | RK3066_CLKSEL0(_core_peri), \ | |
140 | RK3066_CLKSEL1(_acore, _ahclk, _apclk, _h2p), \ | |
141 | }, \ | |
142 | } | |
143 | ||
144 | static struct rockchip_cpuclk_rate_table rk3066_cpuclk_rates[] __initdata = { | |
145 | RK3066_CPUCLK_RATE(1416000000, 2, 3, 1, 2, 1), | |
146 | RK3066_CPUCLK_RATE(1200000000, 2, 3, 1, 2, 1), | |
147 | RK3066_CPUCLK_RATE(1008000000, 2, 2, 1, 2, 1), | |
148 | RK3066_CPUCLK_RATE( 816000000, 2, 2, 1, 2, 1), | |
149 | RK3066_CPUCLK_RATE( 600000000, 1, 2, 1, 2, 1), | |
150 | RK3066_CPUCLK_RATE( 504000000, 1, 1, 1, 2, 1), | |
151 | RK3066_CPUCLK_RATE( 312000000, 0, 1, 1, 1, 0), | |
152 | }; | |
153 | ||
154 | static const struct rockchip_cpuclk_reg_data rk3066_cpuclk_data = { | |
155 | .core_reg = RK2928_CLKSEL_CON(0), | |
156 | .div_core_shift = 0, | |
157 | .div_core_mask = 0x1f, | |
158 | .mux_core_shift = 8, | |
159 | }; | |
160 | ||
161 | #define RK3188_DIV_ACLK_CORE_MASK 0x7 | |
162 | #define RK3188_DIV_ACLK_CORE_SHIFT 3 | |
163 | ||
164 | #define RK3188_CLKSEL1(_aclk_core) \ | |
165 | { \ | |
166 | .reg = RK2928_CLKSEL_CON(1), \ | |
167 | .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\ | |
168 | RK3188_DIV_ACLK_CORE_SHIFT) \ | |
169 | } | |
170 | #define RK3188_CPUCLK_RATE(_prate, _core_peri, _aclk_core) \ | |
171 | { \ | |
172 | .prate = _prate, \ | |
173 | .divs = { \ | |
174 | RK3066_CLKSEL0(_core_peri), \ | |
175 | RK3188_CLKSEL1(_aclk_core), \ | |
176 | }, \ | |
177 | } | |
178 | ||
179 | static struct rockchip_cpuclk_rate_table rk3188_cpuclk_rates[] __initdata = { | |
180 | RK3188_CPUCLK_RATE(1608000000, 2, 3), | |
181 | RK3188_CPUCLK_RATE(1416000000, 2, 3), | |
182 | RK3188_CPUCLK_RATE(1200000000, 2, 3), | |
183 | RK3188_CPUCLK_RATE(1008000000, 2, 3), | |
184 | RK3188_CPUCLK_RATE( 816000000, 2, 3), | |
185 | RK3188_CPUCLK_RATE( 600000000, 1, 3), | |
186 | RK3188_CPUCLK_RATE( 504000000, 1, 3), | |
187 | RK3188_CPUCLK_RATE( 312000000, 0, 1), | |
188 | }; | |
189 | ||
190 | static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = { | |
191 | .core_reg = RK2928_CLKSEL_CON(0), | |
192 | .div_core_shift = 9, | |
193 | .div_core_mask = 0x1f, | |
194 | .mux_core_shift = 8, | |
195 | }; | |
196 | ||
2c14736c HS |
197 | PNAME(mux_pll_p) = { "xin24m", "xin32k" }; |
198 | PNAME(mux_armclk_p) = { "apll", "gpll_armclk" }; | |
199 | PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" }; | |
200 | PNAME(mux_pll_src_gpll_cpll_p) = { "gpll", "cpll" }; | |
201 | PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; | |
202 | PNAME(mux_aclk_cpu_p) = { "apll", "gpll" }; | |
203 | PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" }; | |
204 | PNAME(mux_sclk_i2s0_p) = { "i2s0_pre", "i2s0_frac", "xin12m" }; | |
bea047e0 | 205 | PNAME(mux_sclk_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" }; |
2c14736c HS |
206 | PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" }; |
207 | PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" }; | |
208 | PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" }; | |
209 | PNAME(mux_sclk_uart3_p) = { "uart3_pre", "uart3_frac", "xin24m" }; | |
210 | PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" }; | |
211 | PNAME(mux_mac_p) = { "gpll", "dpll" }; | |
212 | PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" }; | |
213 | ||
12551f02 HS |
214 | static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = { |
215 | [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), | |
216 | RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates), | |
217 | [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), | |
218 | RK2928_MODE_CON, 4, 4, 0, NULL), | |
219 | [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), | |
220 | RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), | |
221 | [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), | |
222 | RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), | |
223 | }; | |
224 | ||
2c14736c HS |
225 | static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = { |
226 | [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), | |
4f8a7c54 | 227 | RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates), |
2c14736c | 228 | [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), |
4f8a7c54 | 229 | RK2928_MODE_CON, 4, 5, 0, NULL), |
2c14736c | 230 | [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8), |
dd79c0be | 231 | RK2928_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), |
2c14736c | 232 | [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12), |
dd79c0be | 233 | RK2928_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates), |
2c14736c HS |
234 | }; |
235 | ||
236 | #define MFLAGS CLK_MUX_HIWORD_MASK | |
237 | #define DFLAGS CLK_DIVIDER_HIWORD_MASK | |
238 | #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) | |
4534b111 | 239 | #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK |
2c14736c HS |
240 | |
241 | /* 2 ^ (val + 1) */ | |
242 | static struct clk_div_table div_core_peri_t[] = { | |
243 | { .val = 0, .div = 2 }, | |
244 | { .val = 1, .div = 4 }, | |
245 | { .val = 2, .div = 8 }, | |
246 | { .val = 3, .div = 16 }, | |
247 | { /* sentinel */ }, | |
248 | }; | |
249 | ||
250 | static struct rockchip_clk_branch common_clk_branches[] __initdata = { | |
251 | /* | |
252 | * Clock-Architecture Diagram 2 | |
253 | */ | |
254 | ||
255 | GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS), | |
256 | ||
257 | /* these two are set by the cpuclk and should not be changed */ | |
258 | COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri", "armclk", 0, | |
259 | RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY, | |
260 | div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS), | |
261 | ||
262 | COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0, | |
263 | RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS, | |
264 | RK2928_CLKGATE_CON(3), 9, GFLAGS), | |
265 | GATE(0, "hclk_vepu", "aclk_vepu", 0, | |
266 | RK2928_CLKGATE_CON(3), 10, GFLAGS), | |
267 | COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0, | |
268 | RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, | |
269 | RK2928_CLKGATE_CON(3), 11, GFLAGS), | |
270 | GATE(0, "hclk_vdpu", "aclk_vdpu", 0, | |
271 | RK2928_CLKGATE_CON(3), 12, GFLAGS), | |
272 | ||
78eaf609 | 273 | GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, |
2c14736c | 274 | RK2928_CLKGATE_CON(1), 7, GFLAGS), |
78eaf609 | 275 | COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED, |
2c14736c HS |
276 | RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, |
277 | RK2928_CLKGATE_CON(0), 2, GFLAGS), | |
278 | ||
279 | GATE(0, "aclk_cpu", "aclk_cpu_pre", 0, | |
280 | RK2928_CLKGATE_CON(0), 3, GFLAGS), | |
281 | ||
2c14736c HS |
282 | GATE(0, "atclk_cpu", "pclk_cpu_pre", 0, |
283 | RK2928_CLKGATE_CON(0), 6, GFLAGS), | |
284 | GATE(0, "pclk_cpu", "pclk_cpu_pre", 0, | |
285 | RK2928_CLKGATE_CON(0), 5, GFLAGS), | |
78eaf609 | 286 | GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED, |
2c14736c HS |
287 | RK2928_CLKGATE_CON(0), 4, GFLAGS), |
288 | ||
78eaf609 | 289 | COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED, |
2c14736c HS |
290 | RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS, |
291 | RK2928_CLKGATE_CON(3), 0, GFLAGS), | |
292 | COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0, | |
293 | RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS, | |
294 | RK2928_CLKGATE_CON(1), 4, GFLAGS), | |
295 | ||
296 | GATE(0, "aclk_peri", "aclk_peri_pre", 0, | |
297 | RK2928_CLKGATE_CON(2), 1, GFLAGS), | |
298 | COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_pre", 0, | |
299 | RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, | |
300 | RK2928_CLKGATE_CON(2), 2, GFLAGS), | |
301 | COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_pre", 0, | |
302 | RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, | |
303 | RK2928_CLKGATE_CON(2), 3, GFLAGS), | |
304 | ||
305 | MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0, | |
306 | RK2928_CLKSEL_CON(29), 0, 1, MFLAGS), | |
307 | COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0, | |
308 | RK2928_CLKSEL_CON(29), 1, 5, DFLAGS, | |
309 | RK2928_CLKGATE_CON(3), 7, GFLAGS), | |
310 | MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0, | |
311 | RK2928_CLKSEL_CON(29), 7, 1, MFLAGS), | |
312 | ||
313 | GATE(0, "pclkin_cif0", "ext_cif0", 0, | |
314 | RK2928_CLKGATE_CON(3), 3, GFLAGS), | |
4534b111 HS |
315 | INVERTER(0, "pclk_cif0", "pclkin_cif0", |
316 | RK2928_CLKSEL_CON(30), 8, IFLAGS), | |
2c14736c HS |
317 | |
318 | /* | |
319 | * the 480m are generated inside the usb block from these clocks, | |
320 | * but they are also a source for the hsicphy clock. | |
321 | */ | |
78eaf609 | 322 | GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED, |
2c14736c | 323 | RK2928_CLKGATE_CON(1), 5, GFLAGS), |
78eaf609 | 324 | GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED, |
2c14736c HS |
325 | RK2928_CLKGATE_CON(1), 6, GFLAGS), |
326 | ||
327 | COMPOSITE(0, "mac_src", mux_mac_p, 0, | |
328 | RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS, | |
329 | RK2928_CLKGATE_CON(2), 5, GFLAGS), | |
330 | MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT, | |
331 | RK2928_CLKSEL_CON(21), 4, 1, MFLAGS), | |
332 | GATE(0, "sclk_mac_lbtest", "sclk_macref", | |
333 | RK2928_CLKGATE_CON(2), 12, 0, GFLAGS), | |
334 | ||
335 | COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0, | |
336 | RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS, | |
337 | RK2928_CLKGATE_CON(2), 6, GFLAGS), | |
d1f931be | 338 | COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src", 0, |
2c14736c | 339 | RK2928_CLKSEL_CON(23), 0, |
d1f931be | 340 | RK2928_CLKGATE_CON(2), 7, GFLAGS), |
4534b111 | 341 | MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0, |
2c14736c | 342 | RK2928_CLKSEL_CON(22), 4, 2, MFLAGS), |
4534b111 HS |
343 | INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out", |
344 | RK2928_CLKSEL_CON(22), 7, IFLAGS), | |
2c14736c HS |
345 | |
346 | COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0, | |
347 | RK2928_CLKSEL_CON(24), 8, 8, DFLAGS, | |
348 | RK2928_CLKGATE_CON(2), 8, GFLAGS), | |
349 | ||
b7bdb7f4 JC |
350 | COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0, |
351 | RK2928_CLKSEL_CON(5), 0, 7, DFLAGS, | |
352 | RK2928_CLKGATE_CON(0), 13, GFLAGS), | |
bea047e0 | 353 | COMPOSITE_FRAC(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT, |
b7bdb7f4 JC |
354 | RK2928_CLKSEL_CON(9), 0, |
355 | RK2928_CLKGATE_CON(0), 14, GFLAGS), | |
bea047e0 | 356 | MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, |
b7bdb7f4 JC |
357 | RK2928_CLKSEL_CON(5), 8, 2, MFLAGS), |
358 | ||
2c14736c HS |
359 | /* |
360 | * Clock-Architecture Diagram 4 | |
361 | */ | |
362 | ||
363 | GATE(SCLK_SMC, "sclk_smc", "hclk_peri", | |
364 | RK2928_CLKGATE_CON(2), 4, 0, GFLAGS), | |
365 | ||
366 | COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0, | |
367 | RK2928_CLKSEL_CON(25), 0, 7, DFLAGS, | |
368 | RK2928_CLKGATE_CON(2), 9, GFLAGS), | |
369 | COMPOSITE_NOMUX(SCLK_SPI1, "sclk_spi1", "pclk_peri", 0, | |
370 | RK2928_CLKSEL_CON(25), 8, 7, DFLAGS, | |
371 | RK2928_CLKGATE_CON(2), 10, GFLAGS), | |
372 | ||
373 | COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc", "hclk_peri", 0, | |
374 | RK2928_CLKSEL_CON(11), 0, 6, DFLAGS, | |
375 | RK2928_CLKGATE_CON(2), 11, GFLAGS), | |
376 | COMPOSITE_NOMUX(SCLK_SDIO, "sclk_sdio", "hclk_peri", 0, | |
377 | RK2928_CLKSEL_CON(12), 0, 6, DFLAGS, | |
378 | RK2928_CLKGATE_CON(2), 13, GFLAGS), | |
379 | COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0, | |
380 | RK2928_CLKSEL_CON(12), 8, 6, DFLAGS, | |
381 | RK2928_CLKGATE_CON(2), 14, GFLAGS), | |
382 | ||
383 | MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0, | |
384 | RK2928_CLKSEL_CON(12), 15, 1, MFLAGS), | |
385 | COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0, | |
386 | RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, | |
387 | RK2928_CLKGATE_CON(1), 8, GFLAGS), | |
388 | COMPOSITE_FRAC(0, "uart0_frac", "uart0_pre", 0, | |
389 | RK2928_CLKSEL_CON(17), 0, | |
390 | RK2928_CLKGATE_CON(1), 9, GFLAGS), | |
391 | MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0, | |
392 | RK2928_CLKSEL_CON(13), 8, 2, MFLAGS), | |
393 | COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0, | |
394 | RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, | |
395 | RK2928_CLKGATE_CON(1), 10, GFLAGS), | |
396 | COMPOSITE_FRAC(0, "uart1_frac", "uart1_pre", 0, | |
397 | RK2928_CLKSEL_CON(18), 0, | |
398 | RK2928_CLKGATE_CON(1), 11, GFLAGS), | |
399 | MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0, | |
400 | RK2928_CLKSEL_CON(14), 8, 2, MFLAGS), | |
401 | COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0, | |
402 | RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, | |
403 | RK2928_CLKGATE_CON(1), 12, GFLAGS), | |
404 | COMPOSITE_FRAC(0, "uart2_frac", "uart2_pre", 0, | |
405 | RK2928_CLKSEL_CON(19), 0, | |
406 | RK2928_CLKGATE_CON(1), 13, GFLAGS), | |
407 | MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0, | |
408 | RK2928_CLKSEL_CON(15), 8, 2, MFLAGS), | |
409 | COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0, | |
410 | RK2928_CLKSEL_CON(16), 0, 7, DFLAGS, | |
411 | RK2928_CLKGATE_CON(1), 14, GFLAGS), | |
412 | COMPOSITE_FRAC(0, "uart3_frac", "uart3_pre", 0, | |
413 | RK2928_CLKSEL_CON(20), 0, | |
414 | RK2928_CLKGATE_CON(1), 15, GFLAGS), | |
415 | MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0, | |
416 | RK2928_CLKSEL_CON(16), 8, 2, MFLAGS), | |
417 | ||
418 | GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS), | |
419 | ||
420 | GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS), | |
421 | GATE(SCLK_TIMER1, "timer1", "xin24m", 0, RK2928_CLKGATE_CON(1), 1, GFLAGS), | |
422 | ||
423 | /* clk_core_pre gates */ | |
424 | GATE(0, "core_dbg", "armclk", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS), | |
425 | ||
426 | /* aclk_cpu gates */ | |
427 | GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS), | |
78eaf609 KY |
428 | GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 12, GFLAGS), |
429 | GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 10, GFLAGS), | |
2c14736c HS |
430 | |
431 | /* hclk_cpu gates */ | |
432 | GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS), | |
433 | GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), | |
434 | GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS), | |
435 | GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS), | |
436 | /* hclk_ahb2apb is part of a clk branch */ | |
437 | GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS), | |
438 | GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS), | |
f0c71718 | 439 | GATE(HCLK_LCDC1, "hclk_lcdc1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS), |
2c14736c HS |
440 | GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS), |
441 | GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS), | |
442 | GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS), | |
443 | ||
444 | /* hclk_peri gates */ | |
78eaf609 KY |
445 | GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS), |
446 | GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS), | |
5039d16a | 447 | GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS), |
2c14736c HS |
448 | GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS), |
449 | GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS), | |
caa6934a JC |
450 | GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS), |
451 | GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), | |
2c14736c HS |
452 | GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS), |
453 | GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS), | |
454 | GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS), | |
455 | GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS), | |
456 | GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 12, GFLAGS), | |
457 | ||
458 | /* aclk_lcdc0_pre gates */ | |
459 | GATE(0, "aclk_vio0", "aclk_lcdc0_pre", 0, RK2928_CLKGATE_CON(6), 13, GFLAGS), | |
460 | GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS), | |
461 | GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS), | |
462 | GATE(ACLK_IPP, "aclk_ipp", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 8, GFLAGS), | |
463 | ||
464 | /* aclk_lcdc1_pre gates */ | |
465 | GATE(0, "aclk_vio1", "aclk_lcdc1_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), | |
466 | GATE(ACLK_LCDC1, "aclk_lcdc1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 3, GFLAGS), | |
467 | GATE(ACLK_RGA, "aclk_rga", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS), | |
468 | ||
469 | /* atclk_cpu gates */ | |
470 | GATE(0, "atclk", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 3, GFLAGS), | |
471 | GATE(0, "trace", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS), | |
472 | ||
473 | /* pclk_cpu gates */ | |
474 | GATE(PCLK_PWM01, "pclk_pwm01", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS), | |
475 | GATE(PCLK_TIMER0, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS), | |
476 | GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), | |
477 | GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS), | |
478 | GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS), | |
479 | GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS), | |
480 | GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), | |
481 | GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS), | |
482 | GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS), | |
483 | GATE(0, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS), | |
484 | GATE(0, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), | |
485 | GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS), | |
78eaf609 KY |
486 | GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), |
487 | GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 5, GFLAGS), | |
2c14736c HS |
488 | |
489 | /* aclk_peri */ | |
490 | GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS), | |
491 | GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS), | |
78eaf609 KY |
492 | GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 4, GFLAGS), |
493 | GATE(0, "aclk_cpu_peri", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 2, GFLAGS), | |
494 | GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 3, GFLAGS), | |
2c14736c HS |
495 | |
496 | /* pclk_peri gates */ | |
78eaf609 | 497 | GATE(0, "pclk_peri_axi_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS), |
2c14736c HS |
498 | GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS), |
499 | GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS), | |
500 | GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS), | |
501 | GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 13, GFLAGS), | |
502 | GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS), | |
503 | GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS), | |
504 | GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), | |
505 | GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS), | |
506 | GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS), | |
507 | GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS), | |
508 | GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS), | |
509 | }; | |
510 | ||
511 | PNAME(mux_rk3066_lcdc0_p) = { "dclk_lcdc0_src", "xin27m" }; | |
512 | PNAME(mux_rk3066_lcdc1_p) = { "dclk_lcdc1_src", "xin27m" }; | |
513 | PNAME(mux_sclk_cif1_p) = { "cif1_pre", "xin24m" }; | |
514 | PNAME(mux_sclk_i2s1_p) = { "i2s1_pre", "i2s1_frac", "xin12m" }; | |
515 | PNAME(mux_sclk_i2s2_p) = { "i2s2_pre", "i2s2_frac", "xin12m" }; | |
516 | ||
517 | static struct clk_div_table div_aclk_cpu_t[] = { | |
518 | { .val = 0, .div = 1 }, | |
519 | { .val = 1, .div = 2 }, | |
520 | { .val = 2, .div = 3 }, | |
521 | { .val = 3, .div = 4 }, | |
522 | { .val = 4, .div = 8 }, | |
523 | { /* sentinel */ }, | |
524 | }; | |
525 | ||
526 | static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { | |
2c14736c | 527 | DIVTBL(0, "aclk_cpu_pre", "armclk", 0, |
2b9bceea HS |
528 | RK2928_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, div_aclk_cpu_t), |
529 | DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0, | |
530 | RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO | |
531 | | CLK_DIVIDER_READ_ONLY), | |
532 | DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0, | |
533 | RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO | |
534 | | CLK_DIVIDER_READ_ONLY), | |
535 | COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0, | |
536 | RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO | |
537 | | CLK_DIVIDER_READ_ONLY, | |
538 | RK2928_CLKGATE_CON(4), 9, GFLAGS), | |
2c14736c | 539 | |
78eaf609 | 540 | GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED, |
2c14736c HS |
541 | RK2928_CLKGATE_CON(9), 4, GFLAGS), |
542 | ||
543 | COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0, | |
544 | RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS, | |
545 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
546 | ||
547 | COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0, | |
548 | RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS, | |
549 | RK2928_CLKGATE_CON(3), 1, GFLAGS), | |
550 | MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, 0, | |
551 | RK2928_CLKSEL_CON(27), 4, 1, MFLAGS), | |
552 | COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0, | |
553 | RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS, | |
554 | RK2928_CLKGATE_CON(3), 2, GFLAGS), | |
555 | MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, 0, | |
556 | RK2928_CLKSEL_CON(28), 4, 1, MFLAGS), | |
557 | ||
558 | COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0, | |
559 | RK2928_CLKSEL_CON(29), 8, 5, DFLAGS, | |
560 | RK2928_CLKGATE_CON(3), 8, GFLAGS), | |
561 | MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0, | |
562 | RK2928_CLKSEL_CON(29), 15, 1, MFLAGS), | |
563 | ||
564 | GATE(0, "pclkin_cif1", "ext_cif1", 0, | |
565 | RK2928_CLKGATE_CON(3), 4, GFLAGS), | |
4534b111 HS |
566 | INVERTER(0, "pclk_cif1", "pclkin_cif1", |
567 | RK2928_CLKSEL_CON(30), 12, IFLAGS), | |
2c14736c HS |
568 | |
569 | COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0, | |
570 | RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS, | |
571 | RK2928_CLKGATE_CON(3), 13, GFLAGS), | |
572 | GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0, | |
573 | RK2928_CLKGATE_CON(5), 15, GFLAGS), | |
574 | ||
575 | GATE(SCLK_TIMER2, "timer2", "xin24m", 0, | |
576 | RK2928_CLKGATE_CON(3), 2, GFLAGS), | |
577 | ||
578 | COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0, | |
579 | RK2928_CLKSEL_CON(34), 0, 16, DFLAGS, | |
580 | RK2928_CLKGATE_CON(2), 15, GFLAGS), | |
581 | ||
582 | MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0, | |
583 | RK2928_CLKSEL_CON(2), 15, 1, MFLAGS), | |
584 | COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, | |
585 | RK2928_CLKSEL_CON(2), 0, 7, DFLAGS, | |
586 | RK2928_CLKGATE_CON(0), 7, GFLAGS), | |
587 | COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0, | |
588 | RK2928_CLKSEL_CON(6), 0, | |
589 | RK2928_CLKGATE_CON(0), 8, GFLAGS), | |
590 | MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0, | |
591 | RK2928_CLKSEL_CON(2), 8, 2, MFLAGS), | |
592 | COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0, | |
593 | RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, | |
594 | RK2928_CLKGATE_CON(0), 9, GFLAGS), | |
595 | COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_pre", 0, | |
596 | RK2928_CLKSEL_CON(7), 0, | |
597 | RK2928_CLKGATE_CON(0), 10, GFLAGS), | |
598 | MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0, | |
599 | RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), | |
600 | COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0, | |
601 | RK2928_CLKSEL_CON(4), 0, 7, DFLAGS, | |
602 | RK2928_CLKGATE_CON(0), 11, GFLAGS), | |
603 | COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_pre", 0, | |
604 | RK2928_CLKSEL_CON(8), 0, | |
605 | RK2928_CLKGATE_CON(0), 12, GFLAGS), | |
606 | MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0, | |
607 | RK2928_CLKSEL_CON(4), 8, 2, MFLAGS), | |
2c14736c HS |
608 | |
609 | GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), | |
610 | GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), | |
611 | GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS), | |
612 | GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), | |
613 | ||
caa6934a JC |
614 | GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED, |
615 | RK2928_CLKGATE_CON(5), 14, GFLAGS), | |
2c14736c HS |
616 | |
617 | GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS), | |
618 | ||
619 | GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS), | |
620 | GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS), | |
621 | GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS), | |
622 | GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), | |
623 | GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), | |
624 | ||
625 | GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), | |
626 | GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 13, GFLAGS), | |
627 | }; | |
628 | ||
629 | static struct clk_div_table div_rk3188_aclk_core_t[] = { | |
630 | { .val = 0, .div = 1 }, | |
631 | { .val = 1, .div = 2 }, | |
632 | { .val = 2, .div = 3 }, | |
633 | { .val = 3, .div = 4 }, | |
634 | { .val = 4, .div = 8 }, | |
635 | { /* sentinel */ }, | |
636 | }; | |
637 | ||
638 | PNAME(mux_hsicphy_p) = { "sclk_otgphy0", "sclk_otgphy1", | |
639 | "gpll", "cpll" }; | |
640 | ||
641 | static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { | |
78eaf609 | 642 | COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED, |
2c14736c HS |
643 | RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, |
644 | div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS), | |
645 | ||
646 | /* do not source aclk_cpu_pre from the apll, to keep complexity down */ | |
647 | COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT, | |
648 | RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS), | |
2b9bceea HS |
649 | DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0, |
650 | RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), | |
651 | DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0, | |
652 | RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), | |
653 | COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0, | |
654 | RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, | |
655 | RK2928_CLKGATE_CON(4), 9, GFLAGS), | |
2c14736c | 656 | |
78eaf609 | 657 | GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED, |
2c14736c HS |
658 | RK2928_CLKGATE_CON(9), 4, GFLAGS), |
659 | ||
660 | COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0, | |
661 | RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS, | |
662 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
663 | ||
664 | COMPOSITE(DCLK_LCDC0, "dclk_lcdc0", mux_pll_src_cpll_gpll_p, 0, | |
665 | RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS, | |
666 | RK2928_CLKGATE_CON(3), 1, GFLAGS), | |
667 | COMPOSITE(DCLK_LCDC1, "dclk_lcdc1", mux_pll_src_cpll_gpll_p, 0, | |
668 | RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS, | |
669 | RK2928_CLKGATE_CON(3), 2, GFLAGS), | |
670 | ||
671 | COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0, | |
672 | RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS, | |
673 | RK2928_CLKGATE_CON(3), 15, GFLAGS), | |
674 | GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0, | |
675 | RK2928_CLKGATE_CON(9), 7, GFLAGS), | |
676 | ||
677 | GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS), | |
678 | GATE(SCLK_TIMER3, "timer3", "xin24m", 0, RK2928_CLKGATE_CON(1), 2, GFLAGS), | |
679 | GATE(SCLK_TIMER4, "timer4", "xin24m", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), | |
680 | GATE(SCLK_TIMER5, "timer5", "xin24m", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS), | |
681 | GATE(SCLK_TIMER6, "timer6", "xin24m", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS), | |
682 | ||
683 | COMPOSITE_NODIV(0, "sclk_hsicphy_480m", mux_hsicphy_p, 0, | |
684 | RK2928_CLKSEL_CON(30), 0, 2, DFLAGS, | |
685 | RK2928_CLKGATE_CON(3), 6, GFLAGS), | |
686 | DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0, | |
12c0a0e8 | 687 | RK2928_CLKSEL_CON(11), 8, 6, DFLAGS), |
2c14736c HS |
688 | |
689 | MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0, | |
690 | RK2928_CLKSEL_CON(2), 15, 1, MFLAGS), | |
691 | COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, | |
692 | RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, | |
693 | RK2928_CLKGATE_CON(0), 9, GFLAGS), | |
694 | COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0, | |
695 | RK2928_CLKSEL_CON(7), 0, | |
696 | RK2928_CLKGATE_CON(0), 10, GFLAGS), | |
697 | MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0, | |
698 | RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), | |
2c14736c HS |
699 | |
700 | GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), | |
701 | GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS), | |
702 | ||
caa6934a JC |
703 | GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED, |
704 | RK2928_CLKGATE_CON(7), 3, GFLAGS), | |
2c14736c HS |
705 | GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), |
706 | ||
707 | GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS), | |
708 | ||
709 | GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), | |
710 | GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), | |
711 | ||
712 | GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), | |
713 | }; | |
714 | ||
692d8328 | 715 | static const char *const rk3188_critical_clocks[] __initconst = { |
fe94f974 HS |
716 | "aclk_cpu", |
717 | "aclk_peri", | |
2fed71e5 | 718 | "hclk_peri", |
1166160a | 719 | "pclk_cpu", |
3bba75a2 | 720 | "pclk_peri", |
fe94f974 HS |
721 | }; |
722 | ||
2c14736c HS |
723 | static void __init rk3188_common_clk_init(struct device_node *np) |
724 | { | |
725 | void __iomem *reg_base; | |
726 | struct clk *clk; | |
727 | ||
728 | reg_base = of_iomap(np, 0); | |
729 | if (!reg_base) { | |
730 | pr_err("%s: could not map cru region\n", __func__); | |
731 | return; | |
732 | } | |
733 | ||
734 | rockchip_clk_init(np, reg_base, CLK_NR_CLKS); | |
735 | ||
736 | /* xin12m is created by an cru-internal divider */ | |
737 | clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2); | |
738 | if (IS_ERR(clk)) | |
739 | pr_warn("%s: could not register clock xin12m: %ld\n", | |
740 | __func__, PTR_ERR(clk)); | |
741 | ||
742 | clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1); | |
743 | if (IS_ERR(clk)) | |
744 | pr_warn("%s: could not register clock usb480m: %ld\n", | |
745 | __func__, PTR_ERR(clk)); | |
746 | ||
2c14736c HS |
747 | rockchip_clk_register_branches(common_clk_branches, |
748 | ARRAY_SIZE(common_clk_branches)); | |
749 | ||
750 | rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), | |
751 | ROCKCHIP_SOFTRST_HIWORD_MASK); | |
6f1294b5 HS |
752 | |
753 | rockchip_register_restart_notifier(RK2928_GLB_SRST_FST); | |
2c14736c HS |
754 | } |
755 | ||
756 | static void __init rk3066a_clk_init(struct device_node *np) | |
757 | { | |
758 | rk3188_common_clk_init(np); | |
12551f02 HS |
759 | rockchip_clk_register_plls(rk3066_pll_clks, |
760 | ARRAY_SIZE(rk3066_pll_clks), | |
11ff376f | 761 | RK3066_GRF_SOC_STATUS); |
2c14736c HS |
762 | rockchip_clk_register_branches(rk3066a_clk_branches, |
763 | ARRAY_SIZE(rk3066a_clk_branches)); | |
0e5bdb3f HS |
764 | rockchip_clk_register_armclk(ARMCLK, "armclk", |
765 | mux_armclk_p, ARRAY_SIZE(mux_armclk_p), | |
766 | &rk3066_cpuclk_data, rk3066_cpuclk_rates, | |
767 | ARRAY_SIZE(rk3066_cpuclk_rates)); | |
bb0f7361 HS |
768 | rockchip_clk_protect_critical(rk3188_critical_clocks, |
769 | ARRAY_SIZE(rk3188_critical_clocks)); | |
2c14736c HS |
770 | } |
771 | CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init); | |
772 | ||
773 | static void __init rk3188a_clk_init(struct device_node *np) | |
774 | { | |
f5f7004f HS |
775 | struct clk *clk1, *clk2; |
776 | unsigned long rate; | |
777 | int ret; | |
778 | ||
2c14736c | 779 | rk3188_common_clk_init(np); |
11ff376f HS |
780 | rockchip_clk_register_plls(rk3188_pll_clks, |
781 | ARRAY_SIZE(rk3188_pll_clks), | |
782 | RK3188_GRF_SOC_STATUS); | |
2c14736c HS |
783 | rockchip_clk_register_branches(rk3188_clk_branches, |
784 | ARRAY_SIZE(rk3188_clk_branches)); | |
0e5bdb3f HS |
785 | rockchip_clk_register_armclk(ARMCLK, "armclk", |
786 | mux_armclk_p, ARRAY_SIZE(mux_armclk_p), | |
787 | &rk3188_cpuclk_data, rk3188_cpuclk_rates, | |
788 | ARRAY_SIZE(rk3188_cpuclk_rates)); | |
f5f7004f HS |
789 | |
790 | /* reparent aclk_cpu_pre from apll */ | |
791 | clk1 = __clk_lookup("aclk_cpu_pre"); | |
792 | clk2 = __clk_lookup("gpll"); | |
793 | if (clk1 && clk2) { | |
794 | rate = clk_get_rate(clk1); | |
795 | ||
796 | ret = clk_set_parent(clk1, clk2); | |
797 | if (ret < 0) | |
798 | pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n", | |
799 | __func__); | |
800 | ||
801 | clk_set_rate(clk1, rate); | |
802 | } else { | |
803 | pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n", | |
804 | __func__); | |
805 | } | |
bb0f7361 HS |
806 | |
807 | rockchip_clk_protect_critical(rk3188_critical_clocks, | |
808 | ARRAY_SIZE(rk3188_critical_clocks)); | |
2c14736c HS |
809 | } |
810 | CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init); | |
811 | ||
812 | static void __init rk3188_clk_init(struct device_node *np) | |
813 | { | |
814 | int i; | |
815 | ||
816 | for (i = 0; i < ARRAY_SIZE(rk3188_pll_clks); i++) { | |
817 | struct rockchip_pll_clock *pll = &rk3188_pll_clks[i]; | |
818 | struct rockchip_pll_rate_table *rate; | |
819 | ||
820 | if (!pll->rate_table) | |
821 | continue; | |
822 | ||
823 | rate = pll->rate_table; | |
824 | while (rate->rate > 0) { | |
2bbfe001 | 825 | rate->nb = 1; |
2c14736c HS |
826 | rate++; |
827 | } | |
828 | } | |
829 | ||
830 | rk3188a_clk_init(np); | |
831 | } | |
832 | CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru", rk3188_clk_init); |