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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
307a2e9a JC |
2 | /* |
3 | * Copyright (c) 2015 Rockchip Electronics Co. Ltd. | |
4 | * Author: Xing Zheng <zhengxing@rock-chips.com> | |
5 | * Jeffy Chen <jeffy.chen@rock-chips.com> | |
307a2e9a JC |
6 | */ |
7 | ||
8 | #include <linux/clk-provider.h> | |
62e59c4e | 9 | #include <linux/io.h> |
307a2e9a JC |
10 | #include <linux/of.h> |
11 | #include <linux/of_address.h> | |
12 | #include <linux/syscore_ops.h> | |
13 | #include <dt-bindings/clock/rk3228-cru.h> | |
14 | #include "clk.h" | |
15 | ||
16 | #define RK3228_GRF_SOC_STATUS0 0x480 | |
17 | ||
18 | enum rk3228_plls { | |
19 | apll, dpll, cpll, gpll, | |
20 | }; | |
21 | ||
22 | static struct rockchip_pll_rate_table rk3228_pll_rates[] = { | |
23 | /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ | |
24 | RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), | |
25 | RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), | |
26 | RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), | |
27 | RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), | |
28 | RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), | |
29 | RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), | |
30 | RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), | |
31 | RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), | |
32 | RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), | |
33 | RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), | |
34 | RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), | |
35 | RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), | |
36 | RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), | |
37 | RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), | |
38 | RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), | |
39 | RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), | |
40 | RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), | |
41 | RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), | |
42 | RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), | |
43 | RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), | |
44 | RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), | |
45 | RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), | |
46 | RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), | |
47 | RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), | |
48 | RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), | |
49 | RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), | |
50 | RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), | |
51 | RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), | |
52 | RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), | |
53 | RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), | |
54 | RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), | |
55 | RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), | |
56 | RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), | |
57 | RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), | |
58 | RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), | |
59 | RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), | |
60 | RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), | |
61 | RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), | |
62 | RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), | |
63 | RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), | |
64 | RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), | |
65 | RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), | |
66 | { /* sentinel */ }, | |
67 | }; | |
68 | ||
69 | #define RK3228_DIV_CPU_MASK 0x1f | |
70 | #define RK3228_DIV_CPU_SHIFT 8 | |
71 | ||
72 | #define RK3228_DIV_PERI_MASK 0xf | |
73 | #define RK3228_DIV_PERI_SHIFT 0 | |
74 | #define RK3228_DIV_ACLK_MASK 0x7 | |
75 | #define RK3228_DIV_ACLK_SHIFT 4 | |
76 | #define RK3228_DIV_HCLK_MASK 0x3 | |
77 | #define RK3228_DIV_HCLK_SHIFT 8 | |
78 | #define RK3228_DIV_PCLK_MASK 0x7 | |
79 | #define RK3228_DIV_PCLK_SHIFT 12 | |
80 | ||
f88b8e73 | 81 | #define RK3228_CLKSEL1(_core_aclk_div, _core_peri_div) \ |
307a2e9a JC |
82 | { \ |
83 | .reg = RK2928_CLKSEL_CON(1), \ | |
84 | .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \ | |
f88b8e73 EZ |
85 | RK3228_DIV_PERI_SHIFT) | \ |
86 | HIWORD_UPDATE(_core_aclk_div, RK3228_DIV_ACLK_MASK, \ | |
87 | RK3228_DIV_ACLK_SHIFT), \ | |
88 | } | |
307a2e9a | 89 | |
f88b8e73 EZ |
90 | #define RK3228_CPUCLK_RATE(_prate, _core_aclk_div, _core_peri_div) \ |
91 | { \ | |
92 | .prate = _prate, \ | |
93 | .divs = { \ | |
94 | RK3228_CLKSEL1(_core_aclk_div, _core_peri_div), \ | |
95 | }, \ | |
307a2e9a JC |
96 | } |
97 | ||
98 | static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = { | |
f88b8e73 EZ |
99 | RK3228_CPUCLK_RATE(1800000000, 1, 7), |
100 | RK3228_CPUCLK_RATE(1704000000, 1, 7), | |
101 | RK3228_CPUCLK_RATE(1608000000, 1, 7), | |
102 | RK3228_CPUCLK_RATE(1512000000, 1, 7), | |
103 | RK3228_CPUCLK_RATE(1488000000, 1, 5), | |
104 | RK3228_CPUCLK_RATE(1416000000, 1, 5), | |
105 | RK3228_CPUCLK_RATE(1392000000, 1, 5), | |
106 | RK3228_CPUCLK_RATE(1296000000, 1, 5), | |
107 | RK3228_CPUCLK_RATE(1200000000, 1, 5), | |
108 | RK3228_CPUCLK_RATE(1104000000, 1, 5), | |
109 | RK3228_CPUCLK_RATE(1008000000, 1, 5), | |
110 | RK3228_CPUCLK_RATE(912000000, 1, 5), | |
111 | RK3228_CPUCLK_RATE(816000000, 1, 3), | |
112 | RK3228_CPUCLK_RATE(696000000, 1, 3), | |
113 | RK3228_CPUCLK_RATE(600000000, 1, 3), | |
114 | RK3228_CPUCLK_RATE(408000000, 1, 1), | |
115 | RK3228_CPUCLK_RATE(312000000, 1, 1), | |
116 | RK3228_CPUCLK_RATE(216000000, 1, 1), | |
117 | RK3228_CPUCLK_RATE(96000000, 1, 1), | |
307a2e9a JC |
118 | }; |
119 | ||
120 | static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = { | |
121 | .core_reg = RK2928_CLKSEL_CON(0), | |
122 | .div_core_shift = 0, | |
123 | .div_core_mask = 0x1f, | |
268aebaa XZ |
124 | .mux_core_alt = 1, |
125 | .mux_core_main = 0, | |
307a2e9a | 126 | .mux_core_shift = 6, |
268aebaa | 127 | .mux_core_mask = 0x1, |
307a2e9a JC |
128 | }; |
129 | ||
130 | PNAME(mux_pll_p) = { "clk_24m", "xin24m" }; | |
131 | ||
132 | PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; | |
133 | PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; | |
134 | PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" }; | |
135 | PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" }; | |
136 | PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" }; | |
137 | PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" }; | |
138 | ||
139 | PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" }; | |
140 | PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" }; | |
141 | PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" }; | |
142 | PNAME(mux_sclk_hdmi_cec_p) = { "cpll", "gpll", "xin24m" }; | |
143 | PNAME(mux_aclk_peri_src_p) = { "cpll_peri", "gpll_peri", "hdmiphy_peri" }; | |
144 | PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" }; | |
145 | PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" }; | |
146 | ||
147 | PNAME(mux_sclk_rga_p) = { "gpll", "cpll", "sclk_rga_src" }; | |
148 | ||
149 | PNAME(mux_sclk_vop_src_p) = { "gpll_vop", "cpll_vop" }; | |
150 | PNAME(mux_dclk_vop_p) = { "hdmiphy", "sclk_vop_pre" }; | |
151 | ||
152 | PNAME(mux_i2s0_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; | |
153 | PNAME(mux_i2s1_pre_p) = { "i2s1_src", "i2s1_frac", "ext_i2s", "xin12m" }; | |
154 | PNAME(mux_i2s_out_p) = { "i2s1_pre", "xin12m" }; | |
155 | PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; | |
156 | PNAME(mux_sclk_spdif_p) = { "sclk_spdif_src", "spdif_frac", "xin12m" }; | |
157 | ||
158 | PNAME(mux_aclk_gpu_pre_p) = { "cpll_gpu", "gpll_gpu", "hdmiphy_gpu", "usb480m_gpu" }; | |
159 | ||
160 | PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; | |
161 | PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; | |
162 | PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; | |
163 | ||
09f68422 XZ |
164 | PNAME(mux_sclk_mac_extclk_p) = { "ext_gmac", "phy_50m_out" }; |
165 | PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_mac_extclk" }; | |
307a2e9a JC |
166 | PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" }; |
167 | ||
168 | static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = { | |
169 | [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), | |
170 | RK2928_MODE_CON, 0, 7, 0, rk3228_pll_rates), | |
171 | [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), | |
172 | RK2928_MODE_CON, 4, 6, 0, NULL), | |
173 | [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6), | |
174 | RK2928_MODE_CON, 8, 8, 0, NULL), | |
175 | [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9), | |
176 | RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates), | |
177 | }; | |
178 | ||
179 | #define MFLAGS CLK_MUX_HIWORD_MASK | |
180 | #define DFLAGS CLK_DIVIDER_HIWORD_MASK | |
181 | #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) | |
182 | ||
cb87df58 XZ |
183 | static struct rockchip_clk_branch rk3228_i2s0_fracmux __initdata = |
184 | MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT, | |
185 | RK2928_CLKSEL_CON(9), 8, 2, MFLAGS); | |
186 | ||
187 | static struct rockchip_clk_branch rk3228_i2s1_fracmux __initdata = | |
188 | MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT, | |
189 | RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); | |
190 | ||
191 | static struct rockchip_clk_branch rk3228_i2s2_fracmux __initdata = | |
192 | MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, | |
193 | RK2928_CLKSEL_CON(16), 8, 2, MFLAGS); | |
194 | ||
195 | static struct rockchip_clk_branch rk3228_spdif_fracmux __initdata = | |
196 | MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT, | |
197 | RK2928_CLKSEL_CON(6), 8, 2, MFLAGS); | |
198 | ||
199 | static struct rockchip_clk_branch rk3228_uart0_fracmux __initdata = | |
200 | MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, | |
201 | RK2928_CLKSEL_CON(13), 8, 2, MFLAGS); | |
202 | ||
203 | static struct rockchip_clk_branch rk3228_uart1_fracmux __initdata = | |
204 | MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, | |
205 | RK2928_CLKSEL_CON(14), 8, 2, MFLAGS); | |
206 | ||
207 | static struct rockchip_clk_branch rk3228_uart2_fracmux __initdata = | |
208 | MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, | |
209 | RK2928_CLKSEL_CON(15), 8, 2, MFLAGS); | |
210 | ||
307a2e9a JC |
211 | static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { |
212 | /* | |
213 | * Clock-Architecture Diagram 1 | |
214 | */ | |
215 | ||
216 | DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, | |
217 | RK2928_CLKSEL_CON(4), 8, 5, DFLAGS), | |
218 | ||
219 | /* PD_DDR */ | |
220 | GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, | |
221 | RK2928_CLKGATE_CON(0), 2, GFLAGS), | |
222 | GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, | |
223 | RK2928_CLKGATE_CON(0), 2, GFLAGS), | |
224 | GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, | |
225 | RK2928_CLKGATE_CON(0), 2, GFLAGS), | |
226 | COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, | |
227 | RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO, | |
228 | RK2928_CLKGATE_CON(7), 1, GFLAGS), | |
229 | GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED, | |
230 | RK2928_CLKGATE_CON(8), 5, GFLAGS), | |
36714529 | 231 | FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4, |
307a2e9a JC |
232 | RK2928_CLKGATE_CON(7), 0, GFLAGS), |
233 | ||
234 | /* PD_CORE */ | |
235 | GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, | |
236 | RK2928_CLKGATE_CON(0), 6, GFLAGS), | |
237 | GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, | |
238 | RK2928_CLKGATE_CON(0), 6, GFLAGS), | |
239 | GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, | |
240 | RK2928_CLKGATE_CON(0), 6, GFLAGS), | |
241 | COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, | |
242 | RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, | |
243 | RK2928_CLKGATE_CON(4), 1, GFLAGS), | |
244 | COMPOSITE_NOMUX(0, "armcore", "armclk", CLK_IGNORE_UNUSED, | |
245 | RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, | |
246 | RK2928_CLKGATE_CON(4), 0, GFLAGS), | |
247 | ||
248 | /* PD_MISC */ | |
249 | MUX(0, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT, | |
250 | RK2928_MISC_CON, 13, 1, MFLAGS), | |
251 | MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT, | |
252 | RK2928_MISC_CON, 14, 1, MFLAGS), | |
253 | MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT, | |
254 | RK2928_MISC_CON, 15, 1, MFLAGS), | |
255 | ||
256 | /* PD_BUS */ | |
257 | GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED, | |
258 | RK2928_CLKGATE_CON(0), 1, GFLAGS), | |
259 | GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED, | |
260 | RK2928_CLKGATE_CON(0), 1, GFLAGS), | |
261 | GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED, | |
262 | RK2928_CLKGATE_CON(0), 1, GFLAGS), | |
263 | COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0, | |
264 | RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS), | |
5d259562 | 265 | GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0, |
307a2e9a | 266 | RK2928_CLKGATE_CON(6), 0, GFLAGS), |
5d259562 | 267 | COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0, |
307a2e9a JC |
268 | RK2928_CLKSEL_CON(1), 8, 2, DFLAGS, |
269 | RK2928_CLKGATE_CON(6), 1, GFLAGS), | |
270 | COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0, | |
271 | RK2928_CLKSEL_CON(1), 12, 3, DFLAGS, | |
272 | RK2928_CLKGATE_CON(6), 2, GFLAGS), | |
5d259562 | 273 | GATE(PCLK_CPU, "pclk_cpu", "pclk_bus_src", 0, |
307a2e9a JC |
274 | RK2928_CLKGATE_CON(6), 3, GFLAGS), |
275 | GATE(0, "pclk_phy_pre", "pclk_bus_src", 0, | |
276 | RK2928_CLKGATE_CON(6), 4, GFLAGS), | |
277 | GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0, | |
278 | RK2928_CLKGATE_CON(6), 13, GFLAGS), | |
279 | ||
280 | /* PD_VIDEO */ | |
5d259562 | 281 | COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, |
307a2e9a JC |
282 | RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS, |
283 | RK2928_CLKGATE_CON(3), 11, GFLAGS), | |
5d259562 | 284 | FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4, |
307a2e9a JC |
285 | RK2928_CLKGATE_CON(4), 4, GFLAGS), |
286 | ||
5d259562 | 287 | COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, |
307a2e9a JC |
288 | RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, |
289 | RK2928_CLKGATE_CON(3), 2, GFLAGS), | |
5d259562 | 290 | FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4, |
307a2e9a JC |
291 | RK2928_CLKGATE_CON(4), 5, GFLAGS), |
292 | ||
5d259562 | 293 | COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0, |
307a2e9a JC |
294 | RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS, |
295 | RK2928_CLKGATE_CON(3), 3, GFLAGS), | |
296 | ||
5d259562 | 297 | COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_pll_src_4plls_p, 0, |
307a2e9a JC |
298 | RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, 8, 5, DFLAGS, |
299 | RK2928_CLKGATE_CON(3), 4, GFLAGS), | |
300 | ||
301 | /* PD_VIO */ | |
5d259562 | 302 | COMPOSITE(ACLK_IEP_PRE, "aclk_iep_pre", mux_pll_src_4plls_p, 0, |
307a2e9a JC |
303 | RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, 0, 5, DFLAGS, |
304 | RK2928_CLKGATE_CON(3), 0, GFLAGS), | |
5d259562 | 305 | DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_iep_pre", 0, |
307a2e9a JC |
306 | RK2928_CLKSEL_CON(2), 0, 5, DFLAGS), |
307 | ||
5d259562 | 308 | COMPOSITE(ACLK_HDCP_PRE, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0, |
307a2e9a JC |
309 | RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS, |
310 | RK2928_CLKGATE_CON(1), 4, GFLAGS), | |
311 | ||
312 | MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0, | |
313 | RK2928_CLKSEL_CON(33), 13, 2, MFLAGS), | |
5d259562 | 314 | COMPOSITE_NOMUX(ACLK_RGA_PRE, "aclk_rga_pre", "sclk_rga_src", 0, |
307a2e9a JC |
315 | RK2928_CLKSEL_CON(33), 8, 5, DFLAGS, |
316 | RK2928_CLKGATE_CON(1), 2, GFLAGS), | |
5d259562 | 317 | COMPOSITE(SCLK_RGA, "sclk_rga", mux_sclk_rga_p, 0, |
307a2e9a JC |
318 | RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS, |
319 | RK2928_CLKGATE_CON(3), 6, GFLAGS), | |
320 | ||
5d259562 | 321 | COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_pll_src_4plls_p, 0, |
307a2e9a JC |
322 | RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, 0, 5, DFLAGS, |
323 | RK2928_CLKGATE_CON(1), 1, GFLAGS), | |
324 | ||
5d259562 | 325 | COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_3plls_p, 0, |
307a2e9a JC |
326 | RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS, |
327 | RK2928_CLKGATE_CON(3), 5, GFLAGS), | |
328 | ||
bdc7deec | 329 | GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0, |
307a2e9a JC |
330 | RK2928_CLKGATE_CON(3), 7, GFLAGS), |
331 | ||
5d259562 | 332 | COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0, |
307a2e9a JC |
333 | RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, 0, 14, DFLAGS, |
334 | RK2928_CLKGATE_CON(3), 8, GFLAGS), | |
335 | ||
336 | /* PD_PERI */ | |
337 | GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED, | |
338 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
339 | GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED, | |
340 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
341 | GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED, | |
342 | RK2928_CLKGATE_CON(2), 0, GFLAGS), | |
343 | COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, 0, | |
344 | RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS), | |
345 | COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0, | |
346 | RK2928_CLKSEL_CON(10), 12, 3, DFLAGS, | |
347 | RK2928_CLKGATE_CON(5), 2, GFLAGS), | |
348 | COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0, | |
349 | RK2928_CLKSEL_CON(10), 8, 2, DFLAGS, | |
350 | RK2928_CLKGATE_CON(5), 1, GFLAGS), | |
351 | GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, | |
352 | RK2928_CLKGATE_CON(5), 0, GFLAGS), | |
353 | ||
354 | GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0, | |
355 | RK2928_CLKGATE_CON(6), 5, GFLAGS), | |
356 | GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0, | |
357 | RK2928_CLKGATE_CON(6), 6, GFLAGS), | |
358 | GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0, | |
359 | RK2928_CLKGATE_CON(6), 7, GFLAGS), | |
360 | GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0, | |
361 | RK2928_CLKGATE_CON(6), 8, GFLAGS), | |
362 | GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0, | |
363 | RK2928_CLKGATE_CON(6), 9, GFLAGS), | |
364 | GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0, | |
365 | RK2928_CLKGATE_CON(6), 10, GFLAGS), | |
366 | ||
5d259562 | 367 | COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0, |
307a2e9a JC |
368 | RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, 0, 5, DFLAGS, |
369 | RK2928_CLKGATE_CON(2), 7, GFLAGS), | |
370 | ||
5d259562 | 371 | COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_2plls_p, 0, |
307a2e9a JC |
372 | RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS, |
373 | RK2928_CLKGATE_CON(2), 6, GFLAGS), | |
374 | ||
5d259562 | 375 | GATE(SCLK_HSADC, "sclk_hsadc", "ext_hsadc", 0, |
67de7901 | 376 | RK2928_CLKGATE_CON(10), 12, GFLAGS), |
307a2e9a | 377 | |
5d259562 | 378 | COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, |
307a2e9a JC |
379 | RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS, |
380 | RK2928_CLKGATE_CON(2), 15, GFLAGS), | |
381 | ||
4b0556a4 | 382 | COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, |
307a2e9a JC |
383 | RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS, |
384 | RK2928_CLKGATE_CON(2), 11, GFLAGS), | |
385 | ||
fe53230c | 386 | COMPOSITE_NODIV(SCLK_SDIO_SRC, "sclk_sdio_src", mux_mmc_src_p, 0, |
307a2e9a JC |
387 | RK2928_CLKSEL_CON(11), 10, 2, MFLAGS, |
388 | RK2928_CLKGATE_CON(2), 13, GFLAGS), | |
389 | DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, | |
390 | RK2928_CLKSEL_CON(12), 0, 8, DFLAGS), | |
391 | ||
392 | COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, | |
393 | RK2928_CLKSEL_CON(11), 12, 2, MFLAGS, | |
394 | RK2928_CLKGATE_CON(2), 14, GFLAGS), | |
395 | DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, | |
396 | RK2928_CLKSEL_CON(12), 8, 8, DFLAGS), | |
397 | ||
398 | /* | |
399 | * Clock-Architecture Diagram 2 | |
400 | */ | |
401 | ||
402 | GATE(0, "gpll_vop", "gpll", 0, | |
403 | RK2928_CLKGATE_CON(3), 1, GFLAGS), | |
404 | GATE(0, "cpll_vop", "cpll", 0, | |
405 | RK2928_CLKGATE_CON(3), 1, GFLAGS), | |
406 | MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0, | |
407 | RK2928_CLKSEL_CON(27), 0, 1, MFLAGS), | |
bdc7deec | 408 | DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0, |
307a2e9a JC |
409 | RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), |
410 | DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, | |
411 | RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), | |
0a9d4ac0 | 412 | MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0, |
307a2e9a JC |
413 | RK2928_CLKSEL_CON(27), 1, 1, MFLAGS), |
414 | ||
36714529 HS |
415 | FACTOR(0, "xin12m", "xin24m", 0, 1, 2), |
416 | ||
307a2e9a JC |
417 | COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, |
418 | RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS, | |
419 | RK2928_CLKGATE_CON(0), 3, GFLAGS), | |
cb87df58 | 420 | COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, |
67de7901 | 421 | RK2928_CLKSEL_CON(8), 0, |
cb87df58 XZ |
422 | RK2928_CLKGATE_CON(0), 4, GFLAGS, |
423 | &rk3228_i2s0_fracmux), | |
424 | GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, | |
307a2e9a JC |
425 | RK2928_CLKGATE_CON(0), 5, GFLAGS), |
426 | ||
427 | COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, | |
428 | RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS, | |
429 | RK2928_CLKGATE_CON(0), 10, GFLAGS), | |
cb87df58 | 430 | COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, |
67de7901 | 431 | RK2928_CLKSEL_CON(7), 0, |
cb87df58 XZ |
432 | RK2928_CLKGATE_CON(0), 11, GFLAGS, |
433 | &rk3228_i2s1_fracmux), | |
434 | GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, | |
307a2e9a JC |
435 | RK2928_CLKGATE_CON(0), 14, GFLAGS), |
436 | COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0, | |
437 | RK2928_CLKSEL_CON(3), 12, 1, MFLAGS, | |
438 | RK2928_CLKGATE_CON(0), 13, GFLAGS), | |
439 | ||
440 | COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, | |
441 | RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS, | |
442 | RK2928_CLKGATE_CON(0), 7, GFLAGS), | |
cb87df58 | 443 | COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, |
67de7901 | 444 | RK2928_CLKSEL_CON(30), 0, |
cb87df58 XZ |
445 | RK2928_CLKGATE_CON(0), 8, GFLAGS, |
446 | &rk3228_i2s2_fracmux), | |
447 | GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT, | |
307a2e9a JC |
448 | RK2928_CLKGATE_CON(0), 9, GFLAGS), |
449 | ||
450 | COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0, | |
451 | RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS, | |
452 | RK2928_CLKGATE_CON(2), 10, GFLAGS), | |
cb87df58 | 453 | COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, |
67de7901 | 454 | RK2928_CLKSEL_CON(20), 0, |
cb87df58 XZ |
455 | RK2928_CLKGATE_CON(2), 12, GFLAGS, |
456 | &rk3228_spdif_fracmux), | |
307a2e9a | 457 | |
f18c0994 | 458 | GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED, |
307a2e9a JC |
459 | RK2928_CLKGATE_CON(1), 3, GFLAGS), |
460 | ||
5d259562 | 461 | GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0, |
307a2e9a | 462 | RK2928_CLKGATE_CON(1), 5, GFLAGS), |
5d259562 | 463 | GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 0, |
307a2e9a JC |
464 | RK2928_CLKGATE_CON(1), 6, GFLAGS), |
465 | ||
a3cb9aa4 | 466 | COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0, |
307a2e9a JC |
467 | RK2928_CLKSEL_CON(24), 6, 10, DFLAGS, |
468 | RK2928_CLKGATE_CON(2), 8, GFLAGS), | |
469 | ||
470 | GATE(0, "cpll_gpu", "cpll", 0, | |
471 | RK2928_CLKGATE_CON(3), 13, GFLAGS), | |
472 | GATE(0, "gpll_gpu", "gpll", 0, | |
473 | RK2928_CLKGATE_CON(3), 13, GFLAGS), | |
474 | GATE(0, "hdmiphy_gpu", "hdmiphy", 0, | |
475 | RK2928_CLKGATE_CON(3), 13, GFLAGS), | |
476 | GATE(0, "usb480m_gpu", "usb480m", 0, | |
477 | RK2928_CLKGATE_CON(3), 13, GFLAGS), | |
478 | COMPOSITE_NOGATE(0, "aclk_gpu_pre", mux_aclk_gpu_pre_p, 0, | |
479 | RK2928_CLKSEL_CON(34), 5, 2, MFLAGS, 0, 5, DFLAGS), | |
480 | ||
481 | COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0, | |
482 | RK2928_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS, | |
483 | RK2928_CLKGATE_CON(2), 9, GFLAGS), | |
484 | ||
485 | /* PD_UART */ | |
486 | COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb480m_p, 0, | |
487 | RK2928_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS, | |
488 | RK2928_CLKGATE_CON(1), 8, GFLAGS), | |
489 | COMPOSITE(0, "uart1_src", mux_pll_src_cpll_gpll_usb480m_p, 0, | |
490 | RK2928_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS, | |
491 | RK2928_CLKGATE_CON(1), 10, GFLAGS), | |
492 | COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p, | |
493 | 0, RK2928_CLKSEL_CON(15), 12, 2, | |
494 | MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS), | |
cb87df58 | 495 | COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, |
307a2e9a | 496 | RK2928_CLKSEL_CON(17), 0, |
cb87df58 XZ |
497 | RK2928_CLKGATE_CON(1), 9, GFLAGS, |
498 | &rk3228_uart0_fracmux), | |
499 | COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, | |
307a2e9a | 500 | RK2928_CLKSEL_CON(18), 0, |
cb87df58 XZ |
501 | RK2928_CLKGATE_CON(1), 11, GFLAGS, |
502 | &rk3228_uart1_fracmux), | |
503 | COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, | |
307a2e9a | 504 | RK2928_CLKSEL_CON(19), 0, |
cb87df58 XZ |
505 | RK2928_CLKGATE_CON(1), 13, GFLAGS, |
506 | &rk3228_uart2_fracmux), | |
307a2e9a JC |
507 | |
508 | COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, | |
509 | RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS, | |
510 | RK2928_CLKGATE_CON(1), 0, GFLAGS), | |
511 | ||
6e3732a2 | 512 | COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_2plls_p, 0, |
307a2e9a JC |
513 | RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS, |
514 | RK2928_CLKGATE_CON(1), 7, GFLAGS), | |
6e3732a2 | 515 | MUX(SCLK_MAC_EXTCLK, "sclk_mac_extclk", mux_sclk_mac_extclk_p, 0, |
307a2e9a | 516 | RK2928_CLKSEL_CON(29), 10, 1, MFLAGS), |
6e3732a2 | 517 | MUX(SCLK_MAC, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0, |
307a2e9a | 518 | RK2928_CLKSEL_CON(5), 5, 1, MFLAGS), |
6e3732a2 | 519 | GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac_pre", 0, |
307a2e9a | 520 | RK2928_CLKGATE_CON(5), 4, GFLAGS), |
6e3732a2 | 521 | GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac_pre", 0, |
307a2e9a | 522 | RK2928_CLKGATE_CON(5), 3, GFLAGS), |
6e3732a2 | 523 | GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac_pre", 0, |
307a2e9a | 524 | RK2928_CLKGATE_CON(5), 5, GFLAGS), |
6e3732a2 | 525 | GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac_pre", 0, |
307a2e9a | 526 | RK2928_CLKGATE_CON(5), 6, GFLAGS), |
6e3732a2 | 527 | COMPOSITE(SCLK_MAC_PHY, "sclk_macphy", mux_sclk_macphy_p, 0, |
307a2e9a JC |
528 | RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS, |
529 | RK2928_CLKGATE_CON(5), 7, GFLAGS), | |
6e3732a2 | 530 | COMPOSITE(SCLK_MAC_OUT, "sclk_gmac_out", mux_pll_src_2plls_p, 0, |
307a2e9a JC |
531 | RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS, |
532 | RK2928_CLKGATE_CON(2), 2, GFLAGS), | |
533 | ||
534 | /* | |
535 | * Clock-Architecture Diagram 3 | |
536 | */ | |
537 | ||
538 | /* PD_VOP */ | |
5d259562 | 539 | GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS), |
307a2e9a | 540 | GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS), |
5d259562 | 541 | GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS), |
307a2e9a JC |
542 | GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS), |
543 | ||
0a9d4ac0 | 544 | GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS), |
307a2e9a JC |
545 | GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS), |
546 | ||
5d259562 | 547 | GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS), |
307a2e9a JC |
548 | GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS), |
549 | ||
5d259562 EZ |
550 | GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS), |
551 | GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS), | |
0a9d4ac0 | 552 | GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS), |
307a2e9a JC |
553 | GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS), |
554 | GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS), | |
555 | GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS), | |
5d259562 EZ |
556 | GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS), |
557 | GATE(HCLK_HDCP_MMU, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS), | |
bdc7deec | 558 | GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS), |
5d259562 EZ |
559 | GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS), |
560 | GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS), | |
307a2e9a JC |
561 | |
562 | /* PD_PERI */ | |
563 | GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS), | |
6e3732a2 | 564 | GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS), |
307a2e9a JC |
565 | |
566 | GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS), | |
567 | GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS), | |
568 | GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS), | |
569 | GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS), | |
5d259562 | 570 | GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS), |
307a2e9a | 571 | GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS), |
5d259562 | 572 | GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS), |
307a2e9a | 573 | GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS), |
5d259562 EZ |
574 | GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS), |
575 | GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS), | |
307a2e9a JC |
576 | GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS), |
577 | GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS), | |
578 | GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS), | |
579 | ||
6e3732a2 | 580 | GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS), |
307a2e9a JC |
581 | GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS), |
582 | ||
583 | /* PD_GPU */ | |
5d259562 | 584 | GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS), |
307a2e9a JC |
585 | GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS), |
586 | ||
587 | /* PD_BUS */ | |
588 | GATE(0, "sclk_initmem_mbist", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS), | |
589 | GATE(0, "aclk_initmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), | |
590 | GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS), | |
591 | GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS), | |
592 | ||
593 | GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS), | |
a45c072b XZ |
594 | GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS), |
595 | GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS), | |
596 | GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS), | |
597 | GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS), | |
5d259562 EZ |
598 | GATE(HCLK_TSP, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS), |
599 | GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS), | |
600 | GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS), | |
307a2e9a JC |
601 | |
602 | GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS), | |
603 | GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS), | |
604 | GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS), | |
605 | ||
5d259562 EZ |
606 | GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS), |
607 | GATE(PCLK_EFUSE_256, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS), | |
307a2e9a JC |
608 | GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS), |
609 | GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS), | |
610 | GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS), | |
611 | GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS), | |
612 | GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS), | |
613 | GATE(0, "pclk_stimer", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), | |
614 | GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS), | |
615 | GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS), | |
616 | GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS), | |
617 | GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS), | |
618 | GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 10, GFLAGS), | |
619 | GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 11, GFLAGS), | |
620 | GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS), | |
621 | GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS), | |
622 | GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS), | |
a3cb9aa4 | 623 | GATE(PCLK_TSADC, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS), |
307a2e9a JC |
624 | GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS), |
625 | GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS), | |
626 | GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS), | |
627 | GATE(0, "pclk_sim", "pclk_cpu", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS), | |
628 | ||
629 | GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS), | |
630 | GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS), | |
bdc7deec | 631 | GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS), |
307a2e9a JC |
632 | GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS), |
633 | GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS), | |
634 | ||
5d259562 | 635 | GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS), |
307a2e9a | 636 | GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS), |
5d259562 | 637 | GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS), |
307a2e9a | 638 | GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS), |
5d259562 | 639 | GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS), |
307a2e9a | 640 | GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS), |
5d259562 | 641 | GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS), |
307a2e9a JC |
642 | GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS), |
643 | ||
644 | /* PD_MMC */ | |
645 | MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3228_SDMMC_CON0, 1), | |
bb07698f | 646 | MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3228_SDMMC_CON1, 0), |
307a2e9a JC |
647 | |
648 | MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK3228_SDIO_CON0, 1), | |
bb07698f | 649 | MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK3228_SDIO_CON1, 0), |
307a2e9a JC |
650 | |
651 | MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3228_EMMC_CON0, 1), | |
bb07698f | 652 | MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3228_EMMC_CON1, 0), |
307a2e9a JC |
653 | }; |
654 | ||
655 | static const char *const rk3228_critical_clocks[] __initconst = { | |
656 | "aclk_cpu", | |
f18c0994 EZ |
657 | "pclk_cpu", |
658 | "hclk_cpu", | |
307a2e9a JC |
659 | "aclk_peri", |
660 | "hclk_peri", | |
661 | "pclk_peri", | |
f18c0994 EZ |
662 | "aclk_rga_noc", |
663 | "aclk_iep_noc", | |
664 | "aclk_vop_noc", | |
665 | "aclk_hdcp_noc", | |
666 | "hclk_vio_ahb_arbi", | |
667 | "hclk_vio_noc", | |
668 | "hclk_vop_noc", | |
669 | "hclk_host0_arb", | |
670 | "hclk_host1_arb", | |
671 | "hclk_host2_arb", | |
672 | "hclk_otg_pmu", | |
673 | "aclk_gpu_noc", | |
674 | "sclk_initmem_mbist", | |
675 | "aclk_initmem", | |
676 | "hclk_rom", | |
677 | "pclk_ddrupctl", | |
678 | "pclk_ddrmon", | |
679 | "pclk_msch_noc", | |
680 | "pclk_stimer", | |
681 | "pclk_ddrphy", | |
682 | "pclk_acodecphy", | |
683 | "pclk_phy_noc", | |
684 | "aclk_vpu_noc", | |
685 | "aclk_rkvdec_noc", | |
686 | "hclk_vpu_noc", | |
687 | "hclk_rkvdec_noc", | |
307a2e9a JC |
688 | }; |
689 | ||
690 | static void __init rk3228_clk_init(struct device_node *np) | |
691 | { | |
ef1d9fee | 692 | struct rockchip_clk_provider *ctx; |
307a2e9a | 693 | void __iomem *reg_base; |
307a2e9a JC |
694 | |
695 | reg_base = of_iomap(np, 0); | |
696 | if (!reg_base) { | |
697 | pr_err("%s: could not map cru region\n", __func__); | |
698 | return; | |
699 | } | |
700 | ||
ef1d9fee XZ |
701 | ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); |
702 | if (IS_ERR(ctx)) { | |
703 | pr_err("%s: rockchip clk init failed\n", __func__); | |
1d003eb0 | 704 | iounmap(reg_base); |
ef1d9fee XZ |
705 | return; |
706 | } | |
307a2e9a | 707 | |
ef1d9fee | 708 | rockchip_clk_register_plls(ctx, rk3228_pll_clks, |
307a2e9a JC |
709 | ARRAY_SIZE(rk3228_pll_clks), |
710 | RK3228_GRF_SOC_STATUS0); | |
ef1d9fee | 711 | rockchip_clk_register_branches(ctx, rk3228_clk_branches, |
307a2e9a JC |
712 | ARRAY_SIZE(rk3228_clk_branches)); |
713 | rockchip_clk_protect_critical(rk3228_critical_clocks, | |
714 | ARRAY_SIZE(rk3228_critical_clocks)); | |
715 | ||
ef1d9fee | 716 | rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", |
307a2e9a JC |
717 | mux_armclk_p, ARRAY_SIZE(mux_armclk_p), |
718 | &rk3228_cpuclk_data, rk3228_cpuclk_rates, | |
719 | ARRAY_SIZE(rk3228_cpuclk_rates)); | |
720 | ||
721 | rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0), | |
722 | ROCKCHIP_SOFTRST_HIWORD_MASK); | |
723 | ||
ef1d9fee XZ |
724 | rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, NULL); |
725 | ||
726 | rockchip_clk_of_add_provider(np, ctx); | |
307a2e9a JC |
727 | } |
728 | CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init); |