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Merge tag 'powerpc-5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[mirror_ubuntu-hirsute-kernel.git] / drivers / clk / rockchip / clk-rk3328.c
CommitLineData
fe3511ad
EZ		 1/*
2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Elaine <zhangqing@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
62e59c4e 17#include <linux/io.h>
fe3511ad
EZ		 18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/syscore_ops.h>
21#include <dt-bindings/clock/rk3328-cru.h>
22#include "clk.h"
23
9bb4db62 24#define RK3328_GRF_SOC_CON4 0x410
fe3511ad
EZ		 25#define RK3328_GRF_SOC_STATUS0 0x480
26#define RK3328_GRF_MAC_CON1 0x904
27#define RK3328_GRF_MAC_CON2 0x908
28
29enum rk3328_plls {
30 apll, dpll, cpll, gpll, npll,
31};
32
33static struct rockchip_pll_rate_table rk3328_pll_rates[] = {
34 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
35 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
55 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
56 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
57 RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
58 RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
59 RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
60 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
61 RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
62 RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
63 RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
64 RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
65 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
66 RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
67 RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
68 RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
69 RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
70 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
71 RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
72 RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
73 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
74 RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
75 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
76 RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
77 { /* sentinel */ },
78};
79
80static struct rockchip_pll_rate_table rk3328_pll_frac_rates[] = {
81 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
a0e447b0 82 RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134218),
fe3511ad 83 /* vco = 1016064000 */
a0e447b0 84 RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671089),
fe3511ad 85 /* vco = 983040000 */
a0e447b0 86 RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671089),
fe3511ad 87 /* vco = 983040000 */
a0e447b0 88 RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671089),
fe3511ad 89 /* vco = 860156000 */
a0e447b0 90 RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797895),
fe3511ad 91 /* vco = 903168000 */
a0e447b0 92 RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066330),
fe3511ad
EZ		 93 /* vco = 819200000 */
94 { /* sentinel */ },
95};
96
97#define RK3328_DIV_ACLKM_MASK 0x7
98#define RK3328_DIV_ACLKM_SHIFT 4
99#define RK3328_DIV_PCLK_DBG_MASK 0xf
100#define RK3328_DIV_PCLK_DBG_SHIFT 0
101
102#define RK3328_CLKSEL1(_aclk_core, _pclk_dbg) \
103{ \
104 .reg = RK3328_CLKSEL_CON(1), \
105 .val = HIWORD_UPDATE(_aclk_core, RK3328_DIV_ACLKM_MASK, \
106 RK3328_DIV_ACLKM_SHIFT) | \
107 HIWORD_UPDATE(_pclk_dbg, RK3328_DIV_PCLK_DBG_MASK, \
108 RK3328_DIV_PCLK_DBG_SHIFT), \
109}
110
111#define RK3328_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
112{ \
113 .prate = _prate, \
114 .divs = { \
115 RK3328_CLKSEL1(_aclk_core, _pclk_dbg), \
116 }, \
117}
118
119static struct rockchip_cpuclk_rate_table rk3328_cpuclk_rates[] __initdata = {
120 RK3328_CPUCLK_RATE(1800000000, 1, 7),
121 RK3328_CPUCLK_RATE(1704000000, 1, 7),
122 RK3328_CPUCLK_RATE(1608000000, 1, 7),
123 RK3328_CPUCLK_RATE(1512000000, 1, 7),
124 RK3328_CPUCLK_RATE(1488000000, 1, 5),
125 RK3328_CPUCLK_RATE(1416000000, 1, 5),
126 RK3328_CPUCLK_RATE(1392000000, 1, 5),
127 RK3328_CPUCLK_RATE(1296000000, 1, 5),
128 RK3328_CPUCLK_RATE(1200000000, 1, 5),
129 RK3328_CPUCLK_RATE(1104000000, 1, 5),
130 RK3328_CPUCLK_RATE(1008000000, 1, 5),
131 RK3328_CPUCLK_RATE(912000000, 1, 5),
132 RK3328_CPUCLK_RATE(816000000, 1, 3),
133 RK3328_CPUCLK_RATE(696000000, 1, 3),
134 RK3328_CPUCLK_RATE(600000000, 1, 3),
135 RK3328_CPUCLK_RATE(408000000, 1, 1),
136 RK3328_CPUCLK_RATE(312000000, 1, 1),
137 RK3328_CPUCLK_RATE(216000000, 1, 1),
138 RK3328_CPUCLK_RATE(96000000, 1, 1),
139};
140
141static const struct rockchip_cpuclk_reg_data rk3328_cpuclk_data = {
142 .core_reg = RK3328_CLKSEL_CON(0),
143 .div_core_shift = 0,
144 .div_core_mask = 0x1f,
145 .mux_core_alt = 1,
146 .mux_core_main = 3,
147 .mux_core_shift = 6,
148 .mux_core_mask = 0x3,
149};
150
151PNAME(mux_pll_p) = { "xin24m" };
152
153PNAME(mux_2plls_p) = { "cpll", "gpll" };
154PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
155PNAME(mux_cpll_gpll_apll_p) = { "cpll", "gpll", "apll" };
156PNAME(mux_2plls_xin24m_p) = { "cpll", "gpll", "xin24m" };
157PNAME(mux_2plls_hdmiphy_p) = { "cpll", "gpll",
158 "dummy_hdmiphy" };
159PNAME(mux_4plls_p) = { "cpll", "gpll",
160 "dummy_hdmiphy",
161 "usb480m" };
162PNAME(mux_2plls_u480m_p) = { "cpll", "gpll",
163 "usb480m" };
164PNAME(mux_2plls_24m_u480m_p) = { "cpll", "gpll",
165 "xin24m", "usb480m" };
166
167PNAME(mux_ddrphy_p) = { "dpll", "apll", "cpll" };
168PNAME(mux_armclk_p) = { "apll_core",
169 "gpll_core",
170 "dpll_core",
171 "npll_core"};
172PNAME(mux_hdmiphy_p) = { "hdmi_phy", "xin24m" };
173PNAME(mux_usb480m_p) = { "usb480m_phy",
174 "xin24m" };
175
176PNAME(mux_i2s0_p) = { "clk_i2s0_div",
177 "clk_i2s0_frac",
178 "xin12m",
179 "xin12m" };
180PNAME(mux_i2s1_p) = { "clk_i2s1_div",
181 "clk_i2s1_frac",
182 "clkin_i2s1",
183 "xin12m" };
184PNAME(mux_i2s2_p) = { "clk_i2s2_div",
185 "clk_i2s2_frac",
186 "clkin_i2s2",
187 "xin12m" };
188PNAME(mux_i2s1out_p) = { "clk_i2s1", "xin12m"};
189PNAME(mux_i2s2out_p) = { "clk_i2s2", "xin12m" };
190PNAME(mux_spdif_p) = { "clk_spdif_div",
191 "clk_spdif_frac",
192 "xin12m",
193 "xin12m" };
194PNAME(mux_uart0_p) = { "clk_uart0_div",
195 "clk_uart0_frac",
196 "xin24m" };
197PNAME(mux_uart1_p) = { "clk_uart1_div",
198 "clk_uart1_frac",
199 "xin24m" };
200PNAME(mux_uart2_p) = { "clk_uart2_div",
201 "clk_uart2_frac",
202 "xin24m" };
203
204PNAME(mux_sclk_cif_p) = { "clk_cif_src",
205 "xin24m" };
206PNAME(mux_dclk_lcdc_p) = { "hdmiphy",
207 "dclk_lcdc_src" };
208PNAME(mux_aclk_peri_pre_p) = { "cpll_peri",
209 "gpll_peri",
210 "hdmiphy_peri" };
211PNAME(mux_ref_usb3otg_src_p) = { "xin24m",
212 "clk_usb3otg_ref" };
213PNAME(mux_xin24m_32k_p) = { "xin24m",
214 "clk_rtc32k" };
215PNAME(mux_mac2io_src_p) = { "clk_mac2io_src",
216 "gmac_clkin" };
217PNAME(mux_mac2phy_src_p) = { "clk_mac2phy_src",
218 "phy_50m_out" };
9bb4db62
EZ		 219PNAME(mux_mac2io_ext_p) = { "clk_mac2io",
220 "gmac_clkin" };
fe3511ad
EZ		 221
222static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = {
223 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
224 0, RK3328_PLL_CON(0),
225 RK3328_MODE_CON, 0, 4, 0, rk3328_pll_frac_rates),
226 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
227 0, RK3328_PLL_CON(8),
228 RK3328_MODE_CON, 4, 3, 0, NULL),
229 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
230 0, RK3328_PLL_CON(16),
231 RK3328_MODE_CON, 8, 2, 0, rk3328_pll_rates),
232 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
233 0, RK3328_PLL_CON(24),
234 RK3328_MODE_CON, 12, 1, 0, rk3328_pll_frac_rates),
235 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
236 0, RK3328_PLL_CON(40),
237 RK3328_MODE_CON, 1, 0, 0, rk3328_pll_rates),
238};
239
240#define MFLAGS CLK_MUX_HIWORD_MASK
241#define DFLAGS CLK_DIVIDER_HIWORD_MASK
242#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
243
244static struct rockchip_clk_branch rk3328_i2s0_fracmux __initdata =
245 MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
246 RK3328_CLKSEL_CON(6), 8, 2, MFLAGS);
247
248static struct rockchip_clk_branch rk3328_i2s1_fracmux __initdata =
249 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT,
250 RK3328_CLKSEL_CON(8), 8, 2, MFLAGS);
251
252static struct rockchip_clk_branch rk3328_i2s2_fracmux __initdata =
253 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
254 RK3328_CLKSEL_CON(10), 8, 2, MFLAGS);
255
256static struct rockchip_clk_branch rk3328_spdif_fracmux __initdata =
257 MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, CLK_SET_RATE_PARENT,
258 RK3328_CLKSEL_CON(12), 8, 2, MFLAGS);
259
260static struct rockchip_clk_branch rk3328_uart0_fracmux __initdata =
261 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
262 RK3328_CLKSEL_CON(14), 8, 2, MFLAGS);
263
264static struct rockchip_clk_branch rk3328_uart1_fracmux __initdata =
265 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
266 RK3328_CLKSEL_CON(16), 8, 2, MFLAGS);
267
268static struct rockchip_clk_branch rk3328_uart2_fracmux __initdata =
269 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
270 RK3328_CLKSEL_CON(18), 8, 2, MFLAGS);
271
272static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
273 /*
274 * Clock-Architecture Diagram 1
275 */
276
277 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
278 RK3328_CLKSEL_CON(2), 8, 5, DFLAGS),
279 COMPOSITE(SCLK_RTC32K, "clk_rtc32k", mux_2plls_xin24m_p, 0,
280 RK3328_CLKSEL_CON(38), 14, 2, MFLAGS, 0, 14, DFLAGS,
281 RK3328_CLKGATE_CON(0), 11, GFLAGS),
282
283 /* PD_MISC */
284 MUX(HDMIPHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
285 RK3328_MISC_CON, 13, 1, MFLAGS),
286 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
287 RK3328_MISC_CON, 15, 1, MFLAGS),
288
289 /*
290 * Clock-Architecture Diagram 2
291 */
292
293 /* PD_CORE */
294 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
295 RK3328_CLKGATE_CON(0), 0, GFLAGS),
296 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
297 RK3328_CLKGATE_CON(0), 2, GFLAGS),
298 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
299 RK3328_CLKGATE_CON(0), 1, GFLAGS),
300 GATE(0, "npll_core", "npll", CLK_IGNORE_UNUSED,
301 RK3328_CLKGATE_CON(0), 12, GFLAGS),
302 COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
303 RK3328_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
304 RK3328_CLKGATE_CON(7), 0, GFLAGS),
305 COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
306 RK3328_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
307 RK3328_CLKGATE_CON(7), 1, GFLAGS),
51a70dbf 308 GATE(0, "aclk_core_niu", "aclk_core", 0,
fe3511ad
EZ		 309 RK3328_CLKGATE_CON(13), 0, GFLAGS),
310 GATE(0, "aclk_gic400", "aclk_core", CLK_IGNORE_UNUSED,
311 RK3328_CLKGATE_CON(13), 1, GFLAGS),
312
313 GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
314 RK3328_CLKGATE_CON(7), 2, GFLAGS),
315
316 /* PD_GPU */
317 COMPOSITE(0, "aclk_gpu_pre", mux_4plls_p, 0,
318 RK3328_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
319 RK3328_CLKGATE_CON(6), 6, GFLAGS),
320 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_SET_RATE_PARENT,
321 RK3328_CLKGATE_CON(14), 0, GFLAGS),
51a70dbf 322 GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0,
fe3511ad
EZ		 323 RK3328_CLKGATE_CON(14), 1, GFLAGS),
324
325 /* PD_DDR */
326 COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
327 RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
328 RK3328_CLKGATE_CON(0), 4, GFLAGS),
329 GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
330 RK3328_CLKGATE_CON(18), 6, GFLAGS),
331 GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
332 RK3328_CLKGATE_CON(18), 5, GFLAGS),
333 GATE(0, "aclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
334 RK3328_CLKGATE_CON(18), 4, GFLAGS),
335 GATE(0, "clk_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
336 RK3328_CLKGATE_CON(0), 6, GFLAGS),
337
338 COMPOSITE(PCLK_DDR, "pclk_ddr", mux_2plls_hdmiphy_p, 0,
339 RK3328_CLKSEL_CON(4), 13, 2, MFLAGS, 8, 3, DFLAGS,
340 RK3328_CLKGATE_CON(7), 4, GFLAGS),
341 GATE(0, "pclk_ddrupctl", "pclk_ddr", CLK_IGNORE_UNUSED,
342 RK3328_CLKGATE_CON(18), 1, GFLAGS),
343 GATE(0, "pclk_ddr_msch", "pclk_ddr", CLK_IGNORE_UNUSED,
344 RK3328_CLKGATE_CON(18), 2, GFLAGS),
345 GATE(0, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
346 RK3328_CLKGATE_CON(18), 3, GFLAGS),
347 GATE(0, "pclk_ddrstdby", "pclk_ddr", CLK_IGNORE_UNUSED,
348 RK3328_CLKGATE_CON(18), 7, GFLAGS),
349 GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
350 RK3328_CLKGATE_CON(18), 9, GFLAGS),
351
352 /*
353 * Clock-Architecture Diagram 3
354 */
355
356 /* PD_BUS */
357 COMPOSITE(ACLK_BUS_PRE, "aclk_bus_pre", mux_2plls_hdmiphy_p, 0,
358 RK3328_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
359 RK3328_CLKGATE_CON(8), 0, GFLAGS),
360 COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_pre", 0,
361 RK3328_CLKSEL_CON(1), 8, 2, DFLAGS,
362 RK3328_CLKGATE_CON(8), 1, GFLAGS),
363 COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", 0,
364 RK3328_CLKSEL_CON(1), 12, 3, DFLAGS,
365 RK3328_CLKGATE_CON(8), 2, GFLAGS),
366 GATE(0, "pclk_bus", "pclk_bus_pre", 0,
367 RK3328_CLKGATE_CON(8), 3, GFLAGS),
368 GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0,
369 RK3328_CLKGATE_CON(8), 4, GFLAGS),
370
371 COMPOSITE(SCLK_TSP, "clk_tsp", mux_2plls_p, 0,
372 RK3328_CLKSEL_CON(21), 15, 1, MFLAGS, 8, 5, DFLAGS,
373 RK3328_CLKGATE_CON(2), 5, GFLAGS),
374 GATE(0, "clk_hsadc_tsp", "ext_gpio3a2", 0,
375 RK3328_CLKGATE_CON(17), 13, GFLAGS),
376
377 /* PD_I2S */
378 COMPOSITE(0, "clk_i2s0_div", mux_2plls_p, 0,
379 RK3328_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
380 RK3328_CLKGATE_CON(1), 1, GFLAGS),
381 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
382 RK3328_CLKSEL_CON(7), 0,
383 RK3328_CLKGATE_CON(1), 2, GFLAGS,
384 &rk3328_i2s0_fracmux),
385 GATE(SCLK_I2S0, "clk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
386 RK3328_CLKGATE_CON(1), 3, GFLAGS),
387
388 COMPOSITE(0, "clk_i2s1_div", mux_2plls_p, 0,
389 RK3328_CLKSEL_CON(8), 15, 1, MFLAGS, 0, 7, DFLAGS,
390 RK3328_CLKGATE_CON(1), 4, GFLAGS),
391 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
392 RK3328_CLKSEL_CON(9), 0,
393 RK3328_CLKGATE_CON(1), 5, GFLAGS,
394 &rk3328_i2s1_fracmux),
395 GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
5c73ac2f 396 RK3328_CLKGATE_CON(1), 6, GFLAGS),
fe3511ad
EZ		 397 COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0,
398 RK3328_CLKSEL_CON(8), 12, 1, MFLAGS,
399 RK3328_CLKGATE_CON(1), 7, GFLAGS),
400
401 COMPOSITE(0, "clk_i2s2_div", mux_2plls_p, 0,
402 RK3328_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 7, DFLAGS,
403 RK3328_CLKGATE_CON(1), 8, GFLAGS),
404 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
405 RK3328_CLKSEL_CON(11), 0,
406 RK3328_CLKGATE_CON(1), 9, GFLAGS,
407 &rk3328_i2s2_fracmux),
408 GATE(SCLK_I2S2, "clk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
409 RK3328_CLKGATE_CON(1), 10, GFLAGS),
410 COMPOSITE_NODIV(SCLK_I2S2_OUT, "i2s2_out", mux_i2s2out_p, 0,
411 RK3328_CLKSEL_CON(10), 12, 1, MFLAGS,
412 RK3328_CLKGATE_CON(1), 11, GFLAGS),
413
414 COMPOSITE(0, "clk_spdif_div", mux_2plls_p, 0,
415 RK3328_CLKSEL_CON(12), 15, 1, MFLAGS, 0, 7, DFLAGS,
416 RK3328_CLKGATE_CON(1), 12, GFLAGS),
417 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
418 RK3328_CLKSEL_CON(13), 0,
419 RK3328_CLKGATE_CON(1), 13, GFLAGS,
420 &rk3328_spdif_fracmux),
421
422 /* PD_UART */
423 COMPOSITE(0, "clk_uart0_div", mux_2plls_u480m_p, 0,
424 RK3328_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
425 RK3328_CLKGATE_CON(1), 14, GFLAGS),
426 COMPOSITE(0, "clk_uart1_div", mux_2plls_u480m_p, 0,
427 RK3328_CLKSEL_CON(16), 12, 2, MFLAGS, 0, 7, DFLAGS,
428 RK3328_CLKGATE_CON(2), 0, GFLAGS),
429 COMPOSITE(0, "clk_uart2_div", mux_2plls_u480m_p, 0,
430 RK3328_CLKSEL_CON(18), 12, 2, MFLAGS, 0, 7, DFLAGS,
431 RK3328_CLKGATE_CON(2), 2, GFLAGS),
432 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
433 RK3328_CLKSEL_CON(15), 0,
434 RK3328_CLKGATE_CON(1), 15, GFLAGS,
435 &rk3328_uart0_fracmux),
436 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
437 RK3328_CLKSEL_CON(17), 0,
438 RK3328_CLKGATE_CON(2), 1, GFLAGS,
439 &rk3328_uart1_fracmux),
440 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
441 RK3328_CLKSEL_CON(19), 0,
442 RK3328_CLKGATE_CON(2), 3, GFLAGS,
443 &rk3328_uart2_fracmux),
444
445 /*
446 * Clock-Architecture Diagram 4
447 */
448
449 COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_2plls_p, 0,
450 RK3328_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 7, DFLAGS,
451 RK3328_CLKGATE_CON(2), 9, GFLAGS),
452 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_2plls_p, 0,
453 RK3328_CLKSEL_CON(34), 15, 1, MFLAGS, 8, 7, DFLAGS,
454 RK3328_CLKGATE_CON(2), 10, GFLAGS),
455 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_2plls_p, 0,
456 RK3328_CLKSEL_CON(35), 7, 1, MFLAGS, 0, 7, DFLAGS,
457 RK3328_CLKGATE_CON(2), 11, GFLAGS),
458 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_2plls_p, 0,
459 RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS,
460 RK3328_CLKGATE_CON(2), 12, GFLAGS),
461 COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0,
fb903392 462 RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
fe3511ad
EZ		 463 RK3328_CLKGATE_CON(2), 4, GFLAGS),
464 COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
465 RK3328_CLKSEL_CON(22), 0, 10, DFLAGS,
466 RK3328_CLKGATE_CON(2), 6, GFLAGS),
467 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "clk_24m", 0,
468 RK3328_CLKSEL_CON(23), 0, 10, DFLAGS,
469 RK3328_CLKGATE_CON(2), 14, GFLAGS),
470 COMPOSITE(SCLK_SPI, "clk_spi", mux_2plls_p, 0,
471 RK3328_CLKSEL_CON(24), 7, 1, MFLAGS, 0, 7, DFLAGS,
472 RK3328_CLKGATE_CON(2), 7, GFLAGS),
473 COMPOSITE(SCLK_PWM, "clk_pwm", mux_2plls_p, 0,
474 RK3328_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 7, DFLAGS,
475 RK3328_CLKGATE_CON(2), 8, GFLAGS),
476 COMPOSITE(SCLK_OTP, "clk_otp", mux_2plls_xin24m_p, 0,
477 RK3328_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 6, DFLAGS,
478 RK3328_CLKGATE_CON(3), 8, GFLAGS),
479 COMPOSITE(SCLK_EFUSE, "clk_efuse", mux_2plls_xin24m_p, 0,
480 RK3328_CLKSEL_CON(5), 14, 2, MFLAGS, 8, 5, DFLAGS,
481 RK3328_CLKGATE_CON(2), 13, GFLAGS),
482 COMPOSITE(SCLK_PDM, "clk_pdm", mux_cpll_gpll_apll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
483 RK3328_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
484 RK3328_CLKGATE_CON(2), 15, GFLAGS),
485
486 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
487 RK3328_CLKGATE_CON(8), 5, GFLAGS),
488 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
489 RK3328_CLKGATE_CON(8), 6, GFLAGS),
490 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
491 RK3328_CLKGATE_CON(8), 7, GFLAGS),
492 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
493 RK3328_CLKGATE_CON(8), 8, GFLAGS),
494 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
495 RK3328_CLKGATE_CON(8), 9, GFLAGS),
496 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
497 RK3328_CLKGATE_CON(8), 10, GFLAGS),
498
499 COMPOSITE(SCLK_WIFI, "clk_wifi", mux_2plls_u480m_p, 0,
500 RK3328_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 6, DFLAGS,
501 RK3328_CLKGATE_CON(0), 10, GFLAGS),
502
503 /*
504 * Clock-Architecture Diagram 5
505 */
506
507 /* PD_VIDEO */
508 COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_4plls_p, 0,
509 RK3328_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
510 RK3328_CLKGATE_CON(6), 0, GFLAGS),
511 FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
512 RK3328_CLKGATE_CON(11), 0, GFLAGS),
513 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", CLK_SET_RATE_PARENT,
514 RK3328_CLKGATE_CON(24), 0, GFLAGS),
515 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", CLK_SET_RATE_PARENT,
516 RK3328_CLKGATE_CON(24), 1, GFLAGS),
51a70dbf 517 GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", 0,
fe3511ad 518 RK3328_CLKGATE_CON(24), 2, GFLAGS),
51a70dbf 519 GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", 0,
fe3511ad
EZ		 520 RK3328_CLKGATE_CON(24), 3, GFLAGS),
521
522 COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_4plls_p, 0,
523 RK3328_CLKSEL_CON(48), 14, 2, MFLAGS, 8, 5, DFLAGS,
524 RK3328_CLKGATE_CON(6), 1, GFLAGS),
525
526 COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_4plls_p, 0,
527 RK3328_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
528 RK3328_CLKGATE_CON(6), 2, GFLAGS),
529
530 COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_4plls_p, 0,
531 RK3328_CLKSEL_CON(50), 6, 2, MFLAGS, 0, 5, DFLAGS,
532 RK3328_CLKGATE_CON(6), 5, GFLAGS),
533 FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
534 RK3328_CLKGATE_CON(11), 8, GFLAGS),
535 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", CLK_SET_RATE_PARENT,
536 RK3328_CLKGATE_CON(23), 0, GFLAGS),
537 GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", CLK_SET_RATE_PARENT,
538 RK3328_CLKGATE_CON(23), 1, GFLAGS),
51a70dbf 539 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 0,
fe3511ad 540 RK3328_CLKGATE_CON(23), 2, GFLAGS),
51a70dbf 541 GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 0,
fe3511ad
EZ		 542 RK3328_CLKGATE_CON(23), 3, GFLAGS),
543
544 COMPOSITE(ACLK_RKVENC, "aclk_rkvenc", mux_4plls_p, 0,
545 RK3328_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
546 RK3328_CLKGATE_CON(6), 3, GFLAGS),
547 FACTOR_GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 0, 1, 4,
548 RK3328_CLKGATE_CON(11), 4, GFLAGS),
51a70dbf 549 GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 0,
fe3511ad 550 RK3328_CLKGATE_CON(25), 0, GFLAGS),
51a70dbf 551 GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0,
fe3511ad
EZ		 552 RK3328_CLKGATE_CON(25), 1, GFLAGS),
553 GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,
fb903392 554 RK3328_CLKGATE_CON(25), 2, GFLAGS),
fe3511ad 555 GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0,
fb903392 556 RK3328_CLKGATE_CON(25), 3, GFLAGS),
fe3511ad 557 GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0,
fb903392 558 RK3328_CLKGATE_CON(25), 4, GFLAGS),
fe3511ad 559 GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0,
fb903392 560 RK3328_CLKGATE_CON(25), 5, GFLAGS),
fe3511ad 561 GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED,
fb903392 562 RK3328_CLKGATE_CON(25), 6, GFLAGS),
fe3511ad
EZ		 563
564 COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
565 RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
566 RK3328_CLKGATE_CON(6), 4, GFLAGS),
567
568 COMPOSITE(SCLK_VENC_DSP, "sclk_venc_dsp", mux_4plls_p, 0,
569 RK3328_CLKSEL_CON(52), 14, 2, MFLAGS, 8, 5, DFLAGS,
570 RK3328_CLKGATE_CON(6), 7, GFLAGS),
571
572 /*
573 * Clock-Architecture Diagram 6
574 */
575
576 /* PD_VIO */
577 COMPOSITE(ACLK_VIO_PRE, "aclk_vio_pre", mux_4plls_p, 0,
578 RK3328_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS,
579 RK3328_CLKGATE_CON(5), 2, GFLAGS),
580 DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_vio_pre", 0,
581 RK3328_CLKSEL_CON(37), 8, 5, DFLAGS),
582
583 COMPOSITE(ACLK_RGA_PRE, "aclk_rga_pre", mux_4plls_p, 0,
584 RK3328_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS,
585 RK3328_CLKGATE_CON(5), 0, GFLAGS),
586 COMPOSITE(SCLK_RGA, "clk_rga", mux_4plls_p, 0,
587 RK3328_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS,
588 RK3328_CLKGATE_CON(5), 1, GFLAGS),
589 COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_4plls_p, 0,
590 RK3328_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
591 RK3328_CLKGATE_CON(5), 5, GFLAGS),
1d334427 592 GATE(SCLK_HDMI_SFC, "sclk_hdmi_sfc", "xin24m", 0,
fe3511ad
EZ		 593 RK3328_CLKGATE_CON(5), 4, GFLAGS),
594
595 COMPOSITE_NODIV(0, "clk_cif_src", mux_2plls_p, 0,
596 RK3328_CLKSEL_CON(42), 7, 1, MFLAGS,
597 RK3328_CLKGATE_CON(5), 3, GFLAGS),
598 COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cif_out", mux_sclk_cif_p, CLK_SET_RATE_PARENT,
599 RK3328_CLKSEL_CON(42), 5, 1, MFLAGS, 0, 5, DFLAGS),
600
601 COMPOSITE(DCLK_LCDC_SRC, "dclk_lcdc_src", mux_gpll_cpll_p, 0,
602 RK3328_CLKSEL_CON(40), 0, 1, MFLAGS, 8, 8, DFLAGS,
603 RK3328_CLKGATE_CON(5), 6, GFLAGS),
604 DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0,
605 RK3328_CLKSEL_CON(40), 3, 3, DFLAGS),
36ec0361 606 MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
fe3511ad
EZ		 607 RK3328_CLKSEL_CON(40), 1, 1, MFLAGS),
608
609 /*
610 * Clock-Architecture Diagram 7
611 */
612
613 /* PD_PERI */
614 GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
615 RK3328_CLKGATE_CON(4), 0, GFLAGS),
616 GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
617 RK3328_CLKGATE_CON(4), 1, GFLAGS),
618 GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
619 RK3328_CLKGATE_CON(4), 2, GFLAGS),
620 COMPOSITE_NOGATE(ACLK_PERI_PRE, "aclk_peri_pre", mux_aclk_peri_pre_p, 0,
621 RK3328_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS),
622 COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED,
623 RK3328_CLKSEL_CON(29), 0, 2, DFLAGS,
624 RK3328_CLKGATE_CON(10), 2, GFLAGS),
625 COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED,
626 RK3328_CLKSEL_CON(29), 4, 3, DFLAGS,
627 RK3328_CLKGATE_CON(10), 1, GFLAGS),
628 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
629 RK3328_CLKGATE_CON(10), 0, GFLAGS),
630
631 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_2plls_24m_u480m_p, 0,
632 RK3328_CLKSEL_CON(30), 8, 2, MFLAGS, 0, 8, DFLAGS,
633 RK3328_CLKGATE_CON(4), 3, GFLAGS),
634
635 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_2plls_24m_u480m_p, 0,
636 RK3328_CLKSEL_CON(31), 8, 2, MFLAGS, 0, 8, DFLAGS,
637 RK3328_CLKGATE_CON(4), 4, GFLAGS),
638
639 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_2plls_24m_u480m_p, 0,
640 RK3328_CLKSEL_CON(32), 8, 2, MFLAGS, 0, 8, DFLAGS,
641 RK3328_CLKGATE_CON(4), 5, GFLAGS),
642
643 COMPOSITE(SCLK_SDMMC_EXT, "clk_sdmmc_ext", mux_2plls_24m_u480m_p, 0,
644 RK3328_CLKSEL_CON(43), 8, 2, MFLAGS, 0, 8, DFLAGS,
645 RK3328_CLKGATE_CON(4), 10, GFLAGS),
646
647 COMPOSITE(SCLK_REF_USB3OTG_SRC, "clk_ref_usb3otg_src", mux_2plls_p, 0,
648 RK3328_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS,
649 RK3328_CLKGATE_CON(4), 9, GFLAGS),
650
651 MUX(SCLK_REF_USB3OTG, "clk_ref_usb3otg", mux_ref_usb3otg_src_p, CLK_SET_RATE_PARENT,
652 RK3328_CLKSEL_CON(45), 8, 1, MFLAGS),
653
654 GATE(SCLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0,
655 RK3328_CLKGATE_CON(4), 7, GFLAGS),
656
657 COMPOSITE(SCLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", mux_xin24m_32k_p, 0,
658 RK3328_CLKSEL_CON(33), 15, 1, MFLAGS, 0, 10, DFLAGS,
659 RK3328_CLKGATE_CON(4), 8, GFLAGS),
660
661 /*
662 * Clock-Architecture Diagram 8
663 */
664
665 /* PD_GMAC */
666 COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,
fb903392 667 RK3328_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
fe3511ad
EZ		 668 RK3328_CLKGATE_CON(3), 2, GFLAGS),
669 COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0,
670 RK3328_CLKSEL_CON(25), 8, 3, DFLAGS,
671 RK3328_CLKGATE_CON(9), 0, GFLAGS),
672
673 COMPOSITE(SCLK_MAC2IO_SRC, "clk_mac2io_src", mux_2plls_p, 0,
674 RK3328_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 5, DFLAGS,
675 RK3328_CLKGATE_CON(3), 1, GFLAGS),
676 GATE(SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", 0,
677 RK3328_CLKGATE_CON(9), 7, GFLAGS),
678 GATE(SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", 0,
679 RK3328_CLKGATE_CON(9), 4, GFLAGS),
680 GATE(SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", 0,
681 RK3328_CLKGATE_CON(9), 5, GFLAGS),
682 GATE(SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", 0,
683 RK3328_CLKGATE_CON(9), 6, GFLAGS),
684 COMPOSITE(SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_p, 0,
685 RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS,
686 RK3328_CLKGATE_CON(3), 5, GFLAGS),
9bb4db62
EZ		 687 MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPARENT,
688 RK3328_GRF_MAC_CON1, 10, 1, MFLAGS),
689 MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_NO_REPARENT,
690 RK3328_GRF_SOC_CON4, 14, 1, MFLAGS),
fe3511ad
EZ		 691
692 COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0,
693 RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS,
694 RK3328_CLKGATE_CON(3), 0, GFLAGS),
695 GATE(SCLK_MAC2PHY_REF, "clk_mac2phy_ref", "clk_mac2phy", 0,
696 RK3328_CLKGATE_CON(9), 3, GFLAGS),
697 GATE(SCLK_MAC2PHY_RXTX, "clk_mac2phy_rxtx", "clk_mac2phy", 0,
698 RK3328_CLKGATE_CON(9), 1, GFLAGS),
699 COMPOSITE_NOMUX(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy", 0,
700 RK3328_CLKSEL_CON(26), 8, 2, DFLAGS,
701 RK3328_CLKGATE_CON(9), 2, GFLAGS),
9bb4db62
EZ		 702 MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p, CLK_SET_RATE_NO_REPARENT,
703 RK3328_GRF_MAC_CON2, 10, 1, MFLAGS),
fe3511ad
EZ		 704
705 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
706
707 /*
708 * Clock-Architecture Diagram 9
709 */
710
711 /* PD_VOP */
712 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(21), 10, GFLAGS),
51a70dbf 713 GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(22), 3, GFLAGS),
fe3511ad 714 GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 2, GFLAGS),
51a70dbf 715 GATE(0, "aclk_vop_niu", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 4, GFLAGS),
fe3511ad
EZ		 716
717 GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 6, GFLAGS),
718 GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 8, GFLAGS),
719 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 15, GFLAGS),
51a70dbf 720 GATE(0, "aclk_vio_niu", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 2, GFLAGS),
fe3511ad
EZ		 721
722 GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 3, GFLAGS),
723 GATE(0, "hclk_vop_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 5, GFLAGS),
724 GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 7, GFLAGS),
725 GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 9, GFLAGS),
726 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 11, GFLAGS),
727 GATE(0, "hclk_ahb1tom", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 12, GFLAGS),
7f872cb3
HS		 728 GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 13, GFLAGS),
729 GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 14, GFLAGS),
fe3511ad 730 GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 0, GFLAGS),
a377f681 731 GATE(0, "hclk_vio_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 1, GFLAGS),
fe3511ad
EZ		 732 GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 4, GFLAGS),
733 GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 5, GFLAGS),
734
735 /* PD_PERI */
736 GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
fb903392 737 GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
fe3511ad
EZ		 738
739 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
740 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
741 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 2, GFLAGS),
742 GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 15, GFLAGS),
743 GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 6, GFLAGS),
744 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 7, GFLAGS),
745 GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 8, GFLAGS),
746 GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 9, GFLAGS),
51a70dbf
HS		 747 GATE(0, "hclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 12, GFLAGS),
748 GATE(0, "pclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 13, GFLAGS),
fe3511ad
EZ		 749
750 /* PD_GMAC */
751 GATE(ACLK_MAC2PHY, "aclk_mac2phy", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 0, GFLAGS),
752 GATE(ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 2, GFLAGS),
51a70dbf 753 GATE(0, "aclk_gmac_niu", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 4, GFLAGS),
fe3511ad
EZ		 754 GATE(PCLK_MAC2PHY, "pclk_mac2phy", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 1, GFLAGS),
755 GATE(PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 3, GFLAGS),
51a70dbf 756 GATE(0, "pclk_gmac_niu", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 5, GFLAGS),
fe3511ad
EZ		 757
758 /* PD_BUS */
51a70dbf 759 GATE(0, "aclk_bus_niu", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 12, GFLAGS),
fe3511ad
EZ		 760 GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 11, GFLAGS),
761 GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 12, GFLAGS),
762 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 0, GFLAGS),
763 GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 1, GFLAGS),
764
765 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 2, GFLAGS),
766 GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 3, GFLAGS),
767 GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 4, GFLAGS),
768 GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 5, GFLAGS),
769 GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 6, GFLAGS),
770 GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 11, GFLAGS),
771 GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 7, GFLAGS),
772 GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 8, GFLAGS),
51a70dbf 773 GATE(0, "hclk_bus_niu", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 13, GFLAGS),
fe3511ad
EZ		 774 GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(28), 0, GFLAGS),
775
51a70dbf 776 GATE(0, "pclk_bus_niu", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 14, GFLAGS),
fe3511ad
EZ		 777 GATE(0, "pclk_efuse", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 9, GFLAGS),
778 GATE(0, "pclk_otp", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 4, GFLAGS),
779 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 10, GFLAGS),
780 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 0, GFLAGS),
781 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 1, GFLAGS),
782 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 2, GFLAGS),
783 GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 3, GFLAGS),
784 GATE(0, "pclk_stimer", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 4, GFLAGS),
785 GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 5, GFLAGS),
786 GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 6, GFLAGS),
787 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 7, GFLAGS),
788 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 8, GFLAGS),
789 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 9, GFLAGS),
790 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 10, GFLAGS),
791 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 11, GFLAGS),
792 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 12, GFLAGS),
793 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 13, GFLAGS),
794 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 14, GFLAGS),
795 GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 15, GFLAGS),
796 GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 0, GFLAGS),
797 GATE(0, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 4, GFLAGS),
798 GATE(0, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 6, GFLAGS),
799 GATE(0, "pclk_sim", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 10, GFLAGS),
800 GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 15, GFLAGS),
801 GATE(0, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 3, GFLAGS),
802
803 GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 1, GFLAGS),
804 GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 2, GFLAGS),
805 GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 2, GFLAGS),
806 GATE(PCLK_USB2_GRF, "pclk_usb2_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 14, GFLAGS),
807 GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 13, GFLAGS),
d0618247 808 GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(17), 5, GFLAGS),
fe3511ad
EZ		 809 GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 7, GFLAGS),
810 GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 8, GFLAGS),
51a70dbf 811 GATE(0, "pclk_phy_niu", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(15), 15, GFLAGS),
fe3511ad
EZ		 812
813 /* PD_MMC */
ce84eca9 814 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
fe3511ad 815 RK3328_SDMMC_CON0, 1),
ce84eca9 816 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
82f4b67f 817 RK3328_SDMMC_CON1, 0),
fe3511ad 818
ce84eca9 819 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
fe3511ad 820 RK3328_SDIO_CON0, 1),
ce84eca9 821 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
82f4b67f 822 RK3328_SDIO_CON1, 0),
fe3511ad 823
ce84eca9 824 MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
fe3511ad 825 RK3328_EMMC_CON0, 1),
ce84eca9 826 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
82f4b67f 827 RK3328_EMMC_CON1, 0),
fe3511ad 828
ce84eca9 829 MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext",
fe3511ad 830 RK3328_SDMMC_EXT_CON0, 1),
ce84eca9 831 MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext",
82f4b67f 832 RK3328_SDMMC_EXT_CON1, 0),
fe3511ad
EZ		 833};
834
835static const char *const rk3328_critical_clocks[] __initconst = {
836 "aclk_bus",
51a70dbf 837 "aclk_bus_niu",
fe3511ad 838 "pclk_bus",
51a70dbf 839 "pclk_bus_niu",
fe3511ad 840 "hclk_bus",
51a70dbf 841 "hclk_bus_niu",
fe3511ad
EZ		 842 "aclk_peri",
843 "hclk_peri",
51a70dbf 844 "hclk_peri_niu",
fe3511ad 845 "pclk_peri",
51a70dbf 846 "pclk_peri_niu",
fe3511ad
EZ		 847 "pclk_dbg",
848 "aclk_core_niu",
849 "aclk_gic400",
850 "aclk_intmem",
851 "hclk_rom",
852 "pclk_grf",
853 "pclk_cru",
854 "pclk_sgrf",
855 "pclk_timer0",
856 "clk_timer0",
857 "pclk_ddr_msch",
858 "pclk_ddr_mon",
859 "pclk_ddr_grf",
860 "clk_ddrupctl",
861 "clk_ddrmsch",
862 "hclk_ahb1tom",
863 "clk_jtag",
864 "pclk_ddrphy",
865 "pclk_pmu",
866 "hclk_otg_pmu",
867 "aclk_rga_niu",
868 "pclk_vio_h2p",
869 "hclk_vio_h2p",
51a70dbf 870 "aclk_vio_niu",
a377f681 871 "hclk_vio_niu",
51a70dbf
HS		 872 "aclk_vop_niu",
873 "hclk_vop_niu",
874 "aclk_gpu_niu",
875 "aclk_rkvdec_niu",
876 "hclk_rkvdec_niu",
877 "aclk_vpu_niu",
878 "hclk_vpu_niu",
879 "aclk_rkvenc_niu",
880 "hclk_rkvenc_niu",
881 "aclk_gmac_niu",
882 "pclk_gmac_niu",
883 "pclk_phy_niu",
fe3511ad
EZ		 884};
885
886static void __init rk3328_clk_init(struct device_node *np)
887{
888 struct rockchip_clk_provider *ctx;
889 void __iomem *reg_base;
890
891 reg_base = of_iomap(np, 0);
892 if (!reg_base) {
893 pr_err("%s: could not map cru region\n", __func__);
894 return;
895 }
896
897 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
898 if (IS_ERR(ctx)) {
899 pr_err("%s: rockchip clk init failed\n", __func__);
900 iounmap(reg_base);
901 return;
902 }
903
904 rockchip_clk_register_plls(ctx, rk3328_pll_clks,
905 ARRAY_SIZE(rk3328_pll_clks),
906 RK3328_GRF_SOC_STATUS0);
907 rockchip_clk_register_branches(ctx, rk3328_clk_branches,
908 ARRAY_SIZE(rk3328_clk_branches));
909 rockchip_clk_protect_critical(rk3328_critical_clocks,
910 ARRAY_SIZE(rk3328_critical_clocks));
911
912 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
913 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
914 &rk3328_cpuclk_data, rk3328_cpuclk_rates,
915 ARRAY_SIZE(rk3328_cpuclk_rates));
916
fb903392 917 rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0),
fe3511ad
EZ		 918 ROCKCHIP_SOFTRST_HIWORD_MASK);
919
920 rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL);
921
922 rockchip_clk_of_add_provider(np, ctx);
923}
924CLK_OF_DECLARE(rk3328_cru, "rockchip,rk3328-cru", rk3328_clk_init);
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