[mirror_ubuntu-zesty-kernel.git] / drivers / clk / samsung / clk-exynos-audss.c

/*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Author: Padmavathi Venna <padma.v@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Common Clock Framework support for Audio Subsystem Clock Controller.
*/

#include <linux/slab.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/syscore_ops.h>
#include <linux/module.h>
#include <linux/platform_device.h>

#include <dt-bindings/clock/exynos-audss-clk.h>

static DEFINE_SPINLOCK(lock);
static struct clk **clk_table;
static void __iomem *reg_base;
static struct clk_onecell_data clk_data;
/*
 * On Exynos5420 this will be a clock which has to be enabled before any
 * access to audss registers. Typically a child of EPLL.
 *
 * On other platforms this will be -ENODEV.
 */
static struct clk *epll;

#define ASS_CLK_SRC 0x0
#define ASS_CLK_DIV 0x4
#define ASS_CLK_GATE 0x8

#ifdef CONFIG_PM_SLEEP
static unsigned long reg_save[][2] = {
	{ ASS_CLK_SRC,  0 },
	{ ASS_CLK_DIV,  0 },
	{ ASS_CLK_GATE, 0 },
};

static int exynos_audss_clk_suspend(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
		reg_save[i][1] = readl(reg_base + reg_save[i][0]);

	return 0;
}

static void exynos_audss_clk_resume(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
		writel(reg_save[i][1], reg_base + reg_save[i][0]);
}

static struct syscore_ops exynos_audss_clk_syscore_ops = {
	.suspend	= exynos_audss_clk_suspend,
	.resume		= exynos_audss_clk_resume,
};
#endif /* CONFIG_PM_SLEEP */

struct exynos_audss_clk_drvdata {
	unsigned int has_adma_clk:1;
	unsigned int has_mst_clk:1;
	unsigned int enable_epll:1;
	unsigned int num_clks;
};

static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
	.num_clks	= EXYNOS_AUDSS_MAX_CLKS - 1,
};

static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
	.num_clks	= EXYNOS_AUDSS_MAX_CLKS - 1,
	.has_mst_clk	= 1,
};

static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
	.num_clks	= EXYNOS_AUDSS_MAX_CLKS,
	.has_adma_clk	= 1,
	.enable_epll	= 1,
};

static const struct of_device_id exynos_audss_clk_of_match[] = {
	{
		.compatible	= "samsung,exynos4210-audss-clock",
		.data		= &exynos4210_drvdata,
	}, {
		.compatible	= "samsung,exynos5250-audss-clock",
		.data		= &exynos4210_drvdata,
	}, {
		.compatible	= "samsung,exynos5410-audss-clock",
		.data		= &exynos5410_drvdata,
	}, {
		.compatible	= "samsung,exynos5420-audss-clock",
		.data		= &exynos5420_drvdata,
	},
	{ },
};
MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);

static void exynos_audss_clk_teardown(void)
{
	int i;

	for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
		if (!IS_ERR(clk_table[i]))
			clk_unregister_mux(clk_table[i]);
	}

	for (; i < EXYNOS_SRP_CLK; i++) {
		if (!IS_ERR(clk_table[i]))
			clk_unregister_divider(clk_table[i]);
	}

	for (; i < clk_data.clk_num; i++) {
		if (!IS_ERR(clk_table[i]))
			clk_unregister_gate(clk_table[i]);
	}
}

/* register exynos_audss clocks */
static int exynos_audss_clk_probe(struct platform_device *pdev)
{
	const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
	const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
	const char *sclk_pcm_p = "sclk_pcm0";
	struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
	const struct exynos_audss_clk_drvdata *variant;
	struct resource *res;
	int i, ret = 0;

	variant = of_device_get_match_data(&pdev->dev);
	if (!variant)
		return -EINVAL;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	reg_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(reg_base)) {
		dev_err(&pdev->dev, "failed to map audss registers\n");
		return PTR_ERR(reg_base);
	}

	epll = ERR_PTR(-ENODEV);

	clk_table = devm_kzalloc(&pdev->dev,
				sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
				GFP_KERNEL);
	if (!clk_table)
		return -ENOMEM;

	clk_data.clks = clk_table;
	clk_data.clk_num = variant->num_clks;

	pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
	pll_in = devm_clk_get(&pdev->dev, "pll_in");
	if (!IS_ERR(pll_ref))
		mout_audss_p[0] = __clk_get_name(pll_ref);
	if (!IS_ERR(pll_in)) {
		mout_audss_p[1] = __clk_get_name(pll_in);

		if (variant->enable_epll) {
			epll = pll_in;

			ret = clk_prepare_enable(epll);
			if (ret) {
				dev_err(&pdev->dev,
					"failed to prepare the epll clock\n");
				return ret;
			}
		}
	}
	clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
				mout_audss_p, ARRAY_SIZE(mout_audss_p),
				CLK_SET_RATE_NO_REPARENT,
				reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);

	cdclk = devm_clk_get(&pdev->dev, "cdclk");
	sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio");
	if (!IS_ERR(cdclk))
		mout_i2s_p[1] = __clk_get_name(cdclk);
	if (!IS_ERR(sclk_audio))
		mout_i2s_p[2] = __clk_get_name(sclk_audio);
	clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
				mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
				CLK_SET_RATE_NO_REPARENT,
				reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);

	clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
				"mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
				0, &lock);

	clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
				"dout_aud_bus", "dout_srp", 0,
				reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);

	clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
				"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
				&lock);

	clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
				"dout_srp", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 0, 0, &lock);

	clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
				"dout_aud_bus", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 2, 0, &lock);

	clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
				"dout_i2s", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 3, 0, &lock);

	clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
				 "sclk_pcm", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 4, 0, &lock);

	sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
	if (!IS_ERR(sclk_pcm_in))
		sclk_pcm_p = __clk_get_name(sclk_pcm_in);
	clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
				sclk_pcm_p, CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 5, 0, &lock);

	if (variant->has_adma_clk) {
		clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
				"dout_srp", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 9, 0, &lock);
	}

	for (i = 0; i < clk_data.clk_num; i++) {
		if (IS_ERR(clk_table[i])) {
			dev_err(&pdev->dev, "failed to register clock %d\n", i);
			ret = PTR_ERR(clk_table[i]);
			goto unregister;
		}
	}

	ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
					&clk_data);
	if (ret) {
		dev_err(&pdev->dev, "failed to add clock provider\n");
		goto unregister;
	}

#ifdef CONFIG_PM_SLEEP
	register_syscore_ops(&exynos_audss_clk_syscore_ops);
#endif
	return 0;

unregister:
	exynos_audss_clk_teardown();

	if (!IS_ERR(epll))
		clk_disable_unprepare(epll);

	return ret;
}

static int exynos_audss_clk_remove(struct platform_device *pdev)
{
#ifdef CONFIG_PM_SLEEP
	unregister_syscore_ops(&exynos_audss_clk_syscore_ops);
#endif

	of_clk_del_provider(pdev->dev.of_node);

	exynos_audss_clk_teardown();

	if (!IS_ERR(epll))
		clk_disable_unprepare(epll);

	return 0;
}

static struct platform_driver exynos_audss_clk_driver = {
	.driver	= {
		.name = "exynos-audss-clk",
		.of_match_table = exynos_audss_clk_of_match,
	},
	.probe = exynos_audss_clk_probe,
	.remove = exynos_audss_clk_remove,
};

module_platform_driver(exynos_audss_clk_driver);

MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:exynos-audss-clk");
Commit	Line	Data
1241ef94 PV	1	/*
	2	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	3	* Author: Padmavathi Venna <padma.v@samsung.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* Common Clock Framework support for Audio Subsystem Clock Controller.
	10	*/
	11
6f1ed07a	12	#include <linux/slab.h>
1241ef94	13	#include <linux/io.h>
6f1ed07a	14	#include <linux/clk.h>
1241ef94 PV	15	#include <linux/clk-provider.h>
1241ef94 PV	16	#include <linux/of_address.h>
7c3ca061	17	#include <linux/of_device.h>
1241ef94	18	#include <linux/syscore_ops.h>
b37a4224 AB	19	#include <linux/module.h>
b37a4224 AB	20	#include <linux/platform_device.h>
1241ef94	21
602408e3	22	#include <dt-bindings/clock/exynos-audss-clk.h>
1241ef94 PV	23
	24	static DEFINE_SPINLOCK(lock);
	25	static struct clk **clk_table;
	26	static void __iomem *reg_base;
	27	static struct clk_onecell_data clk_data;
f1e9203e KK	28	/*
	29	* On Exynos5420 this will be a clock which has to be enabled before any
	30	* access to audss registers. Typically a child of EPLL.
	31	*
	32	* On other platforms this will be -ENODEV.
	33	*/
	34	static struct clk *epll;
1241ef94 PV	35
	36	#define ASS_CLK_SRC 0x0
	37	#define ASS_CLK_DIV 0x4
	38	#define ASS_CLK_GATE 0x8
	39
3fd68c99	40	#ifdef CONFIG_PM_SLEEP
1241ef94	41	static unsigned long reg_save[][2] = {
c17a6163 SN	42	{ ASS_CLK_SRC, 0 },
	43	{ ASS_CLK_DIV, 0 },
	44	{ ASS_CLK_GATE, 0 },
1241ef94 PV	45	};
1241ef94 PV	46
1241ef94 PV	47	static int exynos_audss_clk_suspend(void)
	48	{
	49	int i;
	50
	51	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
	52	reg_save[i][1] = readl(reg_base + reg_save[i][0]);
	53
	54	return 0;
	55	}
	56
	57	static void exynos_audss_clk_resume(void)
	58	{
	59	int i;
	60
	61	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
	62	writel(reg_save[i][1], reg_base + reg_save[i][0]);
	63	}
	64
	65	static struct syscore_ops exynos_audss_clk_syscore_ops = {
	66	.suspend = exynos_audss_clk_suspend,
	67	.resume = exynos_audss_clk_resume,
	68	};
	69	#endif /* CONFIG_PM_SLEEP */
	70
7c3ca061 SN	71	struct exynos_audss_clk_drvdata {
7c3ca061 SN	72	unsigned int has_adma_clk:1;
2ec865b7	73	unsigned int has_mst_clk:1;
7c3ca061 SN	74	unsigned int enable_epll:1;
	75	unsigned int num_clks;
	76	};
	77
	78	static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
	79	.num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
	80	};
	81
2ec865b7 SN	82	static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
	83	.num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
	84	.has_mst_clk = 1,
	85	};
	86
7c3ca061 SN	87	static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
	88	.num_clks = EXYNOS_AUDSS_MAX_CLKS,
	89	.has_adma_clk = 1,
	90	.enable_epll = 1,
	91	};
	92
3538a2cf	93	static const struct of_device_id exynos_audss_clk_of_match[] = {
7c3ca061 SN	94	{
	95	.compatible = "samsung,exynos4210-audss-clock",
	96	.data = &exynos4210_drvdata,
	97	}, {
	98	.compatible = "samsung,exynos5250-audss-clock",
	99	.data = &exynos4210_drvdata,
2ec865b7 SN	100	}, {
	101	.compatible = "samsung,exynos5410-audss-clock",
	102	.data = &exynos5410_drvdata,
7c3ca061 SN	103	}, {
	104	.compatible = "samsung,exynos5420-audss-clock",
	105	.data = &exynos5420_drvdata,
	106	},
	107	{ },
3538a2cf	108	};
34b89b29	109	MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
3538a2cf	110
27c76c43 KK	111	static void exynos_audss_clk_teardown(void)
	112	{
	113	int i;
	114
	115	for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
	116	if (!IS_ERR(clk_table[i]))
	117	clk_unregister_mux(clk_table[i]);
	118	}
	119
	120	for (; i < EXYNOS_SRP_CLK; i++) {
	121	if (!IS_ERR(clk_table[i]))
	122	clk_unregister_divider(clk_table[i]);
	123	}
	124
	125	for (; i < clk_data.clk_num; i++) {
	126	if (!IS_ERR(clk_table[i]))
	127	clk_unregister_gate(clk_table[i]);
	128	}
	129	}
	130
1241ef94	131	/* register exynos_audss clocks */
b37a4224	132	static int exynos_audss_clk_probe(struct platform_device *pdev)
1241ef94	133	{
547f3350 AB	134	const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
	135	const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
	136	const char *sclk_pcm_p = "sclk_pcm0";
	137	struct clk pll_ref, pll_in, cdclk, sclk_audio, *sclk_pcm_in;
7c3ca061 SN	138	const struct exynos_audss_clk_drvdata *variant;
	139	struct resource *res;
	140	int i, ret = 0;
3538a2cf	141
7c3ca061 SN	142	variant = of_device_get_match_data(&pdev->dev);
7c3ca061 SN	143	if (!variant)
3538a2cf	144	return -EINVAL;
b37a4224 AB	145
	146	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	147	reg_base = devm_ioremap_resource(&pdev->dev, res);
	148	if (IS_ERR(reg_base)) {
	149	dev_err(&pdev->dev, "failed to map audss registers\n");
	150	return PTR_ERR(reg_base);
1241ef94	151	}
7c3ca061	152
f1e9203e	153	epll = ERR_PTR(-ENODEV);
1241ef94	154
b37a4224 AB	155	clk_table = devm_kzalloc(&pdev->dev,
b37a4224 AB	156	sizeof(struct clk ) EXYNOS_AUDSS_MAX_CLKS,
1241ef94	157	GFP_KERNEL);
b37a4224 AB	158	if (!clk_table)
b37a4224 AB	159	return -ENOMEM;
1241ef94 PV	160
1241ef94 PV	161	clk_data.clks = clk_table;
7c3ca061	162	clk_data.clk_num = variant->num_clks;
1241ef94	163
547f3350 AB	164	pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
	165	pll_in = devm_clk_get(&pdev->dev, "pll_in");
	166	if (!IS_ERR(pll_ref))
	167	mout_audss_p[0] = __clk_get_name(pll_ref);
f1e9203e	168	if (!IS_ERR(pll_in)) {
547f3350	169	mout_audss_p[1] = __clk_get_name(pll_in);
f1e9203e	170
7c3ca061	171	if (variant->enable_epll) {
f1e9203e KK	172	epll = pll_in;
	173
	174	ret = clk_prepare_enable(epll);
	175	if (ret) {
	176	dev_err(&pdev->dev,
c17a6163	177	"failed to prepare the epll clock\n");
f1e9203e KK	178	return ret;
	179	}
	180	}
	181	}
1241ef94	182	clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
819c1de3 JH	183	mout_audss_p, ARRAY_SIZE(mout_audss_p),
819c1de3 JH	184	CLK_SET_RATE_NO_REPARENT,
1241ef94 PV	185	reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
1241ef94 PV	186
547f3350 AB	187	cdclk = devm_clk_get(&pdev->dev, "cdclk");
	188	sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio");
	189	if (!IS_ERR(cdclk))
	190	mout_i2s_p[1] = __clk_get_name(cdclk);
	191	if (!IS_ERR(sclk_audio))
	192	mout_i2s_p[2] = __clk_get_name(sclk_audio);
1241ef94	193	clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
819c1de3 JH	194	mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
819c1de3 JH	195	CLK_SET_RATE_NO_REPARENT,
1241ef94 PV	196	reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
	197
	198	clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
	199	"mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
	200	0, &lock);
	201
	202	clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
	203	"dout_aud_bus", "dout_srp", 0,
	204	reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
	205
	206	clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
	207	"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
	208	&lock);
	209
	210	clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
	211	"dout_srp", CLK_SET_RATE_PARENT,
	212	reg_base + ASS_CLK_GATE, 0, 0, &lock);
	213
	214	clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
	215	"dout_aud_bus", CLK_SET_RATE_PARENT,
	216	reg_base + ASS_CLK_GATE, 2, 0, &lock);
	217
	218	clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
	219	"dout_i2s", CLK_SET_RATE_PARENT,
	220	reg_base + ASS_CLK_GATE, 3, 0, &lock);
	221
	222	clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
	223	"sclk_pcm", CLK_SET_RATE_PARENT,
	224	reg_base + ASS_CLK_GATE, 4, 0, &lock);
	225
547f3350 AB	226	sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in");
	227	if (!IS_ERR(sclk_pcm_in))
	228	sclk_pcm_p = __clk_get_name(sclk_pcm_in);
1241ef94	229	clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
547f3350	230	sclk_pcm_p, CLK_SET_RATE_PARENT,
1241ef94 PV	231	reg_base + ASS_CLK_GATE, 5, 0, &lock);
1241ef94 PV	232
7c3ca061	233	if (variant->has_adma_clk) {
3538a2cf AB	234	clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
	235	"dout_srp", CLK_SET_RATE_PARENT,
	236	reg_base + ASS_CLK_GATE, 9, 0, &lock);
	237	}
	238
b37a4224 AB	239	for (i = 0; i < clk_data.clk_num; i++) {
	240	if (IS_ERR(clk_table[i])) {
	241	dev_err(&pdev->dev, "failed to register clock %d\n", i);
	242	ret = PTR_ERR(clk_table[i]);
	243	goto unregister;
	244	}
	245	}
	246
	247	ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
	248	&clk_data);
	249	if (ret) {
	250	dev_err(&pdev->dev, "failed to add clock provider\n");
	251	goto unregister;
	252	}
	253
1241ef94 PV	254	#ifdef CONFIG_PM_SLEEP
	255	register_syscore_ops(&exynos_audss_clk_syscore_ops);
	256	#endif
b37a4224 AB	257	return 0;
	258
	259	unregister:
27c76c43	260	exynos_audss_clk_teardown();
b37a4224	261
f1e9203e KK	262	if (!IS_ERR(epll))
	263	clk_disable_unprepare(epll);
	264
b37a4224 AB	265	return ret;
	266	}
	267
	268	static int exynos_audss_clk_remove(struct platform_device *pdev)
	269	{
c31844ff KK	270	#ifdef CONFIG_PM_SLEEP
	271	unregister_syscore_ops(&exynos_audss_clk_syscore_ops);
	272	#endif
	273
b37a4224 AB	274	of_clk_del_provider(pdev->dev.of_node);
b37a4224 AB	275
27c76c43	276	exynos_audss_clk_teardown();
b37a4224	277
f1e9203e KK	278	if (!IS_ERR(epll))
	279	clk_disable_unprepare(epll);
	280
b37a4224	281	return 0;
1241ef94	282	}
b37a4224	283
b37a4224 AB	284	static struct platform_driver exynos_audss_clk_driver = {
	285	.driver = {
	286	.name = "exynos-audss-clk",
b37a4224 AB	287	.of_match_table = exynos_audss_clk_of_match,
	288	},
	289	.probe = exynos_audss_clk_probe,
	290	.remove = exynos_audss_clk_remove,
	291	};
	292
4d252fd5	293	module_platform_driver(exynos_audss_clk_driver);
b37a4224 AB	294
	295	MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
	296	MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
	297	MODULE_LICENSE("GPL v2");
	298	MODULE_ALIAS("platform:exynos-audss-clk");