[mirror_ubuntu-hirsute-kernel.git] / drivers / clk / samsung / clk-exynos-audss.c

/*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Author: Padmavathi Venna <padma.v@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Common Clock Framework support for Audio Subsystem Clock Controller.
*/

#include <linux/slab.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/syscore_ops.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>

#include <dt-bindings/clock/exynos-audss-clk.h>

static DEFINE_SPINLOCK(lock);
static void __iomem *reg_base;
static struct clk_hw_onecell_data *clk_data;
/*
 * On Exynos5420 this will be a clock which has to be enabled before any
 * access to audss registers. Typically a child of EPLL.
 *
 * On other platforms this will be -ENODEV.
 */
static struct clk *epll;

#define ASS_CLK_SRC 0x0
#define ASS_CLK_DIV 0x4
#define ASS_CLK_GATE 0x8

static unsigned long reg_save[][2] = {
	{ ASS_CLK_SRC,  0 },
	{ ASS_CLK_DIV,  0 },
	{ ASS_CLK_GATE, 0 },
};

static int __maybe_unused exynos_audss_clk_suspend(struct device *dev)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
		reg_save[i][1] = readl(reg_base + reg_save[i][0]);

	return 0;
}

static int __maybe_unused exynos_audss_clk_resume(struct device *dev)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
		writel(reg_save[i][1], reg_base + reg_save[i][0]);

	return 0;
}

struct exynos_audss_clk_drvdata {
	unsigned int has_adma_clk:1;
	unsigned int has_mst_clk:1;
	unsigned int enable_epll:1;
	unsigned int num_clks;
};

static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
	.num_clks	= EXYNOS_AUDSS_MAX_CLKS - 1,
	.enable_epll	= 1,
};

static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
	.num_clks	= EXYNOS_AUDSS_MAX_CLKS - 1,
	.has_mst_clk	= 1,
};

static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
	.num_clks	= EXYNOS_AUDSS_MAX_CLKS,
	.has_adma_clk	= 1,
	.enable_epll	= 1,
};

static const struct of_device_id exynos_audss_clk_of_match[] = {
	{
		.compatible	= "samsung,exynos4210-audss-clock",
		.data		= &exynos4210_drvdata,
	}, {
		.compatible	= "samsung,exynos5250-audss-clock",
		.data		= &exynos4210_drvdata,
	}, {
		.compatible	= "samsung,exynos5410-audss-clock",
		.data		= &exynos5410_drvdata,
	}, {
		.compatible	= "samsung,exynos5420-audss-clock",
		.data		= &exynos5420_drvdata,
	},
	{ },
};
MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);

static void exynos_audss_clk_teardown(void)
{
	int i;

	for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
		if (!IS_ERR(clk_data->hws[i]))
			clk_hw_unregister_mux(clk_data->hws[i]);
	}

	for (; i < EXYNOS_SRP_CLK; i++) {
		if (!IS_ERR(clk_data->hws[i]))
			clk_hw_unregister_divider(clk_data->hws[i]);
	}

	for (; i < clk_data->num; i++) {
		if (!IS_ERR(clk_data->hws[i]))
			clk_hw_unregister_gate(clk_data->hws[i]);
	}
}

/* register exynos_audss clocks */
static int exynos_audss_clk_probe(struct platform_device *pdev)
{
	const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
	const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
	const char *sclk_pcm_p = "sclk_pcm0";
	struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
	const struct exynos_audss_clk_drvdata *variant;
	struct clk_hw **clk_table;
	struct resource *res;
	struct device *dev = &pdev->dev;
	int i, ret = 0;

	variant = of_device_get_match_data(&pdev->dev);
	if (!variant)
		return -EINVAL;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	reg_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(reg_base))
		return PTR_ERR(reg_base);

	epll = ERR_PTR(-ENODEV);

	clk_data = devm_kzalloc(dev,
				struct_size(clk_data, hws,
					    EXYNOS_AUDSS_MAX_CLKS),
				GFP_KERNEL);
	if (!clk_data)
		return -ENOMEM;

	clk_data->num = variant->num_clks;
	clk_table = clk_data->hws;

	pll_ref = devm_clk_get(dev, "pll_ref");
	pll_in = devm_clk_get(dev, "pll_in");
	if (!IS_ERR(pll_ref))
		mout_audss_p[0] = __clk_get_name(pll_ref);
	if (!IS_ERR(pll_in)) {
		mout_audss_p[1] = __clk_get_name(pll_in);

		if (variant->enable_epll) {
			epll = pll_in;

			ret = clk_prepare_enable(epll);
			if (ret) {
				dev_err(dev,
					"failed to prepare the epll clock\n");
				return ret;
			}
		}
	}

	/*
	 * Enable runtime PM here to allow the clock core using runtime PM
	 * for the registered clocks. Additionally, we increase the runtime
	 * PM usage count before registering the clocks, to prevent the
	 * clock core from runtime suspending the device.
	 */
	pm_runtime_get_noresume(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss",
				mout_audss_p, ARRAY_SIZE(mout_audss_p),
				CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);

	cdclk = devm_clk_get(dev, "cdclk");
	sclk_audio = devm_clk_get(dev, "sclk_audio");
	if (!IS_ERR(cdclk))
		mout_i2s_p[1] = __clk_get_name(cdclk);
	if (!IS_ERR(sclk_audio))
		mout_i2s_p[2] = __clk_get_name(sclk_audio);
	clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s",
				mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
				CLK_SET_RATE_NO_REPARENT,
				reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);

	clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp",
				"mout_audss", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);

	clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev,
				"dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);

	clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
				"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
				&lock);

	clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk",
				"dout_srp", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 0, 0, &lock);

	clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus",
				"dout_aud_bus", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 2, 0, &lock);

	clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s",
				"dout_i2s", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 3, 0, &lock);

	clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus",
				 "sclk_pcm", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 4, 0, &lock);

	sclk_pcm_in = devm_clk_get(dev, "sclk_pcm_in");
	if (!IS_ERR(sclk_pcm_in))
		sclk_pcm_p = __clk_get_name(sclk_pcm_in);
	clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(dev, "sclk_pcm",
				sclk_pcm_p, CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 5, 0, &lock);

	if (variant->has_adma_clk) {
		clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma",
				"dout_srp", CLK_SET_RATE_PARENT,
				reg_base + ASS_CLK_GATE, 9, 0, &lock);
	}

	for (i = 0; i < clk_data->num; i++) {
		if (IS_ERR(clk_table[i])) {
			dev_err(dev, "failed to register clock %d\n", i);
			ret = PTR_ERR(clk_table[i]);
			goto unregister;
		}
	}

	ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
				     clk_data);
	if (ret) {
		dev_err(dev, "failed to add clock provider\n");
		goto unregister;
	}

	pm_runtime_put_sync(dev);

	return 0;

unregister:
	exynos_audss_clk_teardown();
	pm_runtime_put_sync(dev);
	pm_runtime_disable(dev);

	if (!IS_ERR(epll))
		clk_disable_unprepare(epll);

	return ret;
}

static int exynos_audss_clk_remove(struct platform_device *pdev)
{
	of_clk_del_provider(pdev->dev.of_node);

	exynos_audss_clk_teardown();
	pm_runtime_disable(&pdev->dev);

	if (!IS_ERR(epll))
		clk_disable_unprepare(epll);

	return 0;
}

static const struct dev_pm_ops exynos_audss_clk_pm_ops = {
	SET_RUNTIME_PM_OPS(exynos_audss_clk_suspend, exynos_audss_clk_resume,
			   NULL)
	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
				     pm_runtime_force_resume)
};

static struct platform_driver exynos_audss_clk_driver = {
	.driver	= {
		.name = "exynos-audss-clk",
		.of_match_table = exynos_audss_clk_of_match,
		.pm = &exynos_audss_clk_pm_ops,
	},
	.probe = exynos_audss_clk_probe,
	.remove = exynos_audss_clk_remove,
};

module_platform_driver(exynos_audss_clk_driver);

MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:exynos-audss-clk");
Commit	Line	Data
1241ef94 PV	1	/*
	2	* Copyright (c) 2013 Samsung Electronics Co., Ltd.
	3	* Author: Padmavathi Venna <padma.v@samsung.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* Common Clock Framework support for Audio Subsystem Clock Controller.
	10	*/
	11
6f1ed07a	12	#include <linux/slab.h>
1241ef94	13	#include <linux/io.h>
6f1ed07a	14	#include <linux/clk.h>
1241ef94 PV	15	#include <linux/clk-provider.h>
1241ef94 PV	16	#include <linux/of_address.h>
7c3ca061	17	#include <linux/of_device.h>
1241ef94	18	#include <linux/syscore_ops.h>
b37a4224 AB	19	#include <linux/module.h>
b37a4224 AB	20	#include <linux/platform_device.h>
ae432a9b	21	#include <linux/pm_runtime.h>
1241ef94	22
602408e3	23	#include <dt-bindings/clock/exynos-audss-clk.h>
1241ef94 PV	24
1241ef94 PV	25	static DEFINE_SPINLOCK(lock);
1241ef94	26	static void __iomem *reg_base;
5b2c3da1	27	static struct clk_hw_onecell_data *clk_data;
f1e9203e KK	28	/*
	29	* On Exynos5420 this will be a clock which has to be enabled before any
	30	* access to audss registers. Typically a child of EPLL.
	31	*
	32	* On other platforms this will be -ENODEV.
	33	*/
	34	static struct clk *epll;
1241ef94 PV	35
	36	#define ASS_CLK_SRC 0x0
	37	#define ASS_CLK_DIV 0x4
	38	#define ASS_CLK_GATE 0x8
	39
	40	static unsigned long reg_save[][2] = {
c17a6163 SN	41	{ ASS_CLK_SRC, 0 },
	42	{ ASS_CLK_DIV, 0 },
	43	{ ASS_CLK_GATE, 0 },
1241ef94 PV	44	};
1241ef94 PV	45
ae432a9b	46	static int __maybe_unused exynos_audss_clk_suspend(struct device *dev)
1241ef94 PV	47	{
	48	int i;
	49
	50	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
	51	reg_save[i][1] = readl(reg_base + reg_save[i][0]);
	52
	53	return 0;
	54	}
	55
ae432a9b	56	static int __maybe_unused exynos_audss_clk_resume(struct device *dev)
1241ef94 PV	57	{
	58	int i;
	59
	60	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
	61	writel(reg_save[i][1], reg_base + reg_save[i][0]);
1241ef94	62
a5b16dfa MS	63	return 0;
a5b16dfa MS	64	}
1241ef94	65
7c3ca061 SN	66	struct exynos_audss_clk_drvdata {
7c3ca061 SN	67	unsigned int has_adma_clk:1;
2ec865b7	68	unsigned int has_mst_clk:1;
7c3ca061 SN	69	unsigned int enable_epll:1;
	70	unsigned int num_clks;
	71	};
	72
	73	static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
	74	.num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
5bb4053b	75	.enable_epll = 1,
7c3ca061 SN	76	};
7c3ca061 SN	77
2ec865b7 SN	78	static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
	79	.num_clks = EXYNOS_AUDSS_MAX_CLKS - 1,
	80	.has_mst_clk = 1,
	81	};
	82
7c3ca061 SN	83	static const struct exynos_audss_clk_drvdata exynos5420_drvdata = {
	84	.num_clks = EXYNOS_AUDSS_MAX_CLKS,
	85	.has_adma_clk = 1,
	86	.enable_epll = 1,
	87	};
	88
3538a2cf	89	static const struct of_device_id exynos_audss_clk_of_match[] = {
7c3ca061 SN	90	{
	91	.compatible = "samsung,exynos4210-audss-clock",
	92	.data = &exynos4210_drvdata,
	93	}, {
	94	.compatible = "samsung,exynos5250-audss-clock",
	95	.data = &exynos4210_drvdata,
2ec865b7 SN	96	}, {
	97	.compatible = "samsung,exynos5410-audss-clock",
	98	.data = &exynos5410_drvdata,
7c3ca061 SN	99	}, {
	100	.compatible = "samsung,exynos5420-audss-clock",
	101	.data = &exynos5420_drvdata,
	102	},
	103	{ },
3538a2cf	104	};
34b89b29	105	MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
3538a2cf	106
27c76c43 KK	107	static void exynos_audss_clk_teardown(void)
	108	{
	109	int i;
	110
	111	for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) {
5b2c3da1 MS	112	if (!IS_ERR(clk_data->hws[i]))
5b2c3da1 MS	113	clk_hw_unregister_mux(clk_data->hws[i]);
27c76c43 KK	114	}
	115
	116	for (; i < EXYNOS_SRP_CLK; i++) {
5b2c3da1 MS	117	if (!IS_ERR(clk_data->hws[i]))
5b2c3da1 MS	118	clk_hw_unregister_divider(clk_data->hws[i]);
27c76c43 KK	119	}
27c76c43 KK	120
5b2c3da1 MS	121	for (; i < clk_data->num; i++) {
	122	if (!IS_ERR(clk_data->hws[i]))
	123	clk_hw_unregister_gate(clk_data->hws[i]);
27c76c43 KK	124	}
	125	}
	126
1241ef94	127	/* register exynos_audss clocks */
b37a4224	128	static int exynos_audss_clk_probe(struct platform_device *pdev)
1241ef94	129	{
547f3350 AB	130	const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
	131	const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
	132	const char *sclk_pcm_p = "sclk_pcm0";
	133	struct clk pll_ref, pll_in, cdclk, sclk_audio, *sclk_pcm_in;
7c3ca061	134	const struct exynos_audss_clk_drvdata *variant;
5b2c3da1	135	struct clk_hw **clk_table;
7c3ca061	136	struct resource *res;
232d7e47	137	struct device *dev = &pdev->dev;
7c3ca061	138	int i, ret = 0;
3538a2cf	139
7c3ca061 SN	140	variant = of_device_get_match_data(&pdev->dev);
7c3ca061 SN	141	if (!variant)
3538a2cf	142	return -EINVAL;
b37a4224 AB	143
b37a4224 AB	144	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
232d7e47	145	reg_base = devm_ioremap_resource(dev, res);
073f698d	146	if (IS_ERR(reg_base))
b37a4224	147	return PTR_ERR(reg_base);
7c3ca061	148
f1e9203e	149	epll = ERR_PTR(-ENODEV);
1241ef94	150
232d7e47	151	clk_data = devm_kzalloc(dev,
0ed2dd03 KC	152	struct_size(clk_data, hws,
0ed2dd03 KC	153	EXYNOS_AUDSS_MAX_CLKS),
1241ef94	154	GFP_KERNEL);
5b2c3da1	155	if (!clk_data)
b37a4224	156	return -ENOMEM;
1241ef94	157
5b2c3da1 MS	158	clk_data->num = variant->num_clks;
5b2c3da1 MS	159	clk_table = clk_data->hws;
1241ef94	160
232d7e47 MS	161	pll_ref = devm_clk_get(dev, "pll_ref");
232d7e47 MS	162	pll_in = devm_clk_get(dev, "pll_in");
547f3350 AB	163	if (!IS_ERR(pll_ref))
547f3350 AB	164	mout_audss_p[0] = __clk_get_name(pll_ref);
f1e9203e	165	if (!IS_ERR(pll_in)) {
547f3350	166	mout_audss_p[1] = __clk_get_name(pll_in);
f1e9203e	167
7c3ca061	168	if (variant->enable_epll) {
f1e9203e KK	169	epll = pll_in;
	170
	171	ret = clk_prepare_enable(epll);
	172	if (ret) {
232d7e47	173	dev_err(dev,
c17a6163	174	"failed to prepare the epll clock\n");
f1e9203e KK	175	return ret;
	176	}
	177	}
	178	}
ae432a9b MS	179
	180	/*
	181	* Enable runtime PM here to allow the clock core using runtime PM
	182	* for the registered clocks. Additionally, we increase the runtime
	183	* PM usage count before registering the clocks, to prevent the
	184	* clock core from runtime suspending the device.
	185	*/
	186	pm_runtime_get_noresume(dev);
	187	pm_runtime_set_active(dev);
	188	pm_runtime_enable(dev);
	189
	190	clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss",
819c1de3	191	mout_audss_p, ARRAY_SIZE(mout_audss_p),
7df45a53	192	CLK_SET_RATE_NO_REPARENT \| CLK_SET_RATE_PARENT,
1241ef94 PV	193	reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
1241ef94 PV	194
232d7e47 MS	195	cdclk = devm_clk_get(dev, "cdclk");
232d7e47 MS	196	sclk_audio = devm_clk_get(dev, "sclk_audio");
547f3350 AB	197	if (!IS_ERR(cdclk))
	198	mout_i2s_p[1] = __clk_get_name(cdclk);
	199	if (!IS_ERR(sclk_audio))
	200	mout_i2s_p[2] = __clk_get_name(sclk_audio);
ae432a9b	201	clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s",
819c1de3 JH	202	mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
819c1de3 JH	203	CLK_SET_RATE_NO_REPARENT,
1241ef94 PV	204	reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
1241ef94 PV	205
ae432a9b	206	clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp",
7df45a53 SN	207	"mout_audss", CLK_SET_RATE_PARENT,
7df45a53 SN	208	reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
1241ef94	209
ae432a9b	210	clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev,
7df45a53	211	"dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT,
1241ef94 PV	212	reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
1241ef94 PV	213
ae432a9b	214	clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
1241ef94 PV	215	"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
	216	&lock);
	217
ae432a9b	218	clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk",
1241ef94 PV	219	"dout_srp", CLK_SET_RATE_PARENT,
	220	reg_base + ASS_CLK_GATE, 0, 0, &lock);
	221
ae432a9b	222	clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus",
1241ef94 PV	223	"dout_aud_bus", CLK_SET_RATE_PARENT,
	224	reg_base + ASS_CLK_GATE, 2, 0, &lock);
	225
ae432a9b	226	clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s",
1241ef94 PV	227	"dout_i2s", CLK_SET_RATE_PARENT,
	228	reg_base + ASS_CLK_GATE, 3, 0, &lock);
	229
ae432a9b	230	clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus",
1241ef94 PV	231	"sclk_pcm", CLK_SET_RATE_PARENT,
	232	reg_base + ASS_CLK_GATE, 4, 0, &lock);
	233
232d7e47	234	sclk_pcm_in = devm_clk_get(dev, "sclk_pcm_in");
547f3350 AB	235	if (!IS_ERR(sclk_pcm_in))
547f3350 AB	236	sclk_pcm_p = __clk_get_name(sclk_pcm_in);
ae432a9b	237	clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(dev, "sclk_pcm",
547f3350	238	sclk_pcm_p, CLK_SET_RATE_PARENT,
1241ef94 PV	239	reg_base + ASS_CLK_GATE, 5, 0, &lock);
1241ef94 PV	240
7c3ca061	241	if (variant->has_adma_clk) {
ae432a9b	242	clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma",
3538a2cf AB	243	"dout_srp", CLK_SET_RATE_PARENT,
	244	reg_base + ASS_CLK_GATE, 9, 0, &lock);
	245	}
	246
5b2c3da1	247	for (i = 0; i < clk_data->num; i++) {
b37a4224	248	if (IS_ERR(clk_table[i])) {
232d7e47	249	dev_err(dev, "failed to register clock %d\n", i);
b37a4224 AB	250	ret = PTR_ERR(clk_table[i]);
	251	goto unregister;
	252	}
	253	}
	254
232d7e47	255	ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
5b2c3da1	256	clk_data);
b37a4224	257	if (ret) {
232d7e47	258	dev_err(dev, "failed to add clock provider\n");
b37a4224 AB	259	goto unregister;
	260	}
	261
ae432a9b MS	262	pm_runtime_put_sync(dev);
ae432a9b MS	263
b37a4224 AB	264	return 0;
	265
	266	unregister:
27c76c43	267	exynos_audss_clk_teardown();
ae432a9b MS	268	pm_runtime_put_sync(dev);
ae432a9b MS	269	pm_runtime_disable(dev);
b37a4224	270
f1e9203e KK	271	if (!IS_ERR(epll))
	272	clk_disable_unprepare(epll);
	273
b37a4224 AB	274	return ret;
	275	}
	276
	277	static int exynos_audss_clk_remove(struct platform_device *pdev)
	278	{
b37a4224 AB	279	of_clk_del_provider(pdev->dev.of_node);
b37a4224 AB	280
27c76c43	281	exynos_audss_clk_teardown();
ae432a9b	282	pm_runtime_disable(&pdev->dev);
b37a4224	283
f1e9203e KK	284	if (!IS_ERR(epll))
	285	clk_disable_unprepare(epll);
	286
b37a4224	287	return 0;
1241ef94	288	}
b37a4224	289
a5b16dfa	290	static const struct dev_pm_ops exynos_audss_clk_pm_ops = {
ae432a9b MS	291	SET_RUNTIME_PM_OPS(exynos_audss_clk_suspend, exynos_audss_clk_resume,
	292	NULL)
	293	SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
	294	pm_runtime_force_resume)
a5b16dfa MS	295	};
a5b16dfa MS	296
b37a4224 AB	297	static struct platform_driver exynos_audss_clk_driver = {
	298	.driver = {
	299	.name = "exynos-audss-clk",
b37a4224	300	.of_match_table = exynos_audss_clk_of_match,
a5b16dfa	301	.pm = &exynos_audss_clk_pm_ops,
b37a4224 AB	302	},
	303	.probe = exynos_audss_clk_probe,
	304	.remove = exynos_audss_clk_remove,
	305	};
	306
4d252fd5	307	module_platform_driver(exynos_audss_clk_driver);
b37a4224 AB	308
	309	MODULE_AUTHOR("Padmavathi Venna <padma.v@samsung.com>");
	310	MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
	311	MODULE_LICENSE("GPL v2");
	312	MODULE_ALIAS("platform:exynos-audss-clk");