projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| e062b571 TA |
1 | /* |
| 2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
| 3 | * Copyright (c) 2013 Linaro Ltd. | |
| 4 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | * | |
| 10 | * Common Clock Framework support for all Exynos4 SoCs. | |
| 11 | */ | |
| 12 | ||
| 13 | #include <linux/clk.h> | |
| 14 | #include <linux/clkdev.h> | |
| 15 | #include <linux/clk-provider.h> | |
| 16 | #include <linux/of.h> | |
| 17 | #include <linux/of_address.h> | |
| 18 | ||
| 19 | #include <plat/cpu.h> | |
| 20 | #include "clk.h" | |
| 21 | #include "clk-pll.h" | |
| 22 | ||
| 23 | /* Exynos4 clock controller register offsets */ | |
| 24 | #define SRC_LEFTBUS 0x4200 | |
| 25 | #define E4X12_GATE_IP_IMAGE 0x4930 | |
| 26 | #define GATE_IP_RIGHTBUS 0x8800 | |
| 27 | #define E4X12_GATE_IP_PERIR 0x8960 | |
| 28 | #define SRC_TOP0 0xc210 | |
| 29 | #define SRC_TOP1 0xc214 | |
| 30 | #define SRC_CAM 0xc220 | |
| 31 | #define SRC_TV 0xc224 | |
| 32 | #define SRC_MFC 0xcc28 | |
| 33 | #define SRC_G3D 0xc22c | |
| 34 | #define E4210_SRC_IMAGE 0xc230 | |
| 35 | #define SRC_LCD0 0xc234 | |
| 36 | #define SRC_LCD1 0xc238 | |
| 37 | #define SRC_MAUDIO 0xc23c | |
| 38 | #define SRC_FSYS 0xc240 | |
| 39 | #define SRC_PERIL0 0xc250 | |
| 40 | #define SRC_PERIL1 0xc254 | |
| 41 | #define E4X12_SRC_CAM1 0xc258 | |
| 42 | #define SRC_MASK_CAM 0xc320 | |
| 43 | #define SRC_MASK_TV 0xc324 | |
| 44 | #define SRC_MASK_LCD0 0xc334 | |
| 45 | #define SRC_MASK_LCD1 0xc338 | |
| 46 | #define SRC_MASK_MAUDIO 0xc33c | |
| 47 | #define SRC_MASK_FSYS 0xc340 | |
| 48 | #define SRC_MASK_PERIL0 0xc350 | |
| 49 | #define SRC_MASK_PERIL1 0xc354 | |
| 50 | #define DIV_TOP 0xc510 | |
| 51 | #define DIV_CAM 0xc520 | |
| 52 | #define DIV_TV 0xc524 | |
| 53 | #define DIV_MFC 0xc528 | |
| 54 | #define DIV_G3D 0xc52c | |
| 55 | #define DIV_IMAGE 0xc530 | |
| 56 | #define DIV_LCD0 0xc534 | |
| 57 | #define E4210_DIV_LCD1 0xc538 | |
| 58 | #define E4X12_DIV_ISP 0xc538 | |
| 59 | #define DIV_MAUDIO 0xc53c | |
| 60 | #define DIV_FSYS0 0xc540 | |
| 61 | #define DIV_FSYS1 0xc544 | |
| 62 | #define DIV_FSYS2 0xc548 | |
| 63 | #define DIV_FSYS3 0xc54c | |
| 64 | #define DIV_PERIL0 0xc550 | |
| 65 | #define DIV_PERIL1 0xc554 | |
| 66 | #define DIV_PERIL2 0xc558 | |
| 67 | #define DIV_PERIL3 0xc55c | |
| 68 | #define DIV_PERIL4 0xc560 | |
| 69 | #define DIV_PERIL5 0xc564 | |
| 70 | #define E4X12_DIV_CAM1 0xc568 | |
| 71 | #define GATE_SCLK_CAM 0xc820 | |
| 72 | #define GATE_IP_CAM 0xc920 | |
| 73 | #define GATE_IP_TV 0xc924 | |
| 74 | #define GATE_IP_MFC 0xc928 | |
| 75 | #define GATE_IP_G3D 0xc92c | |
| 76 | #define E4210_GATE_IP_IMAGE 0xc930 | |
| 77 | #define GATE_IP_LCD0 0xc934 | |
| 78 | #define GATE_IP_LCD1 0xc938 | |
| 79 | #define E4X12_GATE_IP_MAUDIO 0xc93c | |
| 80 | #define GATE_IP_FSYS 0xc940 | |
| 81 | #define GATE_IP_GPS 0xc94c | |
| 82 | #define GATE_IP_PERIL 0xc950 | |
| 83 | #define GATE_IP_PERIR 0xc960 | |
| 84 | #define E4X12_MPLL_CON0 0x10108 | |
| 85 | #define E4X12_SRC_DMC 0x10200 | |
| 86 | #define APLL_CON0 0x14100 | |
| 87 | #define E4210_MPLL_CON0 0x14108 | |
| 88 | #define SRC_CPU 0x14200 | |
| 89 | #define DIV_CPU0 0x14500 | |
| 90 | ||
| 91 | /* the exynos4 soc type */ | |
| 92 | enum exynos4_soc { | |
| 93 | EXYNOS4210, | |
| 94 | EXYNOS4X12, | |
| 95 | }; | |
| 96 | ||
| 97 | /* | |
| 98 | * Let each supported clock get a unique id. This id is used to lookup the clock | |
| 99 | * for device tree based platforms. The clocks are categorized into three | |
| 100 | * sections: core, sclk gate and bus interface gate clocks. | |
| 101 | * | |
| 102 | * When adding a new clock to this list, it is advised to choose a clock | |
| 103 | * category and add it to the end of that category. That is because the the | |
| 104 | * device tree source file is referring to these ids and any change in the | |
| 105 | * sequence number of existing clocks will require corresponding change in the | |
| 106 | * device tree files. This limitation would go away when pre-processor support | |
| 107 | * for dtc would be available. | |
| 108 | */ | |
| 109 | enum exynos4_clks { | |
| 110 | none, | |
| 111 | ||
| 112 | /* core clocks */ | |
| 113 | xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll, | |
| 114 | sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100, | |
| 74f7f8ba | 115 | aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, /* 18 */ |
| e062b571 TA |
116 | |
| 117 | /* gate for special clocks (sclk) */ | |
| 118 | sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0, | |
| 119 | sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac, | |
| 120 | sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0, | |
| 121 | sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4, | |
| 122 | sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4, | |
| 123 | sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, | |
| 124 | sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1, | |
| 36fc0972 | 125 | sclk_i2s2, sclk_mipihsi, sclk_mfc, |
| e062b571 TA |
126 | |
| 127 | /* gate clocks */ | |
| 128 | fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0, | |
| 129 | smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi, | |
| 130 | smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d, | |
| 131 | smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1, | |
| 132 | mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0, | |
| 133 | sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie, | |
| 134 | onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3, | |
| 135 | uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, | |
| 136 | spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus, | |
| 137 | spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif, | |
| 138 | audss, mipi_hsi, mdma2, | |
| 139 | ||
| 140 | nr_clks, | |
| 141 | }; | |
| 142 | ||
| 143 | /* | |
| 144 | * list of controller registers to be saved and restored during a | |
| 145 | * suspend/resume cycle. | |
| 146 | */ | |
| 147 | static __initdata unsigned long exynos4_clk_regs[] = { | |
| 148 | SRC_LEFTBUS, | |
| 149 | E4X12_GATE_IP_IMAGE, | |
| 150 | GATE_IP_RIGHTBUS, | |
| 151 | E4X12_GATE_IP_PERIR, | |
| 152 | SRC_TOP0, | |
| 153 | SRC_TOP1, | |
| 154 | SRC_CAM, | |
| 155 | SRC_TV, | |
| 156 | SRC_MFC, | |
| 157 | SRC_G3D, | |
| 158 | E4210_SRC_IMAGE, | |
| 159 | SRC_LCD0, | |
| 160 | SRC_LCD1, | |
| 161 | SRC_MAUDIO, | |
| 162 | SRC_FSYS, | |
| 163 | SRC_PERIL0, | |
| 164 | SRC_PERIL1, | |
| 165 | E4X12_SRC_CAM1, | |
| 166 | SRC_MASK_CAM, | |
| 167 | SRC_MASK_TV, | |
| 168 | SRC_MASK_LCD0, | |
| 169 | SRC_MASK_LCD1, | |
| 170 | SRC_MASK_MAUDIO, | |
| 171 | SRC_MASK_FSYS, | |
| 172 | SRC_MASK_PERIL0, | |
| 173 | SRC_MASK_PERIL1, | |
| 174 | DIV_TOP, | |
| 175 | DIV_CAM, | |
| 176 | DIV_TV, | |
| 177 | DIV_MFC, | |
| 178 | DIV_G3D, | |
| 179 | DIV_IMAGE, | |
| 180 | DIV_LCD0, | |
| 181 | E4210_DIV_LCD1, | |
| 182 | E4X12_DIV_ISP, | |
| 183 | DIV_MAUDIO, | |
| 184 | DIV_FSYS0, | |
| 185 | DIV_FSYS1, | |
| 186 | DIV_FSYS2, | |
| 187 | DIV_FSYS3, | |
| 188 | DIV_PERIL0, | |
| 189 | DIV_PERIL1, | |
| 190 | DIV_PERIL2, | |
| 191 | DIV_PERIL3, | |
| 192 | DIV_PERIL4, | |
| 193 | DIV_PERIL5, | |
| 194 | E4X12_DIV_CAM1, | |
| 195 | GATE_SCLK_CAM, | |
| 196 | GATE_IP_CAM, | |
| 197 | GATE_IP_TV, | |
| 198 | GATE_IP_MFC, | |
| 199 | GATE_IP_G3D, | |
| 200 | E4210_GATE_IP_IMAGE, | |
| 201 | GATE_IP_LCD0, | |
| 202 | GATE_IP_LCD1, | |
| 203 | E4X12_GATE_IP_MAUDIO, | |
| 204 | GATE_IP_FSYS, | |
| 205 | GATE_IP_GPS, | |
| 206 | GATE_IP_PERIL, | |
| 207 | GATE_IP_PERIR, | |
| 208 | E4X12_MPLL_CON0, | |
| 209 | E4X12_SRC_DMC, | |
| 210 | APLL_CON0, | |
| 211 | E4210_MPLL_CON0, | |
| 212 | SRC_CPU, | |
| 213 | DIV_CPU0, | |
| 214 | }; | |
| 215 | ||
| 216 | /* list of all parent clock list */ | |
| 217 | PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; | |
| 218 | PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; | |
| 219 | PNAME(mout_epll_p) = { "fin_pll", "fout_epll", }; | |
| 220 | PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", }; | |
| e062b571 | 221 | PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", }; |
| e062b571 TA |
222 | PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", }; |
| 223 | PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", }; | |
| 224 | PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", }; | |
| 225 | PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", }; | |
| e062b571 TA |
226 | PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", }; |
| 227 | PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", }; | |
| e062b571 TA |
228 | PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", |
| 229 | "spdif_extclk", }; | |
| 230 | ||
| 74f7f8ba TF |
231 | /* Exynos 4210-specific parent groups */ |
| 232 | PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", }; | |
| 233 | PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", }; | |
| 234 | PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", }; | |
| 235 | PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", | |
| 236 | "sclk_usbphy0", "none", "sclk_hdmiphy", | |
| 237 | "sclk_mpll", "sclk_epll", "sclk_vpll", }; | |
| 238 | PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m", | |
| 239 | "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", | |
| 240 | "sclk_epll", "sclk_vpll" }; | |
| 241 | PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m", | |
| 242 | "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", | |
| 243 | "sclk_epll", "sclk_vpll", }; | |
| 244 | PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m", | |
| 245 | "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", | |
| 246 | "sclk_epll", "sclk_vpll", }; | |
| 247 | PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", }; | |
| 248 | PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", }; | |
| 249 | ||
| 250 | /* Exynos 4x12-specific parent groups */ | |
| 251 | PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", }; | |
| 252 | PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", }; | |
| 253 | PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", }; | |
| 254 | PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", | |
| 255 | "none", "sclk_hdmiphy", "mout_mpll_user_t", | |
| 256 | "sclk_epll", "sclk_vpll", }; | |
| 257 | PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m", | |
| 258 | "sclk_usbphy0", "xxti", "xusbxti", | |
| 259 | "mout_mpll_user_t", "sclk_epll", "sclk_vpll" }; | |
| 260 | PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m", | |
| 261 | "sclk_usbphy0", "xxti", "xusbxti", | |
| 262 | "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; | |
| 263 | PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m", | |
| 264 | "sclk_usbphy0", "xxti", "xusbxti", | |
| 265 | "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; | |
| 266 | PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", }; | |
| 267 | ||
| e062b571 TA |
268 | /* fixed rate clocks generated outside the soc */ |
| 269 | struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { | |
| 270 | FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0), | |
| 271 | FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0), | |
| 272 | }; | |
| 273 | ||
| 274 | /* fixed rate clocks generated inside the soc */ | |
| 275 | struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { | |
| 276 | FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), | |
| 277 | FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), | |
| 278 | FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), | |
| 279 | }; | |
| 280 | ||
| 281 | struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { | |
| 282 | FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), | |
| 283 | }; | |
| 284 | ||
| 285 | /* list of mux clocks supported in all exynos4 soc's */ | |
| 286 | struct samsung_mux_clock exynos4_mux_clks[] __initdata = { | |
| 287 | MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), | |
| e062b571 | 288 | MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), |
| e062b571 TA |
289 | MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), |
| 290 | MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), | |
| e062b571 TA |
291 | MUX(none, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1), |
| 292 | MUX(none, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1), | |
| e062b571 | 293 | MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), |
| e062b571 TA |
294 | MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"), |
| 295 | }; | |
| 296 | ||
| 297 | /* list of mux clocks supported in exynos4210 soc */ | |
| 298 | struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { | |
| 74f7f8ba TF |
299 | MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), |
| 300 | MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), | |
| 301 | MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), | |
| 302 | MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1), | |
| e062b571 TA |
303 | MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), |
| 304 | MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1), | |
| 305 | MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1), | |
| 74f7f8ba | 306 | MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), |
| e062b571 TA |
307 | MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), |
| 308 | MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), | |
| 74f7f8ba TF |
309 | MUX(none, "mout_fimd1", group1_p4210, SRC_LCD1, 0, 4), |
| 310 | MUX(none, "mout_mipi1", group1_p4210, SRC_LCD1, 12, 4), | |
| e062b571 | 311 | MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"), |
| 74f7f8ba | 312 | MUX(none, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), |
| e062b571 TA |
313 | MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, |
| 314 | SRC_TOP0, 8, 1, "sclk_vpll"), | |
| 74f7f8ba TF |
315 | MUX(none, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), |
| 316 | MUX(none, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), | |
| 317 | MUX(none, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), | |
| 318 | MUX(none, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), | |
| 319 | MUX(none, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), | |
| 320 | MUX(none, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), | |
| 321 | MUX(none, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), | |
| 322 | MUX(none, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), | |
| 323 | MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), | |
| 324 | MUX(none, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1), | |
| 325 | MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), | |
| 326 | MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4), | |
| 327 | MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4), | |
| 328 | MUX(none, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4), | |
| 329 | MUX(none, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4), | |
| 330 | MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4), | |
| 331 | MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4), | |
| 332 | MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4), | |
| 333 | MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4), | |
| 334 | MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4), | |
| 335 | MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4), | |
| 336 | MUX(none, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4), | |
| 337 | MUX(none, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4), | |
| 338 | MUX(none, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4), | |
| 339 | MUX(none, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4), | |
| 340 | MUX(none, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), | |
| 341 | MUX(none, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), | |
| 342 | MUX(none, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), | |
| e062b571 TA |
343 | }; |
| 344 | ||
| 345 | /* list of mux clocks supported in exynos4x12 soc */ | |
| 346 | struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { | |
| 74f7f8ba TF |
347 | MUX(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12, |
| 348 | SRC_CPU, 24, 1), | |
| 349 | MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12, | |
| 350 | SRC_TOP1, 12, 1), | |
| e062b571 TA |
351 | MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1), |
| 352 | MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1), | |
| 353 | MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1), | |
| 354 | MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1), | |
| 74f7f8ba TF |
355 | MUX(none, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4), |
| 356 | MUX(none, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4), | |
| 357 | MUX(none, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1), | |
| 358 | MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), | |
| e062b571 TA |
359 | MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), |
| 360 | MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), | |
| 361 | MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, | |
| 362 | E4X12_SRC_DMC, 12, 1, "sclk_mpll"), | |
| 363 | MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p, | |
| 364 | SRC_TOP0, 8, 1, "sclk_vpll"), | |
| 74f7f8ba TF |
365 | MUX(none, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), |
| 366 | MUX(none, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), | |
| 367 | MUX(none, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), | |
| 368 | MUX(none, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), | |
| 369 | MUX(none, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), | |
| 370 | MUX(none, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), | |
| 371 | MUX(none, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), | |
| 372 | MUX(none, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), | |
| 373 | MUX(none, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), | |
| 374 | MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), | |
| 375 | MUX(none, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1), | |
| 376 | MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), | |
| 377 | MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4), | |
| 378 | MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4), | |
| 379 | MUX(none, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4), | |
| 380 | MUX(none, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4), | |
| 381 | MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4), | |
| 382 | MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4), | |
| 383 | MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4), | |
| 4c3cc72c | 384 | MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1), |
| 74f7f8ba TF |
385 | MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4), |
| 386 | MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4), | |
| 387 | MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4), | |
| 388 | MUX(none, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4), | |
| 389 | MUX(none, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4), | |
| 390 | MUX(none, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4), | |
| 391 | MUX(none, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4), | |
| 392 | MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4), | |
| 393 | MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4), | |
| 394 | MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4), | |
| e062b571 TA |
395 | }; |
| 396 | ||
| 397 | /* list of divider clocks supported in all exynos4 soc's */ | |
| 398 | struct samsung_div_clock exynos4_div_clks[] __initdata = { | |
| 399 | DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3), | |
| 400 | DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3), | |
| 401 | DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), | |
| 402 | DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), | |
| 403 | DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), | |
| 404 | DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4), | |
| 405 | DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4), | |
| 406 | DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), | |
| 407 | DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), | |
| 408 | DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), | |
| 36fc0972 | 409 | DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4), |
| e062b571 TA |
410 | DIV(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4), |
| 411 | DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), | |
| 412 | DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), | |
| 413 | DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4), | |
| 414 | DIV(none, "div_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8), | |
| 415 | DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), | |
| 416 | DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), | |
| 417 | DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), | |
| 418 | DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), | |
| 419 | DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4), | |
| 420 | DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), | |
| 421 | DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4), | |
| 422 | DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3), | |
| 423 | DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3), | |
| 424 | DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4), | |
| 425 | DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8), | |
| 426 | DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8), | |
| 427 | DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), | |
| 428 | DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), | |
| 429 | DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), | |
| 430 | DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8), | |
| 431 | DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), | |
| 432 | DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), | |
| 433 | DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), | |
| 434 | DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), | |
| 435 | DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), | |
| 436 | DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), | |
| 437 | DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), | |
| 438 | DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), | |
| 439 | DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), | |
| 440 | DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), | |
| 441 | DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), | |
| 442 | DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), | |
| 443 | DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), | |
| 444 | DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "arm_clk"), | |
| 445 | DIV_A(sclk_apll, "sclk_apll", "mout_apll", | |
| 446 | DIV_CPU0, 24, 3, "sclk_apll"), | |
| 447 | DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, | |
| 448 | CLK_SET_RATE_PARENT, 0), | |
| 449 | DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, | |
| 450 | CLK_SET_RATE_PARENT, 0), | |
| 451 | DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, | |
| 452 | CLK_SET_RATE_PARENT, 0), | |
| 453 | DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, | |
| 454 | CLK_SET_RATE_PARENT, 0), | |
| 455 | DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, | |
| 456 | CLK_SET_RATE_PARENT, 0), | |
| 457 | }; | |
| 458 | ||
| 459 | /* list of divider clocks supported in exynos4210 soc */ | |
| 460 | struct samsung_div_clock exynos4210_div_clks[] __initdata = { | |
| 461 | DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4), | |
| 462 | DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), | |
| 463 | DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), | |
| 464 | DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), | |
| 465 | DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4, | |
| 466 | CLK_SET_RATE_PARENT, 0), | |
| 467 | }; | |
| 468 | ||
| 469 | /* list of divider clocks supported in exynos4x12 soc */ | |
| 470 | struct samsung_div_clock exynos4x12_div_clks[] __initdata = { | |
| 471 | DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), | |
| 472 | DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), | |
| 473 | DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), | |
| 474 | DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4), | |
| 475 | DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4), | |
| 476 | }; | |
| 477 | ||
| 478 | /* list of gate clocks supported in all exynos4 soc's */ | |
| 479 | struct samsung_gate_clock exynos4_gate_clks[] __initdata = { | |
| 480 | /* | |
| 481 | * After all Exynos4 based platforms are migrated to use device tree, | |
| 482 | * the device name and clock alias names specified below for some | |
| 483 | * of the clocks can be removed. | |
| 484 | */ | |
| 485 | GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), | |
| 486 | GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), | |
| 487 | GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), | |
| 488 | GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 0xc354, 8, 0, 0), | |
| 489 | GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), | |
| 490 | GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), | |
| 491 | GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), | |
| 492 | GATE(fimd1, "fimd1", "aclk160", GATE_IP_LCD1, 0, 0, 0), | |
| 493 | GATE(mie1, "mie1", "aclk160", GATE_IP_LCD1, 1, 0, 0), | |
| 494 | GATE(dsim1, "dsim1", "aclk160", GATE_IP_LCD1, 3, 0, 0), | |
| 495 | GATE(smmu_fimd1, "smmu_fimd1", "aclk160", GATE_IP_LCD1, 4, 0, 0), | |
| 496 | GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), | |
| 497 | GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), | |
| 498 | GATE(g3d, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0), | |
| 499 | GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), | |
| 500 | GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), | |
| 501 | GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), | |
| 502 | GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), | |
| 503 | GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), | |
| 504 | GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), | |
| 505 | GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, | |
| 506 | CLK_SET_RATE_PARENT, 0), | |
| 507 | GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5, | |
| 508 | CLK_SET_RATE_PARENT, 0), | |
| 509 | GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0", | |
| 510 | SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0), | |
| 69aff2fd TF |
511 | GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0, |
| 512 | CLK_SET_RATE_PARENT, 0), | |
| e062b571 TA |
513 | GATE(sclk_audio1, "sclk_audio1", "div_audio1", 0xc354, 0, |
| 514 | CLK_SET_RATE_PARENT, 0), | |
| 515 | GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0), | |
| 516 | GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), | |
| 517 | GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0), | |
| 518 | GATE_A(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"), | |
| 519 | GATE_A(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"), | |
| 520 | GATE_A(usb_host, "usb_host", "aclk133", | |
| 521 | GATE_IP_FSYS, 12, 0, 0, "usbhost"), | |
| 522 | GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0", | |
| 523 | SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), | |
| 524 | GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1", | |
| 525 | SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), | |
| 526 | GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2", | |
| 527 | SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), | |
| 528 | GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3", | |
| 529 | SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), | |
| 530 | GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0", | |
| 531 | SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"), | |
| 532 | GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1", | |
| 533 | SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"), | |
| 534 | GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0", | |
| 535 | SRC_MASK_LCD0, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), | |
| 536 | GATE_DA(sclk_mmc0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc_pre0", | |
| 537 | SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0, | |
| 538 | "mmc_busclk.2"), | |
| 539 | GATE_DA(sclk_mmc1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc_pre1", | |
| 540 | SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0, | |
| 541 | "mmc_busclk.2"), | |
| 542 | GATE_DA(sclk_mmc2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc_pre2", | |
| 543 | SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0, | |
| 544 | "mmc_busclk.2"), | |
| 545 | GATE_DA(sclk_mmc3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc_pre3", | |
| 546 | SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0, | |
| 547 | "mmc_busclk.2"), | |
| 548 | GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4", | |
| 549 | SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"), | |
| 550 | GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0", | |
| 551 | 0xc350, 0, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), | |
| 552 | GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1", | |
| 553 | 0xc350, 4, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), | |
| 554 | GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2", | |
| 555 | 0xc350, 8, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), | |
| 556 | GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3", | |
| 557 | 0xc350, 12, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), | |
| 558 | GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4", | |
| 559 | 0xc350, 16, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), | |
| 560 | GATE(sclk_audio2, "sclk_audio2", "div_audio2", 0xc354, 4, | |
| 561 | CLK_SET_RATE_PARENT, 0), | |
| 562 | GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0", | |
| 563 | 0xc354, 16, CLK_SET_RATE_PARENT, 0, "spi_busclk0"), | |
| 564 | GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1", | |
| 565 | 0xc354, 20, CLK_SET_RATE_PARENT, 0, "spi_busclk0"), | |
| 566 | GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2", | |
| 567 | 0xc354, 24, CLK_SET_RATE_PARENT, 0, "spi_busclk0"), | |
| 568 | GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160", | |
| 569 | GATE_IP_CAM, 0, 0, 0, "fimc"), | |
| 570 | GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160", | |
| 571 | GATE_IP_CAM, 1, 0, 0, "fimc"), | |
| 572 | GATE_DA(fimc2, "exynos4-fimc.2", "fimc2", "aclk160", | |
| 573 | GATE_IP_CAM, 2, 0, 0, "fimc"), | |
| 574 | GATE_DA(fimc3, "exynos4-fimc.3", "fimc3", "aclk160", | |
| 575 | GATE_IP_CAM, 3, 0, 0, "fimc"), | |
| 576 | GATE_DA(csis0, "s5p-mipi-csis.0", "csis0", "aclk160", | |
| 577 | GATE_IP_CAM, 4, 0, 0, "fimc"), | |
| 578 | GATE_DA(csis1, "s5p-mipi-csis.1", "csis1", "aclk160", | |
| 579 | GATE_IP_CAM, 5, 0, 0, "fimc"), | |
| 580 | GATE_DA(smmu_fimc0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160", | |
| 581 | GATE_IP_CAM, 7, 0, 0, "sysmmu"), | |
| 582 | GATE_DA(smmu_fimc1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160", | |
| 583 | GATE_IP_CAM, 8, 0, 0, "sysmmu"), | |
| 584 | GATE_DA(smmu_fimc2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160", | |
| 585 | GATE_IP_CAM, 9, 0, 0, "sysmmu"), | |
| 586 | GATE_DA(smmu_fimc3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160", | |
| 587 | GATE_IP_CAM, 10, 0, 0, "sysmmu"), | |
| 588 | GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160", | |
| 589 | GATE_IP_CAM, 11, 0, 0, "sysmmu"), | |
| 590 | GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160", | |
| 591 | GATE_IP_TV, 4, 0, 0, "sysmmu"), | |
| 592 | GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"), | |
| 593 | GATE_DA(smmu_mfcl, "exynos-sysmmu.0", "smmu_mfcl", "aclk100", | |
| 594 | GATE_IP_MFC, 1, 0, 0, "sysmmu"), | |
| 595 | GATE_DA(smmu_mfcr, "exynos-sysmmu.1", "smmu_mfcr", "aclk100", | |
| 596 | GATE_IP_MFC, 2, 0, 0, "sysmmu"), | |
| 597 | GATE_DA(fimd0, "exynos4-fb.0", "fimd0", "aclk160", | |
| 598 | GATE_IP_LCD0, 0, 0, 0, "fimd"), | |
| 599 | GATE_DA(smmu_fimd0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160", | |
| 600 | GATE_IP_LCD0, 4, 0, 0, "sysmmu"), | |
| 601 | GATE_DA(pdma0, "dma-pl330.0", "pdma0", "aclk133", | |
| 602 | GATE_IP_FSYS, 0, 0, 0, "dma"), | |
| 603 | GATE_DA(pdma1, "dma-pl330.1", "pdma1", "aclk133", | |
| 604 | GATE_IP_FSYS, 1, 0, 0, "dma"), | |
| 605 | GATE_DA(sdmmc0, "exynos4-sdhci.0", "sdmmc0", "aclk133", | |
| 606 | GATE_IP_FSYS, 5, 0, 0, "hsmmc"), | |
| 607 | GATE_DA(sdmmc1, "exynos4-sdhci.1", "sdmmc1", "aclk133", | |
| 608 | GATE_IP_FSYS, 6, 0, 0, "hsmmc"), | |
| 609 | GATE_DA(sdmmc2, "exynos4-sdhci.2", "sdmmc2", "aclk133", | |
| 610 | GATE_IP_FSYS, 7, 0, 0, "hsmmc"), | |
| 611 | GATE_DA(sdmmc3, "exynos4-sdhci.3", "sdmmc3", "aclk133", | |
| 612 | GATE_IP_FSYS, 8, 0, 0, "hsmmc"), | |
| 613 | GATE_DA(uart0, "exynos4210-uart.0", "uart0", "aclk100", | |
| 614 | GATE_IP_PERIL, 0, 0, 0, "uart"), | |
| 615 | GATE_DA(uart1, "exynos4210-uart.1", "uart1", "aclk100", | |
| 616 | GATE_IP_PERIL, 1, 0, 0, "uart"), | |
| 617 | GATE_DA(uart2, "exynos4210-uart.2", "uart2", "aclk100", | |
| 618 | GATE_IP_PERIL, 2, 0, 0, "uart"), | |
| 619 | GATE_DA(uart3, "exynos4210-uart.3", "uart3", "aclk100", | |
| 620 | GATE_IP_PERIL, 3, 0, 0, "uart"), | |
| 621 | GATE_DA(uart4, "exynos4210-uart.4", "uart4", "aclk100", | |
| 622 | GATE_IP_PERIL, 4, 0, 0, "uart"), | |
| 623 | GATE_DA(i2c0, "s3c2440-i2c.0", "i2c0", "aclk100", | |
| 624 | GATE_IP_PERIL, 6, 0, 0, "i2c"), | |
| 625 | GATE_DA(i2c1, "s3c2440-i2c.1", "i2c1", "aclk100", | |
| 626 | GATE_IP_PERIL, 7, 0, 0, "i2c"), | |
| 627 | GATE_DA(i2c2, "s3c2440-i2c.2", "i2c2", "aclk100", | |
| 628 | GATE_IP_PERIL, 8, 0, 0, "i2c"), | |
| 629 | GATE_DA(i2c3, "s3c2440-i2c.3", "i2c3", "aclk100", | |
| 630 | GATE_IP_PERIL, 9, 0, 0, "i2c"), | |
| 631 | GATE_DA(i2c4, "s3c2440-i2c.4", "i2c4", "aclk100", | |
| 632 | GATE_IP_PERIL, 10, 0, 0, "i2c"), | |
| 633 | GATE_DA(i2c5, "s3c2440-i2c.5", "i2c5", "aclk100", | |
| 634 | GATE_IP_PERIL, 11, 0, 0, "i2c"), | |
| 635 | GATE_DA(i2c6, "s3c2440-i2c.6", "i2c6", "aclk100", | |
| 636 | GATE_IP_PERIL, 12, 0, 0, "i2c"), | |
| 637 | GATE_DA(i2c7, "s3c2440-i2c.7", "i2c7", "aclk100", | |
| 638 | GATE_IP_PERIL, 13, 0, 0, "i2c"), | |
| 639 | GATE_DA(i2c_hdmi, "s3c2440-hdmiphy-i2c", "i2c-hdmi", "aclk100", | |
| 640 | GATE_IP_PERIL, 14, 0, 0, "i2c"), | |
| 641 | GATE_DA(spi0, "exynos4210-spi.0", "spi0", "aclk100", | |
| 642 | GATE_IP_PERIL, 16, 0, 0, "spi"), | |
| 643 | GATE_DA(spi1, "exynos4210-spi.1", "spi1", "aclk100", | |
| 644 | GATE_IP_PERIL, 17, 0, 0, "spi"), | |
| 645 | GATE_DA(spi2, "exynos4210-spi.2", "spi2", "aclk100", | |
| 646 | GATE_IP_PERIL, 18, 0, 0, "spi"), | |
| 647 | GATE_DA(i2s1, "samsung-i2s.1", "i2s1", "aclk100", | |
| 648 | GATE_IP_PERIL, 20, 0, 0, "iis"), | |
| 649 | GATE_DA(i2s2, "samsung-i2s.2", "i2s2", "aclk100", | |
| 650 | GATE_IP_PERIL, 21, 0, 0, "iis"), | |
| 651 | GATE_DA(pcm1, "samsung-pcm.1", "pcm1", "aclk100", | |
| 652 | GATE_IP_PERIL, 22, 0, 0, "pcm"), | |
| 653 | GATE_DA(pcm2, "samsung-pcm.2", "pcm2", "aclk100", | |
| 654 | GATE_IP_PERIL, 23, 0, 0, "pcm"), | |
| 655 | GATE_DA(spdif, "samsung-spdif", "spdif", "aclk100", | |
| 656 | GATE_IP_PERIL, 26, 0, 0, "spdif"), | |
| 657 | GATE_DA(ac97, "samsung-ac97", "ac97", "aclk100", | |
| 658 | GATE_IP_PERIL, 27, 0, 0, "ac97"), | |
| 659 | }; | |
| 660 | ||
| 661 | /* list of gate clocks supported in exynos4210 soc */ | |
| 662 | struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { | |
| 663 | GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), | |
| 664 | GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), | |
| 665 | GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), | |
| 666 | GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0), | |
| 667 | GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), | |
| 668 | GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0), | |
| 669 | GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), | |
| 670 | GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), | |
| 671 | GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), | |
| 672 | GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), | |
| 673 | GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), | |
| 674 | GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), | |
| 675 | GATE(chipid, "chipid", "aclk100", GATE_IP_PERIR, 0, 0, 0), | |
| 676 | GATE(sysreg, "sysreg", "aclk100", GATE_IP_PERIR, 0, 0, 0), | |
| 677 | GATE(hdmi_cec, "hdmi_cec", "aclk100", GATE_IP_PERIR, 11, 0, 0), | |
| 678 | GATE(smmu_rotator, "smmu_rotator", "aclk200", | |
| 679 | E4210_GATE_IP_IMAGE, 4, 0, 0), | |
| 680 | GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1", | |
| 681 | SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), | |
| 682 | GATE(sclk_sata, "sclk_sata", "div_sata", | |
| 683 | SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), | |
| 684 | GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"), | |
| 685 | GATE_A(mct, "mct", "aclk100", GATE_IP_PERIR, 13, 0, 0, "mct"), | |
| 686 | GATE_A(wdt, "watchdog", "aclk100", GATE_IP_PERIR, 14, 0, 0, "watchdog"), | |
| 687 | GATE_A(rtc, "rtc", "aclk100", GATE_IP_PERIR, 15, 0, 0, "rtc"), | |
| 688 | GATE_A(keyif, "keyif", "aclk100", GATE_IP_PERIR, 16, 0, 0, "keypad"), | |
| 689 | GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1", | |
| 690 | SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), | |
| 691 | }; | |
| 692 | ||
| 693 | /* list of gate clocks supported in exynos4x12 soc */ | |
| 694 | struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { | |
| 695 | GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), | |
| 696 | GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), | |
| 697 | GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), | |
| 698 | GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), | |
| 699 | GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0), | |
| 700 | GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), | |
| 701 | GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), | |
| 702 | GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0), | |
| 703 | GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0), | |
| 704 | GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0", | |
| 705 | SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), | |
| 706 | GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0", | |
| 707 | SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0), | |
| 708 | GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi", | |
| 709 | SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), | |
| 710 | GATE(smmu_rotator, "smmu_rotator", "aclk200", | |
| 711 | E4X12_GATE_IP_IMAGE, 4, 0, 0), | |
| 712 | GATE_A(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 0, 0, "mct"), | |
| 713 | GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"), | |
| 714 | GATE_A(keyif, "keyif", "aclk100", | |
| 715 | E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"), | |
| 716 | GATE_A(wdt, "watchdog", "aclk100", | |
| 717 | E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"), | |
| 718 | GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100", | |
| 719 | E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"), | |
| 720 | GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100", | |
| 721 | E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"), | |
| 722 | }; | |
| 723 | ||
| 724 | #ifdef CONFIG_OF | |
| 725 | static struct of_device_id exynos4_clk_ids[] __initdata = { | |
| 726 | { .compatible = "samsung,exynos4210-clock", | |
| 727 | .data = (void *)EXYNOS4210, }, | |
| 728 | { .compatible = "samsung,exynos4412-clock", | |
| 729 | .data = (void *)EXYNOS4X12, }, | |
| 730 | { }, | |
| 731 | }; | |
| 732 | #endif | |
| 733 | ||
| 734 | /* | |
| 735 | * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit | |
| 736 | * resides in chipid register space, outside of the clock controller memory | |
| 737 | * mapped space. So to determine the parent of fin_pll clock, the chipid | |
| 738 | * controller is first remapped and the value of XOM[0] bit is read to | |
| 739 | * determine the parent clock. | |
| 740 | */ | |
| 741 | static void __init exynos4_clk_register_finpll(void) | |
| 742 | { | |
| 743 | struct samsung_fixed_rate_clock fclk; | |
| 744 | struct device_node *np; | |
| 745 | struct clk *clk; | |
| 746 | void __iomem *chipid_base = S5P_VA_CHIPID; | |
| 747 | unsigned long xom, finpll_f = 24000000; | |
| 748 | char *parent_name; | |
| 749 | ||
| 750 | np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid"); | |
| 751 | if (np) | |
| 752 | chipid_base = of_iomap(np, 0); | |
| 753 | ||
| 754 | if (chipid_base) { | |
| 755 | xom = readl(chipid_base + 8); | |
| 756 | parent_name = xom & 1 ? "xusbxti" : "xxti"; | |
| 757 | clk = clk_get(NULL, parent_name); | |
| 758 | if (IS_ERR(clk)) { | |
| 759 | pr_err("%s: failed to lookup parent clock %s, assuming " | |
| 760 | "fin_pll clock frequency is 24MHz\n", __func__, | |
| 761 | parent_name); | |
| 762 | } else { | |
| 763 | finpll_f = clk_get_rate(clk); | |
| 764 | } | |
| 765 | } else { | |
| 766 | pr_err("%s: failed to map chipid registers, assuming " | |
| 767 | "fin_pll clock frequency is 24MHz\n", __func__); | |
| 768 | } | |
| 769 | ||
| 770 | fclk.id = fin_pll; | |
| 771 | fclk.name = "fin_pll"; | |
| 772 | fclk.parent_name = NULL; | |
| 773 | fclk.flags = CLK_IS_ROOT; | |
| 774 | fclk.fixed_rate = finpll_f; | |
| 775 | samsung_clk_register_fixed_rate(&fclk, 1); | |
| 776 | ||
| 777 | if (np) | |
| 778 | iounmap(chipid_base); | |
| 779 | } | |
| 780 | ||
| 781 | /* | |
| 782 | * This function allows non-dt platforms to specify the clock speed of the | |
| 783 | * xxti and xusbxti clocks. These clocks are then registered with the specified | |
| 784 | * clock speed. | |
| 785 | */ | |
| 786 | void __init exynos4_clk_register_fixed_ext(unsigned long xxti_f, | |
| 787 | unsigned long xusbxti_f) | |
| 788 | { | |
| 789 | exynos4_fixed_rate_ext_clks[0].fixed_rate = xxti_f; | |
| 790 | exynos4_fixed_rate_ext_clks[1].fixed_rate = xusbxti_f; | |
| 791 | samsung_clk_register_fixed_rate(exynos4_fixed_rate_ext_clks, | |
| 792 | ARRAY_SIZE(exynos4_fixed_rate_ext_clks)); | |
| 793 | } | |
| 794 | ||
| 795 | static __initdata struct of_device_id ext_clk_match[] = { | |
| 796 | { .compatible = "samsung,clock-xxti", .data = (void *)0, }, | |
| 797 | { .compatible = "samsung,clock-xusbxti", .data = (void *)1, }, | |
| 798 | {}, | |
| 799 | }; | |
| 800 | ||
| 801 | /* register exynos4 clocks */ | |
| 802 | void __init exynos4_clk_init(struct device_node *np) | |
| 803 | { | |
| 804 | void __iomem *reg_base; | |
| 805 | struct clk *apll, *mpll, *epll, *vpll; | |
| 806 | u32 exynos4_soc; | |
| 807 | ||
| 808 | if (np) { | |
| 809 | const struct of_device_id *match; | |
| 810 | match = of_match_node(exynos4_clk_ids, np); | |
| 811 | exynos4_soc = (u32)match->data; | |
| 812 | ||
| 813 | reg_base = of_iomap(np, 0); | |
| 814 | if (!reg_base) | |
| 815 | panic("%s: failed to map registers\n", __func__); | |
| 816 | } else { | |
| 817 | reg_base = S5P_VA_CMU; | |
| 818 | if (soc_is_exynos4210()) | |
| 819 | exynos4_soc = EXYNOS4210; | |
| 820 | else if (soc_is_exynos4212() || soc_is_exynos4412()) | |
| 821 | exynos4_soc = EXYNOS4X12; | |
| 822 | else | |
| 823 | panic("%s: unable to determine soc\n", __func__); | |
| 824 | } | |
| 825 | ||
| 826 | samsung_clk_init(np, reg_base, nr_clks, | |
| 827 | exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs)); | |
| 828 | ||
| 829 | if (np) | |
| 830 | samsung_clk_of_register_fixed_ext(exynos4_fixed_rate_ext_clks, | |
| 831 | ARRAY_SIZE(exynos4_fixed_rate_ext_clks), | |
| 832 | ext_clk_match); | |
| 833 | ||
| 834 | exynos4_clk_register_finpll(); | |
| 835 | ||
| 836 | if (exynos4_soc == EXYNOS4210) { | |
| 837 | apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll", | |
| 838 | reg_base + APLL_CON0, pll_4508); | |
| 839 | mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll", | |
| 840 | reg_base + E4210_MPLL_CON0, pll_4508); | |
| 841 | epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll", | |
| 842 | reg_base + 0xc110, pll_4600); | |
| 843 | vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc", | |
| 844 | reg_base + 0xc120, pll_4650c); | |
| 845 | } else { | |
| 846 | apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll", | |
| 847 | reg_base + APLL_CON0); | |
| 848 | mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll", | |
| 849 | reg_base + E4X12_MPLL_CON0); | |
| 850 | epll = samsung_clk_register_pll36xx("fout_epll", "fin_pll", | |
| 851 | reg_base + 0xc110); | |
| 852 | vpll = samsung_clk_register_pll36xx("fout_vpll", "fin_pll", | |
| 853 | reg_base + 0xc120); | |
| 854 | } | |
| 855 | ||
| 856 | samsung_clk_add_lookup(apll, fout_apll); | |
| 857 | samsung_clk_add_lookup(mpll, fout_mpll); | |
| 858 | samsung_clk_add_lookup(epll, fout_epll); | |
| 859 | samsung_clk_add_lookup(vpll, fout_vpll); | |
| 860 | ||
| 861 | samsung_clk_register_fixed_rate(exynos4_fixed_rate_clks, | |
| 862 | ARRAY_SIZE(exynos4_fixed_rate_clks)); | |
| 863 | samsung_clk_register_mux(exynos4_mux_clks, | |
| 864 | ARRAY_SIZE(exynos4_mux_clks)); | |
| 865 | samsung_clk_register_div(exynos4_div_clks, | |
| 866 | ARRAY_SIZE(exynos4_div_clks)); | |
| 867 | samsung_clk_register_gate(exynos4_gate_clks, | |
| 868 | ARRAY_SIZE(exynos4_gate_clks)); | |
| 869 | ||
| 870 | if (exynos4_soc == EXYNOS4210) { | |
| 871 | samsung_clk_register_fixed_rate(exynos4210_fixed_rate_clks, | |
| 872 | ARRAY_SIZE(exynos4210_fixed_rate_clks)); | |
| 873 | samsung_clk_register_mux(exynos4210_mux_clks, | |
| 874 | ARRAY_SIZE(exynos4210_mux_clks)); | |
| 875 | samsung_clk_register_div(exynos4210_div_clks, | |
| 876 | ARRAY_SIZE(exynos4210_div_clks)); | |
| 877 | samsung_clk_register_gate(exynos4210_gate_clks, | |
| 878 | ARRAY_SIZE(exynos4210_gate_clks)); | |
| 879 | } else { | |
| 880 | samsung_clk_register_mux(exynos4x12_mux_clks, | |
| 881 | ARRAY_SIZE(exynos4x12_mux_clks)); | |
| 882 | samsung_clk_register_div(exynos4x12_div_clks, | |
| 883 | ARRAY_SIZE(exynos4x12_div_clks)); | |
| 884 | samsung_clk_register_gate(exynos4x12_gate_clks, | |
| 885 | ARRAY_SIZE(exynos4x12_gate_clks)); | |
| 886 | } | |
| 887 | ||
| 888 | pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n" | |
| 889 | "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n", | |
| 890 | exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", | |
| 891 | _get_rate("sclk_apll"), _get_rate("sclk_mpll"), | |
| 892 | _get_rate("sclk_epll"), _get_rate("sclk_vpll"), | |
| 893 | _get_rate("arm_clk")); | |
| 894 | } | |
| 895 | CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4_clk_init); | |
| 896 | CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4_clk_init); |