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e062b571 TA |
1 | /* |
2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
3 | * Copyright (c) 2013 Linaro Ltd. | |
4 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Common Clock Framework support for all Exynos4 SoCs. | |
11 | */ | |
12 | ||
2d738237 | 13 | #include <dt-bindings/clock/exynos4.h> |
6f1ed07a | 14 | #include <linux/slab.h> |
e062b571 | 15 | #include <linux/clk.h> |
e062b571 TA |
16 | #include <linux/clk-provider.h> |
17 | #include <linux/of.h> | |
18 | #include <linux/of_address.h> | |
b7b647be | 19 | #include <linux/syscore_ops.h> |
e062b571 | 20 | |
e062b571 | 21 | #include "clk.h" |
6ae5a0b4 | 22 | #include "clk-cpu.h" |
e062b571 TA |
23 | |
24 | /* Exynos4 clock controller register offsets */ | |
25 | #define SRC_LEFTBUS 0x4200 | |
fb948f74 TF |
26 | #define DIV_LEFTBUS 0x4500 |
27 | #define GATE_IP_LEFTBUS 0x4800 | |
e062b571 | 28 | #define E4X12_GATE_IP_IMAGE 0x4930 |
01f7ec26 | 29 | #define CLKOUT_CMU_LEFTBUS 0x4a00 |
fb948f74 TF |
30 | #define SRC_RIGHTBUS 0x8200 |
31 | #define DIV_RIGHTBUS 0x8500 | |
e062b571 TA |
32 | #define GATE_IP_RIGHTBUS 0x8800 |
33 | #define E4X12_GATE_IP_PERIR 0x8960 | |
01f7ec26 | 34 | #define CLKOUT_CMU_RIGHTBUS 0x8a00 |
6d7190f8 TF |
35 | #define EPLL_LOCK 0xc010 |
36 | #define VPLL_LOCK 0xc020 | |
37 | #define EPLL_CON0 0xc110 | |
38 | #define EPLL_CON1 0xc114 | |
39 | #define EPLL_CON2 0xc118 | |
40 | #define VPLL_CON0 0xc120 | |
41 | #define VPLL_CON1 0xc124 | |
42 | #define VPLL_CON2 0xc128 | |
e062b571 TA |
43 | #define SRC_TOP0 0xc210 |
44 | #define SRC_TOP1 0xc214 | |
45 | #define SRC_CAM 0xc220 | |
46 | #define SRC_TV 0xc224 | |
5fdd1b56 | 47 | #define SRC_MFC 0xc228 |
e062b571 TA |
48 | #define SRC_G3D 0xc22c |
49 | #define E4210_SRC_IMAGE 0xc230 | |
50 | #define SRC_LCD0 0xc234 | |
7406ee7c | 51 | #define E4210_SRC_LCD1 0xc238 |
15547015 | 52 | #define E4X12_SRC_ISP 0xc238 |
e062b571 TA |
53 | #define SRC_MAUDIO 0xc23c |
54 | #define SRC_FSYS 0xc240 | |
55 | #define SRC_PERIL0 0xc250 | |
56 | #define SRC_PERIL1 0xc254 | |
57 | #define E4X12_SRC_CAM1 0xc258 | |
fb948f74 | 58 | #define SRC_MASK_TOP 0xc310 |
e062b571 TA |
59 | #define SRC_MASK_CAM 0xc320 |
60 | #define SRC_MASK_TV 0xc324 | |
61 | #define SRC_MASK_LCD0 0xc334 | |
7406ee7c | 62 | #define E4210_SRC_MASK_LCD1 0xc338 |
15547015 | 63 | #define E4X12_SRC_MASK_ISP 0xc338 |
e062b571 TA |
64 | #define SRC_MASK_MAUDIO 0xc33c |
65 | #define SRC_MASK_FSYS 0xc340 | |
66 | #define SRC_MASK_PERIL0 0xc350 | |
67 | #define SRC_MASK_PERIL1 0xc354 | |
68 | #define DIV_TOP 0xc510 | |
69 | #define DIV_CAM 0xc520 | |
70 | #define DIV_TV 0xc524 | |
71 | #define DIV_MFC 0xc528 | |
72 | #define DIV_G3D 0xc52c | |
73 | #define DIV_IMAGE 0xc530 | |
74 | #define DIV_LCD0 0xc534 | |
75 | #define E4210_DIV_LCD1 0xc538 | |
76 | #define E4X12_DIV_ISP 0xc538 | |
77 | #define DIV_MAUDIO 0xc53c | |
78 | #define DIV_FSYS0 0xc540 | |
79 | #define DIV_FSYS1 0xc544 | |
80 | #define DIV_FSYS2 0xc548 | |
81 | #define DIV_FSYS3 0xc54c | |
82 | #define DIV_PERIL0 0xc550 | |
83 | #define DIV_PERIL1 0xc554 | |
84 | #define DIV_PERIL2 0xc558 | |
85 | #define DIV_PERIL3 0xc55c | |
86 | #define DIV_PERIL4 0xc560 | |
87 | #define DIV_PERIL5 0xc564 | |
88 | #define E4X12_DIV_CAM1 0xc568 | |
e323d56e | 89 | #define E4X12_GATE_BUS_FSYS1 0xc744 |
e062b571 TA |
90 | #define GATE_SCLK_CAM 0xc820 |
91 | #define GATE_IP_CAM 0xc920 | |
92 | #define GATE_IP_TV 0xc924 | |
93 | #define GATE_IP_MFC 0xc928 | |
94 | #define GATE_IP_G3D 0xc92c | |
95 | #define E4210_GATE_IP_IMAGE 0xc930 | |
96 | #define GATE_IP_LCD0 0xc934 | |
7406ee7c | 97 | #define E4210_GATE_IP_LCD1 0xc938 |
15547015 | 98 | #define E4X12_GATE_IP_ISP 0xc938 |
e062b571 TA |
99 | #define E4X12_GATE_IP_MAUDIO 0xc93c |
100 | #define GATE_IP_FSYS 0xc940 | |
101 | #define GATE_IP_GPS 0xc94c | |
102 | #define GATE_IP_PERIL 0xc950 | |
1f1f3267 | 103 | #define E4210_GATE_IP_PERIR 0xc960 |
fb948f74 | 104 | #define GATE_BLOCK 0xc970 |
01f7ec26 | 105 | #define CLKOUT_CMU_TOP 0xca00 |
160641e7 | 106 | #define E4X12_MPLL_LOCK 0x10008 |
e062b571 | 107 | #define E4X12_MPLL_CON0 0x10108 |
b950622b | 108 | #define SRC_DMC 0x10200 |
fb948f74 TF |
109 | #define SRC_MASK_DMC 0x10300 |
110 | #define DIV_DMC0 0x10500 | |
111 | #define DIV_DMC1 0x10504 | |
112 | #define GATE_IP_DMC 0x10900 | |
01f7ec26 | 113 | #define CLKOUT_CMU_DMC 0x10a00 |
160641e7 | 114 | #define APLL_LOCK 0x14000 |
52b06016 | 115 | #define E4210_MPLL_LOCK 0x14008 |
e062b571 TA |
116 | #define APLL_CON0 0x14100 |
117 | #define E4210_MPLL_CON0 0x14108 | |
118 | #define SRC_CPU 0x14200 | |
119 | #define DIV_CPU0 0x14500 | |
fb948f74 TF |
120 | #define DIV_CPU1 0x14504 |
121 | #define GATE_SCLK_CPU 0x14800 | |
122 | #define GATE_IP_CPU 0x14900 | |
01f7ec26 | 123 | #define CLKOUT_CMU_CPU 0x14a00 |
42773b28 KK |
124 | #define PWR_CTRL1 0x15020 |
125 | #define E4X12_PWR_CTRL2 0x15024 | |
15547015 AH |
126 | #define E4X12_DIV_ISP0 0x18300 |
127 | #define E4X12_DIV_ISP1 0x18304 | |
1e25810b | 128 | #define E4X12_GATE_ISP0 0x18800 |
15547015 | 129 | #define E4X12_GATE_ISP1 0x18804 |
e062b571 | 130 | |
42773b28 KK |
131 | /* Below definitions are used for PWR_CTRL settings */ |
132 | #define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28) | |
133 | #define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16) | |
134 | #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) | |
135 | #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) | |
136 | #define PWR_CTRL1_USE_CORE3_WFE (1 << 7) | |
137 | #define PWR_CTRL1_USE_CORE2_WFE (1 << 6) | |
138 | #define PWR_CTRL1_USE_CORE1_WFE (1 << 5) | |
139 | #define PWR_CTRL1_USE_CORE0_WFE (1 << 4) | |
140 | #define PWR_CTRL1_USE_CORE3_WFI (1 << 3) | |
141 | #define PWR_CTRL1_USE_CORE2_WFI (1 << 2) | |
142 | #define PWR_CTRL1_USE_CORE1_WFI (1 << 1) | |
143 | #define PWR_CTRL1_USE_CORE0_WFI (1 << 0) | |
144 | ||
e062b571 TA |
145 | /* the exynos4 soc type */ |
146 | enum exynos4_soc { | |
147 | EXYNOS4210, | |
148 | EXYNOS4X12, | |
149 | }; | |
150 | ||
160641e7 YSB |
151 | /* list of PLLs to be registered */ |
152 | enum exynos4_plls { | |
153 | apll, mpll, epll, vpll, | |
154 | nr_plls /* number of PLLs */ | |
155 | }; | |
156 | ||
b7b647be TF |
157 | static void __iomem *reg_base; |
158 | static enum exynos4_soc exynos4_soc; | |
159 | ||
160 | /* | |
161 | * Support for CMU save/restore across system suspends | |
162 | */ | |
163 | #ifdef CONFIG_PM_SLEEP | |
164 | static struct samsung_clk_reg_dump *exynos4_save_common; | |
165 | static struct samsung_clk_reg_dump *exynos4_save_soc; | |
4fcf47e2 | 166 | static struct samsung_clk_reg_dump *exynos4_save_pll; |
b7b647be | 167 | |
e062b571 TA |
168 | /* |
169 | * list of controller registers to be saved and restored during a | |
170 | * suspend/resume cycle. | |
171 | */ | |
d0e4ca56 | 172 | static const unsigned long exynos4210_clk_save[] __initconst = { |
6b5756e8 TF |
173 | E4210_SRC_IMAGE, |
174 | E4210_SRC_LCD1, | |
175 | E4210_SRC_MASK_LCD1, | |
176 | E4210_DIV_LCD1, | |
177 | E4210_GATE_IP_IMAGE, | |
178 | E4210_GATE_IP_LCD1, | |
179 | E4210_GATE_IP_PERIR, | |
180 | E4210_MPLL_CON0, | |
42773b28 | 181 | PWR_CTRL1, |
6b5756e8 TF |
182 | }; |
183 | ||
d0e4ca56 | 184 | static const unsigned long exynos4x12_clk_save[] __initconst = { |
6b5756e8 TF |
185 | E4X12_GATE_IP_IMAGE, |
186 | E4X12_GATE_IP_PERIR, | |
187 | E4X12_SRC_CAM1, | |
188 | E4X12_DIV_ISP, | |
189 | E4X12_DIV_CAM1, | |
190 | E4X12_MPLL_CON0, | |
42773b28 KK |
191 | PWR_CTRL1, |
192 | E4X12_PWR_CTRL2, | |
6b5756e8 TF |
193 | }; |
194 | ||
d0e4ca56 | 195 | static const unsigned long exynos4_clk_pll_regs[] __initconst = { |
4fcf47e2 TF |
196 | EPLL_LOCK, |
197 | VPLL_LOCK, | |
198 | EPLL_CON0, | |
199 | EPLL_CON1, | |
200 | EPLL_CON2, | |
201 | VPLL_CON0, | |
202 | VPLL_CON1, | |
203 | VPLL_CON2, | |
204 | }; | |
205 | ||
d0e4ca56 | 206 | static const unsigned long exynos4_clk_regs[] __initconst = { |
e062b571 | 207 | SRC_LEFTBUS, |
fb948f74 TF |
208 | DIV_LEFTBUS, |
209 | GATE_IP_LEFTBUS, | |
210 | SRC_RIGHTBUS, | |
211 | DIV_RIGHTBUS, | |
e062b571 | 212 | GATE_IP_RIGHTBUS, |
e062b571 TA |
213 | SRC_TOP0, |
214 | SRC_TOP1, | |
215 | SRC_CAM, | |
216 | SRC_TV, | |
217 | SRC_MFC, | |
218 | SRC_G3D, | |
e062b571 | 219 | SRC_LCD0, |
e062b571 TA |
220 | SRC_MAUDIO, |
221 | SRC_FSYS, | |
222 | SRC_PERIL0, | |
223 | SRC_PERIL1, | |
fb948f74 | 224 | SRC_MASK_TOP, |
e062b571 TA |
225 | SRC_MASK_CAM, |
226 | SRC_MASK_TV, | |
227 | SRC_MASK_LCD0, | |
e062b571 TA |
228 | SRC_MASK_MAUDIO, |
229 | SRC_MASK_FSYS, | |
230 | SRC_MASK_PERIL0, | |
231 | SRC_MASK_PERIL1, | |
232 | DIV_TOP, | |
233 | DIV_CAM, | |
234 | DIV_TV, | |
235 | DIV_MFC, | |
236 | DIV_G3D, | |
237 | DIV_IMAGE, | |
238 | DIV_LCD0, | |
e062b571 TA |
239 | DIV_MAUDIO, |
240 | DIV_FSYS0, | |
241 | DIV_FSYS1, | |
242 | DIV_FSYS2, | |
243 | DIV_FSYS3, | |
244 | DIV_PERIL0, | |
245 | DIV_PERIL1, | |
246 | DIV_PERIL2, | |
247 | DIV_PERIL3, | |
248 | DIV_PERIL4, | |
249 | DIV_PERIL5, | |
e062b571 TA |
250 | GATE_SCLK_CAM, |
251 | GATE_IP_CAM, | |
252 | GATE_IP_TV, | |
253 | GATE_IP_MFC, | |
254 | GATE_IP_G3D, | |
e062b571 | 255 | GATE_IP_LCD0, |
e062b571 TA |
256 | GATE_IP_FSYS, |
257 | GATE_IP_GPS, | |
258 | GATE_IP_PERIL, | |
fb948f74 TF |
259 | GATE_BLOCK, |
260 | SRC_MASK_DMC, | |
261 | SRC_DMC, | |
262 | DIV_DMC0, | |
263 | DIV_DMC1, | |
264 | GATE_IP_DMC, | |
e062b571 | 265 | APLL_CON0, |
e062b571 TA |
266 | SRC_CPU, |
267 | DIV_CPU0, | |
fb948f74 TF |
268 | DIV_CPU1, |
269 | GATE_SCLK_CPU, | |
270 | GATE_IP_CPU, | |
01f7ec26 TF |
271 | CLKOUT_CMU_LEFTBUS, |
272 | CLKOUT_CMU_RIGHTBUS, | |
273 | CLKOUT_CMU_TOP, | |
274 | CLKOUT_CMU_DMC, | |
275 | CLKOUT_CMU_CPU, | |
e062b571 TA |
276 | }; |
277 | ||
4fcf47e2 TF |
278 | static const struct samsung_clk_reg_dump src_mask_suspend[] = { |
279 | { .offset = SRC_MASK_TOP, .value = 0x00000001, }, | |
280 | { .offset = SRC_MASK_CAM, .value = 0x11111111, }, | |
281 | { .offset = SRC_MASK_TV, .value = 0x00000111, }, | |
282 | { .offset = SRC_MASK_LCD0, .value = 0x00001111, }, | |
283 | { .offset = SRC_MASK_MAUDIO, .value = 0x00000001, }, | |
284 | { .offset = SRC_MASK_FSYS, .value = 0x01011111, }, | |
285 | { .offset = SRC_MASK_PERIL0, .value = 0x01111111, }, | |
286 | { .offset = SRC_MASK_PERIL1, .value = 0x01110111, }, | |
287 | { .offset = SRC_MASK_DMC, .value = 0x00010000, }, | |
288 | }; | |
289 | ||
290 | static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = { | |
291 | { .offset = E4210_SRC_MASK_LCD1, .value = 0x00001111, }, | |
292 | }; | |
293 | ||
294 | #define PLL_ENABLED (1 << 31) | |
295 | #define PLL_LOCKED (1 << 29) | |
296 | ||
5dcbeca6 MS |
297 | static void exynos4_clk_enable_pll(u32 reg) |
298 | { | |
299 | u32 pll_con = readl(reg_base + reg); | |
300 | pll_con |= PLL_ENABLED; | |
301 | writel(pll_con, reg_base + reg); | |
302 | ||
303 | while (!(pll_con & PLL_LOCKED)) { | |
304 | cpu_relax(); | |
305 | pll_con = readl(reg_base + reg); | |
306 | } | |
307 | } | |
308 | ||
4fcf47e2 TF |
309 | static void exynos4_clk_wait_for_pll(u32 reg) |
310 | { | |
311 | u32 pll_con; | |
312 | ||
313 | pll_con = readl(reg_base + reg); | |
314 | if (!(pll_con & PLL_ENABLED)) | |
315 | return; | |
316 | ||
317 | while (!(pll_con & PLL_LOCKED)) { | |
318 | cpu_relax(); | |
319 | pll_con = readl(reg_base + reg); | |
320 | } | |
321 | } | |
322 | ||
b7b647be TF |
323 | static int exynos4_clk_suspend(void) |
324 | { | |
325 | samsung_clk_save(reg_base, exynos4_save_common, | |
326 | ARRAY_SIZE(exynos4_clk_regs)); | |
4fcf47e2 TF |
327 | samsung_clk_save(reg_base, exynos4_save_pll, |
328 | ARRAY_SIZE(exynos4_clk_pll_regs)); | |
b7b647be | 329 | |
5dcbeca6 MS |
330 | exynos4_clk_enable_pll(EPLL_CON0); |
331 | exynos4_clk_enable_pll(VPLL_CON0); | |
332 | ||
4fcf47e2 | 333 | if (exynos4_soc == EXYNOS4210) { |
b7b647be TF |
334 | samsung_clk_save(reg_base, exynos4_save_soc, |
335 | ARRAY_SIZE(exynos4210_clk_save)); | |
4fcf47e2 TF |
336 | samsung_clk_restore(reg_base, src_mask_suspend_e4210, |
337 | ARRAY_SIZE(src_mask_suspend_e4210)); | |
338 | } else { | |
b7b647be TF |
339 | samsung_clk_save(reg_base, exynos4_save_soc, |
340 | ARRAY_SIZE(exynos4x12_clk_save)); | |
4fcf47e2 TF |
341 | } |
342 | ||
343 | samsung_clk_restore(reg_base, src_mask_suspend, | |
344 | ARRAY_SIZE(src_mask_suspend)); | |
b7b647be TF |
345 | |
346 | return 0; | |
347 | } | |
348 | ||
349 | static void exynos4_clk_resume(void) | |
350 | { | |
4fcf47e2 TF |
351 | samsung_clk_restore(reg_base, exynos4_save_pll, |
352 | ARRAY_SIZE(exynos4_clk_pll_regs)); | |
353 | ||
354 | exynos4_clk_wait_for_pll(EPLL_CON0); | |
355 | exynos4_clk_wait_for_pll(VPLL_CON0); | |
356 | ||
b7b647be TF |
357 | samsung_clk_restore(reg_base, exynos4_save_common, |
358 | ARRAY_SIZE(exynos4_clk_regs)); | |
359 | ||
360 | if (exynos4_soc == EXYNOS4210) | |
361 | samsung_clk_restore(reg_base, exynos4_save_soc, | |
362 | ARRAY_SIZE(exynos4210_clk_save)); | |
363 | else | |
364 | samsung_clk_restore(reg_base, exynos4_save_soc, | |
365 | ARRAY_SIZE(exynos4x12_clk_save)); | |
366 | } | |
367 | ||
368 | static struct syscore_ops exynos4_clk_syscore_ops = { | |
369 | .suspend = exynos4_clk_suspend, | |
370 | .resume = exynos4_clk_resume, | |
371 | }; | |
372 | ||
8f213af2 | 373 | static void __init exynos4_clk_sleep_init(void) |
b7b647be TF |
374 | { |
375 | exynos4_save_common = samsung_clk_alloc_reg_dump(exynos4_clk_regs, | |
376 | ARRAY_SIZE(exynos4_clk_regs)); | |
377 | if (!exynos4_save_common) | |
378 | goto err_warn; | |
379 | ||
380 | if (exynos4_soc == EXYNOS4210) | |
381 | exynos4_save_soc = samsung_clk_alloc_reg_dump( | |
382 | exynos4210_clk_save, | |
383 | ARRAY_SIZE(exynos4210_clk_save)); | |
384 | else | |
385 | exynos4_save_soc = samsung_clk_alloc_reg_dump( | |
386 | exynos4x12_clk_save, | |
387 | ARRAY_SIZE(exynos4x12_clk_save)); | |
388 | if (!exynos4_save_soc) | |
389 | goto err_common; | |
390 | ||
4fcf47e2 TF |
391 | exynos4_save_pll = samsung_clk_alloc_reg_dump(exynos4_clk_pll_regs, |
392 | ARRAY_SIZE(exynos4_clk_pll_regs)); | |
393 | if (!exynos4_save_pll) | |
394 | goto err_soc; | |
395 | ||
b7b647be TF |
396 | register_syscore_ops(&exynos4_clk_syscore_ops); |
397 | return; | |
398 | ||
4fcf47e2 TF |
399 | err_soc: |
400 | kfree(exynos4_save_soc); | |
b7b647be TF |
401 | err_common: |
402 | kfree(exynos4_save_common); | |
403 | err_warn: | |
404 | pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", | |
405 | __func__); | |
406 | } | |
407 | #else | |
8f213af2 | 408 | static void __init exynos4_clk_sleep_init(void) {} |
b7b647be TF |
409 | #endif |
410 | ||
e062b571 TA |
411 | /* list of all parent clock list */ |
412 | PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; | |
413 | PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", }; | |
414 | PNAME(mout_epll_p) = { "fin_pll", "fout_epll", }; | |
415 | PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", }; | |
e062b571 | 416 | PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", }; |
e062b571 TA |
417 | PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", }; |
418 | PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", }; | |
419 | PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", }; | |
420 | PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", }; | |
e062b571 TA |
421 | PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", }; |
422 | PNAME(mout_jpeg_p) = { "mout_jpeg0", "mout_jpeg1", }; | |
e062b571 TA |
423 | PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", |
424 | "spdif_extclk", }; | |
15547015 AH |
425 | PNAME(mout_onenand_p) = {"aclk133", "aclk160", }; |
426 | PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", }; | |
e062b571 | 427 | |
74f7f8ba TF |
428 | /* Exynos 4210-specific parent groups */ |
429 | PNAME(sclk_vpll_p4210) = { "mout_vpllsrc", "fout_vpll", }; | |
430 | PNAME(mout_core_p4210) = { "mout_apll", "sclk_mpll", }; | |
431 | PNAME(sclk_ampll_p4210) = { "sclk_mpll", "sclk_apll", }; | |
432 | PNAME(group1_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", | |
433 | "sclk_usbphy0", "none", "sclk_hdmiphy", | |
434 | "sclk_mpll", "sclk_epll", "sclk_vpll", }; | |
435 | PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m", | |
436 | "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", | |
437 | "sclk_epll", "sclk_vpll" }; | |
438 | PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m", | |
439 | "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", | |
440 | "sclk_epll", "sclk_vpll", }; | |
441 | PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m", | |
442 | "sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll", | |
443 | "sclk_epll", "sclk_vpll", }; | |
444 | PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", }; | |
445 | PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", }; | |
800c9797 TF |
446 | PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", |
447 | "sclk_usbphy1", "sclk_hdmiphy", "none", | |
448 | "sclk_epll", "sclk_vpll" }; | |
01f7ec26 TF |
449 | PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2", |
450 | "div_gdl", "div_gpl" }; | |
451 | PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2", | |
452 | "div_gdr", "div_gpr" }; | |
453 | PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m", | |
454 | "sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy", | |
455 | "cdclk0", "cdclk1", "cdclk2", "spdif_extclk", | |
456 | "aclk160", "aclk133", "aclk200", "aclk100", | |
457 | "sclk_mfc", "sclk_g3d", "sclk_g2d", | |
458 | "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l", | |
459 | "s_rxbyteclkhs0_4l" }; | |
460 | PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc", | |
461 | "div_dphy", "none", "div_pwi" }; | |
462 | PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2", | |
463 | "none", "arm_clk_div_2", "div_corem0", | |
464 | "div_corem1", "div_corem0", "div_atb", | |
465 | "div_periph", "div_pclk_dbg", "div_hpm" }; | |
74f7f8ba TF |
466 | |
467 | /* Exynos 4x12-specific parent groups */ | |
468 | PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", }; | |
469 | PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", }; | |
800c9797 TF |
470 | PNAME(mout_gdl_p4x12) = { "mout_mpll_user_l", "sclk_apll", }; |
471 | PNAME(mout_gdr_p4x12) = { "mout_mpll_user_r", "sclk_apll", }; | |
74f7f8ba TF |
472 | PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", }; |
473 | PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", | |
474 | "none", "sclk_hdmiphy", "mout_mpll_user_t", | |
475 | "sclk_epll", "sclk_vpll", }; | |
476 | PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m", | |
477 | "sclk_usbphy0", "xxti", "xusbxti", | |
478 | "mout_mpll_user_t", "sclk_epll", "sclk_vpll" }; | |
479 | PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m", | |
480 | "sclk_usbphy0", "xxti", "xusbxti", | |
481 | "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; | |
482 | PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m", | |
483 | "sclk_usbphy0", "xxti", "xusbxti", | |
484 | "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; | |
485 | PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", }; | |
15547015 AH |
486 | PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", }; |
487 | PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", }; | |
488 | PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", }; | |
800c9797 TF |
489 | PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", |
490 | "none", "sclk_hdmiphy", "sclk_mpll", | |
491 | "sclk_epll", "sclk_vpll" }; | |
01f7ec26 TF |
492 | PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2", |
493 | "div_gdl", "div_gpl" }; | |
494 | PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2", | |
495 | "div_gdr", "div_gpr" }; | |
496 | PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m", | |
497 | "sclk_usbphy0", "none", "sclk_hdmiphy", | |
498 | "cdclk0", "cdclk1", "cdclk2", "spdif_extclk", | |
499 | "aclk160", "aclk133", "aclk200", "aclk100", | |
500 | "sclk_mfc", "sclk_g3d", "aclk400_mcuisp", | |
501 | "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l", | |
502 | "s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0", | |
503 | "rx_half_byte_clk_csis1", "div_jpeg", | |
504 | "sclk_pwm_isp", "sclk_spi0_isp", | |
505 | "sclk_spi1_isp", "sclk_uart_isp", | |
506 | "sclk_mipihsi", "sclk_hdmi", "sclk_fimd0", | |
507 | "sclk_pcm0" }; | |
508 | PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk", | |
509 | "div_dmc", "div_dphy", "fout_mpll_div_2", | |
510 | "div_pwi", "none", "div_c2c", "div_c2c_aclk" }; | |
511 | PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none", | |
512 | "arm_clk_div_2", "div_corem0", "div_corem1", | |
513 | "div_cores", "div_atb", "div_periph", | |
514 | "div_pclk_dbg", "div_hpm" }; | |
74f7f8ba | 515 | |
e062b571 | 516 | /* fixed rate clocks generated outside the soc */ |
d75f3063 | 517 | static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { |
728f288d SB |
518 | FRATE(CLK_XXTI, "xxti", NULL, 0, 0), |
519 | FRATE(CLK_XUSBXTI, "xusbxti", NULL, 0, 0), | |
e062b571 TA |
520 | }; |
521 | ||
522 | /* fixed rate clocks generated inside the soc */ | |
d0e4ca56 | 523 | static const struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initconst = { |
728f288d | 524 | FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000), |
df019a5c | 525 | FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000), |
728f288d | 526 | FRATE(0, "sclk_usbphy0", NULL, 0, 48000000), |
e062b571 TA |
527 | }; |
528 | ||
d0e4ca56 | 529 | static const struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initconst = { |
728f288d | 530 | FRATE(0, "sclk_usbphy1", NULL, 0, 48000000), |
e062b571 TA |
531 | }; |
532 | ||
d0e4ca56 | 533 | static const struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initconst = { |
01f7ec26 TF |
534 | FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0), |
535 | FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0), | |
536 | FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0), | |
fa0111be | 537 | FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0), |
01f7ec26 TF |
538 | }; |
539 | ||
d0e4ca56 | 540 | static const struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initconst = { |
01f7ec26 TF |
541 | FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0), |
542 | }; | |
543 | ||
d0e4ca56 | 544 | static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initconst = { |
01f7ec26 TF |
545 | FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0), |
546 | FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0), | |
547 | FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0), | |
548 | FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0), | |
549 | }; | |
550 | ||
e062b571 | 551 | /* list of mux clocks supported in all exynos4 soc's */ |
d0e4ca56 | 552 | static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = { |
58f4a5ff MS |
553 | MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, |
554 | CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), | |
4676f0aa | 555 | MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), |
2d738237 AH |
556 | MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), |
557 | MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), | |
558 | MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1, | |
8e1ce839 | 559 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 560 | MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1, |
8e1ce839 | 561 | CLK_SET_RATE_PARENT, 0), |
2d738237 AH |
562 | MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), |
563 | MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), | |
564 | MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1), | |
565 | MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), | |
800c9797 TF |
566 | |
567 | MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1), | |
568 | MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1), | |
e062b571 TA |
569 | }; |
570 | ||
571 | /* list of mux clocks supported in exynos4210 soc */ | |
d0e4ca56 | 572 | static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = { |
2d738237 | 573 | MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), |
4f7641f5 TF |
574 | }; |
575 | ||
d0e4ca56 | 576 | static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = { |
800c9797 | 577 | MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1), |
01f7ec26 TF |
578 | MUX(0, "mout_clkout_leftbus", clkout_left_p4210, |
579 | CLKOUT_CMU_LEFTBUS, 0, 5), | |
800c9797 TF |
580 | |
581 | MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1), | |
01f7ec26 TF |
582 | MUX(0, "mout_clkout_rightbus", clkout_right_p4210, |
583 | CLKOUT_CMU_RIGHTBUS, 0, 5), | |
800c9797 | 584 | |
2d738237 AH |
585 | MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), |
586 | MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), | |
587 | MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), | |
588 | MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1), | |
4676f0aa | 589 | MUX(CLK_MOUT_MIXER, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1), |
2d738237 AH |
590 | MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1), |
591 | MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), | |
592 | MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), | |
593 | MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), | |
594 | MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), | |
595 | MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), | |
596 | MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), | |
597 | MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), | |
800c9797 | 598 | MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1), |
2d738237 AH |
599 | MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1), |
600 | MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), | |
601 | MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), | |
602 | MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), | |
603 | MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), | |
604 | MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), | |
605 | MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), | |
606 | MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), | |
607 | MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), | |
608 | MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), | |
609 | MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1, | |
8e1ce839 | 610 | CLK_SET_RATE_PARENT, 0), |
2d738237 AH |
611 | MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), |
612 | MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4), | |
613 | MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4), | |
614 | MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4), | |
615 | MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4), | |
616 | MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4), | |
617 | MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4), | |
618 | MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4), | |
619 | MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1), | |
620 | MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4), | |
621 | MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4), | |
622 | MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4), | |
623 | MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4), | |
624 | MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4), | |
625 | MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4), | |
626 | MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4), | |
627 | MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), | |
628 | MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), | |
629 | MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), | |
01f7ec26 | 630 | MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5), |
800c9797 TF |
631 | |
632 | MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4), | |
01f7ec26 TF |
633 | MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5), |
634 | ||
635 | MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5), | |
e062b571 TA |
636 | }; |
637 | ||
638 | /* list of mux clocks supported in exynos4x12 soc */ | |
d0e4ca56 | 639 | static const struct samsung_mux_clock exynos4x12_mux_clks[] __initconst = { |
800c9797 TF |
640 | MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1), |
641 | MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1), | |
01f7ec26 TF |
642 | MUX(0, "mout_clkout_leftbus", clkout_left_p4x12, |
643 | CLKOUT_CMU_LEFTBUS, 0, 5), | |
800c9797 TF |
644 | |
645 | MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1), | |
646 | MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1), | |
01f7ec26 TF |
647 | MUX(0, "mout_clkout_rightbus", clkout_right_p4x12, |
648 | CLKOUT_CMU_RIGHTBUS, 0, 5), | |
800c9797 | 649 | |
2d738237 | 650 | MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12, |
e6c3e730 | 651 | SRC_CPU, 24, 1), |
01f7ec26 TF |
652 | MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5), |
653 | ||
2d738237 AH |
654 | MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), |
655 | MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), | |
656 | MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12, | |
74f7f8ba | 657 | SRC_TOP1, 12, 1), |
2d738237 | 658 | MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12, |
15547015 | 659 | SRC_TOP1, 16, 1), |
2d738237 AH |
660 | MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1), |
661 | MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp", | |
662 | mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1), | |
663 | MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1), | |
664 | MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1), | |
665 | MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1), | |
666 | MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1), | |
667 | MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4), | |
668 | MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4), | |
669 | MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1), | |
670 | MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), | |
671 | MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), | |
672 | MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), | |
673 | MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1), | |
674 | MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1), | |
675 | MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), | |
800c9797 | 676 | MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1), |
2d738237 AH |
677 | MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), |
678 | MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), | |
679 | MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), | |
680 | MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), | |
681 | MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), | |
682 | MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), | |
683 | MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), | |
684 | MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), | |
685 | MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), | |
686 | MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1, | |
8e1ce839 | 687 | CLK_SET_RATE_PARENT, 0), |
2d738237 AH |
688 | MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), |
689 | MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4), | |
690 | MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4), | |
691 | MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4), | |
692 | MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4), | |
693 | MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4), | |
694 | MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4), | |
695 | MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4), | |
696 | MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1), | |
697 | MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4), | |
698 | MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4), | |
699 | MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4), | |
700 | MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4), | |
701 | MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4), | |
702 | MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4), | |
703 | MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4), | |
704 | MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4), | |
705 | MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4), | |
706 | MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4), | |
707 | MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4), | |
708 | MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), | |
709 | MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), | |
710 | MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), | |
01f7ec26 TF |
711 | MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5), |
712 | ||
800c9797 TF |
713 | MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1), |
714 | MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4), | |
2d738237 AH |
715 | MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), |
716 | MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), | |
717 | MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), | |
01f7ec26 | 718 | MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5), |
e062b571 TA |
719 | }; |
720 | ||
721 | /* list of divider clocks supported in all exynos4 soc's */ | |
d0e4ca56 | 722 | static const struct samsung_div_clock exynos4_div_clks[] __initconst = { |
e64fb42d | 723 | DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3), |
800c9797 | 724 | DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3), |
01f7ec26 TF |
725 | DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus", |
726 | CLKOUT_CMU_LEFTBUS, 8, 6), | |
800c9797 | 727 | |
e64fb42d | 728 | DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3), |
800c9797 | 729 | DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3), |
01f7ec26 TF |
730 | DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus", |
731 | CLKOUT_CMU_RIGHTBUS, 8, 6), | |
800c9797 | 732 | |
2d738237 | 733 | DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3), |
800c9797 TF |
734 | DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3), |
735 | DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3), | |
736 | DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3), | |
737 | DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3), | |
738 | DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3), | |
6de08891 | 739 | DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3), |
800c9797 TF |
740 | DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), |
741 | DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3), | |
01f7ec26 TF |
742 | DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6), |
743 | ||
2d738237 AH |
744 | DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), |
745 | DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), | |
746 | DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), | |
747 | DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4), | |
748 | DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4), | |
749 | DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), | |
750 | DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), | |
751 | DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), | |
752 | DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4), | |
b511593d | 753 | DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4), |
2d738237 AH |
754 | DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), |
755 | DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), | |
756 | DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4), | |
757 | DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8), | |
758 | DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), | |
759 | DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), | |
760 | DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), | |
761 | DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), | |
762 | DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4), | |
763 | DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4), | |
764 | DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3), | |
765 | DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3), | |
766 | DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3), | |
767 | DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4), | |
768 | DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8), | |
769 | DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8), | |
770 | DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), | |
771 | DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), | |
772 | DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), | |
7e21774d | 773 | DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8, |
86576fbe | 774 | CLK_SET_RATE_PARENT, 0), |
2d738237 AH |
775 | DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), |
776 | DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), | |
777 | DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), | |
778 | DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), | |
779 | DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), | |
780 | DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), | |
781 | DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), | |
782 | DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), | |
783 | DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), | |
784 | DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), | |
785 | DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), | |
786 | DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), | |
787 | DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), | |
2d738237 AH |
788 | DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), |
789 | DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, | |
e062b571 | 790 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 791 | DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, |
e062b571 | 792 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 793 | DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, |
e062b571 | 794 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 795 | DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, |
e062b571 | 796 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 797 | DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, |
e062b571 | 798 | CLK_SET_RATE_PARENT, 0), |
01f7ec26 | 799 | DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6), |
800c9797 | 800 | |
e64fb42d | 801 | DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3), |
800c9797 TF |
802 | DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3), |
803 | DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3), | |
e64fb42d | 804 | DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3), |
800c9797 TF |
805 | DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3), |
806 | DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3), | |
807 | DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4), | |
01f7ec26 | 808 | DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6), |
e062b571 TA |
809 | }; |
810 | ||
811 | /* list of divider clocks supported in exynos4210 soc */ | |
d0e4ca56 | 812 | static const struct samsung_div_clock exynos4210_div_clks[] __initconst = { |
2d738237 AH |
813 | DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), |
814 | DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), | |
815 | DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), | |
816 | DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), | |
817 | DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), | |
818 | DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4, | |
e062b571 TA |
819 | CLK_SET_RATE_PARENT, 0), |
820 | }; | |
821 | ||
822 | /* list of divider clocks supported in exynos4x12 soc */ | |
d0e4ca56 | 823 | static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { |
2d738237 AH |
824 | DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), |
825 | DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), | |
826 | DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), | |
827 | DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4), | |
828 | DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4), | |
829 | DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3), | |
830 | DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3), | |
831 | DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp", | |
cdbf618a | 832 | DIV_TOP, 24, 3), |
2d738237 AH |
833 | DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4), |
834 | DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4), | |
835 | DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8), | |
836 | DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), | |
837 | DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), | |
838 | DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), | |
75920aac MS |
839 | DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), |
840 | DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3), | |
841 | DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3), | |
842 | }; | |
843 | ||
844 | static struct samsung_div_clock exynos4x12_isp_div_clks[] = { | |
2d738237 | 845 | DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, |
a701fe38 | 846 | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 847 | DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, |
a701fe38 | 848 | CLK_GET_RATE_NOCACHE, 0), |
2d738237 AH |
849 | DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), |
850 | DIV_F(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, | |
a701fe38 | 851 | 4, 3, CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 852 | DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, |
a701fe38 | 853 | 8, 3, CLK_GET_RATE_NOCACHE, 0), |
e062b571 TA |
854 | }; |
855 | ||
856 | /* list of gate clocks supported in all exynos4 soc's */ | |
d0e4ca56 | 857 | static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = { |
17d3f1d2 JL |
858 | GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0), |
859 | GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0), | |
2d738237 AH |
860 | GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), |
861 | GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, | |
862 | 0), | |
863 | GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), | |
864 | GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), | |
865 | GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), | |
866 | GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0), | |
867 | GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0), | |
868 | GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0), | |
869 | GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, | |
870 | 0), | |
871 | GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), | |
872 | GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), | |
b511593d | 873 | GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0), |
17d3f1d2 | 874 | GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0), |
2d738237 AH |
875 | GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), |
876 | GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), | |
877 | GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), | |
878 | GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), | |
879 | GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), | |
17d3f1d2 | 880 | GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0), |
2d738237 AH |
881 | GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), |
882 | GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, | |
e062b571 | 883 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 884 | GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5, |
e062b571 | 885 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 886 | GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0", |
e062b571 | 887 | SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0), |
2d738237 | 888 | GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0, |
69aff2fd | 889 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 890 | GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0, |
e062b571 | 891 | CLK_SET_RATE_PARENT, 0), |
2d738237 AH |
892 | GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0), |
893 | GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), | |
894 | GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0), | |
895 | GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0), | |
896 | GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0), | |
897 | GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0), | |
898 | GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0, | |
a11a2f8f | 899 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 900 | GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4, |
a11a2f8f | 901 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 902 | GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8, |
a11a2f8f | 903 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 904 | GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12, |
a11a2f8f | 905 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 906 | GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24, |
a11a2f8f | 907 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 908 | GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28, |
a11a2f8f | 909 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 910 | GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0, |
a11a2f8f | 911 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 912 | GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0, |
a11a2f8f | 913 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 914 | GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4, |
a11a2f8f | 915 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 916 | GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8, |
a11a2f8f | 917 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 918 | GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12, |
a11a2f8f | 919 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 920 | GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16, |
a11a2f8f | 921 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 922 | GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0, |
a11a2f8f | 923 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 924 | GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4, |
a11a2f8f | 925 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 926 | GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8, |
a11a2f8f | 927 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 928 | GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12, |
a11a2f8f | 929 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 930 | GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16, |
a11a2f8f | 931 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 932 | GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4, |
e062b571 | 933 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 934 | GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16, |
a11a2f8f | 935 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 936 | GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20, |
a11a2f8f | 937 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 938 | GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24, |
a11a2f8f | 939 | CLK_SET_RATE_PARENT, 0), |
2d738237 | 940 | GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0, |
a11a2f8f | 941 | 0, 0), |
2d738237 | 942 | GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1, |
a11a2f8f | 943 | 0, 0), |
2d738237 | 944 | GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2, |
a11a2f8f | 945 | 0, 0), |
2d738237 | 946 | GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3, |
a11a2f8f | 947 | 0, 0), |
2d738237 | 948 | GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4, |
a11a2f8f | 949 | 0, 0), |
2d738237 | 950 | GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5, |
a11a2f8f | 951 | 0, 0), |
2d738237 | 952 | GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7, |
a11a2f8f | 953 | 0, 0), |
2d738237 | 954 | GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8, |
a11a2f8f | 955 | 0, 0), |
2d738237 | 956 | GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9, |
a11a2f8f | 957 | 0, 0), |
2d738237 | 958 | GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10, |
a11a2f8f | 959 | 0, 0), |
2d738237 | 960 | GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11, |
a11a2f8f | 961 | 0, 0), |
17d3f1d2 | 962 | GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0), |
2d738237 AH |
963 | GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), |
964 | GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), | |
965 | GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4, | |
a11a2f8f | 966 | 0, 0), |
17d3f1d2 | 967 | GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0), |
2d738237 AH |
968 | GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0), |
969 | GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1, | |
a11a2f8f | 970 | 0, 0), |
2d738237 | 971 | GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2, |
a11a2f8f | 972 | 0, 0), |
17d3f1d2 JL |
973 | GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0), |
974 | GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0), | |
2d738237 | 975 | GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0, |
a11a2f8f | 976 | 0, 0), |
2d738237 | 977 | GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4, |
a11a2f8f | 978 | 0, 0), |
17d3f1d2 | 979 | GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0), |
2d738237 | 980 | GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0, |
a11a2f8f | 981 | 0, 0), |
2d738237 | 982 | GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1, |
a11a2f8f | 983 | 0, 0), |
2d738237 | 984 | GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5, |
a11a2f8f | 985 | 0, 0), |
2d738237 | 986 | GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6, |
a11a2f8f | 987 | 0, 0), |
2d738237 | 988 | GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7, |
a11a2f8f | 989 | 0, 0), |
2d738237 | 990 | GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8, |
a11a2f8f | 991 | 0, 0), |
17d3f1d2 | 992 | GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0), |
2d738237 | 993 | GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0, |
a11a2f8f | 994 | 0, 0), |
2d738237 | 995 | GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1, |
a11a2f8f | 996 | 0, 0), |
2d738237 | 997 | GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2, |
a11a2f8f | 998 | 0, 0), |
2d738237 | 999 | GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3, |
a11a2f8f | 1000 | 0, 0), |
2d738237 | 1001 | GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4, |
a11a2f8f | 1002 | 0, 0), |
2d738237 | 1003 | GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6, |
a11a2f8f | 1004 | 0, 0), |
2d738237 | 1005 | GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7, |
a11a2f8f | 1006 | 0, 0), |
2d738237 | 1007 | GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8, |
a11a2f8f | 1008 | 0, 0), |
2d738237 | 1009 | GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9, |
a11a2f8f | 1010 | 0, 0), |
2d738237 | 1011 | GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10, |
a11a2f8f | 1012 | 0, 0), |
2d738237 | 1013 | GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11, |
a11a2f8f | 1014 | 0, 0), |
2d738237 | 1015 | GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12, |
a11a2f8f | 1016 | 0, 0), |
2d738237 | 1017 | GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13, |
a11a2f8f | 1018 | 0, 0), |
2d738237 | 1019 | GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14, |
a11a2f8f | 1020 | 0, 0), |
2d738237 | 1021 | GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16, |
a11a2f8f | 1022 | 0, 0), |
2d738237 | 1023 | GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17, |
a11a2f8f | 1024 | 0, 0), |
2d738237 | 1025 | GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18, |
a11a2f8f | 1026 | 0, 0), |
2d738237 | 1027 | GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20, |
a11a2f8f | 1028 | 0, 0), |
2d738237 | 1029 | GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21, |
a11a2f8f | 1030 | 0, 0), |
2d738237 | 1031 | GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22, |
a11a2f8f | 1032 | 0, 0), |
2d738237 | 1033 | GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23, |
a11a2f8f | 1034 | 0, 0), |
2d738237 | 1035 | GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26, |
a11a2f8f | 1036 | 0, 0), |
2d738237 | 1037 | GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27, |
a11a2f8f | 1038 | 0, 0), |
94af7a3c | 1039 | GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0), |
17d3f1d2 JL |
1040 | GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0), |
1041 | GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0), | |
1042 | GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0), | |
1043 | GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0), | |
01f7ec26 TF |
1044 | |
1045 | GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus", | |
1046 | CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0), | |
1047 | GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus", | |
1048 | CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0), | |
1049 | GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top", | |
1050 | CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0), | |
1051 | GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc", | |
1052 | CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0), | |
1053 | GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu", | |
1054 | CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0), | |
e062b571 TA |
1055 | }; |
1056 | ||
1057 | /* list of gate clocks supported in exynos4210 soc */ | |
d0e4ca56 | 1058 | static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = { |
2d738237 AH |
1059 | GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), |
1060 | GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), | |
1061 | GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), | |
1062 | GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0), | |
1063 | GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), | |
1064 | GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, | |
1065 | 0), | |
17d3f1d2 JL |
1066 | GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0, |
1067 | 0), | |
1068 | GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0), | |
2d738237 AH |
1069 | GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), |
1070 | GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), | |
1071 | GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), | |
1072 | GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), | |
1073 | GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), | |
1074 | GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), | |
1075 | GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), | |
1076 | GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, | |
056f3d58 | 1077 | CLK_IGNORE_UNUSED, 0), |
2d738237 AH |
1078 | GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, |
1079 | 0), | |
1080 | GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200", | |
e062b571 | 1081 | E4210_GATE_IP_IMAGE, 4, 0, 0), |
2d738237 | 1082 | GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1", |
7406ee7c | 1083 | E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), |
2d738237 | 1084 | GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata", |
e062b571 | 1085 | SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), |
2d738237 AH |
1086 | GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), |
1087 | GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), | |
1088 | GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15, | |
a11a2f8f | 1089 | 0, 0), |
2d738237 | 1090 | GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, |
a11a2f8f | 1091 | 0, 0), |
2d738237 | 1092 | GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, |
a11a2f8f | 1093 | 0, 0), |
2d738237 | 1094 | GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, |
a11a2f8f | 1095 | 0, 0), |
2d738237 | 1096 | GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, |
a11a2f8f | 1097 | 0, 0), |
2d738237 | 1098 | GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0, |
a11a2f8f | 1099 | CLK_SET_RATE_PARENT, 0), |
2d738237 AH |
1100 | GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0, |
1101 | 0), | |
e062b571 TA |
1102 | }; |
1103 | ||
1104 | /* list of gate clocks supported in exynos4x12 soc */ | |
d0e4ca56 | 1105 | static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { |
2d738237 AH |
1106 | GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), |
1107 | GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), | |
1108 | GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), | |
04bc7d96 | 1109 | GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), |
2d738237 AH |
1110 | GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, |
1111 | 0), | |
17d3f1d2 JL |
1112 | GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0, |
1113 | 0), | |
e323d56e | 1114 | GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0), |
2d738237 AH |
1115 | GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), |
1116 | GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), | |
1117 | GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, | |
056f3d58 | 1118 | CLK_IGNORE_UNUSED, 0), |
2d738237 AH |
1119 | GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, |
1120 | 0), | |
1121 | GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0", | |
e062b571 | 1122 | SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), |
2d738237 | 1123 | GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0", |
e062b571 | 1124 | SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0), |
2d738237 | 1125 | GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi", |
e062b571 | 1126 | SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), |
2d738237 | 1127 | GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200", |
e062b571 | 1128 | E4X12_GATE_IP_IMAGE, 4, 0, 0), |
2d738237 | 1129 | GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, |
a11a2f8f | 1130 | 0, 0), |
2d738237 | 1131 | GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, |
a11a2f8f | 1132 | 0, 0), |
2d738237 | 1133 | GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0), |
a37c82a3 | 1134 | GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp", |
15547015 | 1135 | E4X12_GATE_IP_ISP, 0, 0, 0), |
a37c82a3 | 1136 | GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre", |
15547015 | 1137 | E4X12_GATE_IP_ISP, 1, 0, 0), |
a37c82a3 | 1138 | GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre", |
15547015 | 1139 | E4X12_GATE_IP_ISP, 2, 0, 0), |
a37c82a3 | 1140 | GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp", |
15547015 | 1141 | E4X12_GATE_IP_ISP, 3, 0, 0), |
2d738237 AH |
1142 | GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0), |
1143 | GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2, | |
a11a2f8f | 1144 | 0, 0), |
2d738237 | 1145 | GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, |
a11a2f8f | 1146 | 0, 0), |
75920aac MS |
1147 | GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), |
1148 | GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0), | |
1149 | GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, | |
1150 | 0), | |
1151 | }; | |
1152 | ||
1153 | static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = { | |
2d738237 | 1154 | GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, |
a701fe38 | 1155 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1156 | GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, |
a701fe38 | 1157 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1158 | GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, |
a701fe38 | 1159 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1160 | GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, |
a701fe38 | 1161 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1162 | GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, |
a701fe38 | 1163 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1164 | GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, |
a701fe38 | 1165 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1166 | GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, |
a701fe38 | 1167 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1168 | GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, |
a701fe38 | 1169 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1170 | GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, |
a701fe38 | 1171 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1172 | GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, |
a701fe38 | 1173 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1174 | GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, |
a701fe38 | 1175 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1176 | GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, |
a701fe38 | 1177 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1178 | GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, |
a701fe38 | 1179 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1180 | GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, |
a701fe38 | 1181 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1182 | GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, |
a701fe38 | 1183 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1184 | GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, |
a701fe38 | 1185 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1186 | GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, |
a701fe38 | 1187 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1188 | GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, |
a701fe38 | 1189 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1190 | GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, |
a701fe38 | 1191 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1192 | GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, |
a701fe38 | 1193 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1194 | GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, |
a701fe38 | 1195 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1196 | GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, |
a701fe38 | 1197 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1198 | GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, |
a701fe38 | 1199 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1200 | GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, |
a701fe38 | 1201 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1202 | GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, |
a701fe38 | 1203 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
2d738237 | 1204 | GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, |
a701fe38 | 1205 | CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), |
e062b571 TA |
1206 | }; |
1207 | ||
e062b571 TA |
1208 | /* |
1209 | * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit | |
1210 | * resides in chipid register space, outside of the clock controller memory | |
1211 | * mapped space. So to determine the parent of fin_pll clock, the chipid | |
1212 | * controller is first remapped and the value of XOM[0] bit is read to | |
1213 | * determine the parent clock. | |
1214 | */ | |
8f3ac36d | 1215 | static unsigned long __init exynos4_get_xom(void) |
e062b571 | 1216 | { |
25e56eba AB |
1217 | unsigned long xom = 0; |
1218 | void __iomem *chipid_base; | |
e062b571 | 1219 | struct device_node *np; |
e062b571 TA |
1220 | |
1221 | np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid"); | |
25e56eba | 1222 | if (np) { |
e062b571 TA |
1223 | chipid_base = of_iomap(np, 0); |
1224 | ||
25e56eba AB |
1225 | if (chipid_base) |
1226 | xom = readl(chipid_base + 8); | |
1227 | ||
1228 | iounmap(chipid_base); | |
97113ad5 | 1229 | of_node_put(np); |
25e56eba AB |
1230 | } |
1231 | ||
1232 | return xom; | |
1233 | } | |
1234 | ||
976face4 | 1235 | static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx) |
25e56eba AB |
1236 | { |
1237 | struct samsung_fixed_rate_clock fclk; | |
1238 | struct clk *clk; | |
1239 | unsigned long finpll_f = 24000000; | |
1240 | char *parent_name; | |
442f4948 | 1241 | unsigned int xom = exynos4_get_xom(); |
25e56eba AB |
1242 | |
1243 | parent_name = xom & 1 ? "xusbxti" : "xxti"; | |
1244 | clk = clk_get(NULL, parent_name); | |
1245 | if (IS_ERR(clk)) { | |
1246 | pr_err("%s: failed to lookup parent clock %s, assuming " | |
1247 | "fin_pll clock frequency is 24MHz\n", __func__, | |
1248 | parent_name); | |
e062b571 | 1249 | } else { |
25e56eba | 1250 | finpll_f = clk_get_rate(clk); |
e062b571 TA |
1251 | } |
1252 | ||
2d738237 | 1253 | fclk.id = CLK_FIN_PLL; |
e062b571 TA |
1254 | fclk.name = "fin_pll"; |
1255 | fclk.parent_name = NULL; | |
728f288d | 1256 | fclk.flags = 0; |
e062b571 | 1257 | fclk.fixed_rate = finpll_f; |
976face4 | 1258 | samsung_clk_register_fixed_rate(ctx, &fclk, 1); |
e062b571 | 1259 | |
e062b571 TA |
1260 | } |
1261 | ||
305cfab0 | 1262 | static const struct of_device_id ext_clk_match[] __initconst = { |
e062b571 TA |
1263 | { .compatible = "samsung,clock-xxti", .data = (void *)0, }, |
1264 | { .compatible = "samsung,clock-xusbxti", .data = (void *)1, }, | |
1265 | {}, | |
1266 | }; | |
1267 | ||
5fadfc7e | 1268 | /* PLLs PMS values */ |
d0e4ca56 | 1269 | static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = { |
5fadfc7e TF |
1270 | PLL_45XX_RATE(1200000000, 150, 3, 1, 28), |
1271 | PLL_45XX_RATE(1000000000, 250, 6, 1, 28), | |
1272 | PLL_45XX_RATE( 800000000, 200, 6, 1, 28), | |
1273 | PLL_45XX_RATE( 666857142, 389, 14, 1, 13), | |
1274 | PLL_45XX_RATE( 600000000, 100, 4, 1, 13), | |
1275 | PLL_45XX_RATE( 533000000, 533, 24, 1, 5), | |
1276 | PLL_45XX_RATE( 500000000, 250, 6, 2, 28), | |
1277 | PLL_45XX_RATE( 400000000, 200, 6, 2, 28), | |
1278 | PLL_45XX_RATE( 200000000, 200, 6, 3, 28), | |
1279 | { /* sentinel */ } | |
1280 | }; | |
1281 | ||
d0e4ca56 | 1282 | static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = { |
5fadfc7e TF |
1283 | PLL_4600_RATE(192000000, 48, 3, 1, 0, 0), |
1284 | PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0), | |
1285 | PLL_4600_RATE(180000000, 45, 3, 1, 0, 0), | |
1286 | PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1), | |
1287 | PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1), | |
1288 | PLL_4600_RATE( 49151992, 49, 3, 3, 9961, 0), | |
1289 | PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0), | |
1290 | { /* sentinel */ } | |
1291 | }; | |
1292 | ||
d0e4ca56 | 1293 | static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = { |
5fadfc7e TF |
1294 | PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0), |
1295 | PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1, 1, 1), | |
1296 | PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1), | |
1297 | PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0), | |
1298 | PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0), | |
1299 | { /* sentinel */ } | |
1300 | }; | |
1301 | ||
d0e4ca56 | 1302 | static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = { |
c369596f BZ |
1303 | PLL_35XX_RATE(1704000000, 213, 3, 0), |
1304 | PLL_35XX_RATE(1600000000, 200, 3, 0), | |
efb19a85 TF |
1305 | PLL_35XX_RATE(1500000000, 250, 4, 0), |
1306 | PLL_35XX_RATE(1400000000, 175, 3, 0), | |
1307 | PLL_35XX_RATE(1300000000, 325, 6, 0), | |
1308 | PLL_35XX_RATE(1200000000, 200, 4, 0), | |
1309 | PLL_35XX_RATE(1100000000, 275, 6, 0), | |
1310 | PLL_35XX_RATE(1000000000, 125, 3, 0), | |
1311 | PLL_35XX_RATE( 900000000, 150, 4, 0), | |
1312 | PLL_35XX_RATE( 800000000, 100, 3, 0), | |
1313 | PLL_35XX_RATE( 700000000, 175, 3, 1), | |
1314 | PLL_35XX_RATE( 600000000, 200, 4, 1), | |
1315 | PLL_35XX_RATE( 500000000, 125, 3, 1), | |
1316 | PLL_35XX_RATE( 400000000, 100, 3, 1), | |
1317 | PLL_35XX_RATE( 300000000, 200, 4, 2), | |
1318 | PLL_35XX_RATE( 200000000, 100, 3, 2), | |
1319 | { /* sentinel */ } | |
1320 | }; | |
1321 | ||
d0e4ca56 | 1322 | static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = { |
efb19a85 TF |
1323 | PLL_36XX_RATE(192000000, 48, 3, 1, 0), |
1324 | PLL_36XX_RATE(180633605, 45, 3, 1, 10381), | |
1325 | PLL_36XX_RATE(180000000, 45, 3, 1, 0), | |
1326 | PLL_36XX_RATE( 73727996, 73, 3, 3, 47710), | |
1327 | PLL_36XX_RATE( 67737602, 90, 4, 3, 20762), | |
1328 | PLL_36XX_RATE( 49151992, 49, 3, 3, 9961), | |
1329 | PLL_36XX_RATE( 45158401, 45, 3, 3, 10381), | |
1330 | { /* sentinel */ } | |
1331 | }; | |
1332 | ||
d0e4ca56 | 1333 | static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = { |
efb19a85 TF |
1334 | PLL_36XX_RATE(533000000, 133, 3, 1, 16384), |
1335 | PLL_36XX_RATE(440000000, 110, 3, 1, 0), | |
1336 | PLL_36XX_RATE(350000000, 175, 3, 2, 0), | |
1337 | PLL_36XX_RATE(266000000, 133, 3, 2, 0), | |
1338 | PLL_36XX_RATE(160000000, 160, 3, 3, 0), | |
1339 | PLL_36XX_RATE(106031250, 53, 3, 2, 1024), | |
1340 | PLL_36XX_RATE( 53015625, 53, 3, 3, 1024), | |
1341 | { /* sentinel */ } | |
1342 | }; | |
1343 | ||
c50d11f3 | 1344 | static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = { |
58f4a5ff MS |
1345 | [apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll", |
1346 | APLL_LOCK, APLL_CON0, NULL), | |
1347 | [mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", | |
1348 | E4210_MPLL_LOCK, E4210_MPLL_CON0, NULL), | |
1349 | [epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll", | |
1350 | EPLL_LOCK, EPLL_CON0, NULL), | |
1351 | [vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc", | |
1352 | VPLL_LOCK, VPLL_CON0, NULL), | |
52b06016 TF |
1353 | }; |
1354 | ||
c6415963 | 1355 | static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { |
2d738237 | 1356 | [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", |
a11a2f8f | 1357 | APLL_LOCK, APLL_CON0, NULL), |
2d738237 | 1358 | [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", |
a11a2f8f | 1359 | E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL), |
2d738237 | 1360 | [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", |
a11a2f8f | 1361 | EPLL_LOCK, EPLL_CON0, NULL), |
2d738237 | 1362 | [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", |
a11a2f8f | 1363 | VPLL_LOCK, VPLL_CON0, NULL), |
160641e7 YSB |
1364 | }; |
1365 | ||
3a9e9cb6 | 1366 | static void __init exynos4x12_core_down_clock(void) |
42773b28 KK |
1367 | { |
1368 | unsigned int tmp; | |
1369 | ||
1370 | /* | |
1371 | * Enable arm clock down (in idle) and set arm divider | |
1372 | * ratios in WFI/WFE state. | |
1373 | */ | |
1374 | tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) | | |
1375 | PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN | | |
1376 | PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE | | |
1377 | PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI); | |
1378 | /* On Exynos4412 enable it also on core 2 and 3 */ | |
1379 | if (num_possible_cpus() == 4) | |
1380 | tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE | | |
1381 | PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI; | |
21a5560b | 1382 | writel_relaxed(tmp, reg_base + PWR_CTRL1); |
42773b28 KK |
1383 | |
1384 | /* | |
3a9e9cb6 | 1385 | * Disable the clock up feature in case it was enabled by bootloader. |
42773b28 | 1386 | */ |
21a5560b | 1387 | writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2); |
42773b28 KK |
1388 | } |
1389 | ||
6ae5a0b4 TA |
1390 | #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \ |
1391 | (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ | |
1392 | ((periph) << 12) | ((corem1) << 8) | ((corem0) << 4)) | |
1393 | #define E4210_CPU_DIV1(hpm, copy) \ | |
1394 | (((hpm) << 4) | ((copy) << 0)) | |
1395 | ||
1396 | static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = { | |
1397 | { 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), }, | |
1398 | { 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), }, | |
1399 | { 800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), }, | |
1400 | { 500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), }, | |
1401 | { 400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), }, | |
1402 | { 200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), }, | |
1403 | { 0 }, | |
1404 | }; | |
1405 | ||
cd6aceef BZ |
1406 | #define E4412_CPU_DIV1(cores, hpm, copy) \ |
1407 | (((cores) << 8) | ((hpm) << 4) | ((copy) << 0)) | |
1408 | ||
1409 | static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = { | |
c369596f BZ |
1410 | { 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), }, |
1411 | { 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, | |
cd6aceef BZ |
1412 | { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, |
1413 | { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), }, | |
1414 | { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), }, | |
1415 | { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), }, | |
1416 | { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), }, | |
1417 | { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), }, | |
1418 | { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), }, | |
1419 | { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), }, | |
1420 | { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), }, | |
1421 | { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), }, | |
1422 | { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), }, | |
1423 | { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), }, | |
1424 | { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), }, | |
1425 | { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), }, | |
1426 | { 0 }, | |
1427 | }; | |
1428 | ||
e062b571 | 1429 | /* register exynos4 clocks */ |
d75f3063 | 1430 | static void __init exynos4_clk_init(struct device_node *np, |
b7b647be | 1431 | enum exynos4_soc soc) |
e062b571 | 1432 | { |
976face4 | 1433 | struct samsung_clk_provider *ctx; |
b7b647be | 1434 | exynos4_soc = soc; |
442f4948 | 1435 | |
336c18bd TF |
1436 | reg_base = of_iomap(np, 0); |
1437 | if (!reg_base) | |
1438 | panic("%s: failed to map registers\n", __func__); | |
e062b571 | 1439 | |
976face4 | 1440 | ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); |
e062b571 | 1441 | |
976face4 | 1442 | samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks, |
e062b571 TA |
1443 | ARRAY_SIZE(exynos4_fixed_rate_ext_clks), |
1444 | ext_clk_match); | |
1445 | ||
976face4 | 1446 | exynos4_clk_register_finpll(ctx); |
e062b571 TA |
1447 | |
1448 | if (exynos4_soc == EXYNOS4210) { | |
976face4 | 1449 | samsung_clk_register_mux(ctx, exynos4210_mux_early, |
4f7641f5 TF |
1450 | ARRAY_SIZE(exynos4210_mux_early)); |
1451 | ||
5fadfc7e TF |
1452 | if (_get_rate("fin_pll") == 24000000) { |
1453 | exynos4210_plls[apll].rate_table = | |
1454 | exynos4210_apll_rates; | |
1455 | exynos4210_plls[epll].rate_table = | |
1456 | exynos4210_epll_rates; | |
1457 | } | |
1458 | ||
1459 | if (_get_rate("mout_vpllsrc") == 24000000) | |
1460 | exynos4210_plls[vpll].rate_table = | |
1461 | exynos4210_vpll_rates; | |
1462 | ||
976face4 | 1463 | samsung_clk_register_pll(ctx, exynos4210_plls, |
52b06016 | 1464 | ARRAY_SIZE(exynos4210_plls), reg_base); |
e062b571 | 1465 | } else { |
efb19a85 TF |
1466 | if (_get_rate("fin_pll") == 24000000) { |
1467 | exynos4x12_plls[apll].rate_table = | |
1468 | exynos4x12_apll_rates; | |
1469 | exynos4x12_plls[epll].rate_table = | |
1470 | exynos4x12_epll_rates; | |
1471 | exynos4x12_plls[vpll].rate_table = | |
1472 | exynos4x12_vpll_rates; | |
1473 | } | |
e062b571 | 1474 | |
976face4 | 1475 | samsung_clk_register_pll(ctx, exynos4x12_plls, |
c6415963 | 1476 | ARRAY_SIZE(exynos4x12_plls), reg_base); |
e062b571 | 1477 | } |
e062b571 | 1478 | |
976face4 | 1479 | samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks, |
e062b571 | 1480 | ARRAY_SIZE(exynos4_fixed_rate_clks)); |
976face4 | 1481 | samsung_clk_register_mux(ctx, exynos4_mux_clks, |
e062b571 | 1482 | ARRAY_SIZE(exynos4_mux_clks)); |
976face4 | 1483 | samsung_clk_register_div(ctx, exynos4_div_clks, |
e062b571 | 1484 | ARRAY_SIZE(exynos4_div_clks)); |
976face4 | 1485 | samsung_clk_register_gate(ctx, exynos4_gate_clks, |
e062b571 | 1486 | ARRAY_SIZE(exynos4_gate_clks)); |
01f7ec26 TF |
1487 | samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks, |
1488 | ARRAY_SIZE(exynos4_fixed_factor_clks)); | |
e062b571 TA |
1489 | |
1490 | if (exynos4_soc == EXYNOS4210) { | |
976face4 | 1491 | samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks, |
e062b571 | 1492 | ARRAY_SIZE(exynos4210_fixed_rate_clks)); |
976face4 | 1493 | samsung_clk_register_mux(ctx, exynos4210_mux_clks, |
e062b571 | 1494 | ARRAY_SIZE(exynos4210_mux_clks)); |
976face4 | 1495 | samsung_clk_register_div(ctx, exynos4210_div_clks, |
e062b571 | 1496 | ARRAY_SIZE(exynos4210_div_clks)); |
976face4 | 1497 | samsung_clk_register_gate(ctx, exynos4210_gate_clks, |
e062b571 | 1498 | ARRAY_SIZE(exynos4210_gate_clks)); |
01f7ec26 TF |
1499 | samsung_clk_register_fixed_factor(ctx, |
1500 | exynos4210_fixed_factor_clks, | |
1501 | ARRAY_SIZE(exynos4210_fixed_factor_clks)); | |
6ae5a0b4 TA |
1502 | exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", |
1503 | mout_core_p4210[0], mout_core_p4210[1], 0x14200, | |
1504 | e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d), | |
1505 | CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); | |
e062b571 | 1506 | } else { |
75920aac MS |
1507 | struct resource res; |
1508 | ||
976face4 | 1509 | samsung_clk_register_mux(ctx, exynos4x12_mux_clks, |
e062b571 | 1510 | ARRAY_SIZE(exynos4x12_mux_clks)); |
976face4 | 1511 | samsung_clk_register_div(ctx, exynos4x12_div_clks, |
e062b571 | 1512 | ARRAY_SIZE(exynos4x12_div_clks)); |
976face4 | 1513 | samsung_clk_register_gate(ctx, exynos4x12_gate_clks, |
e062b571 | 1514 | ARRAY_SIZE(exynos4x12_gate_clks)); |
01f7ec26 TF |
1515 | samsung_clk_register_fixed_factor(ctx, |
1516 | exynos4x12_fixed_factor_clks, | |
1517 | ARRAY_SIZE(exynos4x12_fixed_factor_clks)); | |
75920aac MS |
1518 | |
1519 | of_address_to_resource(np, 0, &res); | |
1520 | if (resource_size(&res) > 0x18000) { | |
1521 | samsung_clk_register_div(ctx, exynos4x12_isp_div_clks, | |
1522 | ARRAY_SIZE(exynos4x12_isp_div_clks)); | |
1523 | samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks, | |
1524 | ARRAY_SIZE(exynos4x12_isp_gate_clks)); | |
1525 | } | |
1526 | ||
c9194fb6 MS |
1527 | exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", |
1528 | mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, | |
1529 | e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d), | |
1530 | CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); | |
e062b571 TA |
1531 | } |
1532 | ||
3a9e9cb6 BZ |
1533 | if (soc == EXYNOS4X12) |
1534 | exynos4x12_core_down_clock(); | |
b7b647be TF |
1535 | exynos4_clk_sleep_init(); |
1536 | ||
d5e136a2 SN |
1537 | samsung_clk_of_add_provider(np, ctx); |
1538 | ||
e062b571 TA |
1539 | pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n" |
1540 | "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n", | |
1541 | exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", | |
3a647895 | 1542 | _get_rate("sclk_apll"), _get_rate("sclk_mpll"), |
e062b571 | 1543 | _get_rate("sclk_epll"), _get_rate("sclk_vpll"), |
fa0111be | 1544 | _get_rate("div_core2")); |
e062b571 | 1545 | } |
25e56eba AB |
1546 | |
1547 | ||
1548 | static void __init exynos4210_clk_init(struct device_node *np) | |
1549 | { | |
442f4948 | 1550 | exynos4_clk_init(np, EXYNOS4210); |
25e56eba AB |
1551 | } |
1552 | CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init); | |
1553 | ||
1554 | static void __init exynos4412_clk_init(struct device_node *np) | |
1555 | { | |
442f4948 | 1556 | exynos4_clk_init(np, EXYNOS4X12); |
25e56eba AB |
1557 | } |
1558 | CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init); |