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clk: samsung: exynos5250: Sort definitions by registers and bitfield
[mirror_ubuntu-hirsute-kernel.git] / drivers / clk / samsung / clk-exynos5250.c
CommitLineData
6e3ad268
TA		 1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
4 * Author: Thomas Abraham <thomas.ab@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for Exynos5250 SoC.
11*/
12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18
6e3ad268 19#include "clk.h"
6e3ad268 20
8dac3530
YSB		 21#define APLL_LOCK 0x0
22#define APLL_CON0 0x100
6e3ad268
TA		 23#define SRC_CPU 0x200
24#define DIV_CPU0 0x500
8dac3530
YSB		 25#define MPLL_LOCK 0x4000
26#define MPLL_CON0 0x4100
6e3ad268 27#define SRC_CORE1 0x4204
3bf34666 28#define GATE_IP_ACP 0x8800
8dac3530
YSB		 29#define CPLL_LOCK 0x10020
30#define EPLL_LOCK 0x10030
31#define VPLL_LOCK 0x10040
32#define GPLL_LOCK 0x10050
33#define CPLL_CON0 0x10120
34#define EPLL_CON0 0x10130
35#define VPLL_CON0 0x10140
36#define GPLL_CON0 0x10150
6e3ad268
TA		 37#define SRC_TOP0 0x10210
38#define SRC_TOP2 0x10218
39#define SRC_GSCL 0x10220
40#define SRC_DISP1_0 0x1022c
41#define SRC_MAU 0x10240
42#define SRC_FSYS 0x10244
43#define SRC_GEN 0x10248
44#define SRC_PERIC0 0x10250
45#define SRC_PERIC1 0x10254
46#define SRC_MASK_GSCL 0x10320
47#define SRC_MASK_DISP1_0 0x1032c
48#define SRC_MASK_MAU 0x10334
49#define SRC_MASK_FSYS 0x10340
50#define SRC_MASK_GEN 0x10344
51#define SRC_MASK_PERIC0 0x10350
52#define SRC_MASK_PERIC1 0x10354
53#define DIV_TOP0 0x10510
54#define DIV_TOP1 0x10514
55#define DIV_GSCL 0x10520
56#define DIV_DISP1_0 0x1052c
57#define DIV_GEN 0x1053c
58#define DIV_MAU 0x10544
59#define DIV_FSYS0 0x10548
60#define DIV_FSYS1 0x1054c
61#define DIV_FSYS2 0x10550
62#define DIV_PERIC0 0x10558
63#define DIV_PERIC1 0x1055c
64#define DIV_PERIC2 0x10560
65#define DIV_PERIC3 0x10564
66#define DIV_PERIC4 0x10568
67#define DIV_PERIC5 0x1056c
68#define GATE_IP_GSCL 0x10920
2786c962 69#define GATE_IP_DISP1 0x10928
6e3ad268
TA		 70#define GATE_IP_MFC 0x1092c
71#define GATE_IP_GEN 0x10934
72#define GATE_IP_FSYS 0x10944
73#define GATE_IP_PERIC 0x10950
74#define GATE_IP_PERIS 0x10960
8dac3530
YSB		 75#define BPLL_LOCK 0x20010
76#define BPLL_CON0 0x20110
6e3ad268
TA		 77#define SRC_CDREX 0x20200
78#define PLL_DIV2_SEL 0x20a24
79
8dac3530
YSB		 80/* list of PLLs to be registered */
81enum exynos5250_plls {
82 apll, mpll, cpll, epll, vpll, gpll, bpll,
83 nr_plls /* number of PLLs */
84};
85
6e3ad268
TA		 86/*
87 * Let each supported clock get a unique id. This id is used to lookup the clock
88 * for device tree based platforms. The clocks are categorized into three
89 * sections: core, sclk gate and bus interface gate clocks.
90 *
91 * When adding a new clock to this list, it is advised to choose a clock
92 * category and add it to the end of that category. That is because the the
93 * device tree source file is referring to these ids and any change in the
94 * sequence number of existing clocks will require corresponding change in the
95 * device tree files. This limitation would go away when pre-processor support
96 * for dtc would be available.
97 */
98enum exynos5250_clks {
99 none,
100
101 /* core clocks */
8dac3530
YSB		 102 fin_pll, fout_apll, fout_mpll, fout_bpll, fout_gpll, fout_cpll,
103 fout_epll, fout_vpll,
6e3ad268
TA		 104
105 /* gate for special clocks (sclk) */
106 sclk_cam_bayer = 128, sclk_cam0, sclk_cam1, sclk_gscl_wa, sclk_gscl_wb,
107 sclk_fimd1, sclk_mipi1, sclk_dp, sclk_hdmi, sclk_pixel, sclk_audio0,
108 sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
109 sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
110 sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
b38a5040 111 div_i2s1, div_i2s2, sclk_hdmiphy,
6e3ad268
TA		 112
113 /* gate clocks */
114 gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
115 smmu_gscl1, smmu_gscl2, smmu_gscl3, mfc, smmu_mfcl, smmu_mfcr, rotator,
116 jpeg, mdma1, smmu_rotator, smmu_jpeg, smmu_mdma1, pdma0, pdma1, sata,
117 usbotg, mipi_hsi, sdmmc0, sdmmc1, sdmmc2, sdmmc3, sromc, usb2, usb3,
118 sata_phyctrl, sata_phyi2c, uart0, uart1, uart2, uart3, uart4, i2c0,
119 i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, adc, spi0, spi1,
120 spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
121 hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
122 tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
8fb9aeb7
AK		 123 wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, mdma0,
124 smmu_mdma0,
6e3ad268 125
4a453314
RS		 126 /* mux clocks */
127 mout_hdmi = 1024,
128
6e3ad268
TA		 129 nr_clks,
130};
131
132/*
133 * list of controller registers to be saved and restored during a
134 * suspend/resume cycle.
135 */
b6993ecb 136static unsigned long exynos5250_clk_regs[] __initdata = {
6e3ad268
TA		 137 SRC_CPU,
138 DIV_CPU0,
139 SRC_CORE1,
140 SRC_TOP0,
141 SRC_TOP2,
142 SRC_GSCL,
143 SRC_DISP1_0,
144 SRC_MAU,
145 SRC_FSYS,
146 SRC_GEN,
147 SRC_PERIC0,
148 SRC_PERIC1,
149 SRC_MASK_GSCL,
150 SRC_MASK_DISP1_0,
151 SRC_MASK_MAU,
152 SRC_MASK_FSYS,
153 SRC_MASK_GEN,
154 SRC_MASK_PERIC0,
155 SRC_MASK_PERIC1,
156 DIV_TOP0,
157 DIV_TOP1,
158 DIV_GSCL,
159 DIV_DISP1_0,
160 DIV_GEN,
161 DIV_MAU,
162 DIV_FSYS0,
163 DIV_FSYS1,
164 DIV_FSYS2,
165 DIV_PERIC0,
166 DIV_PERIC1,
167 DIV_PERIC2,
168 DIV_PERIC3,
169 DIV_PERIC4,
170 DIV_PERIC5,
171 GATE_IP_GSCL,
172 GATE_IP_MFC,
173 GATE_IP_GEN,
174 GATE_IP_FSYS,
175 GATE_IP_PERIC,
176 GATE_IP_PERIS,
177 SRC_CDREX,
178 PLL_DIV2_SEL,
17d4cacc 179 GATE_IP_DISP1,
406c5989 180 GATE_IP_ACP,
6e3ad268
TA		 181};
182
183/* list of all parent clock list */
184PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
589c603b 185PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
6e3ad268
TA		 186PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
187PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
188PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
189PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
190PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
191PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
192PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
193PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
194PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll" };
195PNAME(mout_bpll_user_p) = { "fin_pll", "sclk_bpll" };
196PNAME(mout_aclk166_p) = { "sclk_cpll", "sclk_mpll_user" };
197PNAME(mout_aclk200_p) = { "sclk_mpll_user", "sclk_bpll_user" };
198PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
199PNAME(mout_usb3_p) = { "sclk_mpll_user", "sclk_cpll" };
200PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
201 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
202 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
203 "sclk_cpll" };
204PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
205 "sclk_uhostphy", "sclk_hdmiphy",
206 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
207 "sclk_cpll" };
208PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
209 "sclk_uhostphy", "sclk_hdmiphy",
210 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
211 "sclk_cpll" };
212PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
213 "sclk_uhostphy", "sclk_hdmiphy",
214 "sclk_mpll_user", "sclk_epll", "sclk_vpll",
215 "sclk_cpll" };
216PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
217 "spdif_extclk" };
218
219/* fixed rate clocks generated outside the soc */
b95e71c6 220static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
6e3ad268
TA		 221 FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0),
222};
223
224/* fixed rate clocks generated inside the soc */
b95e71c6 225static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = {
b38a5040 226 FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
6e3ad268
TA		 227 FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000),
228 FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000),
229 FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000),
230};
231
b95e71c6 232static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
6e3ad268
TA		 233 FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
234 FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
235};
236
8bc2eeb8
VS		 237static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = {
238 MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
239};
240
b95e71c6 241static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
2786c962
TF		 242 /*
243 * NOTE: Following table is sorted by (clock domain, register address,
244 * bitfield shift) triplet in ascending order. When adding new entries,
245 * please make sure that the order is kept, to avoid merge conflicts
246 * and make further work with defined data easier.
247 */
248
249 /*
250 * CMU_CPU
251 */
39b72d89
TB		 252 MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"),
253 MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
2786c962
TF		 254
255 /*
256 * CMU_CORE
257 */
39b72d89 258 MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
2786c962
TF		 259
260 /*
261 * CMU_TOP
262 */
263 MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
264 MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
265 MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
266
6e3ad268 267 MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
2786c962
TF		 268 MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1),
269 MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
6e3ad268
TA		 270 MUX(none, "sclk_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
271 MUX(none, "sclk_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
2786c962 272
6e3ad268
TA		 273 MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
274 MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
275 MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
276 MUX(none, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
277 MUX(none, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
2786c962 278
6e3ad268
TA		 279 MUX(none, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
280 MUX(none, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
281 MUX(none, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
4a453314 282 MUX(mout_hdmi, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
2786c962 283
6e3ad268 284 MUX(none, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
2786c962 285
6e3ad268
TA		 286 MUX(none, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
287 MUX(none, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
288 MUX(none, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
289 MUX(none, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
290 MUX(none, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
291 MUX(none, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
2786c962 292
6e3ad268 293 MUX(none, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
2786c962 294
6e3ad268
TA		 295 MUX(none, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
296 MUX(none, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
297 MUX(none, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
298 MUX(none, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
299 MUX(none, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
2786c962 300
6e3ad268
TA		 301 MUX(none, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
302 MUX(none, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
303 MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
304 MUX(none, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
305 MUX(none, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
306 MUX(none, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
2786c962
TF		 307
308 /*
309 * CMU_CDREX
310 */
311 MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
312
313 MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
314 MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
6e3ad268
TA		 315};
316
b95e71c6 317static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
2786c962
TF		 318 /*
319 * NOTE: Following table is sorted by (clock domain, register address,
320 * bitfield shift) triplet in ascending order. When adding new entries,
321 * please make sure that the order is kept, to avoid merge conflicts
322 * and make further work with defined data easier.
323 */
324
325 /*
326 * CMU_CPU
327 */
6e3ad268
TA		 328 DIV(none, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
329 DIV(none, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
2786c962
TF		 330 DIV_A(none, "armclk", "div_arm", DIV_CPU0, 28, 3, "armclk"),
331
332 /*
333 * CMU_TOP
334 */
6e3ad268 335 DIV(none, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
6e3ad268 336 DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
6e3ad268 337 DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
2786c962
TF		 338 DIV(none, "aclk266", "sclk_mpll_user", DIV_TOP0, 16, 3),
339 DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
340
341 DIV(none, "aclk66_pre", "sclk_mpll_user", DIV_TOP1, 24, 3),
342
6e3ad268
TA		 343 DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
344 DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
345 DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
346 DIV(none, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
347 DIV(none, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
2786c962 348
6e3ad268
TA		 349 DIV(none, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
350 DIV(none, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
2786c962
TF		 351 DIV_F(none, "div_mipi1_pre", "div_mipi1",
352 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
6e3ad268 353 DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
2786c962
TF		 354 DIV(sclk_pixel, "div_hdmi_pixel", "sclk_vpll", DIV_DISP1_0, 28, 4),
355
6e3ad268 356 DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
2786c962 357
6e3ad268
TA		 358 DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
359 DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
2786c962 360
6e3ad268
TA		 361 DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
362 DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
2786c962 363
37746c9a 364 DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
2786c962
TF		 365 DIV_F(none, "div_mmc_pre0", "div_mmc0",
366 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
37746c9a 367 DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
2786c962
TF		 368 DIV_F(none, "div_mmc_pre1", "div_mmc1",
369 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
370
37746c9a 371 DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
2786c962
TF		 372 DIV_F(none, "div_mmc_pre2", "div_mmc2",
373 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
37746c9a 374 DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
2786c962
TF		 375 DIV_F(none, "div_mmc_pre3", "div_mmc3",
376 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
377
6e3ad268
TA		 378 DIV(none, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
379 DIV(none, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
380 DIV(none, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
381 DIV(none, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
2786c962 382
6e3ad268 383 DIV(none, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
2786c962
TF		 384 DIV_F(none, "div_spi_pre0", "div_spi0",
385 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
6e3ad268 386 DIV(none, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
2786c962
TF		 387 DIV_F(none, "div_spi_pre1", "div_spi1",
388 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
389
6e3ad268 390 DIV(none, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
2786c962
TF		 391 DIV_F(none, "div_spi_pre2", "div_spi2",
392 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
393
6e3ad268 394 DIV(none, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
2786c962 395
6e3ad268
TA		 396 DIV(none, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
397 DIV(none, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
398 DIV(none, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
399 DIV(none, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
2786c962 400
79d743c1
PV		 401 DIV(div_i2s1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
402 DIV(div_i2s2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
6e3ad268
TA		 403};
404
b95e71c6 405static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
2786c962
TF		 406 /*
407 * NOTE: Following table is sorted by (clock domain, register address,
408 * bitfield shift) triplet in ascending order. When adding new entries,
409 * please make sure that the order is kept, to avoid merge conflicts
410 * and make further work with defined data easier.
411 */
412
413 /*
414 * CMU_ACP
415 */
416 GATE(mdma0, "mdma0", "aclk266", GATE_IP_ACP, 1, 0, 0),
417 GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
418 GATE(smmu_mdma0, "smmu_mdma0", "aclk266", GATE_IP_ACP, 5, 0, 0),
419
420 /*
421 * CMU_TOP
422 */
423 GATE(sclk_cam_bayer, "sclk_cam_bayer", "div_cam_bayer",
424 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
425 GATE(sclk_cam0, "sclk_cam0", "div_cam0",
426 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
427 GATE(sclk_cam1, "sclk_cam1", "div_cam1",
428 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
429 GATE(sclk_gscl_wa, "sclk_gscl_wa", "div_gscl_wa",
430 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
431 GATE(sclk_gscl_wb, "sclk_gscl_wb", "div_gscl_wb",
432 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
433
434 GATE(sclk_fimd1, "sclk_fimd1", "div_fimd1",
435 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
436 GATE(sclk_mipi1, "sclk_mipi1", "div_mipi1",
437 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
438 GATE(sclk_dp, "sclk_dp", "div_dp",
439 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
440 GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
441 SRC_MASK_DISP1_0, 20, 0, 0),
442
443 GATE(sclk_audio0, "sclk_audio0", "div_audio0",
444 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
445
446 GATE(sclk_mmc0, "sclk_mmc0", "div_mmc_pre0",
447 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
448 GATE(sclk_mmc1, "sclk_mmc1", "div_mmc_pre1",
449 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
450 GATE(sclk_mmc2, "sclk_mmc2", "div_mmc_pre2",
451 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
452 GATE(sclk_mmc3, "sclk_mmc3", "div_mmc_pre3",
453 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
454 GATE(sclk_sata, "sclk_sata", "div_sata",
455 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
456 GATE(sclk_usb3, "sclk_usb3", "div_usb3",
457 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
458
459 GATE(sclk_jpeg, "sclk_jpeg", "div_jpeg",
460 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
461
462 GATE(sclk_uart0, "sclk_uart0", "div_uart0",
463 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
464 GATE(sclk_uart1, "sclk_uart1", "div_uart1",
465 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
466 GATE(sclk_uart2, "sclk_uart2", "div_uart2",
467 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
468 GATE(sclk_uart3, "sclk_uart3", "div_uart3",
469 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
470 GATE(sclk_pwm, "sclk_pwm", "div_pwm",
471 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
472
473 GATE(sclk_audio1, "sclk_audio1", "div_audio1",
474 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
475 GATE(sclk_audio2, "sclk_audio2", "div_audio2",
476 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
477 GATE(sclk_spdif, "sclk_spdif", "mout_spdif",
478 SRC_MASK_PERIC1, 4, 0, 0),
479 GATE(sclk_spi0, "sclk_spi0", "div_spi_pre0",
480 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
481 GATE(sclk_spi1, "sclk_spi1", "div_spi_pre1",
482 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
483 GATE(sclk_spi2, "sclk_spi2", "div_spi_pre2",
484 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
485
6e3ad268
TA		 486 GATE(gscl0, "gscl0", "none", GATE_IP_GSCL, 0, 0, 0),
487 GATE(gscl1, "gscl1", "none", GATE_IP_GSCL, 1, 0, 0),
488 GATE(gscl2, "gscl2", "aclk266", GATE_IP_GSCL, 2, 0, 0),
489 GATE(gscl3, "gscl3", "aclk266", GATE_IP_GSCL, 3, 0, 0),
490 GATE(gscl_wa, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
491 GATE(gscl_wb, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
492 GATE(smmu_gscl0, "smmu_gscl0", "aclk266", GATE_IP_GSCL, 7, 0, 0),
493 GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0),
494 GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
495 GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
2786c962
TF		 496
497 GATE(fimd1, "fimd1", "aclk200", GATE_IP_DISP1, 0, 0, 0),
498 GATE(mie1, "mie1", "aclk200", GATE_IP_DISP1, 1, 0, 0),
499 GATE(dsim0, "dsim0", "aclk200", GATE_IP_DISP1, 3, 0, 0),
500 GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
501 GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
502 GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
503
6e3ad268 504 GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
97c3557c 505 GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 1, 0, 0),
2786c962
TF		 506 GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 2, 0, 0),
507
6e3ad268
TA		 508 GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
509 GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0),
510 GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
511 GATE(smmu_rotator, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0),
512 GATE(smmu_jpeg, "smmu_jpeg", "aclk166", GATE_IP_GEN, 7, 0, 0),
513 GATE(smmu_mdma1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0),
2786c962 514
6e3ad268
TA		 515 GATE(pdma0, "pdma0", "aclk200", GATE_IP_FSYS, 1, 0, 0),
516 GATE(pdma1, "pdma1", "aclk200", GATE_IP_FSYS, 2, 0, 0),
517 GATE(sata, "sata", "aclk200", GATE_IP_FSYS, 6, 0, 0),
518 GATE(usbotg, "usbotg", "aclk200", GATE_IP_FSYS, 7, 0, 0),
519 GATE(mipi_hsi, "mipi_hsi", "aclk200", GATE_IP_FSYS, 8, 0, 0),
520 GATE(sdmmc0, "sdmmc0", "aclk200", GATE_IP_FSYS, 12, 0, 0),
521 GATE(sdmmc1, "sdmmc1", "aclk200", GATE_IP_FSYS, 13, 0, 0),
522 GATE(sdmmc2, "sdmmc2", "aclk200", GATE_IP_FSYS, 14, 0, 0),
523 GATE(sdmmc3, "sdmmc3", "aclk200", GATE_IP_FSYS, 15, 0, 0),
524 GATE(sromc, "sromc", "aclk200", GATE_IP_FSYS, 17, 0, 0),
525 GATE(usb2, "usb2", "aclk200", GATE_IP_FSYS, 18, 0, 0),
526 GATE(usb3, "usb3", "aclk200", GATE_IP_FSYS, 19, 0, 0),
527 GATE(sata_phyctrl, "sata_phyctrl", "aclk200", GATE_IP_FSYS, 24, 0, 0),
528 GATE(sata_phyi2c, "sata_phyi2c", "aclk200", GATE_IP_FSYS, 25, 0, 0),
2786c962 529
6e3ad268
TA		 530 GATE(uart0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
531 GATE(uart1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
532 GATE(uart2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
533 GATE(uart3, "uart3", "aclk66", GATE_IP_PERIC, 3, 0, 0),
534 GATE(uart4, "uart4", "aclk66", GATE_IP_PERIC, 4, 0, 0),
535 GATE(i2c0, "i2c0", "aclk66", GATE_IP_PERIC, 6, 0, 0),
536 GATE(i2c1, "i2c1", "aclk66", GATE_IP_PERIC, 7, 0, 0),
537 GATE(i2c2, "i2c2", "aclk66", GATE_IP_PERIC, 8, 0, 0),
538 GATE(i2c3, "i2c3", "aclk66", GATE_IP_PERIC, 9, 0, 0),
539 GATE(i2c4, "i2c4", "aclk66", GATE_IP_PERIC, 10, 0, 0),
540 GATE(i2c5, "i2c5", "aclk66", GATE_IP_PERIC, 11, 0, 0),
541 GATE(i2c6, "i2c6", "aclk66", GATE_IP_PERIC, 12, 0, 0),
542 GATE(i2c7, "i2c7", "aclk66", GATE_IP_PERIC, 13, 0, 0),
543 GATE(i2c_hdmi, "i2c_hdmi", "aclk66", GATE_IP_PERIC, 14, 0, 0),
544 GATE(adc, "adc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
545 GATE(spi0, "spi0", "aclk66", GATE_IP_PERIC, 16, 0, 0),
546 GATE(spi1, "spi1", "aclk66", GATE_IP_PERIC, 17, 0, 0),
547 GATE(spi2, "spi2", "aclk66", GATE_IP_PERIC, 18, 0, 0),
548 GATE(i2s1, "i2s1", "aclk66", GATE_IP_PERIC, 20, 0, 0),
549 GATE(i2s2, "i2s2", "aclk66", GATE_IP_PERIC, 21, 0, 0),
550 GATE(pcm1, "pcm1", "aclk66", GATE_IP_PERIC, 22, 0, 0),
551 GATE(pcm2, "pcm2", "aclk66", GATE_IP_PERIC, 23, 0, 0),
552 GATE(pwm, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
553 GATE(spdif, "spdif", "aclk66", GATE_IP_PERIC, 26, 0, 0),
554 GATE(ac97, "ac97", "aclk66", GATE_IP_PERIC, 27, 0, 0),
555 GATE(hsi2c0, "hsi2c0", "aclk66", GATE_IP_PERIC, 28, 0, 0),
556 GATE(hsi2c1, "hsi2c1", "aclk66", GATE_IP_PERIC, 29, 0, 0),
557 GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
558 GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
2786c962 559
6e3ad268 560 GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
2feed5ae
AK		 561 GATE(sysreg, "sysreg", "aclk66",
562 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
346f372f 563 GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
2786c962
TF		 564 GATE(cmu_top, "cmu_top", "aclk66",
565 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
566 GATE(cmu_core, "cmu_core", "aclk66",
567 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
568 GATE(cmu_mem, "cmu_mem", "aclk66",
569 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
6e3ad268
TA		 570 GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
571 GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
572 GATE(tzpc2, "tzpc2", "aclk66", GATE_IP_PERIS, 8, 0, 0),
573 GATE(tzpc3, "tzpc3", "aclk66", GATE_IP_PERIS, 9, 0, 0),
574 GATE(tzpc4, "tzpc4", "aclk66", GATE_IP_PERIS, 10, 0, 0),
575 GATE(tzpc5, "tzpc5", "aclk66", GATE_IP_PERIS, 11, 0, 0),
576 GATE(tzpc6, "tzpc6", "aclk66", GATE_IP_PERIS, 12, 0, 0),
577 GATE(tzpc7, "tzpc7", "aclk66", GATE_IP_PERIS, 13, 0, 0),
578 GATE(tzpc8, "tzpc8", "aclk66", GATE_IP_PERIS, 14, 0, 0),
579 GATE(tzpc9, "tzpc9", "aclk66", GATE_IP_PERIS, 15, 0, 0),
580 GATE(hdmi_cec, "hdmi_cec", "aclk66", GATE_IP_PERIS, 16, 0, 0),
581 GATE(mct, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
582 GATE(wdt, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
583 GATE(rtc, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
584 GATE(tmu, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
6e3ad268
TA		 585};
586
b6993ecb 587static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
d2127ac4
VS		 588 /* sorted in descending order */
589 /* PLL_36XX_RATE(rate, m, p, s, k) */
590 PLL_36XX_RATE(266000000, 266, 3, 3, 0),
591 /* Not in UM, but need for eDP on snow */
592 PLL_36XX_RATE(70500000, 94, 2, 4, 0),
593 { },
594};
595
b6993ecb 596static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = {
d2127ac4
VS		 597 /* sorted in descending order */
598 /* PLL_36XX_RATE(rate, m, p, s, k) */
599 PLL_36XX_RATE(192000000, 64, 2, 2, 0),
600 PLL_36XX_RATE(180633600, 90, 3, 2, 20762),
601 PLL_36XX_RATE(180000000, 90, 3, 2, 0),
602 PLL_36XX_RATE(73728000, 98, 2, 4, 19923),
603 PLL_36XX_RATE(67737600, 90, 2, 4, 20762),
604 PLL_36XX_RATE(49152000, 98, 3, 4, 19923),
605 PLL_36XX_RATE(45158400, 90, 3, 4, 20762),
606 PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
607 { },
608};
609
b6993ecb 610static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
8dac3530 611 [apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
3ff6e0d8 612 APLL_CON0, "fout_apll", NULL),
8dac3530 613 [mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", MPLL_LOCK,
3ff6e0d8 614 MPLL_CON0, "fout_mpll", NULL),
8dac3530 615 [bpll] = PLL(pll_35xx, fout_bpll, "fout_bpll", "fin_pll", BPLL_LOCK,
3ff6e0d8 616 BPLL_CON0, NULL),
8dac3530 617 [gpll] = PLL(pll_35xx, fout_gpll, "fout_gpll", "fin_pll", GPLL_LOCK,
3ff6e0d8 618 GPLL_CON0, NULL),
8dac3530 619 [cpll] = PLL(pll_35xx, fout_cpll, "fout_cpll", "fin_pll", CPLL_LOCK,
3ff6e0d8 620 CPLL_CON0, NULL),
8dac3530 621 [epll] = PLL(pll_36xx, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,
3ff6e0d8 622 EPLL_CON0, NULL),
8dac3530 623 [vpll] = PLL(pll_36xx, fout_vpll, "fout_vpll", "mout_vpllsrc",
3ff6e0d8 624 VPLL_LOCK, VPLL_CON0, NULL),
8dac3530
YSB		 625};
626
b6993ecb 627static struct of_device_id ext_clk_match[] __initdata = {
6e3ad268
TA		 628 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
629 { },
630};
631
632/* register exynox5250 clocks */
b95e71c6 633static void __init exynos5250_clk_init(struct device_node *np)
6e3ad268
TA		 634{
635 void __iomem *reg_base;
6e3ad268
TA		 636
637 if (np) {
638 reg_base = of_iomap(np, 0);
639 if (!reg_base)
640 panic("%s: failed to map registers\n", __func__);
641 } else {
642 panic("%s: unable to determine soc\n", __func__);
643 }
644
645 samsung_clk_init(np, reg_base, nr_clks,
6b5756e8
TF		 646 exynos5250_clk_regs, ARRAY_SIZE(exynos5250_clk_regs),
647 NULL, 0);
6e3ad268
TA		 648 samsung_clk_of_register_fixed_ext(exynos5250_fixed_rate_ext_clks,
649 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
650 ext_clk_match);
8bc2eeb8
VS		 651 samsung_clk_register_mux(exynos5250_pll_pmux_clks,
652 ARRAY_SIZE(exynos5250_pll_pmux_clks));
d2127ac4 653
22e9e758 654 if (_get_rate("fin_pll") == 24 * MHZ)
d2127ac4
VS		 655 exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
656
22e9e758 657 if (_get_rate("mout_vpllsrc") == 24 * MHZ)
d2127ac4
VS		 658 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
659
8dac3530
YSB		 660 samsung_clk_register_pll(exynos5250_plls, ARRAY_SIZE(exynos5250_plls),
661 reg_base);
6e3ad268
TA		 662 samsung_clk_register_fixed_rate(exynos5250_fixed_rate_clks,
663 ARRAY_SIZE(exynos5250_fixed_rate_clks));
664 samsung_clk_register_fixed_factor(exynos5250_fixed_factor_clks,
665 ARRAY_SIZE(exynos5250_fixed_factor_clks));
666 samsung_clk_register_mux(exynos5250_mux_clks,
667 ARRAY_SIZE(exynos5250_mux_clks));
668 samsung_clk_register_div(exynos5250_div_clks,
669 ARRAY_SIZE(exynos5250_div_clks));
670 samsung_clk_register_gate(exynos5250_gate_clks,
671 ARRAY_SIZE(exynos5250_gate_clks));
672
673 pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
674 _get_rate("armclk"));
675}
676CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
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