]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/clk/samsung/clk-exynos5250.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
[mirror_ubuntu-hirsute-kernel.git] / drivers / clk / samsung / clk-exynos5250.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
6e3ad268
TA		 2/*
3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
4 * Copyright (c) 2013 Linaro Ltd.
5 * Author: Thomas Abraham <thomas.ab@samsung.com>
6 *
6e3ad268
TA		 7 * Common Clock Framework support for Exynos5250 SoC.
8*/
9
2fe8f00c 10#include <dt-bindings/clock/exynos5250.h>
6e3ad268 11#include <linux/clk-provider.h>
62e59c4e 12#include <linux/io.h>
6e3ad268
TA		 13#include <linux/of.h>
14#include <linux/of_address.h>
15
6e3ad268 16#include "clk.h"
d7cc4c81 17#include "clk-cpu.h"
edcefb96 18#include "clk-exynos5-subcmu.h"
6e3ad268 19
8dac3530
YSB		 20#define APLL_LOCK 0x0
21#define APLL_CON0 0x100
6e3ad268
TA		 22#define SRC_CPU 0x200
23#define DIV_CPU0 0x500
9a8f3995
ADK		 24#define PWR_CTRL1 0x1020
25#define PWR_CTRL2 0x1024
8dac3530
YSB		 26#define MPLL_LOCK 0x4000
27#define MPLL_CON0 0x4100
6e3ad268 28#define SRC_CORE1 0x4204
3bf34666 29#define GATE_IP_ACP 0x8800
bfed1074
CK		 30#define GATE_IP_ISP0 0xc800
31#define GATE_IP_ISP1 0xc804
8dac3530
YSB		 32#define CPLL_LOCK 0x10020
33#define EPLL_LOCK 0x10030
34#define VPLL_LOCK 0x10040
35#define GPLL_LOCK 0x10050
36#define CPLL_CON0 0x10120
37#define EPLL_CON0 0x10130
38#define VPLL_CON0 0x10140
39#define GPLL_CON0 0x10150
6e3ad268 40#define SRC_TOP0 0x10210
20b82ae2 41#define SRC_TOP1 0x10214
6e3ad268 42#define SRC_TOP2 0x10218
796d1f4c 43#define SRC_TOP3 0x1021c
6e3ad268
TA		 44#define SRC_GSCL 0x10220
45#define SRC_DISP1_0 0x1022c
46#define SRC_MAU 0x10240
47#define SRC_FSYS 0x10244
48#define SRC_GEN 0x10248
49#define SRC_PERIC0 0x10250
50#define SRC_PERIC1 0x10254
51#define SRC_MASK_GSCL 0x10320
52#define SRC_MASK_DISP1_0 0x1032c
53#define SRC_MASK_MAU 0x10334
54#define SRC_MASK_FSYS 0x10340
55#define SRC_MASK_GEN 0x10344
56#define SRC_MASK_PERIC0 0x10350
57#define SRC_MASK_PERIC1 0x10354
58#define DIV_TOP0 0x10510
59#define DIV_TOP1 0x10514
60#define DIV_GSCL 0x10520
61#define DIV_DISP1_0 0x1052c
62#define DIV_GEN 0x1053c
63#define DIV_MAU 0x10544
64#define DIV_FSYS0 0x10548
65#define DIV_FSYS1 0x1054c
66#define DIV_FSYS2 0x10550
67#define DIV_PERIC0 0x10558
68#define DIV_PERIC1 0x1055c
69#define DIV_PERIC2 0x10560
70#define DIV_PERIC3 0x10564
71#define DIV_PERIC4 0x10568
72#define DIV_PERIC5 0x1056c
73#define GATE_IP_GSCL 0x10920
2786c962 74#define GATE_IP_DISP1 0x10928
6e3ad268 75#define GATE_IP_MFC 0x1092c
20b82ae2 76#define GATE_IP_G3D 0x10930
6e3ad268
TA		 77#define GATE_IP_GEN 0x10934
78#define GATE_IP_FSYS 0x10944
79#define GATE_IP_PERIC 0x10950
80#define GATE_IP_PERIS 0x10960
8dac3530
YSB		 81#define BPLL_LOCK 0x20010
82#define BPLL_CON0 0x20110
6e3ad268
TA		 83#define SRC_CDREX 0x20200
84#define PLL_DIV2_SEL 0x20a24
85
9a8f3995
ADK		 86/*Below definitions are used for PWR_CTRL settings*/
87#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
88#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
89#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
90#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
91#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
92#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
93#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
94#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
95
96#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
97#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
98#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
99#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
100#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
101#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
102
8dac3530
YSB		 103/* list of PLLs to be registered */
104enum exynos5250_plls {
105 apll, mpll, cpll, epll, vpll, gpll, bpll,
106 nr_plls /* number of PLLs */
107};
108
c3b6c1d7
TF		 109static void __iomem *reg_base;
110
6e3ad268
TA		 111/*
112 * list of controller registers to be saved and restored during a
113 * suspend/resume cycle.
114 */
5b37e849 115static const unsigned long exynos5250_clk_regs[] __initconst = {
6e3ad268
TA		 116 SRC_CPU,
117 DIV_CPU0,
9a8f3995
ADK		 118 PWR_CTRL1,
119 PWR_CTRL2,
6e3ad268
TA		 120 SRC_CORE1,
121 SRC_TOP0,
20b82ae2 122 SRC_TOP1,
6e3ad268 123 SRC_TOP2,
796d1f4c 124 SRC_TOP3,
6e3ad268
TA		 125 SRC_GSCL,
126 SRC_DISP1_0,
127 SRC_MAU,
128 SRC_FSYS,
129 SRC_GEN,
130 SRC_PERIC0,
131 SRC_PERIC1,
132 SRC_MASK_GSCL,
133 SRC_MASK_DISP1_0,
134 SRC_MASK_MAU,
135 SRC_MASK_FSYS,
136 SRC_MASK_GEN,
137 SRC_MASK_PERIC0,
138 SRC_MASK_PERIC1,
139 DIV_TOP0,
140 DIV_TOP1,
141 DIV_GSCL,
142 DIV_DISP1_0,
143 DIV_GEN,
144 DIV_MAU,
145 DIV_FSYS0,
146 DIV_FSYS1,
147 DIV_FSYS2,
148 DIV_PERIC0,
149 DIV_PERIC1,
150 DIV_PERIC2,
151 DIV_PERIC3,
152 DIV_PERIC4,
153 DIV_PERIC5,
154 GATE_IP_GSCL,
155 GATE_IP_MFC,
20b82ae2 156 GATE_IP_G3D,
6e3ad268
TA		 157 GATE_IP_GEN,
158 GATE_IP_FSYS,
159 GATE_IP_PERIC,
160 GATE_IP_PERIS,
161 SRC_CDREX,
162 PLL_DIV2_SEL,
17d4cacc 163 GATE_IP_DISP1,
406c5989 164 GATE_IP_ACP,
bfed1074
CK		 165 GATE_IP_ISP0,
166 GATE_IP_ISP1,
6e3ad268
TA		 167};
168
169/* list of all parent clock list */
170PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
38ee3754 171PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
6e3ad268
TA		 172PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
173PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
174PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
175PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
176PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
177PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
178PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
179PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
20b82ae2 180PNAME(mout_gpll_p) = { "fin_pll", "fout_gpll" };
38ee3754
TF		 181PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" };
182PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" };
183PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" };
184PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" };
b4dc272b
TV		 185PNAME(mout_aclk300_p) = { "mout_aclk300_disp1_mid",
186 "mout_aclk300_disp1_mid1" };
20b82ae2 187PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" };
3818f117 188PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
796d1f4c 189PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
b4dc272b
TV		 190PNAME(mout_aclk300_sub_p) = { "fin_pll", "div_aclk300_disp" };
191PNAME(mout_aclk300_disp1_mid1_p) = { "mout_vpll", "mout_cpll" };
96987ded 192PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
bfed1074 193PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" };
6e3ad268 194PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" };
38ee3754 195PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" };
6e3ad268
TA		 196PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
197 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy",
38ee3754 198 "mout_mpll_user", "mout_epll", "mout_vpll",
256dd646
TF		 199 "mout_cpll", "none", "none",
200 "none", "none", "none",
201 "none" };
6e3ad268 202PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
bfeb9f27 203 "sclk_uhostphy", "fin_pll",
38ee3754 204 "mout_mpll_user", "mout_epll", "mout_vpll",
256dd646
TF		 205 "mout_cpll", "none", "none",
206 "none", "none", "none",
207 "none" };
6e3ad268 208PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
bfeb9f27 209 "sclk_uhostphy", "fin_pll",
38ee3754 210 "mout_mpll_user", "mout_epll", "mout_vpll",
256dd646
TF		 211 "mout_cpll", "none", "none",
212 "none", "none", "none",
213 "none" };
6e3ad268 214PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
bfeb9f27 215 "sclk_uhostphy", "fin_pll",
38ee3754 216 "mout_mpll_user", "mout_epll", "mout_vpll",
256dd646
TF		 217 "mout_cpll", "none", "none",
218 "none", "none", "none",
219 "none" };
6e3ad268
TA		 220PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2",
221 "spdif_extclk" };
222
223/* fixed rate clocks generated outside the soc */
b95e71c6 224static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = {
728f288d 225 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
6e3ad268
TA		 226};
227
228/* fixed rate clocks generated inside the soc */
5b37e849 229static const struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initconst = {
728f288d
SB		 230 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
231 FRATE(0, "sclk_hdmi27m", NULL, 0, 27000000),
232 FRATE(0, "sclk_dptxphy", NULL, 0, 24000000),
233 FRATE(0, "sclk_uhostphy", NULL, 0, 48000000),
6e3ad268
TA		 234};
235
5b37e849 236static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initconst = {
2fe8f00c
AH		 237 FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0),
238 FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0),
6e3ad268
TA		 239};
240
5b37e849 241static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = {
2fe8f00c 242 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
8bc2eeb8
VS		 243};
244
5b37e849 245static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
2786c962
TF		 246 /*
247 * NOTE: Following table is sorted by (clock domain, register address,
248 * bitfield shift) triplet in ascending order. When adding new entries,
249 * please make sure that the order is kept, to avoid merge conflicts
250 * and make further work with defined data easier.
251 */
252
253 /*
254 * CMU_CPU
255 */
29964890
MS		 256 MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
257 CLK_SET_RATE_PARENT, 0),
258 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
2786c962
TF		 259
260 /*
261 * CMU_CORE
262 */
29964890 263 MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
2786c962
TF		 264
265 /*
266 * CMU_TOP
267 */
2fe8f00c
AH		 268 MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
269 MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
b4dc272b
TV		 270 MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1),
271 MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1),
2fe8f00c 272 MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
20b82ae2
AK		 273 MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
274
b4dc272b
TV		 275 MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1,
276 8, 1),
bfed1074 277 MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1),
20b82ae2 278 MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
2fe8f00c
AH		 279
280 MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1),
281 MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1),
282 MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1),
283 MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1),
284 MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
20b82ae2 285 MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
2fe8f00c 286
b4dc272b
TV		 287 MUX(CLK_MOUT_ACLK200_DISP1_SUB, "mout_aclk200_disp1_sub",
288 mout_aclk200_sub_p, SRC_TOP3, 4, 1),
289 MUX(CLK_MOUT_ACLK300_DISP1_SUB, "mout_aclk300_disp1_sub",
290 mout_aclk300_sub_p, SRC_TOP3, 6, 1),
2fe8f00c 291 MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
bfed1074
CK		 292 MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1),
293 MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p,
294 SRC_TOP3, 20, 1),
2fe8f00c
AH		 295 MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1),
296
297 MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4),
298 MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4),
299 MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4),
300 MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4),
301 MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4),
302
303 MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4),
304 MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4),
305 MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4),
306 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1),
307
308 MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4),
309
310 MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4),
311 MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4),
312 MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4),
313 MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4),
314 MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1),
315 MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1),
316
317 MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4),
318
319 MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4),
320 MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4),
321 MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4),
322 MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4),
323 MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4),
324
325 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4),
326 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4),
327 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2),
328 MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4),
329 MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4),
330 MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4),
2786c962
TF		 331
332 /*
333 * CMU_CDREX
334 */
2fe8f00c 335 MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
2786c962 336
2fe8f00c
AH		 337 MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
338 MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
6e3ad268
TA		 339};
340
5b37e849 341static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
2786c962
TF		 342 /*
343 * NOTE: Following table is sorted by (clock domain, register address,
344 * bitfield shift) triplet in ascending order. When adding new entries,
345 * please make sure that the order is kept, to avoid merge conflicts
346 * and make further work with defined data easier.
347 */
348
349 /*
350 * CMU_CPU
351 */
2fe8f00c
AH		 352 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
353 DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
29964890 354 DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
2786c962
TF		 355
356 /*
357 * CMU_TOP
358 */
2fe8f00c
AH		 359 DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3),
360 DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
361 DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
362 DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3),
363 DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
20b82ae2
AK		 364 DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
365 24, 3),
b4dc272b 366 DIV(0, "div_aclk300_disp", "mout_aclk300", DIV_TOP0, 28, 3),
2fe8f00c 367
bfed1074 368 DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3),
2fe8f00c
AH		 369 DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
370
371 DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
372 DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
373 DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
374 DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4),
375 DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4),
376
377 DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4),
378 DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4),
379 DIV_F(0, "div_mipi1_pre", "div_mipi1",
2786c962 380 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0),
2fe8f00c
AH		 381 DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
382 DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4),
2786c962 383
2fe8f00c 384 DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
2786c962 385
2fe8f00c 386 DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
35399dda 387 DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
2786c962 388
2fe8f00c
AH		 389 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
390 DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
2786c962 391
2fe8f00c
AH		 392 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
393 DIV_F(0, "div_mmc_pre0", "div_mmc0",
2786c962 394 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
2fe8f00c
AH		 395 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
396 DIV_F(0, "div_mmc_pre1", "div_mmc1",
2786c962
TF		 397 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
398
2fe8f00c
AH		 399 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
400 DIV_F(0, "div_mmc_pre2", "div_mmc2",
2786c962 401 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
2fe8f00c
AH		 402 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
403 DIV_F(0, "div_mmc_pre3", "div_mmc3",
2786c962
TF		 404 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0),
405
2fe8f00c
AH		 406 DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
407 DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
408 DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
409 DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
2786c962 410
2fe8f00c
AH		 411 DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4),
412 DIV_F(0, "div_spi_pre0", "div_spi0",
2786c962 413 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0),
2fe8f00c
AH		 414 DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4),
415 DIV_F(0, "div_spi_pre1", "div_spi1",
2786c962
TF		 416 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0),
417
2fe8f00c
AH		 418 DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4),
419 DIV_F(0, "div_spi_pre2", "div_spi2",
2786c962
TF		 420 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0),
421
2fe8f00c 422 DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4),
2786c962 423
2fe8f00c
AH		 424 DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4),
425 DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8),
426 DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4),
427 DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8),
2786c962 428
2fe8f00c
AH		 429 DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6),
430 DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6),
6e3ad268
TA		 431};
432
5b37e849 433static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = {
2786c962
TF		 434 /*
435 * NOTE: Following table is sorted by (clock domain, register address,
436 * bitfield shift) triplet in ascending order. When adding new entries,
437 * please make sure that the order is kept, to avoid merge conflicts
438 * and make further work with defined data easier.
439 */
440
441 /*
442 * CMU_ACP
443 */
2fe8f00c 444 GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
5b73721b 445 GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
2fe8f00c
AH		 446 GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
447 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
2786c962
TF		 448
449 /*
450 * CMU_TOP
451 */
2fe8f00c 452 GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer",
2786c962 453 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0),
2fe8f00c 454 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
2786c962 455 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0),
2fe8f00c 456 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
2786c962 457 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0),
2fe8f00c 458 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa",
2786c962 459 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0),
2fe8f00c 460 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb",
2786c962
TF		 461 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0),
462
2fe8f00c 463 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
2786c962 464 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0),
2fe8f00c 465 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1",
2786c962 466 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0),
2fe8f00c 467 GATE(CLK_SCLK_DP, "sclk_dp", "div_dp",
2786c962 468 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0),
2fe8f00c 469 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
2786c962
TF		 470 SRC_MASK_DISP1_0, 20, 0, 0),
471
2fe8f00c 472 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
2786c962
TF		 473 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0),
474
2fe8f00c 475 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
2786c962 476 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
2fe8f00c 477 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
2786c962 478 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2fe8f00c 479 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
2786c962 480 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
2fe8f00c 481 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3",
2786c962 482 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0),
2fe8f00c 483 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
2786c962 484 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
2fe8f00c 485 GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3",
2786c962
TF		 486 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0),
487
2fe8f00c 488 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
2786c962
TF		 489 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0),
490
2fe8f00c 491 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
2786c962 492 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
2fe8f00c 493 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
2786c962 494 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
2fe8f00c 495 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
2786c962 496 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
2fe8f00c 497 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
2786c962 498 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0),
2fe8f00c 499 GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm",
2786c962
TF		 500 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0),
501
2fe8f00c 502 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
2786c962 503 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
2fe8f00c 504 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
2786c962 505 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
2fe8f00c 506 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
2786c962 507 SRC_MASK_PERIC1, 4, 0, 0),
2fe8f00c 508 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
2786c962 509 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0),
2fe8f00c 510 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1",
2786c962 511 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
2fe8f00c 512 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2",
2786c962
TF		 513 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0),
514
2fe8f00c
AH		 515 GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0,
516 0),
517 GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0,
518 0),
519 GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0,
520 0),
521 GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0,
522 0),
5b23fcee
MS		 523 GATE(CLK_CAMIF_TOP, "camif_top", "mout_aclk266_gscl_sub",
524 GATE_IP_GSCL, 4, 0, 0),
2fe8f00c
AH		 525 GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0),
526 GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0),
527 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub",
796d1f4c 528 GATE_IP_GSCL, 7, 0, 0),
2fe8f00c 529 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub",
796d1f4c 530 GATE_IP_GSCL, 8, 0, 0),
2fe8f00c 531 GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub",
796d1f4c 532 GATE_IP_GSCL, 9, 0, 0),
2fe8f00c 533 GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub",
796d1f4c 534 GATE_IP_GSCL, 10, 0, 0),
5b23fcee
MS		 535 GATE(CLK_SMMU_FIMC_LITE0, "smmu_fimc_lite0", "mout_aclk266_gscl_sub",
536 GATE_IP_GSCL, 11, 0, 0),
537 GATE(CLK_SMMU_FIMC_LITE1, "smmu_fimc_lite1", "mout_aclk266_gscl_sub",
538 GATE_IP_GSCL, 12, 0, 0),
38ee3754 539
2fe8f00c
AH		 540
541 GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0),
542 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0,
543 0),
544 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
545 0),
20b82ae2
AK		 546 GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0,
547 CLK_SET_RATE_PARENT, 0),
2fe8f00c
AH		 548 GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0),
549 GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0),
550 GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0),
551 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0,
552 0),
553 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0),
554 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0),
555
556 GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0),
557 GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0),
558 GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0),
559 GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0),
560 GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0),
561 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0),
562 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0),
563 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0),
564 GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0),
565 GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0),
566 GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0),
567 GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0),
568 GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200",
38ee3754 569 GATE_IP_FSYS, 24, 0, 0),
2fe8f00c
AH		 570 GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0,
571 0),
572
573 GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0),
574 GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0),
575 GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0),
576 GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0),
577 GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0),
578 GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0),
579 GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0),
580 GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0),
581 GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0),
582 GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0),
583 GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0),
584 GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0),
585 GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0),
586 GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0),
587 GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0),
588 GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0),
589 GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0),
590 GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0),
591 GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0),
592 GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0),
593 GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0),
594 GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0),
595 GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
596 GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0),
597 GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0),
598 GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0),
599 GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0),
600 GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0),
601 GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0),
602
603 GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0),
604 GATE(CLK_SYSREG, "sysreg", "div_aclk66",
2feed5ae 605 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
2fe8f00c
AH		 606 GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED,
607 0),
608 GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
2786c962 609 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0),
2fe8f00c 610 GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66",
2786c962 611 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0),
2fe8f00c 612 GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66",
2786c962 613 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0),
2fe8f00c
AH		 614 GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0),
615 GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0),
616 GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0),
617 GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0),
618 GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0),
619 GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0),
620 GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0),
621 GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0),
622 GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0),
623 GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0),
624 GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0),
625 GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0),
626 GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0),
627 GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
628 GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
bfed1074
CK		 629 GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
630 GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub",
631 GATE_IP_ISP0, 8, 0, 0),
632 GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub",
633 GATE_IP_ISP0, 9, 0, 0),
634 GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub",
635 GATE_IP_ISP0, 10, 0, 0),
636 GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub",
637 GATE_IP_ISP0, 11, 0, 0),
638 GATE(CLK_SMMU_FIMC_SCP, "smmu_fimc_scp", "mout_aclk_266_isp_sub",
639 GATE_IP_ISP0, 12, 0, 0),
640 GATE(CLK_SMMU_FIMC_MCU, "smmu_fimc_mcu", "mout_aclk_400_isp_sub",
641 GATE_IP_ISP0, 13, 0, 0),
642 GATE(CLK_SMMU_FIMC_ODC, "smmu_fimc_odc", "mout_aclk_266_isp_sub",
643 GATE_IP_ISP1, 4, 0, 0),
644 GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub",
645 GATE_IP_ISP1, 5, 0, 0),
646 GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub",
647 GATE_IP_ISP1, 6, 0, 0),
648 GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub",
649 GATE_IP_ISP1, 7, 0, 0),
6e3ad268
TA		 650};
651
edcefb96
MS		 652static const struct samsung_gate_clock exynos5250_disp_gate_clks[] __initconst = {
653 GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0,
654 0),
655 GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0,
656 0),
657 GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0,
658 0),
659 GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0),
660 GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0,
661 0),
662 GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0,
663 0),
664 GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
665 GATE_IP_DISP1, 9, 0, 0),
666 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
667 GATE_IP_DISP1, 8, 0, 0),
668};
669
670static struct exynos5_subcmu_reg_dump exynos5250_disp_suspend_regs[] = {
671 { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
672 { SRC_TOP3, 0, BIT(4) }, /* MUX mout_aclk200_disp1_sub */
673 { SRC_TOP3, 0, BIT(6) }, /* MUX mout_aclk300_disp1_sub */
674};
675
676static const struct exynos5_subcmu_info exynos5250_disp_subcmu = {
677 .gate_clks = exynos5250_disp_gate_clks,
678 .nr_gate_clks = ARRAY_SIZE(exynos5250_disp_gate_clks),
679 .suspend_regs = exynos5250_disp_suspend_regs,
680 .nr_suspend_regs = ARRAY_SIZE(exynos5250_disp_suspend_regs),
681 .pd_name = "DISP1",
682};
683
5b37e849 684static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {
d2127ac4
VS		 685 /* sorted in descending order */
686 /* PLL_36XX_RATE(rate, m, p, s, k) */
1d5013f1 687 PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
d2127ac4 688 /* Not in UM, but need for eDP on snow */
1d5013f1 689 PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
d2127ac4
VS		 690 { },
691};
692
5b37e849 693static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = {
d2127ac4
VS		 694 /* sorted in descending order */
695 /* PLL_36XX_RATE(rate, m, p, s, k) */
1d5013f1
AH		 696 PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0),
697 PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762),
698 PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0),
699 PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
700 PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762),
701 PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923),
702 PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762),
703 PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719),
d2127ac4
VS		 704 { },
705};
706
5b37e849 707static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {
f521ac8b 708 /* sorted in descending order */
1d5013f1
AH		 709 /* PLL_35XX_RATE(fin, rate, m, p, s) */
710 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
711 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
712 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
713 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
714 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
715 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
716 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
717 PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
718 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
719 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
720 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
721 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
722 PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
723 PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
724 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
725 PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
f521ac8b
AB		 726};
727
b6993ecb 728static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
29964890
MS		 729 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
730 APLL_CON0, NULL),
731 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
732 MPLL_CON0, NULL),
2fe8f00c 733 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
3ff6e0d8 734 BPLL_CON0, NULL),
2fe8f00c 735 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
3ff6e0d8 736 GPLL_CON0, NULL),
2fe8f00c 737 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
3ff6e0d8 738 CPLL_CON0, NULL),
2fe8f00c 739 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
3ff6e0d8 740 EPLL_CON0, NULL),
2fe8f00c 741 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
3ff6e0d8 742 VPLL_LOCK, VPLL_CON0, NULL),
8dac3530
YSB		 743};
744
d7cc4c81
TA		 745#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \
746 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
747 ((periph) << 12) | ((acp) << 8) | ((cpud) << 4)))
748#define E5250_CPU_DIV1(hpm, copy) \
749 (((hpm) << 4) | (copy))
750
751static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
752 { 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
753 { 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
754 { 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
755 { 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
756 { 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
757 { 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
758 { 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
759 { 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
760 { 900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
761 { 800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
762 { 700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
763 { 600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
764 { 500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
765 { 400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
766 { 300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
767 { 200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
768 { 0 },
769};
770
305cfab0 771static const struct of_device_id ext_clk_match[] __initconst = {
6e3ad268
TA		 772 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
773 { },
774};
775
776/* register exynox5250 clocks */
b95e71c6 777static void __init exynos5250_clk_init(struct device_node *np)
6e3ad268 778{
976face4 779 struct samsung_clk_provider *ctx;
9a8f3995 780 unsigned int tmp;
976face4 781
6e3ad268
TA		 782 if (np) {
783 reg_base = of_iomap(np, 0);
784 if (!reg_base)
785 panic("%s: failed to map registers\n", __func__);
786 } else {
787 panic("%s: unable to determine soc\n", __func__);
788 }
789
976face4 790 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
dfb86ade 791
976face4 792 samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
6e3ad268
TA		 793 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
794 ext_clk_match);
976face4 795 samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
8bc2eeb8 796 ARRAY_SIZE(exynos5250_pll_pmux_clks));
d2127ac4 797
f521ac8b 798 if (_get_rate("fin_pll") == 24 * MHZ) {
d2127ac4 799 exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
f521ac8b
AB		 800 exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
801 }
d2127ac4 802
22e9e758 803 if (_get_rate("mout_vpllsrc") == 24 * MHZ)
d2127ac4
VS		 804 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;
805
976face4
RS		 806 samsung_clk_register_pll(ctx, exynos5250_plls,
807 ARRAY_SIZE(exynos5250_plls),
808 reg_base);
809 samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
6e3ad268 810 ARRAY_SIZE(exynos5250_fixed_rate_clks));
976face4 811 samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,
6e3ad268 812 ARRAY_SIZE(exynos5250_fixed_factor_clks));
976face4 813 samsung_clk_register_mux(ctx, exynos5250_mux_clks,
6e3ad268 814 ARRAY_SIZE(exynos5250_mux_clks));
976face4 815 samsung_clk_register_div(ctx, exynos5250_div_clks,
6e3ad268 816 ARRAY_SIZE(exynos5250_div_clks));
976face4 817 samsung_clk_register_gate(ctx, exynos5250_gate_clks,
6e3ad268 818 ARRAY_SIZE(exynos5250_gate_clks));
d7cc4c81
TA		 819 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
820 mout_cpu_p[0], mout_cpu_p[1], 0x200,
821 exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
822 CLK_CPU_HAS_DIV1);
6e3ad268 823
9a8f3995
ADK		 824 /*
825 * Enable arm clock down (in idle) and set arm divider
826 * ratios in WFI/WFE state.
827 */
828 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
829 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
830 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
831 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
832 __raw_writel(tmp, reg_base + PWR_CTRL1);
833
834 /*
835 * Enable arm clock up (on exiting idle). Set arm divider
836 * ratios when not in idle along with the standby duration
837 * ratios.
838 */
839 tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
840 PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
841 PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
842 __raw_writel(tmp, reg_base + PWR_CTRL2);
843
c41b0ff2
MS		 844 samsung_clk_sleep_init(reg_base, exynos5250_clk_regs,
845 ARRAY_SIZE(exynos5250_clk_regs));
edcefb96 846 exynos5_subcmus_init(ctx, 1, &exynos5250_disp_subcmu);
c3b6c1d7 847
d5e136a2
SN		 848 samsung_clk_of_add_provider(np, ctx);
849
6e3ad268 850 pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
38ee3754 851 _get_rate("div_arm2"));
6e3ad268 852}
edcefb96 853CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
Ubuntu Hirsute Linux kernel mirror