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clk: samsung: exynos5433: Add clocks for CMU_HEVC domain
[mirror_ubuntu-hirsute-kernel.git] / drivers / clk / samsung / clk-exynos5433.c
CommitLineData
96bd6224
CC		 1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos5443 SoC.
10 */
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of.h>
16
17#include <dt-bindings/clock/exynos5433.h>
18
19#include "clk.h"
20#include "clk-pll.h"
21
22/*
23 * Register offset definitions for CMU_TOP
24 */
25#define ISP_PLL_LOCK 0x0000
26#define AUD_PLL_LOCK 0x0004
27#define ISP_PLL_CON0 0x0100
28#define ISP_PLL_CON1 0x0104
29#define ISP_PLL_FREQ_DET 0x0108
30#define AUD_PLL_CON0 0x0110
31#define AUD_PLL_CON1 0x0114
32#define AUD_PLL_CON2 0x0118
33#define AUD_PLL_FREQ_DET 0x011c
34#define MUX_SEL_TOP0 0x0200
35#define MUX_SEL_TOP1 0x0204
36#define MUX_SEL_TOP2 0x0208
37#define MUX_SEL_TOP3 0x020c
38#define MUX_SEL_TOP4 0x0210
39#define MUX_SEL_TOP_MSCL 0x0220
40#define MUX_SEL_TOP_CAM1 0x0224
41#define MUX_SEL_TOP_DISP 0x0228
42#define MUX_SEL_TOP_FSYS0 0x0230
43#define MUX_SEL_TOP_FSYS1 0x0234
44#define MUX_SEL_TOP_PERIC0 0x0238
45#define MUX_SEL_TOP_PERIC1 0x023c
46#define MUX_ENABLE_TOP0 0x0300
47#define MUX_ENABLE_TOP1 0x0304
48#define MUX_ENABLE_TOP2 0x0308
49#define MUX_ENABLE_TOP3 0x030c
50#define MUX_ENABLE_TOP4 0x0310
51#define MUX_ENABLE_TOP_MSCL 0x0320
52#define MUX_ENABLE_TOP_CAM1 0x0324
53#define MUX_ENABLE_TOP_DISP 0x0328
54#define MUX_ENABLE_TOP_FSYS0 0x0330
55#define MUX_ENABLE_TOP_FSYS1 0x0334
56#define MUX_ENABLE_TOP_PERIC0 0x0338
57#define MUX_ENABLE_TOP_PERIC1 0x033c
58#define MUX_STAT_TOP0 0x0400
59#define MUX_STAT_TOP1 0x0404
60#define MUX_STAT_TOP2 0x0408
61#define MUX_STAT_TOP3 0x040c
62#define MUX_STAT_TOP4 0x0410
63#define MUX_STAT_TOP_MSCL 0x0420
64#define MUX_STAT_TOP_CAM1 0x0424
65#define MUX_STAT_TOP_FSYS0 0x0430
66#define MUX_STAT_TOP_FSYS1 0x0434
67#define MUX_STAT_TOP_PERIC0 0x0438
68#define MUX_STAT_TOP_PERIC1 0x043c
69#define DIV_TOP0 0x0600
70#define DIV_TOP1 0x0604
71#define DIV_TOP2 0x0608
72#define DIV_TOP3 0x060c
73#define DIV_TOP4 0x0610
74#define DIV_TOP_MSCL 0x0618
75#define DIV_TOP_CAM10 0x061c
76#define DIV_TOP_CAM11 0x0620
77#define DIV_TOP_FSYS0 0x062c
78#define DIV_TOP_FSYS1 0x0630
79#define DIV_TOP_FSYS2 0x0634
80#define DIV_TOP_PERIC0 0x0638
81#define DIV_TOP_PERIC1 0x063c
82#define DIV_TOP_PERIC2 0x0640
83#define DIV_TOP_PERIC3 0x0644
84#define DIV_TOP_PERIC4 0x0648
85#define DIV_TOP_PLL_FREQ_DET 0x064c
86#define DIV_STAT_TOP0 0x0700
87#define DIV_STAT_TOP1 0x0704
88#define DIV_STAT_TOP2 0x0708
89#define DIV_STAT_TOP3 0x070c
90#define DIV_STAT_TOP4 0x0710
91#define DIV_STAT_TOP_MSCL 0x0718
92#define DIV_STAT_TOP_CAM10 0x071c
93#define DIV_STAT_TOP_CAM11 0x0720
94#define DIV_STAT_TOP_FSYS0 0x072c
95#define DIV_STAT_TOP_FSYS1 0x0730
96#define DIV_STAT_TOP_FSYS2 0x0734
97#define DIV_STAT_TOP_PERIC0 0x0738
98#define DIV_STAT_TOP_PERIC1 0x073c
99#define DIV_STAT_TOP_PERIC2 0x0740
100#define DIV_STAT_TOP_PERIC3 0x0744
101#define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
102#define ENABLE_ACLK_TOP 0x0800
103#define ENABLE_SCLK_TOP 0x0a00
104#define ENABLE_SCLK_TOP_MSCL 0x0a04
105#define ENABLE_SCLK_TOP_CAM1 0x0a08
106#define ENABLE_SCLK_TOP_DISP 0x0a0c
107#define ENABLE_SCLK_TOP_FSYS 0x0a10
108#define ENABLE_SCLK_TOP_PERIC 0x0a14
109#define ENABLE_IP_TOP 0x0b00
110#define ENABLE_CMU_TOP 0x0c00
111#define ENABLE_CMU_TOP_DIV_STAT 0x0c04
112
113static unsigned long top_clk_regs[] __initdata = {
114 ISP_PLL_LOCK,
115 AUD_PLL_LOCK,
116 ISP_PLL_CON0,
117 ISP_PLL_CON1,
118 ISP_PLL_FREQ_DET,
119 AUD_PLL_CON0,
120 AUD_PLL_CON1,
121 AUD_PLL_CON2,
122 AUD_PLL_FREQ_DET,
123 MUX_SEL_TOP0,
124 MUX_SEL_TOP1,
125 MUX_SEL_TOP2,
126 MUX_SEL_TOP3,
127 MUX_SEL_TOP4,
128 MUX_SEL_TOP_MSCL,
129 MUX_SEL_TOP_CAM1,
130 MUX_SEL_TOP_DISP,
131 MUX_SEL_TOP_FSYS0,
132 MUX_SEL_TOP_FSYS1,
133 MUX_SEL_TOP_PERIC0,
134 MUX_SEL_TOP_PERIC1,
135 MUX_ENABLE_TOP0,
136 MUX_ENABLE_TOP1,
137 MUX_ENABLE_TOP2,
138 MUX_ENABLE_TOP3,
139 MUX_ENABLE_TOP4,
140 MUX_ENABLE_TOP_MSCL,
141 MUX_ENABLE_TOP_CAM1,
142 MUX_ENABLE_TOP_DISP,
143 MUX_ENABLE_TOP_FSYS0,
144 MUX_ENABLE_TOP_FSYS1,
145 MUX_ENABLE_TOP_PERIC0,
146 MUX_ENABLE_TOP_PERIC1,
147 MUX_STAT_TOP0,
148 MUX_STAT_TOP1,
149 MUX_STAT_TOP2,
150 MUX_STAT_TOP3,
151 MUX_STAT_TOP4,
152 MUX_STAT_TOP_MSCL,
153 MUX_STAT_TOP_CAM1,
154 MUX_STAT_TOP_FSYS0,
155 MUX_STAT_TOP_FSYS1,
156 MUX_STAT_TOP_PERIC0,
157 MUX_STAT_TOP_PERIC1,
158 DIV_TOP0,
159 DIV_TOP1,
160 DIV_TOP2,
161 DIV_TOP3,
162 DIV_TOP4,
163 DIV_TOP_MSCL,
164 DIV_TOP_CAM10,
165 DIV_TOP_CAM11,
166 DIV_TOP_FSYS0,
167 DIV_TOP_FSYS1,
168 DIV_TOP_FSYS2,
169 DIV_TOP_PERIC0,
170 DIV_TOP_PERIC1,
171 DIV_TOP_PERIC2,
172 DIV_TOP_PERIC3,
173 DIV_TOP_PERIC4,
174 DIV_TOP_PLL_FREQ_DET,
175 DIV_STAT_TOP0,
176 DIV_STAT_TOP1,
177 DIV_STAT_TOP2,
178 DIV_STAT_TOP3,
179 DIV_STAT_TOP4,
180 DIV_STAT_TOP_MSCL,
181 DIV_STAT_TOP_CAM10,
182 DIV_STAT_TOP_CAM11,
183 DIV_STAT_TOP_FSYS0,
184 DIV_STAT_TOP_FSYS1,
185 DIV_STAT_TOP_FSYS2,
186 DIV_STAT_TOP_PERIC0,
187 DIV_STAT_TOP_PERIC1,
188 DIV_STAT_TOP_PERIC2,
189 DIV_STAT_TOP_PERIC3,
190 DIV_STAT_TOP_PLL_FREQ_DET,
191 ENABLE_ACLK_TOP,
192 ENABLE_SCLK_TOP,
193 ENABLE_SCLK_TOP_MSCL,
194 ENABLE_SCLK_TOP_CAM1,
195 ENABLE_SCLK_TOP_DISP,
196 ENABLE_SCLK_TOP_FSYS,
197 ENABLE_SCLK_TOP_PERIC,
198 ENABLE_IP_TOP,
199 ENABLE_CMU_TOP,
200 ENABLE_CMU_TOP_DIV_STAT,
201};
202
203/* list of all parent clock list */
204PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
205PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
206PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
207PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
208PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
209PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
210PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
23236496 211PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
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CC		 212
213PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
214PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
215PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
216 "mout_mfc_pll_user", };
217PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
218
23236496
CC		 219PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
220 "mout_mphy_pll_user", };
221PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
222 "mout_bus_pll_user", };
223PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
224
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CC		 225PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
226 "mout_mphy_pll_user", };
227PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
228 "mout_mphy_pll_user", };
229PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a",
230 "mout_mphy_pll_user", };
231
232PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
233PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
234
235PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
236PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
237PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
238PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
239PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
240
23236496
CC		 241PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
242 "oscclk", "ioclk_spdif_extclk", };
243PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
244 "mout_aud_pll_user_t",};
245PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
246 "mout_aud_pll_user_t",};
247
2a1808a6
CC		 248PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
249
56bcf3f3
CC		 250static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
251 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
252};
253
23236496
CC		 254static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
255 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
256 FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000),
257 FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),
258 /* Xi2s1SDI input clock for SPDIF */
259 FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000),
d0f5de66
CC		 260 /* XspiCLK[4:0] input clock for SPI */
261 FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000),
262 FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000),
263 FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000),
264 FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000),
265 FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000),
266 /* Xi2s1SCLK input clock for I2S1_BCLK */
267 FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000),
23236496
CC		 268};
269
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CC		 270static struct samsung_mux_clock top_mux_clks[] __initdata = {
271 /* MUX_SEL_TOP0 */
272 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
273 4, 1),
274 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
275 0, 1),
276
277 /* MUX_SEL_TOP1 */
278 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
279 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
280 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
281 MUX_SEL_TOP1, 8, 1),
282 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
283 MUX_SEL_TOP1, 4, 1),
284 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
285 MUX_SEL_TOP1, 0, 1),
286
287 /* MUX_SEL_TOP2 */
288 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
289 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
290 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
291 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
292 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
293 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
294 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
295 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
296 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
297 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
298 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
299 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
300
301 /* MUX_SEL_TOP3 */
302 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
303 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
304 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
305 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
306 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
307 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
308 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
309 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
310 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
311 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
312 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
313 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
314
23236496
CC		 315 /* MUX_SEL_TOP4 */
316 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
317 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
318 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
319 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
320 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
321 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
322
96bd6224
CC		 323 /* MUX_SEL_TOP_MSCL */
324 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
325 MUX_SEL_TOP_MSCL, 8, 1),
326 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
327 MUX_SEL_TOP_MSCL, 4, 1),
328 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
329 MUX_SEL_TOP_MSCL, 0, 1),
330
23236496
CC		 331 /* MUX_SEL_TOP_CAM1 */
332 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
333 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
334 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
335 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
336 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
337 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
338 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
339 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
340 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
341 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
342 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
343 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
344
96bd6224
CC		 345 /* MUX_SEL_TOP_FSYS0 */
346 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
347 MUX_SEL_TOP_FSYS0, 28, 1),
348 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
349 MUX_SEL_TOP_FSYS0, 24, 1),
350 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
351 MUX_SEL_TOP_FSYS0, 20, 1),
352 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
353 MUX_SEL_TOP_FSYS0, 16, 1),
354 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
355 MUX_SEL_TOP_FSYS0, 12, 1),
356 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
357 MUX_SEL_TOP_FSYS0, 8, 1),
358 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
359 MUX_SEL_TOP_FSYS0, 4, 1),
360 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
361 MUX_SEL_TOP_FSYS0, 0, 1),
362
23236496
CC		 363 /* MUX_SEL_TOP_FSYS1 */
364 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
365 MUX_SEL_TOP_FSYS1, 12, 1),
366 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
367 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
368 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
369 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
370 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
371 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
372
96bd6224
CC		 373 /* MUX_SEL_TOP_PERIC0 */
374 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
375 MUX_SEL_TOP_PERIC0, 28, 1),
376 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
377 MUX_SEL_TOP_PERIC0, 24, 1),
378 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
379 MUX_SEL_TOP_PERIC0, 20, 1),
380 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
381 MUX_SEL_TOP_PERIC0, 16, 1),
382 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
383 MUX_SEL_TOP_PERIC0, 12, 1),
384 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
385 MUX_SEL_TOP_PERIC0, 8, 1),
386 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
387 MUX_SEL_TOP_PERIC0, 4, 1),
388 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
389 MUX_SEL_TOP_PERIC0, 0, 1),
23236496
CC		 390
391 /* MUX_SEL_TOP_PERIC1 */
392 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
393 MUX_SEL_TOP_PERIC1, 16, 1),
394 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
395 MUX_SEL_TOP_PERIC1, 12, 2),
396 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
397 MUX_SEL_TOP_PERIC1, 4, 2),
398 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
399 MUX_SEL_TOP_PERIC1, 0, 2),
2a1808a6
CC		 400
401 /* MUX_SEL_TOP_DISP */
402 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
403 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
96bd6224
CC		 404};
405
406static struct samsung_div_clock top_div_clks[] __initdata = {
a29308da
CC		 407 /* DIV_TOP1 */
408 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
409 DIV_TOP1, 28, 3),
410 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
411 DIV_TOP1, 24, 3),
412 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
413 DIV_TOP1, 20, 3),
414 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
415 DIV_TOP1, 12, 3),
416 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
417 DIV_TOP1, 8, 3),
418 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
419 DIV_TOP1, 0, 3),
420
96bd6224 421 /* DIV_TOP2 */
b274bbfd
CC		 422 DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
423 DIV_TOP2, 4, 3),
96bd6224
CC		 424 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
425 DIV_TOP2, 0, 3),
426
427 /* DIV_TOP3 */
428 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
429 "mout_bus_pll_user", DIV_TOP3, 24, 3),
430 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
431 "mout_bus_pll_user", DIV_TOP3, 20, 3),
432 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
433 "mout_bus_pll_user", DIV_TOP3, 16, 3),
434 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
435 "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
436 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
437 "mout_bus_pll_user", DIV_TOP3, 8, 3),
438 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
439 "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
440 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
441 "mout_bus_pll_user", DIV_TOP3, 0, 3),
442
5785d6e6
CC		 443 /* DIV_TOP4 */
444 DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
445 DIV_TOP4, 8, 3),
446 DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
447 DIV_TOP4, 4, 3),
448 DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
449 DIV_TOP4, 0, 3),
450
b274bbfd
CC		 451 /* DIV_TOP_MSCL */
452 DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
453 DIV_TOP_MSCL, 0, 4),
454
96bd6224
CC		 455 /* DIV_TOP_FSYS0 */
456 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
457 DIV_TOP_FSYS0, 16, 8),
458 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
459 DIV_TOP_FSYS0, 12, 4),
460 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
461 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
462 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
463 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
464
465 /* DIV_TOP_FSYS1 */
466 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
467 DIV_TOP_FSYS1, 4, 8),
468 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
469 DIV_TOP_FSYS1, 0, 4),
470
4b801355
CC		 471 /* DIV_TOP_FSYS2 */
472 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
473 DIV_TOP_FSYS2, 12, 3),
474 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
475 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
476 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
477 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
478 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
479 DIV_TOP_FSYS2, 0, 4),
480
96bd6224
CC		 481 /* DIV_TOP_PERIC0 */
482 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
483 DIV_TOP_PERIC0, 16, 8),
484 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
485 DIV_TOP_PERIC0, 12, 4),
486 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
487 DIV_TOP_PERIC0, 4, 8),
488 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
489 DIV_TOP_PERIC0, 0, 4),
490
491 /* DIV_TOP_PERIC1 */
492 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
493 DIV_TOP_PERIC1, 4, 8),
494 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
495 DIV_TOP_PERIC1, 0, 4),
496
497 /* DIV_TOP_PERIC2 */
498 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
499 DIV_TOP_PERIC2, 8, 4),
500 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
501 DIV_TOP_PERIC2, 4, 4),
502 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
503 DIV_TOP_PERIC2, 0, 4),
504
23236496
CC		 505 /* DIV_TOP_PERIC3 */
506 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
507 DIV_TOP_PERIC3, 16, 6),
508 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
509 DIV_TOP_PERIC3, 8, 8),
510 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
511 DIV_TOP_PERIC3, 4, 4),
512 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
513 DIV_TOP_PERIC3, 0, 4),
514
96bd6224
CC		 515 /* DIV_TOP_PERIC4 */
516 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
517 DIV_TOP_PERIC4, 16, 8),
518 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
519 DIV_TOP_PERIC4, 12, 4),
520 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
521 DIV_TOP_PERIC4, 4, 8),
522 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
523 DIV_TOP_PERIC4, 0, 4),
524};
525
526static struct samsung_gate_clock top_gate_clks[] __initdata = {
527 /* ENABLE_ACLK_TOP */
5785d6e6
CC		 528 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
529 ENABLE_ACLK_TOP, 30, 0, 0),
530 GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
531 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
532 29, CLK_IGNORE_UNUSED, 0),
533 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
534 ENABLE_ACLK_TOP, 26,
535 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
536 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
537 ENABLE_ACLK_TOP, 25,
538 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
539 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
540 ENABLE_ACLK_TOP, 24,
541 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
542 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
543 ENABLE_ACLK_TOP, 23,
544 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
96bd6224
CC		 545 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
546 ENABLE_ACLK_TOP, 22,
547 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
548 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
549 ENABLE_ACLK_TOP, 21,
550 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
b274bbfd
CC		 551 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
552 ENABLE_ACLK_TOP, 19,
553 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
96bd6224
CC		 554 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
555 ENABLE_ACLK_TOP, 18,
556 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
2a2f33e8
CC		 557 GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
558 ENABLE_ACLK_TOP, 15,
559 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
560 GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
561 ENABLE_ACLK_TOP, 14,
562 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
45e58aa5
CC		 563 GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
564 ENABLE_ACLK_TOP, 5,
565 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
9910b6bb
CC		 566 GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
567 ENABLE_ACLK_TOP, 3,
568 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
a29308da
CC		 569 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
570 ENABLE_ACLK_TOP, 2,
571 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
572 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
573 ENABLE_ACLK_TOP, 0,
574 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
96bd6224 575
b274bbfd
CC		 576 /* ENABLE_SCLK_TOP_MSCL */
577 GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
578 ENABLE_SCLK_TOP_MSCL, 0, 0, 0),
579
96bd6224 580 /* ENABLE_SCLK_TOP_FSYS */
4b801355
CC		 581 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
582 ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
96bd6224
CC		 583 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
584 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
585 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
586 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
587 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
588 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
4b801355
CC		 589 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
590 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
591 3, CLK_SET_RATE_PARENT, 0),
592 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
593 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
594 1, CLK_SET_RATE_PARENT, 0),
595 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
596 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
597 0, CLK_SET_RATE_PARENT, 0),
96bd6224
CC		 598
599 /* ENABLE_SCLK_TOP_PERIC */
600 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
601 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
602 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
603 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
23236496
CC		 604 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
605 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
606 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
607 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
608 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
609 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
96bd6224
CC		 610 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
611 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0),
612 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
613 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0),
614 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
615 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0),
616 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
617 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
618 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
619 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
620 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
621 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
23236496
CC		 622
623 /* MUX_ENABLE_TOP_PERIC1 */
624 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
625 MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
626 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
627 MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
628 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
629 MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
96bd6224
CC		 630};
631
632/*
633 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
634 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
635 */
636static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
637 PLL_35XX_RATE(2500000000U, 625, 6, 0),
638 PLL_35XX_RATE(2400000000U, 500, 5, 0),
639 PLL_35XX_RATE(2300000000U, 575, 6, 0),
640 PLL_35XX_RATE(2200000000U, 550, 6, 0),
641 PLL_35XX_RATE(2100000000U, 350, 4, 0),
642 PLL_35XX_RATE(2000000000U, 500, 6, 0),
643 PLL_35XX_RATE(1900000000U, 475, 6, 0),
644 PLL_35XX_RATE(1800000000U, 375, 5, 0),
645 PLL_35XX_RATE(1700000000U, 425, 6, 0),
646 PLL_35XX_RATE(1600000000U, 400, 6, 0),
647 PLL_35XX_RATE(1500000000U, 250, 4, 0),
648 PLL_35XX_RATE(1400000000U, 350, 6, 0),
649 PLL_35XX_RATE(1332000000U, 222, 4, 0),
650 PLL_35XX_RATE(1300000000U, 325, 6, 0),
651 PLL_35XX_RATE(1200000000U, 500, 5, 1),
652 PLL_35XX_RATE(1100000000U, 550, 6, 1),
653 PLL_35XX_RATE(1086000000U, 362, 4, 1),
654 PLL_35XX_RATE(1066000000U, 533, 6, 1),
655 PLL_35XX_RATE(1000000000U, 500, 6, 1),
656 PLL_35XX_RATE(933000000U, 311, 4, 1),
657 PLL_35XX_RATE(921000000U, 307, 4, 1),
658 PLL_35XX_RATE(900000000U, 375, 5, 1),
659 PLL_35XX_RATE(825000000U, 275, 4, 1),
660 PLL_35XX_RATE(800000000U, 400, 6, 1),
661 PLL_35XX_RATE(733000000U, 733, 12, 1),
662 PLL_35XX_RATE(700000000U, 360, 6, 1),
663 PLL_35XX_RATE(667000000U, 222, 4, 1),
664 PLL_35XX_RATE(633000000U, 211, 4, 1),
665 PLL_35XX_RATE(600000000U, 500, 5, 2),
666 PLL_35XX_RATE(552000000U, 460, 5, 2),
667 PLL_35XX_RATE(550000000U, 550, 6, 2),
668 PLL_35XX_RATE(543000000U, 362, 4, 2),
669 PLL_35XX_RATE(533000000U, 533, 6, 2),
670 PLL_35XX_RATE(500000000U, 500, 6, 2),
671 PLL_35XX_RATE(444000000U, 370, 5, 2),
672 PLL_35XX_RATE(420000000U, 350, 5, 2),
673 PLL_35XX_RATE(400000000U, 400, 6, 2),
674 PLL_35XX_RATE(350000000U, 360, 6, 2),
675 PLL_35XX_RATE(333000000U, 222, 4, 2),
676 PLL_35XX_RATE(300000000U, 500, 5, 3),
677 PLL_35XX_RATE(266000000U, 532, 6, 3),
678 PLL_35XX_RATE(200000000U, 400, 6, 3),
679 PLL_35XX_RATE(166000000U, 332, 6, 3),
680 PLL_35XX_RATE(160000000U, 320, 6, 3),
681 PLL_35XX_RATE(133000000U, 552, 6, 4),
682 PLL_35XX_RATE(100000000U, 400, 6, 4),
683 { /* sentinel */ }
684};
685
686/* AUD_PLL */
687static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
688 PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
689 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
690 PLL_36XX_RATE(384000000U, 128, 2, 2, 0),
691 PLL_36XX_RATE(368640000U, 246, 4, 2, -15729),
692 PLL_36XX_RATE(361507200U, 181, 3, 2, -16148),
693 PLL_36XX_RATE(338688000U, 113, 2, 2, -6816),
694 PLL_36XX_RATE(294912000U, 98, 1, 3, 19923),
695 PLL_36XX_RATE(288000000U, 96, 1, 3, 0),
696 PLL_36XX_RATE(252000000U, 84, 1, 3, 0),
697 { /* sentinel */ }
698};
699
700static struct samsung_pll_clock top_pll_clks[] __initdata = {
701 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
702 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
703 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
704 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
705};
706
707static struct samsung_cmu_info top_cmu_info __initdata = {
708 .pll_clks = top_pll_clks,
709 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
710 .mux_clks = top_mux_clks,
711 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
712 .div_clks = top_div_clks,
713 .nr_div_clks = ARRAY_SIZE(top_div_clks),
714 .gate_clks = top_gate_clks,
715 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
23236496
CC		 716 .fixed_clks = top_fixed_clks,
717 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
56bcf3f3
CC		 718 .fixed_factor_clks = top_fixed_factor_clks,
719 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
96bd6224
CC		 720 .nr_clk_ids = TOP_NR_CLK,
721 .clk_regs = top_clk_regs,
722 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
723};
724
725static void __init exynos5433_cmu_top_init(struct device_node *np)
726{
727 samsung_cmu_register_one(np, &top_cmu_info);
728}
729CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
730 exynos5433_cmu_top_init);
731
732/*
733 * Register offset definitions for CMU_CPIF
734 */
735#define MPHY_PLL_LOCK 0x0000
736#define MPHY_PLL_CON0 0x0100
737#define MPHY_PLL_CON1 0x0104
738#define MPHY_PLL_FREQ_DET 0x010c
739#define MUX_SEL_CPIF0 0x0200
740#define DIV_CPIF 0x0600
741#define ENABLE_SCLK_CPIF 0x0a00
742
743static unsigned long cpif_clk_regs[] __initdata = {
744 MPHY_PLL_LOCK,
745 MPHY_PLL_CON0,
746 MPHY_PLL_CON1,
747 MPHY_PLL_FREQ_DET,
748 MUX_SEL_CPIF0,
749 ENABLE_SCLK_CPIF,
750};
751
752/* list of all parent clock list */
753PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
754
755static struct samsung_pll_clock cpif_pll_clks[] __initdata = {
756 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
757 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
758};
759
760static struct samsung_mux_clock cpif_mux_clks[] __initdata = {
761 /* MUX_SEL_CPIF0 */
762 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
763 0, 1),
764};
765
766static struct samsung_div_clock cpif_div_clks[] __initdata = {
767 /* DIV_CPIF */
768 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
769 0, 6),
770};
771
772static struct samsung_gate_clock cpif_gate_clks[] __initdata = {
773 /* ENABLE_SCLK_CPIF */
774 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
775 ENABLE_SCLK_CPIF, 9, 0, 0),
776 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
777 ENABLE_SCLK_CPIF, 4, 0, 0),
778};
779
780static struct samsung_cmu_info cpif_cmu_info __initdata = {
781 .pll_clks = cpif_pll_clks,
782 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
783 .mux_clks = cpif_mux_clks,
784 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks),
785 .div_clks = cpif_div_clks,
786 .nr_div_clks = ARRAY_SIZE(cpif_div_clks),
787 .gate_clks = cpif_gate_clks,
788 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
789 .nr_clk_ids = CPIF_NR_CLK,
790 .clk_regs = cpif_clk_regs,
791 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
792};
793
794static void __init exynos5433_cmu_cpif_init(struct device_node *np)
795{
796 samsung_cmu_register_one(np, &cpif_cmu_info);
797}
798CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
799 exynos5433_cmu_cpif_init);
800
801/*
802 * Register offset definitions for CMU_MIF
803 */
804#define MEM0_PLL_LOCK 0x0000
805#define MEM1_PLL_LOCK 0x0004
806#define BUS_PLL_LOCK 0x0008
807#define MFC_PLL_LOCK 0x000c
808#define MEM0_PLL_CON0 0x0100
809#define MEM0_PLL_CON1 0x0104
810#define MEM0_PLL_FREQ_DET 0x010c
811#define MEM1_PLL_CON0 0x0110
812#define MEM1_PLL_CON1 0x0114
813#define MEM1_PLL_FREQ_DET 0x011c
814#define BUS_PLL_CON0 0x0120
815#define BUS_PLL_CON1 0x0124
816#define BUS_PLL_FREQ_DET 0x012c
817#define MFC_PLL_CON0 0x0130
818#define MFC_PLL_CON1 0x0134
819#define MFC_PLL_FREQ_DET 0x013c
06d2f9df
CC		 820#define MUX_SEL_MIF0 0x0200
821#define MUX_SEL_MIF1 0x0204
822#define MUX_SEL_MIF2 0x0208
823#define MUX_SEL_MIF3 0x020c
824#define MUX_SEL_MIF4 0x0210
825#define MUX_SEL_MIF5 0x0214
826#define MUX_SEL_MIF6 0x0218
827#define MUX_SEL_MIF7 0x021c
828#define MUX_ENABLE_MIF0 0x0300
829#define MUX_ENABLE_MIF1 0x0304
830#define MUX_ENABLE_MIF2 0x0308
831#define MUX_ENABLE_MIF3 0x030c
832#define MUX_ENABLE_MIF4 0x0310
833#define MUX_ENABLE_MIF5 0x0314
834#define MUX_ENABLE_MIF6 0x0318
835#define MUX_ENABLE_MIF7 0x031c
836#define MUX_STAT_MIF0 0x0400
837#define MUX_STAT_MIF1 0x0404
838#define MUX_STAT_MIF2 0x0408
839#define MUX_STAT_MIF3 0x040c
840#define MUX_STAT_MIF4 0x0410
841#define MUX_STAT_MIF5 0x0414
842#define MUX_STAT_MIF6 0x0418
843#define MUX_STAT_MIF7 0x041c
844#define DIV_MIF1 0x0604
845#define DIV_MIF2 0x0608
846#define DIV_MIF3 0x060c
847#define DIV_MIF4 0x0610
848#define DIV_MIF5 0x0614
849#define DIV_MIF_PLL_FREQ_DET 0x0618
850#define DIV_STAT_MIF1 0x0704
851#define DIV_STAT_MIF2 0x0708
852#define DIV_STAT_MIF3 0x070c
853#define DIV_STAT_MIF4 0x0710
854#define DIV_STAT_MIF5 0x0714
855#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
856#define ENABLE_ACLK_MIF0 0x0800
857#define ENABLE_ACLK_MIF1 0x0804
858#define ENABLE_ACLK_MIF2 0x0808
859#define ENABLE_ACLK_MIF3 0x080c
860#define ENABLE_PCLK_MIF 0x0900
861#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
862#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
863#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
864#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
865#define ENABLE_SCLK_MIF 0x0a00
866#define ENABLE_IP_MIF0 0x0b00
867#define ENABLE_IP_MIF1 0x0b04
868#define ENABLE_IP_MIF2 0x0b08
869#define ENABLE_IP_MIF3 0x0b0c
870#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
871#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
872#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
873#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
874#define CLKOUT_CMU_MIF 0x0c00
875#define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
876#define DREX_FREQ_CTRL0 0x1000
877#define DREX_FREQ_CTRL1 0x1004
878#define PAUSE 0x1008
879#define DDRPHY_LOCK_CTRL 0x100c
96bd6224
CC		 880
881static unsigned long mif_clk_regs[] __initdata = {
882 MEM0_PLL_LOCK,
883 MEM1_PLL_LOCK,
884 BUS_PLL_LOCK,
885 MFC_PLL_LOCK,
886 MEM0_PLL_CON0,
887 MEM0_PLL_CON1,
888 MEM0_PLL_FREQ_DET,
889 MEM1_PLL_CON0,
890 MEM1_PLL_CON1,
891 MEM1_PLL_FREQ_DET,
892 BUS_PLL_CON0,
893 BUS_PLL_CON1,
894 BUS_PLL_FREQ_DET,
895 MFC_PLL_CON0,
896 MFC_PLL_CON1,
897 MFC_PLL_FREQ_DET,
06d2f9df
CC		 898 MUX_SEL_MIF0,
899 MUX_SEL_MIF1,
900 MUX_SEL_MIF2,
901 MUX_SEL_MIF3,
902 MUX_SEL_MIF4,
903 MUX_SEL_MIF5,
904 MUX_SEL_MIF6,
905 MUX_SEL_MIF7,
906 MUX_ENABLE_MIF0,
907 MUX_ENABLE_MIF1,
908 MUX_ENABLE_MIF2,
909 MUX_ENABLE_MIF3,
910 MUX_ENABLE_MIF4,
911 MUX_ENABLE_MIF5,
912 MUX_ENABLE_MIF6,
913 MUX_ENABLE_MIF7,
914 MUX_STAT_MIF0,
915 MUX_STAT_MIF1,
916 MUX_STAT_MIF2,
917 MUX_STAT_MIF3,
918 MUX_STAT_MIF4,
919 MUX_STAT_MIF5,
920 MUX_STAT_MIF6,
921 MUX_STAT_MIF7,
922 DIV_MIF1,
923 DIV_MIF2,
924 DIV_MIF3,
925 DIV_MIF4,
926 DIV_MIF5,
927 DIV_MIF_PLL_FREQ_DET,
928 DIV_STAT_MIF1,
929 DIV_STAT_MIF2,
930 DIV_STAT_MIF3,
931 DIV_STAT_MIF4,
932 DIV_STAT_MIF5,
933 DIV_STAT_MIF_PLL_FREQ_DET,
934 ENABLE_ACLK_MIF0,
935 ENABLE_ACLK_MIF1,
936 ENABLE_ACLK_MIF2,
937 ENABLE_ACLK_MIF3,
938 ENABLE_PCLK_MIF,
939 ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
940 ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
941 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
942 ENABLE_PCLK_MIF_SECURE_RTC,
943 ENABLE_SCLK_MIF,
944 ENABLE_IP_MIF0,
945 ENABLE_IP_MIF1,
946 ENABLE_IP_MIF2,
947 ENABLE_IP_MIF3,
948 ENABLE_IP_MIF_SECURE_DREX0_TZ,
949 ENABLE_IP_MIF_SECURE_DREX1_TZ,
950 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
951 ENABLE_IP_MIF_SECURE_RTC,
952 CLKOUT_CMU_MIF,
953 CLKOUT_CMU_MIF_DIV_STAT,
954 DREX_FREQ_CTRL0,
955 DREX_FREQ_CTRL1,
956 PAUSE,
957 DDRPHY_LOCK_CTRL,
96bd6224
CC		 958};
959
960static struct samsung_pll_clock mif_pll_clks[] __initdata = {
961 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
962 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
963 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
964 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates),
965 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
966 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates),
967 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
968 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
969};
970
06d2f9df
CC		 971/* list of all parent clock list */
972PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", };
973PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", };
974PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
975PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
976PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", };
977PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", };
978PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", };
979PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", };
980
981PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
982PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
983PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
984PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
985
986PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", };
987PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
988
989PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a",
990 "mout_bus_pll_div2", };
991PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
992
993PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
994 "sclk_mphy_pll", };
995PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
996 "mout_mfc_pll_div2", };
997PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", };
998PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
999 "sclk_mphy_pll", };
1000PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
1001 "mout_mfc_pll_div2", };
1002
1003PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
1004 "sclk_mphy_pll", };
1005PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
1006 "mout_mfc_pll_div2", };
1007PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1008PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1009PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", };
1010
1011PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1012PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1013
1014PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
1015 "sclk_mphy_pll", };
1016PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1017 "mout_mfc_pll_div2", };
1018PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1019PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1020
1021static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = {
1022 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1023 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1024 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1025 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1026 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1027};
1028
1029static struct samsung_mux_clock mif_mux_clks[] __initdata = {
1030 /* MUX_SEL_MIF0 */
1031 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1032 MUX_SEL_MIF0, 28, 1),
1033 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
1034 MUX_SEL_MIF0, 24, 1),
1035 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
1036 MUX_SEL_MIF0, 20, 1),
1037 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
1038 MUX_SEL_MIF0, 16, 1),
1039 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
1040 12, 1),
1041 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
1042 8, 1),
1043 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
1044 4, 1),
1045 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
1046 0, 1),
1047
1048 /* MUX_SEL_MIF1 */
1049 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
1050 MUX_SEL_MIF1, 24, 1),
1051 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
1052 MUX_SEL_MIF1, 20, 1),
1053 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
1054 MUX_SEL_MIF1, 16, 1),
1055 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
1056 MUX_SEL_MIF1, 12, 1),
1057 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
1058 MUX_SEL_MIF1, 8, 1),
1059 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
1060 MUX_SEL_MIF1, 4, 1),
1061
1062 /* MUX_SEL_MIF2 */
1063 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
1064 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
1065 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
1066 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1067
1068 /* MUX_SEL_MIF3 */
1069 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
1070 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
1071 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
1072 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1073
1074 /* MUX_SEL_MIF4 */
1075 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
1076 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1077 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1078 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1079 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1080 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1081 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1082 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1083 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1084 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1085 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1086 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1087
1088 /* MUX_SEL_MIF5 */
1089 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1090 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1091 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1092 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1093 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1094 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1095 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1096 MUX_SEL_MIF5, 8, 1),
1097 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1098 MUX_SEL_MIF5, 4, 1),
1099 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1100 MUX_SEL_MIF5, 0, 1),
1101
1102 /* MUX_SEL_MIF6 */
1103 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1104 MUX_SEL_MIF6, 8, 1),
1105 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1106 MUX_SEL_MIF6, 4, 1),
1107 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1108 MUX_SEL_MIF6, 0, 1),
1109
1110 /* MUX_SEL_MIF7 */
1111 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1112 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1113 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1114 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1115 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1116 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1117 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1118 MUX_SEL_MIF7, 8, 1),
1119 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1120 MUX_SEL_MIF7, 4, 1),
1121 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1122 MUX_SEL_MIF7, 0, 1),
1123};
1124
1125static struct samsung_div_clock mif_div_clks[] __initdata = {
1126 /* DIV_MIF1 */
1127 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1128 DIV_MIF1, 16, 2),
1129 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1130 12, 2),
1131 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1132 8, 2),
1133 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1134 4, 4),
1135
1136 /* DIV_MIF2 */
1137 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1138 DIV_MIF2, 20, 3),
1139 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1140 DIV_MIF2, 16, 4),
1141 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1142 DIV_MIF2, 12, 4),
1143 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1144 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1145 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1146 DIV_MIF2, 4, 2),
1147 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1148 DIV_MIF2, 0, 3),
1149
1150 /* DIV_MIF3 */
1151 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1152 DIV_MIF3, 16, 4),
1153 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1154 DIV_MIF3, 4, 3),
1155 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1156 DIV_MIF3, 0, 3),
1157
1158 /* DIV_MIF4 */
1159 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1160 DIV_MIF4, 24, 4),
1161 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1162 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1163 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1164 DIV_MIF4, 16, 4),
1165 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1166 DIV_MIF4, 12, 4),
1167 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1168 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1169 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1170 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1171 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1172 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1173
1174 /* DIV_MIF5 */
1175 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1176 0, 3),
1177};
1178
1179static struct samsung_gate_clock mif_gate_clks[] __initdata = {
1180 /* ENABLE_ACLK_MIF0 */
1181 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1182 19, CLK_IGNORE_UNUSED, 0),
1183 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1184 18, CLK_IGNORE_UNUSED, 0),
1185 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1186 17, CLK_IGNORE_UNUSED, 0),
1187 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1188 16, CLK_IGNORE_UNUSED, 0),
1189 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1190 15, CLK_IGNORE_UNUSED, 0),
1191 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1192 14, CLK_IGNORE_UNUSED, 0),
1193 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1194 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1195 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1196 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1197 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1198 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1199 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1200 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1201 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1202 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1203 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1204 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1205 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1206 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1207 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1208 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1209 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1210 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1211 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1212 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1213 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1214 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1215 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1216 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1217 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1218 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1219 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1220 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1221
1222 /* ENABLE_ACLK_MIF1 */
1223 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1224 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1225 CLK_IGNORE_UNUSED, 0),
1226 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1227 "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1228 27, CLK_IGNORE_UNUSED, 0),
1229 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1230 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1231 26, CLK_IGNORE_UNUSED, 0),
1232 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1233 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1234 25, CLK_IGNORE_UNUSED, 0),
1235 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1236 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1237 24, CLK_IGNORE_UNUSED, 0),
1238 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1239 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1240 23, CLK_IGNORE_UNUSED, 0),
1241 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1242 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1243 22, CLK_IGNORE_UNUSED, 0),
1244 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1245 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1246 21, CLK_IGNORE_UNUSED, 0),
1247 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1248 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1249 20, CLK_IGNORE_UNUSED, 0),
1250 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1251 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1252 19, CLK_IGNORE_UNUSED, 0),
1253 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1254 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1255 18, CLK_IGNORE_UNUSED, 0),
1256 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1257 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1258 17, CLK_IGNORE_UNUSED, 0),
1259 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1260 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1261 16, CLK_IGNORE_UNUSED, 0),
1262 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1263 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1264 15, CLK_IGNORE_UNUSED, 0),
1265 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1266 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1267 14, CLK_IGNORE_UNUSED, 0),
1268 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1269 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1270 13, CLK_IGNORE_UNUSED, 0),
1271 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1272 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1273 12, CLK_IGNORE_UNUSED, 0),
1274 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1275 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1276 11, CLK_IGNORE_UNUSED, 0),
1277 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1278 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1279 10, CLK_IGNORE_UNUSED, 0),
1280 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1281 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1282 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1283 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1284 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1285 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1286 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1287 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1288 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1289 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1290 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1291 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1292 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1293 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1294 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1295 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1296 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1297 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1298 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1299 0, CLK_IGNORE_UNUSED, 0),
1300
1301 /* ENABLE_ACLK_MIF2 */
1302 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1303 ENABLE_ACLK_MIF2, 20, 0, 0),
1304 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1305 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1306 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1307 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1308 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1309 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1310 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1311 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1312 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1313 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1314 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1315 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1316 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1317 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1318 CLK_IGNORE_UNUSED, 0),
1319 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1320 "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1321 5, CLK_IGNORE_UNUSED, 0),
1322 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1323 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1324 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1325 "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1326 3, CLK_IGNORE_UNUSED, 0),
1327 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1328 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1329
1330 /* ENABLE_ACLK_MIF3 */
1331 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1332 ENABLE_ACLK_MIF3, 4,
1333 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1334 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1335 ENABLE_ACLK_MIF3, 1,
1336 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1337 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1338 ENABLE_ACLK_MIF3, 0,
1339 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1340
1341 /* ENABLE_PCLK_MIF */
1342 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1343 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1344 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1345 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1346 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1347 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1348 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1349 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1350 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1351 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1352 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1353 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1354 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1355 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1356 CLK_IGNORE_UNUSED, 0),
1357 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1358 ENABLE_PCLK_MIF, 19, 0, 0),
1359 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1360 ENABLE_PCLK_MIF, 18, 0, 0),
1361 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1362 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1363 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1364 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1365 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1366 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1367 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1368 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1369 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1370 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1371 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1372 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1373 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1374 ENABLE_PCLK_MIF, 11, 0, 0),
1375 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1376 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1377 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1378 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1379 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1380 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1381 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1382 ENABLE_PCLK_MIF, 7, 0, 0),
1383 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1384 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1385 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1386 ENABLE_PCLK_MIF, 5, 0, 0),
1387 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1388 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1389 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1390 ENABLE_PCLK_MIF, 2, 0, 0),
1391 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1392 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1393
1394 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1395 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1396 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0),
1397
1398 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1399 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1400 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0),
1401
1402 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1403 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1404 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1405
1406 /* ENABLE_PCLK_MIF_SECURE_RTC */
1407 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1408 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1409
1410 /* ENABLE_SCLK_MIF */
1411 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1412 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1413 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1414 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1415 14, CLK_IGNORE_UNUSED, 0),
1416 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1417 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1418 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1419 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1420 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1421 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1422 7, CLK_IGNORE_UNUSED, 0),
1423 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1424 "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1425 6, CLK_IGNORE_UNUSED, 0),
1426 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1427 "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1428 5, CLK_IGNORE_UNUSED, 0),
1429 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1430 ENABLE_SCLK_MIF, 4,
1431 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1432 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1433 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1434 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1435 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1436 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1437 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1438 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1439 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
2a1808a6
CC		 1440
1441 /* ENABLE_SCLK_TOP_DISP */
1442 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
1443 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
1444 CLK_IGNORE_UNUSED, 0),
06d2f9df
CC		 1445};
1446
96bd6224
CC		 1447static struct samsung_cmu_info mif_cmu_info __initdata = {
1448 .pll_clks = mif_pll_clks,
1449 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
06d2f9df
CC		 1450 .mux_clks = mif_mux_clks,
1451 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
1452 .div_clks = mif_div_clks,
1453 .nr_div_clks = ARRAY_SIZE(mif_div_clks),
1454 .gate_clks = mif_gate_clks,
1455 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
1456 .fixed_factor_clks = mif_fixed_factor_clks,
1457 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
96bd6224
CC		 1458 .nr_clk_ids = MIF_NR_CLK,
1459 .clk_regs = mif_clk_regs,
1460 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
1461};
1462
1463static void __init exynos5433_cmu_mif_init(struct device_node *np)
1464{
1465 samsung_cmu_register_one(np, &mif_cmu_info);
1466}
1467CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1468 exynos5433_cmu_mif_init);
1469
1470/*
1471 * Register offset definitions for CMU_PERIC
1472 */
1473#define DIV_PERIC 0x0600
d0f5de66 1474#define DIV_STAT_PERIC 0x0700
96bd6224
CC		 1475#define ENABLE_ACLK_PERIC 0x0800
1476#define ENABLE_PCLK_PERIC0 0x0900
1477#define ENABLE_PCLK_PERIC1 0x0904
1478#define ENABLE_SCLK_PERIC 0x0A00
1479#define ENABLE_IP_PERIC0 0x0B00
1480#define ENABLE_IP_PERIC1 0x0B04
1481#define ENABLE_IP_PERIC2 0x0B08
1482
1483static unsigned long peric_clk_regs[] __initdata = {
1484 DIV_PERIC,
d0f5de66 1485 DIV_STAT_PERIC,
96bd6224
CC		 1486 ENABLE_ACLK_PERIC,
1487 ENABLE_PCLK_PERIC0,
1488 ENABLE_PCLK_PERIC1,
1489 ENABLE_SCLK_PERIC,
1490 ENABLE_IP_PERIC0,
1491 ENABLE_IP_PERIC1,
1492 ENABLE_IP_PERIC2,
1493};
1494
d0f5de66
CC		 1495static struct samsung_div_clock peric_div_clks[] __initdata = {
1496 /* DIV_PERIC */
1497 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1498 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1499};
1500
96bd6224 1501static struct samsung_gate_clock peric_gate_clks[] __initdata = {
d0f5de66
CC		 1502 /* ENABLE_ACLK_PERIC */
1503 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1504 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1505 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1506 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1507 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1508 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1509 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1510 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1511
96bd6224 1512 /* ENABLE_PCLK_PERIC0 */
d0f5de66
CC		 1513 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1514 31, CLK_SET_RATE_PARENT, 0),
1515 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1516 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1517 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1518 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1519 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1520 28, CLK_SET_RATE_PARENT, 0),
1521 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1522 26, CLK_SET_RATE_PARENT, 0),
1523 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1524 25, CLK_SET_RATE_PARENT, 0),
1525 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1526 24, CLK_SET_RATE_PARENT, 0),
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CC		 1527 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1528 23, CLK_SET_RATE_PARENT, 0),
1529 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1530 22, CLK_SET_RATE_PARENT, 0),
1531 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1532 21, CLK_SET_RATE_PARENT, 0),
d0f5de66
CC		 1533 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1534 20, CLK_SET_RATE_PARENT, 0),
1535 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1536 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1537 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1538 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1539 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1540 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1541 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1542 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1543 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1544 ENABLE_PCLK_PERIC0, 15,
1545 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
96bd6224
CC		 1546 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1547 14, CLK_SET_RATE_PARENT, 0),
1548 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1549 13, CLK_SET_RATE_PARENT, 0),
1550 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1551 12, CLK_SET_RATE_PARENT, 0),
1552 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1553 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1554 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1555 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1556 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1557 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1558 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1559 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1560 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1561 7, CLK_SET_RATE_PARENT, 0),
1562 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1563 6, CLK_SET_RATE_PARENT, 0),
1564 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1565 5, CLK_SET_RATE_PARENT, 0),
1566 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1567 4, CLK_SET_RATE_PARENT, 0),
1568 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1569 3, CLK_SET_RATE_PARENT, 0),
1570 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1571 2, CLK_SET_RATE_PARENT, 0),
1572 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1573 1, CLK_SET_RATE_PARENT, 0),
1574 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1575 0, CLK_SET_RATE_PARENT, 0),
1576
1577 /* ENABLE_PCLK_PERIC1 */
1578 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1579 9, CLK_SET_RATE_PARENT, 0),
1580 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1581 8, CLK_SET_RATE_PARENT, 0),
1582 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1583 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1584 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1585 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1586 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1587 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1588 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1589 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1590 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1591 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1592 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1593 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1594 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1595 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1596 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1597 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1598
1599 /* ENABLE_SCLK_PERIC */
d0f5de66
CC		 1600 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1601 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1602 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1603 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
96bd6224
CC		 1604 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1605 19, CLK_SET_RATE_PARENT, 0),
1606 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1607 18, CLK_SET_RATE_PARENT, 0),
d0f5de66
CC		 1608 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1609 17, 0, 0),
1610 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1611 16, 0, 0),
1612 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1613 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1614 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1615 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1616 ENABLE_SCLK_PERIC, 12,
1617 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1618 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1619 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1620 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1621 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1622 CLK_SET_RATE_PARENT, 0),
1623 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1624 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1625 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1626 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1627 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1628 ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
96bd6224
CC		 1629 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1630 5, CLK_SET_RATE_PARENT, 0),
1631 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
d0f5de66 1632 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
96bd6224
CC		 1633 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1634 3, CLK_SET_RATE_PARENT, 0),
1635 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1636 ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
1637 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1638 ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
1639 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1640 ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
1641};
1642
1643static struct samsung_cmu_info peric_cmu_info __initdata = {
d0f5de66
CC		 1644 .div_clks = peric_div_clks,
1645 .nr_div_clks = ARRAY_SIZE(peric_div_clks),
96bd6224
CC		 1646 .gate_clks = peric_gate_clks,
1647 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
1648 .nr_clk_ids = PERIC_NR_CLK,
1649 .clk_regs = peric_clk_regs,
1650 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
1651};
1652
1653static void __init exynos5433_cmu_peric_init(struct device_node *np)
1654{
1655 samsung_cmu_register_one(np, &peric_cmu_info);
1656}
1657
1658CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1659 exynos5433_cmu_peric_init);
1660
1661/*
1662 * Register offset definitions for CMU_PERIS
1663 */
56bcf3f3
CC		 1664#define ENABLE_ACLK_PERIS 0x0800
1665#define ENABLE_PCLK_PERIS 0x0900
1666#define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
1667#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
1668#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
1669#define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
1670#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
1671#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
1672#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
1673#define ENABLE_SCLK_PERIS 0x0a00
1674#define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
1675#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
1676#define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
1677#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
1678#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
1679#define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
1680#define ENABLE_IP_PERIS0 0x0b00
1681#define ENABLE_IP_PERIS1 0x0b04
1682#define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
1683#define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
1684#define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
1685#define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
1686#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
1687#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1688#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
96bd6224
CC		 1689
1690static unsigned long peris_clk_regs[] __initdata = {
1691 ENABLE_ACLK_PERIS,
1692 ENABLE_PCLK_PERIS,
56bcf3f3
CC		 1693 ENABLE_PCLK_PERIS_SECURE_TZPC,
1694 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1695 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1696 ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1697 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1698 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1699 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1700 ENABLE_SCLK_PERIS,
1701 ENABLE_SCLK_PERIS_SECURE_SECKEY,
1702 ENABLE_SCLK_PERIS_SECURE_CHIPID,
1703 ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1704 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1705 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1706 ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1707 ENABLE_IP_PERIS0,
1708 ENABLE_IP_PERIS1,
1709 ENABLE_IP_PERIS_SECURE_TZPC,
1710 ENABLE_IP_PERIS_SECURE_SECKEY,
1711 ENABLE_IP_PERIS_SECURE_CHIPID,
1712 ENABLE_IP_PERIS_SECURE_TOPRTC,
1713 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1714 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1715 ENABLE_IP_PERIS_SECURE_OTP_CON,
96bd6224
CC		 1716};
1717
1718static struct samsung_gate_clock peris_gate_clks[] __initdata = {
56bcf3f3
CC		 1719 /* ENABLE_ACLK_PERIS */
1720 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1721 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1722 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1723 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1724 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1725 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1726
96bd6224
CC		 1727 /* ENABLE_PCLK_PERIS */
1728 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1729 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1730 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1731 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1732 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1733 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1734 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1735 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1736 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1737 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1738 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1739 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1740 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1741 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1742 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1743 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1744 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1745 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1746 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1747 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
56bcf3f3
CC		 1748
1749 /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1750 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1751 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, 0, 0),
1752 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1753 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, 0, 0),
1754 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1755 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, 0, 0),
1756 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1757 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, 0, 0),
1758 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1759 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, 0, 0),
1760 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1761 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, 0, 0),
1762 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1763 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, 0, 0),
1764 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1765 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, 0, 0),
1766 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1767 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, 0, 0),
1768 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1769 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, 0, 0),
1770 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1771 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, 0, 0),
1772 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1773 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, 0, 0),
1774 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1775 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, 0, 0),
1776
1777 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1778 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1779 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, 0, 0),
1780
1781 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1782 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1783 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, 0, 0),
1784
1785 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1786 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1787 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1788
1789 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1790 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1791 "aclk_peris_66",
1792 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1793
1794 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1795 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1796 "aclk_peris_66",
1797 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1798
1799 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1800 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1801 "aclk_peris_66",
1802 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1803
1804 /* ENABLE_SCLK_PERIS */
1805 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1806 ENABLE_SCLK_PERIS, 10, 0, 0),
1807 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1808 ENABLE_SCLK_PERIS, 4, 0, 0),
1809 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1810 ENABLE_SCLK_PERIS, 3, 0, 0),
1811
1812 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1813 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1814 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, 0, 0),
1815
1816 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1817 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1818 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
1819
1820 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1821 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1822 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1823
1824 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1825 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1826 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1827
1828 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1829 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1830 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1831
1832 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1833 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1834 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
96bd6224
CC		 1835};
1836
1837static struct samsung_cmu_info peris_cmu_info __initdata = {
1838 .gate_clks = peris_gate_clks,
1839 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1840 .nr_clk_ids = PERIS_NR_CLK,
1841 .clk_regs = peris_clk_regs,
1842 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
1843};
1844
1845static void __init exynos5433_cmu_peris_init(struct device_node *np)
1846{
1847 samsung_cmu_register_one(np, &peris_cmu_info);
1848}
1849
1850CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1851 exynos5433_cmu_peris_init);
1852
1853/*
1854 * Register offset definitions for CMU_FSYS
1855 */
1856#define MUX_SEL_FSYS0 0x0200
1857#define MUX_SEL_FSYS1 0x0204
1858#define MUX_SEL_FSYS2 0x0208
1859#define MUX_SEL_FSYS3 0x020c
1860#define MUX_SEL_FSYS4 0x0210
1861#define MUX_ENABLE_FSYS0 0x0300
1862#define MUX_ENABLE_FSYS1 0x0304
1863#define MUX_ENABLE_FSYS2 0x0308
1864#define MUX_ENABLE_FSYS3 0x030c
1865#define MUX_ENABLE_FSYS4 0x0310
1866#define MUX_STAT_FSYS0 0x0400
1867#define MUX_STAT_FSYS1 0x0404
1868#define MUX_STAT_FSYS2 0x0408
1869#define MUX_STAT_FSYS3 0x040c
1870#define MUX_STAT_FSYS4 0x0410
1871#define MUX_IGNORE_FSYS2 0x0508
1872#define MUX_IGNORE_FSYS3 0x050c
1873#define ENABLE_ACLK_FSYS0 0x0800
1874#define ENABLE_ACLK_FSYS1 0x0804
1875#define ENABLE_PCLK_FSYS 0x0900
1876#define ENABLE_SCLK_FSYS 0x0a00
1877#define ENABLE_IP_FSYS0 0x0b00
1878#define ENABLE_IP_FSYS1 0x0b04
1879
1880/* list of all parent clock list */
4b801355 1881PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
96bd6224 1882PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", };
4b801355
CC		 1883PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
1884PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
96bd6224
CC		 1885PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
1886PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", };
1887PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", };
4b801355
CC		 1888PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",};
1889PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", };
1890
1891PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
1892 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
1893PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
1894 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
1895PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
1896 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
1897PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
1898 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
1899PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
1900 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
1901PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
1902 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
1903PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
1904 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
1905PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
1906 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
1907PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
1908 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
1909PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
1910 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
1911PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
1912 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
1913PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
1914 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
1915PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
1916 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
1917PNAME(mout_sclk_mphy_p)
1918 = { "mout_sclk_ufs_mphy_user",
1919 "mout_phyclk_lli_mphy_to_ufs_user", };
96bd6224
CC		 1920
1921static unsigned long fsys_clk_regs[] __initdata = {
1922 MUX_SEL_FSYS0,
1923 MUX_SEL_FSYS1,
1924 MUX_SEL_FSYS2,
1925 MUX_SEL_FSYS3,
1926 MUX_SEL_FSYS4,
1927 MUX_ENABLE_FSYS0,
1928 MUX_ENABLE_FSYS1,
1929 MUX_ENABLE_FSYS2,
1930 MUX_ENABLE_FSYS3,
1931 MUX_ENABLE_FSYS4,
1932 MUX_STAT_FSYS0,
1933 MUX_STAT_FSYS1,
1934 MUX_STAT_FSYS2,
1935 MUX_STAT_FSYS3,
1936 MUX_STAT_FSYS4,
1937 MUX_IGNORE_FSYS2,
1938 MUX_IGNORE_FSYS3,
1939 ENABLE_ACLK_FSYS0,
1940 ENABLE_ACLK_FSYS1,
1941 ENABLE_PCLK_FSYS,
1942 ENABLE_SCLK_FSYS,
1943 ENABLE_IP_FSYS0,
1944 ENABLE_IP_FSYS1,
1945};
1946
4b801355
CC		 1947static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = {
1948 /* PHY clocks from USBDRD30_PHY */
1949 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
1950 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
1951 CLK_IS_ROOT, 60000000),
1952 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
1953 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
1954 CLK_IS_ROOT, 125000000),
1955 /* PHY clocks from USBHOST30_PHY */
1956 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
1957 "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
1958 CLK_IS_ROOT, 60000000),
1959 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
1960 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
1961 CLK_IS_ROOT, 125000000),
1962 /* PHY clocks from USBHOST20_PHY */
1963 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
1964 "phyclk_usbhost20_phy_freeclk_phy", NULL, CLK_IS_ROOT,
1965 60000000),
1966 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
1967 "phyclk_usbhost20_phy_phyclock_phy", NULL, CLK_IS_ROOT,
1968 60000000),
1969 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
1970 "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
1971 CLK_IS_ROOT, 48000000),
1972 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
1973 "phyclk_usbhost20_phy_hsic1_phy", NULL, CLK_IS_ROOT,
1974 60000000),
1975 /* PHY clocks from UFS_PHY */
1976 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
1977 NULL, CLK_IS_ROOT, 300000000),
1978 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
1979 NULL, CLK_IS_ROOT, 300000000),
1980 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
1981 NULL, CLK_IS_ROOT, 300000000),
1982 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
1983 NULL, CLK_IS_ROOT, 300000000),
1984 /* PHY clocks from LLI_PHY */
1985 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
1986 NULL, CLK_IS_ROOT, 26000000),
1987};
1988
96bd6224
CC		 1989static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
1990 /* MUX_SEL_FSYS0 */
4b801355
CC		 1991 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
1992 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
96bd6224
CC		 1993 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
1994 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
1995
1996 /* MUX_SEL_FSYS1 */
4b801355
CC		 1997 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
1998 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
1999 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
2000 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
96bd6224
CC		 2001 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
2002 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
2003 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
2004 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
2005 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
2006 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
4b801355
CC		 2007 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
2008 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
2009 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
2010 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2011
2012 /* MUX_SEL_FSYS2 */
2013 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
2014 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2015 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
2016 MUX_SEL_FSYS2, 28, 1),
2017 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
2018 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2019 mout_phyclk_usbhost30_uhost30_phyclock_user_p,
2020 MUX_SEL_FSYS2, 24, 1),
2021 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
2022 "mout_phyclk_usbhost20_phy_hsic1",
2023 mout_phyclk_usbhost20_phy_hsic1_p,
2024 MUX_SEL_FSYS2, 20, 1),
2025 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2026 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2027 mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2028 MUX_SEL_FSYS2, 16, 1),
2029 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2030 "mout_phyclk_usbhost20_phy_phyclock_user",
2031 mout_phyclk_usbhost20_phy_phyclock_user_p,
2032 MUX_SEL_FSYS2, 12, 1),
2033 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2034 "mout_phyclk_usbhost20_phy_freeclk_user",
2035 mout_phyclk_usbhost20_phy_freeclk_user_p,
2036 MUX_SEL_FSYS2, 8, 1),
2037 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2038 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2039 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2040 MUX_SEL_FSYS2, 4, 1),
2041 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2042 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2043 mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2044 MUX_SEL_FSYS2, 0, 1),
2045
2046 /* MUX_SEL_FSYS3 */
2047 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2048 "mout_phyclk_ufs_rx1_symbol_user",
2049 mout_phyclk_ufs_rx1_symbol_user_p,
2050 MUX_SEL_FSYS3, 16, 1),
2051 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2052 "mout_phyclk_ufs_rx0_symbol_user",
2053 mout_phyclk_ufs_rx0_symbol_user_p,
2054 MUX_SEL_FSYS3, 12, 1),
2055 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2056 "mout_phyclk_ufs_tx1_symbol_user",
2057 mout_phyclk_ufs_tx1_symbol_user_p,
2058 MUX_SEL_FSYS3, 8, 1),
2059 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2060 "mout_phyclk_ufs_tx0_symbol_user",
2061 mout_phyclk_ufs_tx0_symbol_user_p,
2062 MUX_SEL_FSYS3, 4, 1),
2063 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2064 "mout_phyclk_lli_mphy_to_ufs_user",
2065 mout_phyclk_lli_mphy_to_ufs_user_p,
2066 MUX_SEL_FSYS3, 0, 1),
2067
2068 /* MUX_SEL_FSYS4 */
2069 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2070 MUX_SEL_FSYS4, 0, 1),
96bd6224
CC		 2071};
2072
2073static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
2074 /* ENABLE_ACLK_FSYS0 */
2075 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2076 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2077 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
2078 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2079 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
2080 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2081 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
2082 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2083 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
2084 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2085 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
2086 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2087 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
2088 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2089 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2090 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2091 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2092 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2093 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2094 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2095 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
2096 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2097
4b801355
CC		 2098 /* ENABLE_ACLK_FSYS1 */
2099 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2100 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2101 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2102 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2103 26, CLK_IGNORE_UNUSED, 0),
2104 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2105 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2106 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2107 ENABLE_ACLK_FSYS1, 24, 0, 0),
2108 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2109 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2110 22, CLK_IGNORE_UNUSED, 0),
2111 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2112 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2113 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2114 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2115 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2116 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2117 13, 0, 0),
2118 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2119 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2120 12, 0, 0),
2121 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2122 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2123 11, CLK_IGNORE_UNUSED, 0),
2124 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2125 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2126 10, CLK_IGNORE_UNUSED, 0),
2127 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2128 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2129 9, CLK_IGNORE_UNUSED, 0),
2130 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2131 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2132 8, CLK_IGNORE_UNUSED, 0),
2133 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2134 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2135 7, CLK_IGNORE_UNUSED, 0),
2136 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2137 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2138 6, CLK_IGNORE_UNUSED, 0),
2139 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2140 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2141 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2142 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2143 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2144 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2145 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2146 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2147 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2148 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2149 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2150 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2151
2152 /* ENABLE_PCLK_FSYS */
2153 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2154 ENABLE_PCLK_FSYS, 17, 0, 0),
2155 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2156 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2157 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2158 ENABLE_PCLK_FSYS, 14, 0, 0),
2159 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2160 ENABLE_PCLK_FSYS, 13, 0, 0),
2161 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2162 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2163 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2164 ENABLE_PCLK_FSYS, 5, 0, 0),
2165 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2166 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2167 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2168 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2169 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2170 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2171 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2172 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2173 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2174 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2175 0, CLK_IGNORE_UNUSED, 0),
2176
96bd6224 2177 /* ENABLE_SCLK_FSYS */
4b801355
CC		 2178 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2179 ENABLE_SCLK_FSYS, 21, 0, 0),
2180 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2181 "phyclk_usbhost30_uhost30_pipe_pclk",
2182 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2183 ENABLE_SCLK_FSYS, 18, 0, 0),
2184 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2185 "phyclk_usbhost30_uhost30_phyclock",
2186 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2187 ENABLE_SCLK_FSYS, 17, 0, 0),
2188 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2189 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2190 16, 0, 0),
2191 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2192 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2193 15, 0, 0),
2194 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2195 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2196 14, 0, 0),
2197 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2198 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2199 13, 0, 0),
2200 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2201 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2202 12, 0, 0),
2203 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2204 "phyclk_usbhost20_phy_clk48mohci",
2205 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2206 ENABLE_SCLK_FSYS, 11, 0, 0),
2207 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2208 "phyclk_usbhost20_phy_phyclock",
2209 "mout_phyclk_usbhost20_phy_phyclock_user",
2210 ENABLE_SCLK_FSYS, 10, 0, 0),
2211 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2212 "phyclk_usbhost20_phy_freeclk",
2213 "mout_phyclk_usbhost20_phy_freeclk_user",
2214 ENABLE_SCLK_FSYS, 9, 0, 0),
2215 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2216 "phyclk_usbdrd30_udrd30_pipe_pclk",
2217 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2218 ENABLE_SCLK_FSYS, 8, 0, 0),
2219 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2220 "phyclk_usbdrd30_udrd30_phyclock",
2221 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2222 ENABLE_SCLK_FSYS, 7, 0, 0),
2223 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2224 ENABLE_SCLK_FSYS, 6, 0, 0),
2225 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2226 ENABLE_SCLK_FSYS, 5, 0, 0),
96bd6224
CC		 2227 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
2228 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2229 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
2230 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2231 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
2232 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
4b801355
CC		 2233 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2234 ENABLE_SCLK_FSYS, 1, 0, 0),
2235 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2236 ENABLE_SCLK_FSYS, 0, 0, 0),
96bd6224
CC		 2237
2238 /* ENABLE_IP_FSYS0 */
2239 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2240 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2241};
2242
2243static struct samsung_cmu_info fsys_cmu_info __initdata = {
2244 .mux_clks = fsys_mux_clks,
2245 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
2246 .gate_clks = fsys_gate_clks,
2247 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
4b801355
CC		 2248 .fixed_clks = fsys_fixed_clks,
2249 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
96bd6224
CC		 2250 .nr_clk_ids = FSYS_NR_CLK,
2251 .clk_regs = fsys_clk_regs,
2252 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
2253};
2254
2255static void __init exynos5433_cmu_fsys_init(struct device_node *np)
2256{
2257 samsung_cmu_register_one(np, &fsys_cmu_info);
2258}
2259
2260CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
2261 exynos5433_cmu_fsys_init);
a29308da
CC		 2262
2263/*
2264 * Register offset definitions for CMU_G2D
2265 */
2266#define MUX_SEL_G2D0 0x0200
2267#define MUX_SEL_ENABLE_G2D0 0x0300
2268#define MUX_SEL_STAT_G2D0 0x0400
2269#define DIV_G2D 0x0600
2270#define DIV_STAT_G2D 0x0700
2271#define DIV_ENABLE_ACLK_G2D 0x0800
2272#define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
2273#define DIV_ENABLE_PCLK_G2D 0x0900
2274#define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
2275#define DIV_ENABLE_IP_G2D0 0x0b00
2276#define DIV_ENABLE_IP_G2D1 0x0b04
2277#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2278
2279static unsigned long g2d_clk_regs[] __initdata = {
2280 MUX_SEL_G2D0,
2281 MUX_SEL_ENABLE_G2D0,
2282 MUX_SEL_STAT_G2D0,
2283 DIV_G2D,
2284 DIV_STAT_G2D,
2285 DIV_ENABLE_ACLK_G2D,
2286 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
2287 DIV_ENABLE_PCLK_G2D,
2288 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
2289 DIV_ENABLE_IP_G2D0,
2290 DIV_ENABLE_IP_G2D1,
2291 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2292};
2293
2294/* list of all parent clock list */
2295PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
2296PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
2297
2298static struct samsung_mux_clock g2d_mux_clks[] __initdata = {
2299 /* MUX_SEL_G2D0 */
2300 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2301 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
2302 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
2303 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2304};
2305
2306static struct samsung_div_clock g2d_div_clks[] __initdata = {
2307 /* DIV_G2D */
2308 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2309 DIV_G2D, 0, 2),
2310};
2311
2312static struct samsung_gate_clock g2d_gate_clks[] __initdata = {
2313 /* DIV_ENABLE_ACLK_G2D */
2314 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2315 DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2316 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2317 DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2318 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2319 DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2320 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2321 DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2322 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2323 DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2324 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
2325 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
2326 7, 0, 0),
2327 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2328 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2329 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2330 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2331 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2332 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2333 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
2334 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2335 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2336 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2337 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
2338 DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2339 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
2340 DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2341
2342 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2343 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2344 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2345
2346 /* DIV_ENABLE_PCLK_G2D */
2347 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
2348 DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2349 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
2350 DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2351 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
2352 DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2353 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
2354 DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2355 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2356 DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2357 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
2358 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2359 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
2360 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2361 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
2362 0, 0, 0),
2363
2364 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2365 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2366 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2367};
2368
2369static struct samsung_cmu_info g2d_cmu_info __initdata = {
2370 .mux_clks = g2d_mux_clks,
2371 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
2372 .div_clks = g2d_div_clks,
2373 .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
2374 .gate_clks = g2d_gate_clks,
2375 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
2376 .nr_clk_ids = G2D_NR_CLK,
2377 .clk_regs = g2d_clk_regs,
2378 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
2379};
2380
2381static void __init exynos5433_cmu_g2d_init(struct device_node *np)
2382{
2383 samsung_cmu_register_one(np, &g2d_cmu_info);
2384}
2385
2386CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
2387 exynos5433_cmu_g2d_init);
2a1808a6
CC		 2388
2389/*
2390 * Register offset definitions for CMU_DISP
2391 */
2392#define DISP_PLL_LOCK 0x0000
2393#define DISP_PLL_CON0 0x0100
2394#define DISP_PLL_CON1 0x0104
2395#define DISP_PLL_FREQ_DET 0x0108
2396#define MUX_SEL_DISP0 0x0200
2397#define MUX_SEL_DISP1 0x0204
2398#define MUX_SEL_DISP2 0x0208
2399#define MUX_SEL_DISP3 0x020c
2400#define MUX_SEL_DISP4 0x0210
2401#define MUX_ENABLE_DISP0 0x0300
2402#define MUX_ENABLE_DISP1 0x0304
2403#define MUX_ENABLE_DISP2 0x0308
2404#define MUX_ENABLE_DISP3 0x030c
2405#define MUX_ENABLE_DISP4 0x0310
2406#define MUX_STAT_DISP0 0x0400
2407#define MUX_STAT_DISP1 0x0404
2408#define MUX_STAT_DISP2 0x0408
2409#define MUX_STAT_DISP3 0x040c
2410#define MUX_STAT_DISP4 0x0410
2411#define MUX_IGNORE_DISP2 0x0508
2412#define DIV_DISP 0x0600
2413#define DIV_DISP_PLL_FREQ_DET 0x0604
2414#define DIV_STAT_DISP 0x0700
2415#define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
2416#define ENABLE_ACLK_DISP0 0x0800
2417#define ENABLE_ACLK_DISP1 0x0804
2418#define ENABLE_PCLK_DISP 0x0900
2419#define ENABLE_SCLK_DISP 0x0a00
2420#define ENABLE_IP_DISP0 0x0b00
2421#define ENABLE_IP_DISP1 0x0b04
2422#define CLKOUT_CMU_DISP 0x0c00
2423#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2424
2425static unsigned long disp_clk_regs[] __initdata = {
2426 DISP_PLL_LOCK,
2427 DISP_PLL_CON0,
2428 DISP_PLL_CON1,
2429 DISP_PLL_FREQ_DET,
2430 MUX_SEL_DISP0,
2431 MUX_SEL_DISP1,
2432 MUX_SEL_DISP2,
2433 MUX_SEL_DISP3,
2434 MUX_SEL_DISP4,
2435 MUX_ENABLE_DISP0,
2436 MUX_ENABLE_DISP1,
2437 MUX_ENABLE_DISP2,
2438 MUX_ENABLE_DISP3,
2439 MUX_ENABLE_DISP4,
2440 MUX_STAT_DISP0,
2441 MUX_STAT_DISP1,
2442 MUX_STAT_DISP2,
2443 MUX_STAT_DISP3,
2444 MUX_STAT_DISP4,
2445 MUX_IGNORE_DISP2,
2446 DIV_DISP,
2447 DIV_DISP_PLL_FREQ_DET,
2448 DIV_STAT_DISP,
2449 DIV_STAT_DISP_PLL_FREQ_DET,
2450 ENABLE_ACLK_DISP0,
2451 ENABLE_ACLK_DISP1,
2452 ENABLE_PCLK_DISP,
2453 ENABLE_SCLK_DISP,
2454 ENABLE_IP_DISP0,
2455 ENABLE_IP_DISP1,
2456 CLKOUT_CMU_DISP,
2457 CLKOUT_CMU_DISP_DIV_STAT,
2458};
2459
2460/* list of all parent clock list */
2461PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", };
2462PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", };
2463PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", };
2464PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", };
2465PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk",
2466 "sclk_decon_tv_eclk_disp", };
2467PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk",
2468 "sclk_decon_vclk_disp", };
2469PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk",
2470 "sclk_decon_eclk_disp", };
2471PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk",
2472 "sclk_decon_tv_vclk_disp", };
2473PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", };
2474
2475PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk",
2476 "phyclk_mipidphy1_bitclkdiv8_phy", };
2477PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk",
2478 "phyclk_mipidphy1_rxclkesc0_phy", };
2479PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk",
2480 "phyclk_mipidphy0_bitclkdiv8_phy", };
2481PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk",
2482 "phyclk_mipidphy0_rxclkesc0_phy", };
2483PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk",
2484 "phyclk_hdmiphy_tmds_clko_phy", };
2485PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk",
2486 "phyclk_hdmiphy_pixel_clko_phy", };
2487
2488PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
2489 "mout_sclk_dsim0_user", };
2490PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
2491 "mout_sclk_decon_tv_eclk_user", };
2492PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
2493 "mout_sclk_decon_vclk_user", };
2494PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
2495 "mout_sclk_decon_eclk_user", };
2496
2497PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
2498 "mout_sclk_dsim1_user", };
2499PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2500 "mout_phyclk_hdmiphy_pixel_clko_user",
2501 "mout_sclk_decon_tv_vclk_b_disp", };
2502PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2503 "mout_sclk_decon_tv_vclk_user", };
2504
2505static struct samsung_pll_clock disp_pll_clks[] __initdata = {
2506 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2507 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
2508};
2509
2510static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = {
2511 /*
2512 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2513 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2514 * and sclk_decon_{vclk|tv_vclk}.
2515 */
2516 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2517 1, 2, 0),
2518 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2519 1, 2, 0),
2520};
2521
2522static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
2523 /* PHY clocks from MIPI_DPHY1 */
2524 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2525 188000000),
2526 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2527 100000000),
2528 /* PHY clocks from MIPI_DPHY0 */
2529 FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2530 188000000),
2531 FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2532 100000000),
2533 /* PHY clocks from HDMI_PHY */
2534 FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000),
2535 FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000),
2536};
2537
2538static struct samsung_mux_clock disp_mux_clks[] __initdata = {
2539 /* MUX_SEL_DISP0 */
2540 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2541 0, 1),
2542
2543 /* MUX_SEL_DISP1 */
2544 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2545 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2546 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2547 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2548 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2549 MUX_SEL_DISP1, 20, 1),
2550 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2551 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2552 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2553 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2554 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2555 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2556 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2557 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2558 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2559 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2560
2561 /* MUX_SEL_DISP2 */
2562 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2563 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2564 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2565 20, 1),
2566 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2567 "mout_phyclk_mipidphy1_rxclkesc0_user",
2568 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2569 16, 1),
2570 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2571 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2572 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2573 12, 1),
2574 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2575 "mout_phyclk_mipidphy0_rxclkesc0_user",
2576 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2577 8, 1),
2578 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2579 "mout_phyclk_hdmiphy_tmds_clko_user",
2580 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2581 4, 1),
2582 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2583 "mout_phyclk_hdmiphy_pixel_clko_user",
2584 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2585 0, 1),
2586
2587 /* MUX_SEL_DISP3 */
2588 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2589 MUX_SEL_DISP3, 12, 1),
2590 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2591 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2592 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2593 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2594 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2595 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2596
2597 /* MUX_SEL_DISP4 */
2598 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2599 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2600 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2601 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2602 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2603 "mout_sclk_decon_tv_vclk_c_disp",
2604 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2605 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2606 "mout_sclk_decon_tv_vclk_b_disp",
2607 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2608 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2609 "mout_sclk_decon_tv_vclk_a_disp",
2610 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2611};
2612
2613static struct samsung_div_clock disp_div_clks[] __initdata = {
2614 /* DIV_DISP */
2615 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2616 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2617 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2618 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2619 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2620 DIV_DISP, 16, 3),
2621 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2622 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2623 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2624 "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2625 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2626 "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2627 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2628 DIV_DISP, 0, 2),
2629};
2630
2631static struct samsung_gate_clock disp_gate_clks[] __initdata = {
2632 /* ENABLE_ACLK_DISP0 */
2633 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2634 ENABLE_ACLK_DISP0, 2, 0, 0),
2635 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2636 ENABLE_ACLK_DISP0, 0, 0, 0),
2637
2638 /* ENABLE_ACLK_DISP1 */
2639 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2640 ENABLE_ACLK_DISP1, 25, 0, 0),
2641 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2642 ENABLE_ACLK_DISP1, 24, 0, 0),
2643 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2644 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2645 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2646 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2647 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2648 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2649 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2650 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2651 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2652 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2653 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2654 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2655 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2656 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2657 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2658 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2659 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2660 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2661 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2662 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2663 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2664 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2665 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2666 "div_pclk_disp", ENABLE_ACLK_DISP1,
2667 12, CLK_IGNORE_UNUSED, 0),
2668 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2669 "div_pclk_disp", ENABLE_ACLK_DISP1,
2670 11, CLK_IGNORE_UNUSED, 0),
2671 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2672 "div_pclk_disp", ENABLE_ACLK_DISP1,
2673 10, CLK_IGNORE_UNUSED, 0),
2674 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2675 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2676 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2677 ENABLE_ACLK_DISP1, 7, 0, 0),
2678 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2679 ENABLE_ACLK_DISP1, 6, 0, 0),
2680 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2681 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2682 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2683 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2684 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2685 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2686 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2687 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2688 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2689 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2690 CLK_IGNORE_UNUSED, 0),
2691 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2692 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2693 0, CLK_IGNORE_UNUSED, 0),
2694
2695 /* ENABLE_PCLK_DISP */
2696 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2697 ENABLE_PCLK_DISP, 23, 0, 0),
2698 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2699 ENABLE_PCLK_DISP, 22, 0, 0),
2700 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2701 ENABLE_PCLK_DISP, 21, 0, 0),
2702 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2703 ENABLE_PCLK_DISP, 20, 0, 0),
2704 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2705 ENABLE_PCLK_DISP, 19, 0, 0),
2706 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2707 ENABLE_PCLK_DISP, 18, 0, 0),
2708 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2709 ENABLE_PCLK_DISP, 17, 0, 0),
2710 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2711 ENABLE_PCLK_DISP, 16, 0, 0),
2712 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2713 ENABLE_PCLK_DISP, 15, 0, 0),
2714 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2715 ENABLE_PCLK_DISP, 14, 0, 0),
2716 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2717 ENABLE_PCLK_DISP, 13, 0, 0),
2718 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2719 ENABLE_PCLK_DISP, 12, 0, 0),
2720 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2721 ENABLE_PCLK_DISP, 11, 0, 0),
2722 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2723 ENABLE_PCLK_DISP, 10, 0, 0),
2724 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2725 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2726 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2727 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2728 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2729 ENABLE_PCLK_DISP, 7, 0, 0),
2730 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2731 ENABLE_PCLK_DISP, 6, 0, 0),
2732 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2733 ENABLE_PCLK_DISP, 5, 0, 0),
2734 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2735 ENABLE_PCLK_DISP, 3, 0, 0),
2736 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2737 ENABLE_PCLK_DISP, 2, 0, 0),
2738 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2739 ENABLE_PCLK_DISP, 1, 0, 0),
2740
2741 /* ENABLE_SCLK_DISP */
2742 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2743 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2744 ENABLE_SCLK_DISP, 26, 0, 0),
2745 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2746 "mout_phyclk_mipidphy1_rxclkesc0_user",
2747 ENABLE_SCLK_DISP, 25, 0, 0),
2748 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2749 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2750 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2751 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2752 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2753 ENABLE_SCLK_DISP, 22, 0, 0),
2754 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2755 "div_sclk_decon_tv_vclk_disp",
2756 ENABLE_SCLK_DISP, 21, 0, 0),
2757 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2758 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2759 ENABLE_SCLK_DISP, 15, 0, 0),
2760 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2761 "mout_phyclk_mipidphy0_rxclkesc0_user",
2762 ENABLE_SCLK_DISP, 14, 0, 0),
2763 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2764 "mout_phyclk_hdmiphy_tmds_clko_user",
2765 ENABLE_SCLK_DISP, 13, 0, 0),
2766 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2767 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2768 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2769 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2770 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2771 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2772 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2773 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2774 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2775 ENABLE_SCLK_DISP, 7, 0, 0),
2776 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2777 ENABLE_SCLK_DISP, 6, 0, 0),
2778 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2779 ENABLE_SCLK_DISP, 5, 0, 0),
2780 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2781 "div_sclk_decon_tv_eclk_disp",
2782 ENABLE_SCLK_DISP, 4, 0, 0),
2783 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2784 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2785 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2786 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2787};
2788
2789static struct samsung_cmu_info disp_cmu_info __initdata = {
2790 .pll_clks = disp_pll_clks,
2791 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
2792 .mux_clks = disp_mux_clks,
2793 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
2794 .div_clks = disp_div_clks,
2795 .nr_div_clks = ARRAY_SIZE(disp_div_clks),
2796 .gate_clks = disp_gate_clks,
2797 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
2798 .fixed_clks = disp_fixed_clks,
2799 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
2800 .fixed_factor_clks = disp_fixed_factor_clks,
2801 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
2802 .nr_clk_ids = DISP_NR_CLK,
2803 .clk_regs = disp_clk_regs,
2804 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
2805};
2806
2807static void __init exynos5433_cmu_disp_init(struct device_node *np)
2808{
2809 samsung_cmu_register_one(np, &disp_cmu_info);
2810}
2811
2812CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
2813 exynos5433_cmu_disp_init);
2e997c03
CC		 2814
2815/*
2816 * Register offset definitions for CMU_AUD
2817 */
2818#define MUX_SEL_AUD0 0x0200
2819#define MUX_SEL_AUD1 0x0204
2820#define MUX_ENABLE_AUD0 0x0300
2821#define MUX_ENABLE_AUD1 0x0304
2822#define MUX_STAT_AUD0 0x0400
2823#define DIV_AUD0 0x0600
2824#define DIV_AUD1 0x0604
2825#define DIV_STAT_AUD0 0x0700
2826#define DIV_STAT_AUD1 0x0704
2827#define ENABLE_ACLK_AUD 0x0800
2828#define ENABLE_PCLK_AUD 0x0900
2829#define ENABLE_SCLK_AUD0 0x0a00
2830#define ENABLE_SCLK_AUD1 0x0a04
2831#define ENABLE_IP_AUD0 0x0b00
2832#define ENABLE_IP_AUD1 0x0b04
2833
2834static unsigned long aud_clk_regs[] __initdata = {
2835 MUX_SEL_AUD0,
2836 MUX_SEL_AUD1,
2837 MUX_ENABLE_AUD0,
2838 MUX_ENABLE_AUD1,
2839 MUX_STAT_AUD0,
2840 DIV_AUD0,
2841 DIV_AUD1,
2842 DIV_STAT_AUD0,
2843 DIV_STAT_AUD1,
2844 ENABLE_ACLK_AUD,
2845 ENABLE_PCLK_AUD,
2846 ENABLE_SCLK_AUD0,
2847 ENABLE_SCLK_AUD1,
2848 ENABLE_IP_AUD0,
2849 ENABLE_IP_AUD1,
2850};
2851
2852/* list of all parent clock list */
2853PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
2854PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2855
2856static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = {
2857 FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 33000000),
2858 FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 25000000),
2859 FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 50000000),
2860};
2861
2862static struct samsung_mux_clock aud_mux_clks[] __initdata = {
2863 /* MUX_SEL_AUD0 */
2864 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2865 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2866
2867 /* MUX_SEL_AUD1 */
2868 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
2869 MUX_SEL_AUD1, 8, 1),
2870 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
2871 MUX_SEL_AUD1, 0, 1),
2872};
2873
2874static struct samsung_div_clock aud_div_clks[] __initdata = {
2875 /* DIV_AUD0 */
2876 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2877 12, 4),
2878 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
2879 8, 4),
2880 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
2881 4, 4),
2882 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
2883 0, 4),
2884
2885 /* DIV_AUD1 */
2886 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
2887 "mout_aud_pll_user", DIV_AUD1, 16, 5),
2888 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
2889 DIV_AUD1, 12, 4),
2890 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2891 DIV_AUD1, 4, 8),
2892 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
2893 DIV_AUD1, 0, 4),
2894};
2895
2896static struct samsung_gate_clock aud_gate_clks[] __initdata = {
2897 /* ENABLE_ACLK_AUD */
2898 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2899 ENABLE_ACLK_AUD, 12, 0, 0),
2900 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
2901 ENABLE_ACLK_AUD, 7, 0, 0),
2902 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
2903 ENABLE_ACLK_AUD, 0, 4, 0),
2904 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
2905 ENABLE_ACLK_AUD, 0, 3, 0),
2906 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
2907 ENABLE_ACLK_AUD, 0, 2, 0),
2908 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
2909 0, 1, 0),
2910 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
2911 0, CLK_IGNORE_UNUSED, 0),
2912
2913 /* ENABLE_PCLK_AUD */
2914 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
2915 13, 0, 0),
2916 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
2917 12, 0, 0),
2918 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
2919 11, 0, 0),
2920 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
2921 ENABLE_PCLK_AUD, 10, 0, 0),
2922 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
2923 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
2924 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
2925 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
2926 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
2927 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
2928 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
2929 ENABLE_PCLK_AUD, 6, 0, 0),
2930 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
2931 ENABLE_PCLK_AUD, 5, 0, 0),
2932 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
2933 ENABLE_PCLK_AUD, 4, 0, 0),
2934 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
2935 ENABLE_PCLK_AUD, 3, 0, 0),
2936 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
2937 2, 0, 0),
2938 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
2939 ENABLE_PCLK_AUD, 0, 0, 0),
2940
2941 /* ENABLE_SCLK_AUD0 */
2942 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
2943 2, 0, 0),
2944 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
2945 ENABLE_SCLK_AUD0, 1, 0, 0),
2946 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
2947 0, 0, 0),
2948
2949 /* ENABLE_SCLK_AUD1 */
2950 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
2951 ENABLE_SCLK_AUD1, 6, 0, 0),
2952 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
2953 ENABLE_SCLK_AUD1, 5, 0, 0),
2954 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
2955 ENABLE_SCLK_AUD1, 4, 0, 0),
2956 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
2957 ENABLE_SCLK_AUD1, 3, 0, 0),
2958 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
2959 ENABLE_SCLK_AUD1, 2, 0, 0),
2960 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
2961 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
2962 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
2963 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
2964};
2965
2966static struct samsung_cmu_info aud_cmu_info __initdata = {
2967 .mux_clks = aud_mux_clks,
2968 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
2969 .div_clks = aud_div_clks,
2970 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
2971 .gate_clks = aud_gate_clks,
2972 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
2973 .fixed_clks = aud_fixed_clks,
2974 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
2975 .nr_clk_ids = AUD_NR_CLK,
2976 .clk_regs = aud_clk_regs,
2977 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
2978};
2979
2980static void __init exynos5433_cmu_aud_init(struct device_node *np)
2981{
2982 samsung_cmu_register_one(np, &aud_cmu_info);
2983}
2984CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
2985 exynos5433_cmu_aud_init);
5785d6e6
CC		 2986
2987
2988/*
2989 * Register offset definitions for CMU_BUS{0|1|2}
2990 */
2991#define DIV_BUS 0x0600
2992#define DIV_STAT_BUS 0x0700
2993#define ENABLE_ACLK_BUS 0x0800
2994#define ENABLE_PCLK_BUS 0x0900
2995#define ENABLE_IP_BUS0 0x0b00
2996#define ENABLE_IP_BUS1 0x0b04
2997
2998#define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
2999#define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
3000#define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
3001
3002/* list of all parent clock list */
3003PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
3004
3005#define CMU_BUS_COMMON_CLK_REGS \
3006 DIV_BUS, \
3007 DIV_STAT_BUS, \
3008 ENABLE_ACLK_BUS, \
3009 ENABLE_PCLK_BUS, \
3010 ENABLE_IP_BUS0, \
3011 ENABLE_IP_BUS1
3012
3013static unsigned long bus01_clk_regs[] __initdata = {
3014 CMU_BUS_COMMON_CLK_REGS,
3015};
3016
3017static unsigned long bus2_clk_regs[] __initdata = {
3018 MUX_SEL_BUS2,
3019 MUX_ENABLE_BUS2,
3020 MUX_STAT_BUS2,
3021 CMU_BUS_COMMON_CLK_REGS,
3022};
3023
3024static struct samsung_div_clock bus0_div_clks[] __initdata = {
3025 /* DIV_BUS0 */
3026 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3027 DIV_BUS, 0, 3),
3028};
3029
3030/* CMU_BUS0 clocks */
3031static struct samsung_gate_clock bus0_gate_clks[] __initdata = {
3032 /* ENABLE_ACLK_BUS0 */
3033 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3034 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3035 GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
3036 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3037 GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
3038 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3039
3040 /* ENABLE_PCLK_BUS0 */
3041 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3042 ENABLE_PCLK_BUS, 2, 0, 0),
3043 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
3044 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3045 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3046 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3047};
3048
3049/* CMU_BUS1 clocks */
3050static struct samsung_div_clock bus1_div_clks[] __initdata = {
3051 /* DIV_BUS1 */
3052 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3053 DIV_BUS, 0, 3),
3054};
3055
3056static struct samsung_gate_clock bus1_gate_clks[] __initdata = {
3057 /* ENABLE_ACLK_BUS1 */
3058 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3059 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3060 GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
3061 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3062 GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
3063 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3064
3065 /* ENABLE_PCLK_BUS1 */
3066 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3067 ENABLE_PCLK_BUS, 2, 0, 0),
3068 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
3069 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3070 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3071 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3072};
3073
3074/* CMU_BUS2 clocks */
3075static struct samsung_mux_clock bus2_mux_clks[] __initdata = {
3076 /* MUX_SEL_BUS2 */
3077 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3078 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3079};
3080
3081static struct samsung_div_clock bus2_div_clks[] __initdata = {
3082 /* DIV_BUS2 */
3083 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3084 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3085};
3086
3087static struct samsung_gate_clock bus2_gate_clks[] __initdata = {
3088 /* ENABLE_ACLK_BUS2 */
3089 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3090 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3091 GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
3092 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3093 GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
3094 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3095 1, CLK_IGNORE_UNUSED, 0),
3096 GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
3097 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3098 0, CLK_IGNORE_UNUSED, 0),
3099
3100 /* ENABLE_PCLK_BUS2 */
3101 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3102 ENABLE_PCLK_BUS, 2, 0, 0),
3103 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
3104 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3105 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3106 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3107};
3108
3109#define CMU_BUS_INFO_CLKS(id) \
3110 .div_clks = bus##id##_div_clks, \
3111 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
3112 .gate_clks = bus##id##_gate_clks, \
3113 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
3114 .nr_clk_ids = BUSx_NR_CLK
3115
3116static struct samsung_cmu_info bus0_cmu_info __initdata = {
3117 CMU_BUS_INFO_CLKS(0),
3118 .clk_regs = bus01_clk_regs,
3119 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3120};
3121
3122static struct samsung_cmu_info bus1_cmu_info __initdata = {
3123 CMU_BUS_INFO_CLKS(1),
3124 .clk_regs = bus01_clk_regs,
3125 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3126};
3127
3128static struct samsung_cmu_info bus2_cmu_info __initdata = {
3129 CMU_BUS_INFO_CLKS(2),
3130 .mux_clks = bus2_mux_clks,
3131 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
3132 .clk_regs = bus2_clk_regs,
3133 .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs),
3134};
3135
3136#define exynos5433_cmu_bus_init(id) \
3137static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3138{ \
3139 samsung_cmu_register_one(np, &bus##id##_cmu_info); \
3140} \
3141CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
3142 "samsung,exynos5433-cmu-bus"#id, \
3143 exynos5433_cmu_bus##id##_init)
3144
3145exynos5433_cmu_bus_init(0);
3146exynos5433_cmu_bus_init(1);
3147exynos5433_cmu_bus_init(2);
453e519e
CC		 3148
3149/*
3150 * Register offset definitions for CMU_G3D
3151 */
3152#define G3D_PLL_LOCK 0x0000
3153#define G3D_PLL_CON0 0x0100
3154#define G3D_PLL_CON1 0x0104
3155#define G3D_PLL_FREQ_DET 0x010c
3156#define MUX_SEL_G3D 0x0200
3157#define MUX_ENABLE_G3D 0x0300
3158#define MUX_STAT_G3D 0x0400
3159#define DIV_G3D 0x0600
3160#define DIV_G3D_PLL_FREQ_DET 0x0604
3161#define DIV_STAT_G3D 0x0700
3162#define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
3163#define ENABLE_ACLK_G3D 0x0800
3164#define ENABLE_PCLK_G3D 0x0900
3165#define ENABLE_SCLK_G3D 0x0a00
3166#define ENABLE_IP_G3D0 0x0b00
3167#define ENABLE_IP_G3D1 0x0b04
3168#define CLKOUT_CMU_G3D 0x0c00
3169#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3170#define CLK_STOPCTRL 0x1000
3171
3172static unsigned long g3d_clk_regs[] __initdata = {
3173 G3D_PLL_LOCK,
3174 G3D_PLL_CON0,
3175 G3D_PLL_CON1,
3176 G3D_PLL_FREQ_DET,
3177 MUX_SEL_G3D,
3178 MUX_ENABLE_G3D,
3179 MUX_STAT_G3D,
3180 DIV_G3D,
3181 DIV_G3D_PLL_FREQ_DET,
3182 DIV_STAT_G3D,
3183 DIV_STAT_G3D_PLL_FREQ_DET,
3184 ENABLE_ACLK_G3D,
3185 ENABLE_PCLK_G3D,
3186 ENABLE_SCLK_G3D,
3187 ENABLE_IP_G3D0,
3188 ENABLE_IP_G3D1,
3189 CLKOUT_CMU_G3D,
3190 CLKOUT_CMU_G3D_DIV_STAT,
3191 CLK_STOPCTRL,
3192};
3193
3194/* list of all parent clock list */
3195PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
3196PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
3197
3198static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
3199 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3200 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
3201};
3202
3203static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
3204 /* MUX_SEL_G3D */
3205 MUX(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3206 MUX_SEL_G3D, 8, 1),
3207 MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3208 MUX_SEL_G3D, 0, 1),
3209};
3210
3211static struct samsung_div_clock g3d_div_clks[] __initdata = {
3212 /* DIV_G3D */
3213 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3214 8, 2),
3215 DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
3216 4, 3),
3217 DIV(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3218 0, 3),
3219};
3220
3221static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
3222 /* ENABLE_ACLK_G3D */
3223 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3224 ENABLE_ACLK_G3D, 7, 0, 0),
3225 GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
3226 ENABLE_ACLK_G3D, 6, 0, 0),
3227 GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3228 ENABLE_ACLK_G3D, 5, 0, 0),
3229 GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3230 ENABLE_ACLK_G3D, 4, 0, 0),
3231 GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3232 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3233 GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
3234 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3235 GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
3236 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3237 GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
3238 ENABLE_ACLK_G3D, 0, 0, 0),
3239
3240 /* ENABLE_PCLK_G3D */
3241 GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
3242 ENABLE_PCLK_G3D, 3, 0, 0),
3243 GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
3244 ENABLE_PCLK_G3D, 2, 0, 0),
3245 GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
3246 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3247 GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
3248 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3249
3250 /* ENABLE_SCLK_G3D */
3251 GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3252 ENABLE_SCLK_G3D, 0, 0, 0),
3253};
3254
3255static struct samsung_cmu_info g3d_cmu_info __initdata = {
3256 .pll_clks = g3d_pll_clks,
3257 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
3258 .mux_clks = g3d_mux_clks,
3259 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
3260 .div_clks = g3d_div_clks,
3261 .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
3262 .gate_clks = g3d_gate_clks,
3263 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
3264 .nr_clk_ids = G3D_NR_CLK,
3265 .clk_regs = g3d_clk_regs,
3266 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
3267};
3268
3269static void __init exynos5433_cmu_g3d_init(struct device_node *np)
3270{
3271 samsung_cmu_register_one(np, &g3d_cmu_info);
3272}
3273CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
3274 exynos5433_cmu_g3d_init);
2a2f33e8
CC		 3275
3276/*
3277 * Register offset definitions for CMU_GSCL
3278 */
3279#define MUX_SEL_GSCL 0x0200
3280#define MUX_ENABLE_GSCL 0x0300
3281#define MUX_STAT_GSCL 0x0400
3282#define ENABLE_ACLK_GSCL 0x0800
3283#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
3284#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
3285#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
3286#define ENABLE_PCLK_GSCL 0x0900
3287#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
3288#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
3289#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
3290#define ENABLE_IP_GSCL0 0x0b00
3291#define ENABLE_IP_GSCL1 0x0b04
3292#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
3293#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3294#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3295
3296static unsigned long gscl_clk_regs[] __initdata = {
3297 MUX_SEL_GSCL,
3298 MUX_ENABLE_GSCL,
3299 MUX_STAT_GSCL,
3300 ENABLE_ACLK_GSCL,
3301 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
3302 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
3303 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
3304 ENABLE_PCLK_GSCL,
3305 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
3306 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
3307 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
3308 ENABLE_IP_GSCL0,
3309 ENABLE_IP_GSCL1,
3310 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
3311 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
3312 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3313};
3314
3315/* list of all parent clock list */
3316PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
3317PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
3318
3319static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
3320 /* MUX_SEL_GSCL */
3321 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3322 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
3323 MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
3324 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3325};
3326
3327static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
3328 /* ENABLE_ACLK_GSCL */
3329 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3330 ENABLE_ACLK_GSCL, 11, 0, 0),
3331 GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3332 ENABLE_ACLK_GSCL, 10, 0, 0),
3333 GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3334 ENABLE_ACLK_GSCL, 9, 0, 0),
3335 GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
3336 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
3337 8, CLK_IGNORE_UNUSED, 0),
3338 GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3339 ENABLE_ACLK_GSCL, 7, 0, 0),
3340 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3341 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3342 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3343 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0),
3344 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3345 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0),
3346 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3347 ENABLE_ACLK_GSCL, 3, 0, 0),
3348 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
3349 ENABLE_ACLK_GSCL, 2, 0, 0),
3350 GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
3351 ENABLE_ACLK_GSCL, 1, 0, 0),
3352 GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
3353 ENABLE_ACLK_GSCL, 0, 0, 0),
3354
3355 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3356 GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3357 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3358
3359 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3360 GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3361 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3362
3363 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3364 GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3365 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3366
3367 /* ENABLE_PCLK_GSCL */
3368 GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3369 ENABLE_PCLK_GSCL, 7, 0, 0),
3370 GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3371 ENABLE_PCLK_GSCL, 6, 0, 0),
3372 GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3373 ENABLE_PCLK_GSCL, 5, 0, 0),
3374 GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3375 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3376 GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
3377 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3378 3, CLK_IGNORE_UNUSED, 0),
3379 GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
3380 ENABLE_PCLK_GSCL, 2, 0, 0),
3381 GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
3382 ENABLE_PCLK_GSCL, 1, 0, 0),
3383 GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
3384 ENABLE_PCLK_GSCL, 0, 0, 0),
3385
3386 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3387 GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3388 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3389
3390 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3391 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3392 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3393
3394 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3395 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3396 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3397};
3398
3399static struct samsung_cmu_info gscl_cmu_info __initdata = {
3400 .mux_clks = gscl_mux_clks,
3401 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
3402 .gate_clks = gscl_gate_clks,
3403 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
3404 .nr_clk_ids = GSCL_NR_CLK,
3405 .clk_regs = gscl_clk_regs,
3406 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
3407};
3408
3409static void __init exynos5433_cmu_gscl_init(struct device_node *np)
3410{
3411 samsung_cmu_register_one(np, &gscl_cmu_info);
3412}
3413CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
3414 exynos5433_cmu_gscl_init);
df40a13c
CC		 3415
3416/*
3417 * Register offset definitions for CMU_APOLLO
3418 */
3419#define APOLLO_PLL_LOCK 0x0000
3420#define APOLLO_PLL_CON0 0x0100
3421#define APOLLO_PLL_CON1 0x0104
3422#define APOLLO_PLL_FREQ_DET 0x010c
3423#define MUX_SEL_APOLLO0 0x0200
3424#define MUX_SEL_APOLLO1 0x0204
3425#define MUX_SEL_APOLLO2 0x0208
3426#define MUX_ENABLE_APOLLO0 0x0300
3427#define MUX_ENABLE_APOLLO1 0x0304
3428#define MUX_ENABLE_APOLLO2 0x0308
3429#define MUX_STAT_APOLLO0 0x0400
3430#define MUX_STAT_APOLLO1 0x0404
3431#define MUX_STAT_APOLLO2 0x0408
3432#define DIV_APOLLO0 0x0600
3433#define DIV_APOLLO1 0x0604
3434#define DIV_APOLLO_PLL_FREQ_DET 0x0608
3435#define DIV_STAT_APOLLO0 0x0700
3436#define DIV_STAT_APOLLO1 0x0704
3437#define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
3438#define ENABLE_ACLK_APOLLO 0x0800
3439#define ENABLE_PCLK_APOLLO 0x0900
3440#define ENABLE_SCLK_APOLLO 0x0a00
3441#define ENABLE_IP_APOLLO0 0x0b00
3442#define ENABLE_IP_APOLLO1 0x0b04
3443#define CLKOUT_CMU_APOLLO 0x0c00
3444#define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
3445#define ARMCLK_STOPCTRL 0x1000
3446#define APOLLO_PWR_CTRL 0x1020
3447#define APOLLO_PWR_CTRL2 0x1024
3448#define APOLLO_INTR_SPREAD_ENABLE 0x1080
3449#define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3450#define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3451
3452static unsigned long apollo_clk_regs[] __initdata = {
3453 APOLLO_PLL_LOCK,
3454 APOLLO_PLL_CON0,
3455 APOLLO_PLL_CON1,
3456 APOLLO_PLL_FREQ_DET,
3457 MUX_SEL_APOLLO0,
3458 MUX_SEL_APOLLO1,
3459 MUX_SEL_APOLLO2,
3460 MUX_ENABLE_APOLLO0,
3461 MUX_ENABLE_APOLLO1,
3462 MUX_ENABLE_APOLLO2,
3463 MUX_STAT_APOLLO0,
3464 MUX_STAT_APOLLO1,
3465 MUX_STAT_APOLLO2,
3466 DIV_APOLLO0,
3467 DIV_APOLLO1,
3468 DIV_APOLLO_PLL_FREQ_DET,
3469 DIV_STAT_APOLLO0,
3470 DIV_STAT_APOLLO1,
3471 DIV_STAT_APOLLO_PLL_FREQ_DET,
3472 ENABLE_ACLK_APOLLO,
3473 ENABLE_PCLK_APOLLO,
3474 ENABLE_SCLK_APOLLO,
3475 ENABLE_IP_APOLLO0,
3476 ENABLE_IP_APOLLO1,
3477 CLKOUT_CMU_APOLLO,
3478 CLKOUT_CMU_APOLLO_DIV_STAT,
3479 ARMCLK_STOPCTRL,
3480 APOLLO_PWR_CTRL,
3481 APOLLO_PWR_CTRL2,
3482 APOLLO_INTR_SPREAD_ENABLE,
3483 APOLLO_INTR_SPREAD_USE_STANDBYWFI,
3484 APOLLO_INTR_SPREAD_BLOCKING_DURATION,
3485};
3486
3487/* list of all parent clock list */
3488PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", };
3489PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
3490PNAME(mout_apollo_p) = { "mout_apollo_pll",
3491 "mout_bus_pll_apollo_user", };
3492
3493static struct samsung_pll_clock apollo_pll_clks[] __initdata = {
3494 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3495 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates),
3496};
3497
3498static struct samsung_mux_clock apollo_mux_clks[] __initdata = {
3499 /* MUX_SEL_APOLLO0 */
3500 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3501 MUX_SEL_APOLLO0, 0, 1, 0, CLK_MUX_READ_ONLY),
3502
3503 /* MUX_SEL_APOLLO1 */
3504 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
3505 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3506
3507 /* MUX_SEL_APOLLO2 */
3508 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3509 0, 1, 0, CLK_MUX_READ_ONLY),
3510};
3511
3512static struct samsung_div_clock apollo_div_clks[] __initdata = {
3513 /* DIV_APOLLO0 */
3514 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3515 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
3516 CLK_DIVIDER_READ_ONLY),
3517 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3518 DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
3519 CLK_DIVIDER_READ_ONLY),
3520 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3521 DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
3522 CLK_DIVIDER_READ_ONLY),
3523 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3524 DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
3525 CLK_DIVIDER_READ_ONLY),
3526 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3527 DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
3528 CLK_DIVIDER_READ_ONLY),
3529 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3530 DIV_APOLLO0, 4, 3, CLK_GET_RATE_NOCACHE,
3531 CLK_DIVIDER_READ_ONLY),
3532 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
3533 DIV_APOLLO0, 0, 3, CLK_GET_RATE_NOCACHE,
3534 CLK_DIVIDER_READ_ONLY),
3535
3536 /* DIV_APOLLO1 */
3537 DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
3538 DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
3539 CLK_DIVIDER_READ_ONLY),
3540 DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
3541 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3542 CLK_DIVIDER_READ_ONLY),
3543};
3544
3545static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
3546 /* ENABLE_ACLK_APOLLO */
3547 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3548 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3549 6, CLK_IGNORE_UNUSED, 0),
3550 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
3551 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3552 5, CLK_IGNORE_UNUSED, 0),
3553 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
3554 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3555 4, CLK_IGNORE_UNUSED, 0),
3556 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
3557 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3558 3, CLK_IGNORE_UNUSED, 0),
3559 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
3560 "div_aclk_apollo", ENABLE_ACLK_APOLLO,
3561 2, CLK_IGNORE_UNUSED, 0),
3562 GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
3563 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3564 1, CLK_IGNORE_UNUSED, 0),
3565 GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
3566 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3567 0, CLK_IGNORE_UNUSED, 0),
3568
3569 /* ENABLE_PCLK_APOLLO */
3570 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
3571 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
3572 2, CLK_IGNORE_UNUSED, 0),
3573 GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
3574 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3575 GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
3576 "div_pclk_apollo", ENABLE_PCLK_APOLLO,
3577 0, CLK_IGNORE_UNUSED, 0),
3578
3579 /* ENABLE_SCLK_APOLLO */
3580 GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
3581 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3582 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3583 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3584 GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo_pll",
3585 ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0),
3586};
3587
3588static struct samsung_cmu_info apollo_cmu_info __initdata = {
3589 .pll_clks = apollo_pll_clks,
3590 .nr_pll_clks = ARRAY_SIZE(apollo_pll_clks),
3591 .mux_clks = apollo_mux_clks,
3592 .nr_mux_clks = ARRAY_SIZE(apollo_mux_clks),
3593 .div_clks = apollo_div_clks,
3594 .nr_div_clks = ARRAY_SIZE(apollo_div_clks),
3595 .gate_clks = apollo_gate_clks,
3596 .nr_gate_clks = ARRAY_SIZE(apollo_gate_clks),
3597 .nr_clk_ids = APOLLO_NR_CLK,
3598 .clk_regs = apollo_clk_regs,
3599 .nr_clk_regs = ARRAY_SIZE(apollo_clk_regs),
3600};
3601
3602static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3603{
3604 samsung_cmu_register_one(np, &apollo_cmu_info);
3605}
3606CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3607 exynos5433_cmu_apollo_init);
6c5d76d1
CC		 3608
3609/*
3610 * Register offset definitions for CMU_ATLAS
3611 */
3612#define ATLAS_PLL_LOCK 0x0000
3613#define ATLAS_PLL_CON0 0x0100
3614#define ATLAS_PLL_CON1 0x0104
3615#define ATLAS_PLL_FREQ_DET 0x010c
3616#define MUX_SEL_ATLAS0 0x0200
3617#define MUX_SEL_ATLAS1 0x0204
3618#define MUX_SEL_ATLAS2 0x0208
3619#define MUX_ENABLE_ATLAS0 0x0300
3620#define MUX_ENABLE_ATLAS1 0x0304
3621#define MUX_ENABLE_ATLAS2 0x0308
3622#define MUX_STAT_ATLAS0 0x0400
3623#define MUX_STAT_ATLAS1 0x0404
3624#define MUX_STAT_ATLAS2 0x0408
3625#define DIV_ATLAS0 0x0600
3626#define DIV_ATLAS1 0x0604
3627#define DIV_ATLAS_PLL_FREQ_DET 0x0608
3628#define DIV_STAT_ATLAS0 0x0700
3629#define DIV_STAT_ATLAS1 0x0704
3630#define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
3631#define ENABLE_ACLK_ATLAS 0x0800
3632#define ENABLE_PCLK_ATLAS 0x0900
3633#define ENABLE_SCLK_ATLAS 0x0a00
3634#define ENABLE_IP_ATLAS0 0x0b00
3635#define ENABLE_IP_ATLAS1 0x0b04
3636#define CLKOUT_CMU_ATLAS 0x0c00
3637#define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
3638#define ARMCLK_STOPCTRL 0x1000
3639#define ATLAS_PWR_CTRL 0x1020
3640#define ATLAS_PWR_CTRL2 0x1024
3641#define ATLAS_INTR_SPREAD_ENABLE 0x1080
3642#define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3643#define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3644
3645static unsigned long atlas_clk_regs[] __initdata = {
3646 ATLAS_PLL_LOCK,
3647 ATLAS_PLL_CON0,
3648 ATLAS_PLL_CON1,
3649 ATLAS_PLL_FREQ_DET,
3650 MUX_SEL_ATLAS0,
3651 MUX_SEL_ATLAS1,
3652 MUX_SEL_ATLAS2,
3653 MUX_ENABLE_ATLAS0,
3654 MUX_ENABLE_ATLAS1,
3655 MUX_ENABLE_ATLAS2,
3656 MUX_STAT_ATLAS0,
3657 MUX_STAT_ATLAS1,
3658 MUX_STAT_ATLAS2,
3659 DIV_ATLAS0,
3660 DIV_ATLAS1,
3661 DIV_ATLAS_PLL_FREQ_DET,
3662 DIV_STAT_ATLAS0,
3663 DIV_STAT_ATLAS1,
3664 DIV_STAT_ATLAS_PLL_FREQ_DET,
3665 ENABLE_ACLK_ATLAS,
3666 ENABLE_PCLK_ATLAS,
3667 ENABLE_SCLK_ATLAS,
3668 ENABLE_IP_ATLAS0,
3669 ENABLE_IP_ATLAS1,
3670 CLKOUT_CMU_ATLAS,
3671 CLKOUT_CMU_ATLAS_DIV_STAT,
3672 ARMCLK_STOPCTRL,
3673 ATLAS_PWR_CTRL,
3674 ATLAS_PWR_CTRL2,
3675 ATLAS_INTR_SPREAD_ENABLE,
3676 ATLAS_INTR_SPREAD_USE_STANDBYWFI,
3677 ATLAS_INTR_SPREAD_BLOCKING_DURATION,
3678};
3679
3680/* list of all parent clock list */
3681PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", };
3682PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
3683PNAME(mout_atlas_p) = { "mout_atlas_pll",
3684 "mout_bus_pll_atlas_user", };
3685
3686static struct samsung_pll_clock atlas_pll_clks[] __initdata = {
3687 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3688 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates),
3689};
3690
3691static struct samsung_mux_clock atlas_mux_clks[] __initdata = {
3692 /* MUX_SEL_ATLAS0 */
3693 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3694 MUX_SEL_ATLAS0, 0, 1, 0, CLK_MUX_READ_ONLY),
3695
3696 /* MUX_SEL_ATLAS1 */
3697 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
3698 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3699
3700 /* MUX_SEL_ATLAS2 */
3701 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
3702 0, 1, 0, CLK_MUX_READ_ONLY),
3703};
3704
3705static struct samsung_div_clock atlas_div_clks[] __initdata = {
3706 /* DIV_ATLAS0 */
3707 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3708 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
3709 CLK_DIVIDER_READ_ONLY),
3710 DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
3711 DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
3712 CLK_DIVIDER_READ_ONLY),
3713 DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
3714 DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
3715 CLK_DIVIDER_READ_ONLY),
3716 DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
3717 DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
3718 CLK_DIVIDER_READ_ONLY),
3719 DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
3720 DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
3721 CLK_DIVIDER_READ_ONLY),
3722 DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
3723 DIV_ATLAS0, 4, 3, CLK_GET_RATE_NOCACHE,
3724 CLK_DIVIDER_READ_ONLY),
3725 DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
3726 DIV_ATLAS0, 0, 3, CLK_GET_RATE_NOCACHE,
3727 CLK_DIVIDER_READ_ONLY),
3728
3729 /* DIV_ATLAS1 */
3730 DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
3731 DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
3732 CLK_DIVIDER_READ_ONLY),
3733 DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
3734 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3735 CLK_DIVIDER_READ_ONLY),
3736};
3737
3738static struct samsung_gate_clock atlas_gate_clks[] __initdata = {
3739 /* ENABLE_ACLK_ATLAS */
3740 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3741 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3742 9, CLK_IGNORE_UNUSED, 0),
3743 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
3744 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3745 8, CLK_IGNORE_UNUSED, 0),
3746 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
3747 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3748 7, CLK_IGNORE_UNUSED, 0),
3749 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
3750 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3751 6, CLK_IGNORE_UNUSED, 0),
3752 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
3753 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3754 5, CLK_IGNORE_UNUSED, 0),
3755 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
3756 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3757 4, CLK_IGNORE_UNUSED, 0),
3758 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
3759 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3760 3, CLK_IGNORE_UNUSED, 0),
3761 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
3762 "div_aclk_atlas", ENABLE_ACLK_ATLAS,
3763 2, CLK_IGNORE_UNUSED, 0),
3764 GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3765 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3766 GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
3767 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3768
3769 /* ENABLE_PCLK_ATLAS */
3770 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
3771 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3772 5, CLK_IGNORE_UNUSED, 0),
3773 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
3774 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3775 4, CLK_IGNORE_UNUSED, 0),
3776 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
3777 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3778 3, CLK_IGNORE_UNUSED, 0),
3779 GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
3780 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3781 GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
3782 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3783 GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
3784 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3785
3786 /* ENABLE_SCLK_ATLAS */
3787 GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
3788 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3789 GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3790 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3791 GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
3792 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3793 GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
3794 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3795 GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
3796 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3797 GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3798 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3799 GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
3800 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3801 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3802 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3803 GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2",
3804 ENABLE_SCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3805};
3806
3807static struct samsung_cmu_info atlas_cmu_info __initdata = {
3808 .pll_clks = atlas_pll_clks,
3809 .nr_pll_clks = ARRAY_SIZE(atlas_pll_clks),
3810 .mux_clks = atlas_mux_clks,
3811 .nr_mux_clks = ARRAY_SIZE(atlas_mux_clks),
3812 .div_clks = atlas_div_clks,
3813 .nr_div_clks = ARRAY_SIZE(atlas_div_clks),
3814 .gate_clks = atlas_gate_clks,
3815 .nr_gate_clks = ARRAY_SIZE(atlas_gate_clks),
3816 .nr_clk_ids = ATLAS_NR_CLK,
3817 .clk_regs = atlas_clk_regs,
3818 .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs),
3819};
3820
3821static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3822{
3823 samsung_cmu_register_one(np, &atlas_cmu_info);
3824}
3825CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3826 exynos5433_cmu_atlas_init);
b274bbfd
CC		 3827
3828/*
3829 * Register offset definitions for CMU_MSCL
3830 */
3831#define MUX_SEL_MSCL0 0x0200
3832#define MUX_SEL_MSCL1 0x0204
3833#define MUX_ENABLE_MSCL0 0x0300
3834#define MUX_ENABLE_MSCL1 0x0304
3835#define MUX_STAT_MSCL0 0x0400
3836#define MUX_STAT_MSCL1 0x0404
3837#define DIV_MSCL 0x0600
3838#define DIV_STAT_MSCL 0x0700
3839#define ENABLE_ACLK_MSCL 0x0800
3840#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
3841#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
3842#define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
3843#define ENABLE_PCLK_MSCL 0x0900
3844#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
3845#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
3846#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x000c
3847#define ENABLE_SCLK_MSCL 0x0a00
3848#define ENABLE_IP_MSCL0 0x0b00
3849#define ENABLE_IP_MSCL1 0x0b04
3850#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
3851#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
3852#define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
3853
3854static unsigned long mscl_clk_regs[] __initdata = {
3855 MUX_SEL_MSCL0,
3856 MUX_SEL_MSCL1,
3857 MUX_ENABLE_MSCL0,
3858 MUX_ENABLE_MSCL1,
3859 MUX_STAT_MSCL0,
3860 MUX_STAT_MSCL1,
3861 DIV_MSCL,
3862 DIV_STAT_MSCL,
3863 ENABLE_ACLK_MSCL,
3864 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
3865 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
3866 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
3867 ENABLE_PCLK_MSCL,
3868 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
3869 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
3870 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
3871 ENABLE_SCLK_MSCL,
3872 ENABLE_IP_MSCL0,
3873 ENABLE_IP_MSCL1,
3874 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
3875 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
3876 ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
3877};
3878
3879/* list of all parent clock list */
3880PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", };
3881PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
3882PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
3883 "mout_aclk_mscl_400_user", };
3884
3885static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
3886 /* MUX_SEL_MSCL0 */
3887 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
3888 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
3889 MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
3890 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
3891
3892 /* MUX_SEL_MSCL1 */
3893 MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
3894 MUX_SEL_MSCL1, 0, 1),
3895};
3896
3897static struct samsung_div_clock mscl_div_clks[] __initdata = {
3898 /* DIV_MSCL */
3899 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
3900 DIV_MSCL, 0, 3),
3901};
3902
3903static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
3904 /* ENABLE_ACLK_MSCL */
3905 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
3906 ENABLE_ACLK_MSCL, 9, 0, 0),
3907 GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
3908 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
3909 GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
3910 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
3911 GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
3912 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
3913 GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
3914 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
3915 GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
3916 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
3917 GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
3918 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
3919 GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
3920 ENABLE_ACLK_MSCL, 2, 0, 0),
3921 GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
3922 ENABLE_ACLK_MSCL, 1, 0, 0),
3923 GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
3924 ENABLE_ACLK_MSCL, 0, 0, 0),
3925
3926 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
3927 GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
3928 "mout_aclk_mscl_400_user",
3929 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
3930 0, CLK_IGNORE_UNUSED, 0),
3931
3932 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
3933 GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
3934 "mout_aclk_mscl_400_user",
3935 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
3936 0, CLK_IGNORE_UNUSED, 0),
3937
3938 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
3939 GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
3940 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
3941 0, CLK_IGNORE_UNUSED, 0),
3942
3943 /* ENABLE_PCLK_MSCL */
3944 GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
3945 ENABLE_PCLK_MSCL, 7, 0, 0),
3946 GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
3947 ENABLE_PCLK_MSCL, 6, 0, 0),
3948 GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
3949 ENABLE_PCLK_MSCL, 5, 0, 0),
3950 GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
3951 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
3952 GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
3953 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
3954 GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
3955 ENABLE_PCLK_MSCL, 2, 0, 0),
3956 GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
3957 ENABLE_PCLK_MSCL, 1, 0, 0),
3958 GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
3959 ENABLE_PCLK_MSCL, 0, 0, 0),
3960
3961 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
3962 GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
3963 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
3964 0, CLK_IGNORE_UNUSED, 0),
3965
3966 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
3967 GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
3968 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
3969 0, CLK_IGNORE_UNUSED, 0),
3970
3971 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
3972 GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
3973 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
3974 0, CLK_IGNORE_UNUSED, 0),
3975
3976 /* ENABLE_SCLK_MSCL */
3977 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
3978 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3979};
3980
3981static struct samsung_cmu_info mscl_cmu_info __initdata = {
3982 .mux_clks = mscl_mux_clks,
3983 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
3984 .div_clks = mscl_div_clks,
3985 .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
3986 .gate_clks = mscl_gate_clks,
3987 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
3988 .nr_clk_ids = MSCL_NR_CLK,
3989 .clk_regs = mscl_clk_regs,
3990 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
3991};
3992
3993static void __init exynos5433_cmu_mscl_init(struct device_node *np)
3994{
3995 samsung_cmu_register_one(np, &mscl_cmu_info);
3996}
3997CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
3998 exynos5433_cmu_mscl_init);
9910b6bb
CC		 3999
4000/*
4001 * Register offset definitions for CMU_MFC
4002 */
4003#define MUX_SEL_MFC 0x0200
4004#define MUX_ENABLE_MFC 0x0300
4005#define MUX_STAT_MFC 0x0400
4006#define DIV_MFC 0x0600
4007#define DIV_STAT_MFC 0x0700
4008#define ENABLE_ACLK_MFC 0x0800
4009#define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
4010#define ENABLE_PCLK_MFC 0x0900
4011#define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
4012#define ENABLE_IP_MFC0 0x0b00
4013#define ENABLE_IP_MFC1 0x0b04
4014#define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4015
4016static unsigned long mfc_clk_regs[] __initdata = {
4017 MUX_SEL_MFC,
4018 MUX_ENABLE_MFC,
4019 MUX_STAT_MFC,
4020 DIV_MFC,
4021 DIV_STAT_MFC,
4022 ENABLE_ACLK_MFC,
4023 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4024 ENABLE_PCLK_MFC,
4025 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4026 ENABLE_IP_MFC0,
4027 ENABLE_IP_MFC1,
4028 ENABLE_IP_MFC_SECURE_SMMU_MFC,
4029};
4030
4031PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
4032
4033static struct samsung_mux_clock mfc_mux_clks[] __initdata = {
4034 /* MUX_SEL_MFC */
4035 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4036 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4037};
4038
4039static struct samsung_div_clock mfc_div_clks[] __initdata = {
4040 /* DIV_MFC */
4041 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4042 DIV_MFC, 0, 2),
4043};
4044
4045static struct samsung_gate_clock mfc_gate_clks[] __initdata = {
4046 /* ENABLE_ACLK_MFC */
4047 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4048 ENABLE_ACLK_MFC, 6, 0, 0),
4049 GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4050 ENABLE_ACLK_MFC, 5, 0, 0),
4051 GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4052 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4053 GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4054 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4055 GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
4056 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4057 GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4058 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4059 GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
4060 ENABLE_ACLK_MFC, 0, 0, 0),
4061
4062 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4063 GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4064 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4065 1, CLK_IGNORE_UNUSED, 0),
4066 GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4067 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4068 0, CLK_IGNORE_UNUSED, 0),
4069
4070 /* ENABLE_PCLK_MFC */
4071 GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
4072 ENABLE_PCLK_MFC, 4, 0, 0),
4073 GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
4074 ENABLE_PCLK_MFC, 3, 0, 0),
4075 GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
4076 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4077 GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
4078 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4079 GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
4080 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4081
4082 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4083 GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
4084 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4085 1, CLK_IGNORE_UNUSED, 0),
4086 GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
4087 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4088 0, CLK_IGNORE_UNUSED, 0),
4089};
4090
4091static struct samsung_cmu_info mfc_cmu_info __initdata = {
4092 .mux_clks = mfc_mux_clks,
4093 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
4094 .div_clks = mfc_div_clks,
4095 .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
4096 .gate_clks = mfc_gate_clks,
4097 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
4098 .nr_clk_ids = MFC_NR_CLK,
4099 .clk_regs = mfc_clk_regs,
4100 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
4101};
4102
4103static void __init exynos5433_cmu_mfc_init(struct device_node *np)
4104{
4105 samsung_cmu_register_one(np, &mfc_cmu_info);
4106}
4107CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
4108 exynos5433_cmu_mfc_init);
45e58aa5
CC		 4109
4110/*
4111 * Register offset definitions for CMU_HEVC
4112 */
4113#define MUX_SEL_HEVC 0x0200
4114#define MUX_ENABLE_HEVC 0x0300
4115#define MUX_STAT_HEVC 0x0400
4116#define DIV_HEVC 0x0600
4117#define DIV_STAT_HEVC 0x0700
4118#define ENABLE_ACLK_HEVC 0x0800
4119#define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
4120#define ENABLE_PCLK_HEVC 0x0900
4121#define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
4122#define ENABLE_IP_HEVC0 0x0b00
4123#define ENABLE_IP_HEVC1 0x0b04
4124#define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
4125
4126static unsigned long hevc_clk_regs[] __initdata = {
4127 MUX_SEL_HEVC,
4128 MUX_ENABLE_HEVC,
4129 MUX_STAT_HEVC,
4130 DIV_HEVC,
4131 DIV_STAT_HEVC,
4132 ENABLE_ACLK_HEVC,
4133 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4134 ENABLE_PCLK_HEVC,
4135 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4136 ENABLE_IP_HEVC0,
4137 ENABLE_IP_HEVC1,
4138 ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
4139};
4140
4141PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
4142
4143static struct samsung_mux_clock hevc_mux_clks[] __initdata = {
4144 /* MUX_SEL_HEVC */
4145 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4146 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4147};
4148
4149static struct samsung_div_clock hevc_div_clks[] __initdata = {
4150 /* DIV_HEVC */
4151 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4152 DIV_HEVC, 0, 2),
4153};
4154
4155static struct samsung_gate_clock hevc_gate_clks[] __initdata = {
4156 /* ENABLE_ACLK_HEVC */
4157 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4158 ENABLE_ACLK_HEVC, 6, 0, 0),
4159 GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
4160 ENABLE_ACLK_HEVC, 5, 0, 0),
4161 GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
4162 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4163 GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
4164 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4165 GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
4166 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4167 GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
4168 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4169 GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
4170 ENABLE_ACLK_HEVC, 0, 0, 0),
4171
4172 /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
4173 GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
4174 "mout_aclk_hevc_400_user",
4175 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4176 1, CLK_IGNORE_UNUSED, 0),
4177 GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
4178 "mout_aclk_hevc_400_user",
4179 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4180 0, CLK_IGNORE_UNUSED, 0),
4181
4182 /* ENABLE_PCLK_HEVC */
4183 GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
4184 ENABLE_PCLK_HEVC, 4, 0, 0),
4185 GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
4186 ENABLE_PCLK_HEVC, 3, 0, 0),
4187 GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
4188 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4189 GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
4190 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4191 GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
4192 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4193
4194 /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
4195 GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
4196 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4197 1, CLK_IGNORE_UNUSED, 0),
4198 GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
4199 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4200 0, CLK_IGNORE_UNUSED, 0),
4201};
4202
4203static struct samsung_cmu_info hevc_cmu_info __initdata = {
4204 .mux_clks = hevc_mux_clks,
4205 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
4206 .div_clks = hevc_div_clks,
4207 .nr_div_clks = ARRAY_SIZE(hevc_div_clks),
4208 .gate_clks = hevc_gate_clks,
4209 .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
4210 .nr_clk_ids = HEVC_NR_CLK,
4211 .clk_regs = hevc_clk_regs,
4212 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
4213};
4214
4215static void __init exynos5433_cmu_hevc_init(struct device_node *np)
4216{
4217 samsung_cmu_register_one(np, &hevc_cmu_info);
4218}
4219CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
4220 exynos5433_cmu_hevc_init);
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