]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/clk/samsung/clk-exynos5433.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
clk: samsung: exynos5433: Add clocks for CMU_MFC domain
[mirror_ubuntu-hirsute-kernel.git] / drivers / clk / samsung / clk-exynos5433.c
CommitLineData
96bd6224
CC		 1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos5443 SoC.
10 */
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of.h>
16
17#include <dt-bindings/clock/exynos5433.h>
18
19#include "clk.h"
20#include "clk-pll.h"
21
22/*
23 * Register offset definitions for CMU_TOP
24 */
25#define ISP_PLL_LOCK 0x0000
26#define AUD_PLL_LOCK 0x0004
27#define ISP_PLL_CON0 0x0100
28#define ISP_PLL_CON1 0x0104
29#define ISP_PLL_FREQ_DET 0x0108
30#define AUD_PLL_CON0 0x0110
31#define AUD_PLL_CON1 0x0114
32#define AUD_PLL_CON2 0x0118
33#define AUD_PLL_FREQ_DET 0x011c
34#define MUX_SEL_TOP0 0x0200
35#define MUX_SEL_TOP1 0x0204
36#define MUX_SEL_TOP2 0x0208
37#define MUX_SEL_TOP3 0x020c
38#define MUX_SEL_TOP4 0x0210
39#define MUX_SEL_TOP_MSCL 0x0220
40#define MUX_SEL_TOP_CAM1 0x0224
41#define MUX_SEL_TOP_DISP 0x0228
42#define MUX_SEL_TOP_FSYS0 0x0230
43#define MUX_SEL_TOP_FSYS1 0x0234
44#define MUX_SEL_TOP_PERIC0 0x0238
45#define MUX_SEL_TOP_PERIC1 0x023c
46#define MUX_ENABLE_TOP0 0x0300
47#define MUX_ENABLE_TOP1 0x0304
48#define MUX_ENABLE_TOP2 0x0308
49#define MUX_ENABLE_TOP3 0x030c
50#define MUX_ENABLE_TOP4 0x0310
51#define MUX_ENABLE_TOP_MSCL 0x0320
52#define MUX_ENABLE_TOP_CAM1 0x0324
53#define MUX_ENABLE_TOP_DISP 0x0328
54#define MUX_ENABLE_TOP_FSYS0 0x0330
55#define MUX_ENABLE_TOP_FSYS1 0x0334
56#define MUX_ENABLE_TOP_PERIC0 0x0338
57#define MUX_ENABLE_TOP_PERIC1 0x033c
58#define MUX_STAT_TOP0 0x0400
59#define MUX_STAT_TOP1 0x0404
60#define MUX_STAT_TOP2 0x0408
61#define MUX_STAT_TOP3 0x040c
62#define MUX_STAT_TOP4 0x0410
63#define MUX_STAT_TOP_MSCL 0x0420
64#define MUX_STAT_TOP_CAM1 0x0424
65#define MUX_STAT_TOP_FSYS0 0x0430
66#define MUX_STAT_TOP_FSYS1 0x0434
67#define MUX_STAT_TOP_PERIC0 0x0438
68#define MUX_STAT_TOP_PERIC1 0x043c
69#define DIV_TOP0 0x0600
70#define DIV_TOP1 0x0604
71#define DIV_TOP2 0x0608
72#define DIV_TOP3 0x060c
73#define DIV_TOP4 0x0610
74#define DIV_TOP_MSCL 0x0618
75#define DIV_TOP_CAM10 0x061c
76#define DIV_TOP_CAM11 0x0620
77#define DIV_TOP_FSYS0 0x062c
78#define DIV_TOP_FSYS1 0x0630
79#define DIV_TOP_FSYS2 0x0634
80#define DIV_TOP_PERIC0 0x0638
81#define DIV_TOP_PERIC1 0x063c
82#define DIV_TOP_PERIC2 0x0640
83#define DIV_TOP_PERIC3 0x0644
84#define DIV_TOP_PERIC4 0x0648
85#define DIV_TOP_PLL_FREQ_DET 0x064c
86#define DIV_STAT_TOP0 0x0700
87#define DIV_STAT_TOP1 0x0704
88#define DIV_STAT_TOP2 0x0708
89#define DIV_STAT_TOP3 0x070c
90#define DIV_STAT_TOP4 0x0710
91#define DIV_STAT_TOP_MSCL 0x0718
92#define DIV_STAT_TOP_CAM10 0x071c
93#define DIV_STAT_TOP_CAM11 0x0720
94#define DIV_STAT_TOP_FSYS0 0x072c
95#define DIV_STAT_TOP_FSYS1 0x0730
96#define DIV_STAT_TOP_FSYS2 0x0734
97#define DIV_STAT_TOP_PERIC0 0x0738
98#define DIV_STAT_TOP_PERIC1 0x073c
99#define DIV_STAT_TOP_PERIC2 0x0740
100#define DIV_STAT_TOP_PERIC3 0x0744
101#define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
102#define ENABLE_ACLK_TOP 0x0800
103#define ENABLE_SCLK_TOP 0x0a00
104#define ENABLE_SCLK_TOP_MSCL 0x0a04
105#define ENABLE_SCLK_TOP_CAM1 0x0a08
106#define ENABLE_SCLK_TOP_DISP 0x0a0c
107#define ENABLE_SCLK_TOP_FSYS 0x0a10
108#define ENABLE_SCLK_TOP_PERIC 0x0a14
109#define ENABLE_IP_TOP 0x0b00
110#define ENABLE_CMU_TOP 0x0c00
111#define ENABLE_CMU_TOP_DIV_STAT 0x0c04
112
113static unsigned long top_clk_regs[] __initdata = {
114 ISP_PLL_LOCK,
115 AUD_PLL_LOCK,
116 ISP_PLL_CON0,
117 ISP_PLL_CON1,
118 ISP_PLL_FREQ_DET,
119 AUD_PLL_CON0,
120 AUD_PLL_CON1,
121 AUD_PLL_CON2,
122 AUD_PLL_FREQ_DET,
123 MUX_SEL_TOP0,
124 MUX_SEL_TOP1,
125 MUX_SEL_TOP2,
126 MUX_SEL_TOP3,
127 MUX_SEL_TOP4,
128 MUX_SEL_TOP_MSCL,
129 MUX_SEL_TOP_CAM1,
130 MUX_SEL_TOP_DISP,
131 MUX_SEL_TOP_FSYS0,
132 MUX_SEL_TOP_FSYS1,
133 MUX_SEL_TOP_PERIC0,
134 MUX_SEL_TOP_PERIC1,
135 MUX_ENABLE_TOP0,
136 MUX_ENABLE_TOP1,
137 MUX_ENABLE_TOP2,
138 MUX_ENABLE_TOP3,
139 MUX_ENABLE_TOP4,
140 MUX_ENABLE_TOP_MSCL,
141 MUX_ENABLE_TOP_CAM1,
142 MUX_ENABLE_TOP_DISP,
143 MUX_ENABLE_TOP_FSYS0,
144 MUX_ENABLE_TOP_FSYS1,
145 MUX_ENABLE_TOP_PERIC0,
146 MUX_ENABLE_TOP_PERIC1,
147 MUX_STAT_TOP0,
148 MUX_STAT_TOP1,
149 MUX_STAT_TOP2,
150 MUX_STAT_TOP3,
151 MUX_STAT_TOP4,
152 MUX_STAT_TOP_MSCL,
153 MUX_STAT_TOP_CAM1,
154 MUX_STAT_TOP_FSYS0,
155 MUX_STAT_TOP_FSYS1,
156 MUX_STAT_TOP_PERIC0,
157 MUX_STAT_TOP_PERIC1,
158 DIV_TOP0,
159 DIV_TOP1,
160 DIV_TOP2,
161 DIV_TOP3,
162 DIV_TOP4,
163 DIV_TOP_MSCL,
164 DIV_TOP_CAM10,
165 DIV_TOP_CAM11,
166 DIV_TOP_FSYS0,
167 DIV_TOP_FSYS1,
168 DIV_TOP_FSYS2,
169 DIV_TOP_PERIC0,
170 DIV_TOP_PERIC1,
171 DIV_TOP_PERIC2,
172 DIV_TOP_PERIC3,
173 DIV_TOP_PERIC4,
174 DIV_TOP_PLL_FREQ_DET,
175 DIV_STAT_TOP0,
176 DIV_STAT_TOP1,
177 DIV_STAT_TOP2,
178 DIV_STAT_TOP3,
179 DIV_STAT_TOP4,
180 DIV_STAT_TOP_MSCL,
181 DIV_STAT_TOP_CAM10,
182 DIV_STAT_TOP_CAM11,
183 DIV_STAT_TOP_FSYS0,
184 DIV_STAT_TOP_FSYS1,
185 DIV_STAT_TOP_FSYS2,
186 DIV_STAT_TOP_PERIC0,
187 DIV_STAT_TOP_PERIC1,
188 DIV_STAT_TOP_PERIC2,
189 DIV_STAT_TOP_PERIC3,
190 DIV_STAT_TOP_PLL_FREQ_DET,
191 ENABLE_ACLK_TOP,
192 ENABLE_SCLK_TOP,
193 ENABLE_SCLK_TOP_MSCL,
194 ENABLE_SCLK_TOP_CAM1,
195 ENABLE_SCLK_TOP_DISP,
196 ENABLE_SCLK_TOP_FSYS,
197 ENABLE_SCLK_TOP_PERIC,
198 ENABLE_IP_TOP,
199 ENABLE_CMU_TOP,
200 ENABLE_CMU_TOP_DIV_STAT,
201};
202
203/* list of all parent clock list */
204PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
205PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
206PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
207PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
208PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
209PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
210PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
23236496 211PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
96bd6224
CC		 212
213PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
214PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
215PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
216 "mout_mfc_pll_user", };
217PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
218
23236496
CC		 219PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
220 "mout_mphy_pll_user", };
221PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
222 "mout_bus_pll_user", };
223PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
224
96bd6224
CC		 225PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
226 "mout_mphy_pll_user", };
227PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
228 "mout_mphy_pll_user", };
229PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a",
230 "mout_mphy_pll_user", };
231
232PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
233PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
234
235PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
236PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
237PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
238PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
239PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
240
23236496
CC		 241PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
242 "oscclk", "ioclk_spdif_extclk", };
243PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
244 "mout_aud_pll_user_t",};
245PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
246 "mout_aud_pll_user_t",};
247
2a1808a6
CC		 248PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
249
56bcf3f3
CC		 250static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
251 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
252};
253
23236496
CC		 254static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
255 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
256 FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000),
257 FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),
258 /* Xi2s1SDI input clock for SPDIF */
259 FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000),
d0f5de66
CC		 260 /* XspiCLK[4:0] input clock for SPI */
261 FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000),
262 FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000),
263 FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000),
264 FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000),
265 FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000),
266 /* Xi2s1SCLK input clock for I2S1_BCLK */
267 FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000),
23236496
CC		 268};
269
96bd6224
CC		 270static struct samsung_mux_clock top_mux_clks[] __initdata = {
271 /* MUX_SEL_TOP0 */
272 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
273 4, 1),
274 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
275 0, 1),
276
277 /* MUX_SEL_TOP1 */
278 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
279 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
280 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
281 MUX_SEL_TOP1, 8, 1),
282 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
283 MUX_SEL_TOP1, 4, 1),
284 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
285 MUX_SEL_TOP1, 0, 1),
286
287 /* MUX_SEL_TOP2 */
288 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
289 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
290 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
291 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
292 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
293 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
294 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
295 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
296 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
297 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
298 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
299 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
300
301 /* MUX_SEL_TOP3 */
302 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
303 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
304 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
305 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
306 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
307 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
308 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
309 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
310 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
311 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
312 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
313 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
314
23236496
CC		 315 /* MUX_SEL_TOP4 */
316 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
317 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
318 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
319 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
320 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
321 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
322
96bd6224
CC		 323 /* MUX_SEL_TOP_MSCL */
324 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
325 MUX_SEL_TOP_MSCL, 8, 1),
326 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
327 MUX_SEL_TOP_MSCL, 4, 1),
328 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
329 MUX_SEL_TOP_MSCL, 0, 1),
330
23236496
CC		 331 /* MUX_SEL_TOP_CAM1 */
332 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
333 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
334 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
335 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
336 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
337 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
338 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
339 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
340 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
341 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
342 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
343 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
344
96bd6224
CC		 345 /* MUX_SEL_TOP_FSYS0 */
346 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
347 MUX_SEL_TOP_FSYS0, 28, 1),
348 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
349 MUX_SEL_TOP_FSYS0, 24, 1),
350 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
351 MUX_SEL_TOP_FSYS0, 20, 1),
352 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
353 MUX_SEL_TOP_FSYS0, 16, 1),
354 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
355 MUX_SEL_TOP_FSYS0, 12, 1),
356 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
357 MUX_SEL_TOP_FSYS0, 8, 1),
358 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
359 MUX_SEL_TOP_FSYS0, 4, 1),
360 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
361 MUX_SEL_TOP_FSYS0, 0, 1),
362
23236496
CC		 363 /* MUX_SEL_TOP_FSYS1 */
364 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
365 MUX_SEL_TOP_FSYS1, 12, 1),
366 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
367 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
368 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
369 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
370 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
371 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
372
96bd6224
CC		 373 /* MUX_SEL_TOP_PERIC0 */
374 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
375 MUX_SEL_TOP_PERIC0, 28, 1),
376 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
377 MUX_SEL_TOP_PERIC0, 24, 1),
378 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
379 MUX_SEL_TOP_PERIC0, 20, 1),
380 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
381 MUX_SEL_TOP_PERIC0, 16, 1),
382 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
383 MUX_SEL_TOP_PERIC0, 12, 1),
384 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
385 MUX_SEL_TOP_PERIC0, 8, 1),
386 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
387 MUX_SEL_TOP_PERIC0, 4, 1),
388 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
389 MUX_SEL_TOP_PERIC0, 0, 1),
23236496
CC		 390
391 /* MUX_SEL_TOP_PERIC1 */
392 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
393 MUX_SEL_TOP_PERIC1, 16, 1),
394 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
395 MUX_SEL_TOP_PERIC1, 12, 2),
396 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
397 MUX_SEL_TOP_PERIC1, 4, 2),
398 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
399 MUX_SEL_TOP_PERIC1, 0, 2),
2a1808a6
CC		 400
401 /* MUX_SEL_TOP_DISP */
402 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
403 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
96bd6224
CC		 404};
405
406static struct samsung_div_clock top_div_clks[] __initdata = {
a29308da
CC		 407 /* DIV_TOP1 */
408 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
409 DIV_TOP1, 28, 3),
410 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
411 DIV_TOP1, 24, 3),
412 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
413 DIV_TOP1, 20, 3),
414 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
415 DIV_TOP1, 12, 3),
416 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
417 DIV_TOP1, 8, 3),
418 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
419 DIV_TOP1, 0, 3),
420
96bd6224 421 /* DIV_TOP2 */
b274bbfd
CC		 422 DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
423 DIV_TOP2, 4, 3),
96bd6224
CC		 424 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
425 DIV_TOP2, 0, 3),
426
427 /* DIV_TOP3 */
428 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
429 "mout_bus_pll_user", DIV_TOP3, 24, 3),
430 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
431 "mout_bus_pll_user", DIV_TOP3, 20, 3),
432 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
433 "mout_bus_pll_user", DIV_TOP3, 16, 3),
434 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
435 "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
436 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
437 "mout_bus_pll_user", DIV_TOP3, 8, 3),
438 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
439 "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
440 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
441 "mout_bus_pll_user", DIV_TOP3, 0, 3),
442
5785d6e6
CC		 443 /* DIV_TOP4 */
444 DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
445 DIV_TOP4, 8, 3),
446 DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
447 DIV_TOP4, 4, 3),
448 DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
449 DIV_TOP4, 0, 3),
450
b274bbfd
CC		 451 /* DIV_TOP_MSCL */
452 DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
453 DIV_TOP_MSCL, 0, 4),
454
96bd6224
CC		 455 /* DIV_TOP_FSYS0 */
456 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
457 DIV_TOP_FSYS0, 16, 8),
458 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
459 DIV_TOP_FSYS0, 12, 4),
460 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
461 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
462 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
463 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
464
465 /* DIV_TOP_FSYS1 */
466 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
467 DIV_TOP_FSYS1, 4, 8),
468 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
469 DIV_TOP_FSYS1, 0, 4),
470
4b801355
CC		 471 /* DIV_TOP_FSYS2 */
472 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
473 DIV_TOP_FSYS2, 12, 3),
474 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
475 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
476 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
477 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
478 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
479 DIV_TOP_FSYS2, 0, 4),
480
96bd6224
CC		 481 /* DIV_TOP_PERIC0 */
482 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
483 DIV_TOP_PERIC0, 16, 8),
484 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
485 DIV_TOP_PERIC0, 12, 4),
486 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
487 DIV_TOP_PERIC0, 4, 8),
488 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
489 DIV_TOP_PERIC0, 0, 4),
490
491 /* DIV_TOP_PERIC1 */
492 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
493 DIV_TOP_PERIC1, 4, 8),
494 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
495 DIV_TOP_PERIC1, 0, 4),
496
497 /* DIV_TOP_PERIC2 */
498 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
499 DIV_TOP_PERIC2, 8, 4),
500 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
501 DIV_TOP_PERIC2, 4, 4),
502 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
503 DIV_TOP_PERIC2, 0, 4),
504
23236496
CC		 505 /* DIV_TOP_PERIC3 */
506 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
507 DIV_TOP_PERIC3, 16, 6),
508 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
509 DIV_TOP_PERIC3, 8, 8),
510 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
511 DIV_TOP_PERIC3, 4, 4),
512 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
513 DIV_TOP_PERIC3, 0, 4),
514
96bd6224
CC		 515 /* DIV_TOP_PERIC4 */
516 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
517 DIV_TOP_PERIC4, 16, 8),
518 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
519 DIV_TOP_PERIC4, 12, 4),
520 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
521 DIV_TOP_PERIC4, 4, 8),
522 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
523 DIV_TOP_PERIC4, 0, 4),
524};
525
526static struct samsung_gate_clock top_gate_clks[] __initdata = {
527 /* ENABLE_ACLK_TOP */
5785d6e6
CC		 528 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
529 ENABLE_ACLK_TOP, 30, 0, 0),
530 GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
531 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
532 29, CLK_IGNORE_UNUSED, 0),
533 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
534 ENABLE_ACLK_TOP, 26,
535 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
536 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
537 ENABLE_ACLK_TOP, 25,
538 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
539 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
540 ENABLE_ACLK_TOP, 24,
541 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
542 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
543 ENABLE_ACLK_TOP, 23,
544 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
96bd6224
CC		 545 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
546 ENABLE_ACLK_TOP, 22,
547 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
548 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
549 ENABLE_ACLK_TOP, 21,
550 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
b274bbfd
CC		 551 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
552 ENABLE_ACLK_TOP, 19,
553 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
96bd6224
CC		 554 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
555 ENABLE_ACLK_TOP, 18,
556 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
2a2f33e8
CC		 557 GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
558 ENABLE_ACLK_TOP, 15,
559 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
560 GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
561 ENABLE_ACLK_TOP, 14,
562 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
9910b6bb
CC		 563 GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
564 ENABLE_ACLK_TOP, 3,
565 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
a29308da
CC		 566 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
567 ENABLE_ACLK_TOP, 2,
568 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
569 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
570 ENABLE_ACLK_TOP, 0,
571 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
96bd6224 572
b274bbfd
CC		 573 /* ENABLE_SCLK_TOP_MSCL */
574 GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
575 ENABLE_SCLK_TOP_MSCL, 0, 0, 0),
576
96bd6224 577 /* ENABLE_SCLK_TOP_FSYS */
4b801355
CC		 578 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
579 ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
96bd6224
CC		 580 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
581 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
582 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
583 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
584 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
585 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
4b801355
CC		 586 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
587 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
588 3, CLK_SET_RATE_PARENT, 0),
589 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
590 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
591 1, CLK_SET_RATE_PARENT, 0),
592 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
593 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
594 0, CLK_SET_RATE_PARENT, 0),
96bd6224
CC		 595
596 /* ENABLE_SCLK_TOP_PERIC */
597 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
598 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
599 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
600 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
23236496
CC		 601 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
602 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
603 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
604 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
605 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
606 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
96bd6224
CC		 607 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
608 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0),
609 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
610 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0),
611 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
612 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0),
613 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
614 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
615 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
616 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
617 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
618 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
23236496
CC		 619
620 /* MUX_ENABLE_TOP_PERIC1 */
621 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
622 MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
623 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
624 MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
625 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
626 MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
96bd6224
CC		 627};
628
629/*
630 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
631 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
632 */
633static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
634 PLL_35XX_RATE(2500000000U, 625, 6, 0),
635 PLL_35XX_RATE(2400000000U, 500, 5, 0),
636 PLL_35XX_RATE(2300000000U, 575, 6, 0),
637 PLL_35XX_RATE(2200000000U, 550, 6, 0),
638 PLL_35XX_RATE(2100000000U, 350, 4, 0),
639 PLL_35XX_RATE(2000000000U, 500, 6, 0),
640 PLL_35XX_RATE(1900000000U, 475, 6, 0),
641 PLL_35XX_RATE(1800000000U, 375, 5, 0),
642 PLL_35XX_RATE(1700000000U, 425, 6, 0),
643 PLL_35XX_RATE(1600000000U, 400, 6, 0),
644 PLL_35XX_RATE(1500000000U, 250, 4, 0),
645 PLL_35XX_RATE(1400000000U, 350, 6, 0),
646 PLL_35XX_RATE(1332000000U, 222, 4, 0),
647 PLL_35XX_RATE(1300000000U, 325, 6, 0),
648 PLL_35XX_RATE(1200000000U, 500, 5, 1),
649 PLL_35XX_RATE(1100000000U, 550, 6, 1),
650 PLL_35XX_RATE(1086000000U, 362, 4, 1),
651 PLL_35XX_RATE(1066000000U, 533, 6, 1),
652 PLL_35XX_RATE(1000000000U, 500, 6, 1),
653 PLL_35XX_RATE(933000000U, 311, 4, 1),
654 PLL_35XX_RATE(921000000U, 307, 4, 1),
655 PLL_35XX_RATE(900000000U, 375, 5, 1),
656 PLL_35XX_RATE(825000000U, 275, 4, 1),
657 PLL_35XX_RATE(800000000U, 400, 6, 1),
658 PLL_35XX_RATE(733000000U, 733, 12, 1),
659 PLL_35XX_RATE(700000000U, 360, 6, 1),
660 PLL_35XX_RATE(667000000U, 222, 4, 1),
661 PLL_35XX_RATE(633000000U, 211, 4, 1),
662 PLL_35XX_RATE(600000000U, 500, 5, 2),
663 PLL_35XX_RATE(552000000U, 460, 5, 2),
664 PLL_35XX_RATE(550000000U, 550, 6, 2),
665 PLL_35XX_RATE(543000000U, 362, 4, 2),
666 PLL_35XX_RATE(533000000U, 533, 6, 2),
667 PLL_35XX_RATE(500000000U, 500, 6, 2),
668 PLL_35XX_RATE(444000000U, 370, 5, 2),
669 PLL_35XX_RATE(420000000U, 350, 5, 2),
670 PLL_35XX_RATE(400000000U, 400, 6, 2),
671 PLL_35XX_RATE(350000000U, 360, 6, 2),
672 PLL_35XX_RATE(333000000U, 222, 4, 2),
673 PLL_35XX_RATE(300000000U, 500, 5, 3),
674 PLL_35XX_RATE(266000000U, 532, 6, 3),
675 PLL_35XX_RATE(200000000U, 400, 6, 3),
676 PLL_35XX_RATE(166000000U, 332, 6, 3),
677 PLL_35XX_RATE(160000000U, 320, 6, 3),
678 PLL_35XX_RATE(133000000U, 552, 6, 4),
679 PLL_35XX_RATE(100000000U, 400, 6, 4),
680 { /* sentinel */ }
681};
682
683/* AUD_PLL */
684static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
685 PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
686 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
687 PLL_36XX_RATE(384000000U, 128, 2, 2, 0),
688 PLL_36XX_RATE(368640000U, 246, 4, 2, -15729),
689 PLL_36XX_RATE(361507200U, 181, 3, 2, -16148),
690 PLL_36XX_RATE(338688000U, 113, 2, 2, -6816),
691 PLL_36XX_RATE(294912000U, 98, 1, 3, 19923),
692 PLL_36XX_RATE(288000000U, 96, 1, 3, 0),
693 PLL_36XX_RATE(252000000U, 84, 1, 3, 0),
694 { /* sentinel */ }
695};
696
697static struct samsung_pll_clock top_pll_clks[] __initdata = {
698 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
699 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
700 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
701 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
702};
703
704static struct samsung_cmu_info top_cmu_info __initdata = {
705 .pll_clks = top_pll_clks,
706 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
707 .mux_clks = top_mux_clks,
708 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
709 .div_clks = top_div_clks,
710 .nr_div_clks = ARRAY_SIZE(top_div_clks),
711 .gate_clks = top_gate_clks,
712 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
23236496
CC		 713 .fixed_clks = top_fixed_clks,
714 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
56bcf3f3
CC		 715 .fixed_factor_clks = top_fixed_factor_clks,
716 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
96bd6224
CC		 717 .nr_clk_ids = TOP_NR_CLK,
718 .clk_regs = top_clk_regs,
719 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
720};
721
722static void __init exynos5433_cmu_top_init(struct device_node *np)
723{
724 samsung_cmu_register_one(np, &top_cmu_info);
725}
726CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
727 exynos5433_cmu_top_init);
728
729/*
730 * Register offset definitions for CMU_CPIF
731 */
732#define MPHY_PLL_LOCK 0x0000
733#define MPHY_PLL_CON0 0x0100
734#define MPHY_PLL_CON1 0x0104
735#define MPHY_PLL_FREQ_DET 0x010c
736#define MUX_SEL_CPIF0 0x0200
737#define DIV_CPIF 0x0600
738#define ENABLE_SCLK_CPIF 0x0a00
739
740static unsigned long cpif_clk_regs[] __initdata = {
741 MPHY_PLL_LOCK,
742 MPHY_PLL_CON0,
743 MPHY_PLL_CON1,
744 MPHY_PLL_FREQ_DET,
745 MUX_SEL_CPIF0,
746 ENABLE_SCLK_CPIF,
747};
748
749/* list of all parent clock list */
750PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
751
752static struct samsung_pll_clock cpif_pll_clks[] __initdata = {
753 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
754 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
755};
756
757static struct samsung_mux_clock cpif_mux_clks[] __initdata = {
758 /* MUX_SEL_CPIF0 */
759 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
760 0, 1),
761};
762
763static struct samsung_div_clock cpif_div_clks[] __initdata = {
764 /* DIV_CPIF */
765 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
766 0, 6),
767};
768
769static struct samsung_gate_clock cpif_gate_clks[] __initdata = {
770 /* ENABLE_SCLK_CPIF */
771 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
772 ENABLE_SCLK_CPIF, 9, 0, 0),
773 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
774 ENABLE_SCLK_CPIF, 4, 0, 0),
775};
776
777static struct samsung_cmu_info cpif_cmu_info __initdata = {
778 .pll_clks = cpif_pll_clks,
779 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
780 .mux_clks = cpif_mux_clks,
781 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks),
782 .div_clks = cpif_div_clks,
783 .nr_div_clks = ARRAY_SIZE(cpif_div_clks),
784 .gate_clks = cpif_gate_clks,
785 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
786 .nr_clk_ids = CPIF_NR_CLK,
787 .clk_regs = cpif_clk_regs,
788 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
789};
790
791static void __init exynos5433_cmu_cpif_init(struct device_node *np)
792{
793 samsung_cmu_register_one(np, &cpif_cmu_info);
794}
795CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
796 exynos5433_cmu_cpif_init);
797
798/*
799 * Register offset definitions for CMU_MIF
800 */
801#define MEM0_PLL_LOCK 0x0000
802#define MEM1_PLL_LOCK 0x0004
803#define BUS_PLL_LOCK 0x0008
804#define MFC_PLL_LOCK 0x000c
805#define MEM0_PLL_CON0 0x0100
806#define MEM0_PLL_CON1 0x0104
807#define MEM0_PLL_FREQ_DET 0x010c
808#define MEM1_PLL_CON0 0x0110
809#define MEM1_PLL_CON1 0x0114
810#define MEM1_PLL_FREQ_DET 0x011c
811#define BUS_PLL_CON0 0x0120
812#define BUS_PLL_CON1 0x0124
813#define BUS_PLL_FREQ_DET 0x012c
814#define MFC_PLL_CON0 0x0130
815#define MFC_PLL_CON1 0x0134
816#define MFC_PLL_FREQ_DET 0x013c
06d2f9df
CC		 817#define MUX_SEL_MIF0 0x0200
818#define MUX_SEL_MIF1 0x0204
819#define MUX_SEL_MIF2 0x0208
820#define MUX_SEL_MIF3 0x020c
821#define MUX_SEL_MIF4 0x0210
822#define MUX_SEL_MIF5 0x0214
823#define MUX_SEL_MIF6 0x0218
824#define MUX_SEL_MIF7 0x021c
825#define MUX_ENABLE_MIF0 0x0300
826#define MUX_ENABLE_MIF1 0x0304
827#define MUX_ENABLE_MIF2 0x0308
828#define MUX_ENABLE_MIF3 0x030c
829#define MUX_ENABLE_MIF4 0x0310
830#define MUX_ENABLE_MIF5 0x0314
831#define MUX_ENABLE_MIF6 0x0318
832#define MUX_ENABLE_MIF7 0x031c
833#define MUX_STAT_MIF0 0x0400
834#define MUX_STAT_MIF1 0x0404
835#define MUX_STAT_MIF2 0x0408
836#define MUX_STAT_MIF3 0x040c
837#define MUX_STAT_MIF4 0x0410
838#define MUX_STAT_MIF5 0x0414
839#define MUX_STAT_MIF6 0x0418
840#define MUX_STAT_MIF7 0x041c
841#define DIV_MIF1 0x0604
842#define DIV_MIF2 0x0608
843#define DIV_MIF3 0x060c
844#define DIV_MIF4 0x0610
845#define DIV_MIF5 0x0614
846#define DIV_MIF_PLL_FREQ_DET 0x0618
847#define DIV_STAT_MIF1 0x0704
848#define DIV_STAT_MIF2 0x0708
849#define DIV_STAT_MIF3 0x070c
850#define DIV_STAT_MIF4 0x0710
851#define DIV_STAT_MIF5 0x0714
852#define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
853#define ENABLE_ACLK_MIF0 0x0800
854#define ENABLE_ACLK_MIF1 0x0804
855#define ENABLE_ACLK_MIF2 0x0808
856#define ENABLE_ACLK_MIF3 0x080c
857#define ENABLE_PCLK_MIF 0x0900
858#define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
859#define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
860#define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
861#define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
862#define ENABLE_SCLK_MIF 0x0a00
863#define ENABLE_IP_MIF0 0x0b00
864#define ENABLE_IP_MIF1 0x0b04
865#define ENABLE_IP_MIF2 0x0b08
866#define ENABLE_IP_MIF3 0x0b0c
867#define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
868#define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
869#define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
870#define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
871#define CLKOUT_CMU_MIF 0x0c00
872#define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
873#define DREX_FREQ_CTRL0 0x1000
874#define DREX_FREQ_CTRL1 0x1004
875#define PAUSE 0x1008
876#define DDRPHY_LOCK_CTRL 0x100c
96bd6224
CC		 877
878static unsigned long mif_clk_regs[] __initdata = {
879 MEM0_PLL_LOCK,
880 MEM1_PLL_LOCK,
881 BUS_PLL_LOCK,
882 MFC_PLL_LOCK,
883 MEM0_PLL_CON0,
884 MEM0_PLL_CON1,
885 MEM0_PLL_FREQ_DET,
886 MEM1_PLL_CON0,
887 MEM1_PLL_CON1,
888 MEM1_PLL_FREQ_DET,
889 BUS_PLL_CON0,
890 BUS_PLL_CON1,
891 BUS_PLL_FREQ_DET,
892 MFC_PLL_CON0,
893 MFC_PLL_CON1,
894 MFC_PLL_FREQ_DET,
06d2f9df
CC		 895 MUX_SEL_MIF0,
896 MUX_SEL_MIF1,
897 MUX_SEL_MIF2,
898 MUX_SEL_MIF3,
899 MUX_SEL_MIF4,
900 MUX_SEL_MIF5,
901 MUX_SEL_MIF6,
902 MUX_SEL_MIF7,
903 MUX_ENABLE_MIF0,
904 MUX_ENABLE_MIF1,
905 MUX_ENABLE_MIF2,
906 MUX_ENABLE_MIF3,
907 MUX_ENABLE_MIF4,
908 MUX_ENABLE_MIF5,
909 MUX_ENABLE_MIF6,
910 MUX_ENABLE_MIF7,
911 MUX_STAT_MIF0,
912 MUX_STAT_MIF1,
913 MUX_STAT_MIF2,
914 MUX_STAT_MIF3,
915 MUX_STAT_MIF4,
916 MUX_STAT_MIF5,
917 MUX_STAT_MIF6,
918 MUX_STAT_MIF7,
919 DIV_MIF1,
920 DIV_MIF2,
921 DIV_MIF3,
922 DIV_MIF4,
923 DIV_MIF5,
924 DIV_MIF_PLL_FREQ_DET,
925 DIV_STAT_MIF1,
926 DIV_STAT_MIF2,
927 DIV_STAT_MIF3,
928 DIV_STAT_MIF4,
929 DIV_STAT_MIF5,
930 DIV_STAT_MIF_PLL_FREQ_DET,
931 ENABLE_ACLK_MIF0,
932 ENABLE_ACLK_MIF1,
933 ENABLE_ACLK_MIF2,
934 ENABLE_ACLK_MIF3,
935 ENABLE_PCLK_MIF,
936 ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
937 ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
938 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
939 ENABLE_PCLK_MIF_SECURE_RTC,
940 ENABLE_SCLK_MIF,
941 ENABLE_IP_MIF0,
942 ENABLE_IP_MIF1,
943 ENABLE_IP_MIF2,
944 ENABLE_IP_MIF3,
945 ENABLE_IP_MIF_SECURE_DREX0_TZ,
946 ENABLE_IP_MIF_SECURE_DREX1_TZ,
947 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
948 ENABLE_IP_MIF_SECURE_RTC,
949 CLKOUT_CMU_MIF,
950 CLKOUT_CMU_MIF_DIV_STAT,
951 DREX_FREQ_CTRL0,
952 DREX_FREQ_CTRL1,
953 PAUSE,
954 DDRPHY_LOCK_CTRL,
96bd6224
CC		 955};
956
957static struct samsung_pll_clock mif_pll_clks[] __initdata = {
958 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
959 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
960 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
961 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates),
962 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
963 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates),
964 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
965 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
966};
967
06d2f9df
CC		 968/* list of all parent clock list */
969PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", };
970PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", };
971PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
972PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
973PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", };
974PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", };
975PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", };
976PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", };
977
978PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
979PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
980PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
981PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
982
983PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", };
984PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
985
986PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a",
987 "mout_bus_pll_div2", };
988PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
989
990PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
991 "sclk_mphy_pll", };
992PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
993 "mout_mfc_pll_div2", };
994PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", };
995PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
996 "sclk_mphy_pll", };
997PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
998 "mout_mfc_pll_div2", };
999
1000PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
1001 "sclk_mphy_pll", };
1002PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
1003 "mout_mfc_pll_div2", };
1004PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1005PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1006PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", };
1007
1008PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1009PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1010
1011PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
1012 "sclk_mphy_pll", };
1013PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1014 "mout_mfc_pll_div2", };
1015PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1016PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1017
1018static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = {
1019 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1020 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1021 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1022 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1023 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1024};
1025
1026static struct samsung_mux_clock mif_mux_clks[] __initdata = {
1027 /* MUX_SEL_MIF0 */
1028 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1029 MUX_SEL_MIF0, 28, 1),
1030 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
1031 MUX_SEL_MIF0, 24, 1),
1032 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
1033 MUX_SEL_MIF0, 20, 1),
1034 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
1035 MUX_SEL_MIF0, 16, 1),
1036 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
1037 12, 1),
1038 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
1039 8, 1),
1040 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
1041 4, 1),
1042 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
1043 0, 1),
1044
1045 /* MUX_SEL_MIF1 */
1046 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
1047 MUX_SEL_MIF1, 24, 1),
1048 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
1049 MUX_SEL_MIF1, 20, 1),
1050 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
1051 MUX_SEL_MIF1, 16, 1),
1052 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
1053 MUX_SEL_MIF1, 12, 1),
1054 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
1055 MUX_SEL_MIF1, 8, 1),
1056 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
1057 MUX_SEL_MIF1, 4, 1),
1058
1059 /* MUX_SEL_MIF2 */
1060 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
1061 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
1062 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
1063 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1064
1065 /* MUX_SEL_MIF3 */
1066 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
1067 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
1068 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
1069 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1070
1071 /* MUX_SEL_MIF4 */
1072 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
1073 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1074 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1075 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1076 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1077 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1078 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1079 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1080 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1081 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1082 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1083 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1084
1085 /* MUX_SEL_MIF5 */
1086 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1087 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1088 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1089 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1090 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1091 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1092 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1093 MUX_SEL_MIF5, 8, 1),
1094 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1095 MUX_SEL_MIF5, 4, 1),
1096 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1097 MUX_SEL_MIF5, 0, 1),
1098
1099 /* MUX_SEL_MIF6 */
1100 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1101 MUX_SEL_MIF6, 8, 1),
1102 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1103 MUX_SEL_MIF6, 4, 1),
1104 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1105 MUX_SEL_MIF6, 0, 1),
1106
1107 /* MUX_SEL_MIF7 */
1108 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1109 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1110 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1111 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1112 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1113 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1114 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1115 MUX_SEL_MIF7, 8, 1),
1116 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1117 MUX_SEL_MIF7, 4, 1),
1118 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1119 MUX_SEL_MIF7, 0, 1),
1120};
1121
1122static struct samsung_div_clock mif_div_clks[] __initdata = {
1123 /* DIV_MIF1 */
1124 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1125 DIV_MIF1, 16, 2),
1126 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1127 12, 2),
1128 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1129 8, 2),
1130 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1131 4, 4),
1132
1133 /* DIV_MIF2 */
1134 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1135 DIV_MIF2, 20, 3),
1136 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1137 DIV_MIF2, 16, 4),
1138 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1139 DIV_MIF2, 12, 4),
1140 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1141 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1142 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1143 DIV_MIF2, 4, 2),
1144 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1145 DIV_MIF2, 0, 3),
1146
1147 /* DIV_MIF3 */
1148 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1149 DIV_MIF3, 16, 4),
1150 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1151 DIV_MIF3, 4, 3),
1152 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1153 DIV_MIF3, 0, 3),
1154
1155 /* DIV_MIF4 */
1156 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1157 DIV_MIF4, 24, 4),
1158 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1159 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1160 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1161 DIV_MIF4, 16, 4),
1162 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1163 DIV_MIF4, 12, 4),
1164 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1165 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1166 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1167 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1168 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1169 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1170
1171 /* DIV_MIF5 */
1172 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1173 0, 3),
1174};
1175
1176static struct samsung_gate_clock mif_gate_clks[] __initdata = {
1177 /* ENABLE_ACLK_MIF0 */
1178 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1179 19, CLK_IGNORE_UNUSED, 0),
1180 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1181 18, CLK_IGNORE_UNUSED, 0),
1182 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1183 17, CLK_IGNORE_UNUSED, 0),
1184 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1185 16, CLK_IGNORE_UNUSED, 0),
1186 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1187 15, CLK_IGNORE_UNUSED, 0),
1188 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1189 14, CLK_IGNORE_UNUSED, 0),
1190 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1191 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1192 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1193 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1194 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1195 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1196 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1197 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1198 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1199 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1200 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1201 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1202 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1203 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1204 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1205 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1206 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1207 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1208 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1209 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1210 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1211 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1212 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1213 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1214 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1215 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1216 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1217 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1218
1219 /* ENABLE_ACLK_MIF1 */
1220 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1221 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1222 CLK_IGNORE_UNUSED, 0),
1223 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1224 "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1225 27, CLK_IGNORE_UNUSED, 0),
1226 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1227 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1228 26, CLK_IGNORE_UNUSED, 0),
1229 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1230 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1231 25, CLK_IGNORE_UNUSED, 0),
1232 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1233 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1234 24, CLK_IGNORE_UNUSED, 0),
1235 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1236 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1237 23, CLK_IGNORE_UNUSED, 0),
1238 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1239 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1240 22, CLK_IGNORE_UNUSED, 0),
1241 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1242 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1243 21, CLK_IGNORE_UNUSED, 0),
1244 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1245 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1246 20, CLK_IGNORE_UNUSED, 0),
1247 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1248 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1249 19, CLK_IGNORE_UNUSED, 0),
1250 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1251 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1252 18, CLK_IGNORE_UNUSED, 0),
1253 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1254 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1255 17, CLK_IGNORE_UNUSED, 0),
1256 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1257 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1258 16, CLK_IGNORE_UNUSED, 0),
1259 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1260 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1261 15, CLK_IGNORE_UNUSED, 0),
1262 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1263 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1264 14, CLK_IGNORE_UNUSED, 0),
1265 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1266 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1267 13, CLK_IGNORE_UNUSED, 0),
1268 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1269 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1270 12, CLK_IGNORE_UNUSED, 0),
1271 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1272 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1273 11, CLK_IGNORE_UNUSED, 0),
1274 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1275 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1276 10, CLK_IGNORE_UNUSED, 0),
1277 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1278 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1279 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1280 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1281 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1282 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1283 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1284 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1285 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1286 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1287 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1288 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1289 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1290 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1291 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1292 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1293 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1294 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1295 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1296 0, CLK_IGNORE_UNUSED, 0),
1297
1298 /* ENABLE_ACLK_MIF2 */
1299 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1300 ENABLE_ACLK_MIF2, 20, 0, 0),
1301 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1302 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1303 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1304 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1305 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1306 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1307 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1308 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1309 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1310 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1311 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1312 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1313 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1314 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1315 CLK_IGNORE_UNUSED, 0),
1316 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1317 "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1318 5, CLK_IGNORE_UNUSED, 0),
1319 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1320 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1321 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1322 "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1323 3, CLK_IGNORE_UNUSED, 0),
1324 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1325 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1326
1327 /* ENABLE_ACLK_MIF3 */
1328 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1329 ENABLE_ACLK_MIF3, 4,
1330 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1331 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1332 ENABLE_ACLK_MIF3, 1,
1333 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1334 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1335 ENABLE_ACLK_MIF3, 0,
1336 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1337
1338 /* ENABLE_PCLK_MIF */
1339 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1340 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1341 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1342 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1343 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1344 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1345 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1346 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1347 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1348 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1349 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1350 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1351 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1352 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1353 CLK_IGNORE_UNUSED, 0),
1354 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1355 ENABLE_PCLK_MIF, 19, 0, 0),
1356 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1357 ENABLE_PCLK_MIF, 18, 0, 0),
1358 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1359 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1360 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1361 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1362 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1363 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1364 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1365 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1366 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1367 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1368 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1369 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1370 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1371 ENABLE_PCLK_MIF, 11, 0, 0),
1372 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1373 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1374 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1375 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1376 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1377 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1378 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1379 ENABLE_PCLK_MIF, 7, 0, 0),
1380 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1381 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1382 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1383 ENABLE_PCLK_MIF, 5, 0, 0),
1384 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1385 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1386 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1387 ENABLE_PCLK_MIF, 2, 0, 0),
1388 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1389 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1390
1391 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1392 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1393 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0),
1394
1395 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1396 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1397 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0),
1398
1399 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1400 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1401 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1402
1403 /* ENABLE_PCLK_MIF_SECURE_RTC */
1404 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1405 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1406
1407 /* ENABLE_SCLK_MIF */
1408 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1409 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1410 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1411 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1412 14, CLK_IGNORE_UNUSED, 0),
1413 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1414 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1415 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1416 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1417 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1418 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1419 7, CLK_IGNORE_UNUSED, 0),
1420 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1421 "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1422 6, CLK_IGNORE_UNUSED, 0),
1423 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1424 "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1425 5, CLK_IGNORE_UNUSED, 0),
1426 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1427 ENABLE_SCLK_MIF, 4,
1428 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1429 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1430 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1431 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1432 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1433 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1434 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1435 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1436 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
2a1808a6
CC		 1437
1438 /* ENABLE_SCLK_TOP_DISP */
1439 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
1440 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
1441 CLK_IGNORE_UNUSED, 0),
06d2f9df
CC		 1442};
1443
96bd6224
CC		 1444static struct samsung_cmu_info mif_cmu_info __initdata = {
1445 .pll_clks = mif_pll_clks,
1446 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
06d2f9df
CC		 1447 .mux_clks = mif_mux_clks,
1448 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
1449 .div_clks = mif_div_clks,
1450 .nr_div_clks = ARRAY_SIZE(mif_div_clks),
1451 .gate_clks = mif_gate_clks,
1452 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
1453 .fixed_factor_clks = mif_fixed_factor_clks,
1454 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
96bd6224
CC		 1455 .nr_clk_ids = MIF_NR_CLK,
1456 .clk_regs = mif_clk_regs,
1457 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
1458};
1459
1460static void __init exynos5433_cmu_mif_init(struct device_node *np)
1461{
1462 samsung_cmu_register_one(np, &mif_cmu_info);
1463}
1464CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1465 exynos5433_cmu_mif_init);
1466
1467/*
1468 * Register offset definitions for CMU_PERIC
1469 */
1470#define DIV_PERIC 0x0600
d0f5de66 1471#define DIV_STAT_PERIC 0x0700
96bd6224
CC		 1472#define ENABLE_ACLK_PERIC 0x0800
1473#define ENABLE_PCLK_PERIC0 0x0900
1474#define ENABLE_PCLK_PERIC1 0x0904
1475#define ENABLE_SCLK_PERIC 0x0A00
1476#define ENABLE_IP_PERIC0 0x0B00
1477#define ENABLE_IP_PERIC1 0x0B04
1478#define ENABLE_IP_PERIC2 0x0B08
1479
1480static unsigned long peric_clk_regs[] __initdata = {
1481 DIV_PERIC,
d0f5de66 1482 DIV_STAT_PERIC,
96bd6224
CC		 1483 ENABLE_ACLK_PERIC,
1484 ENABLE_PCLK_PERIC0,
1485 ENABLE_PCLK_PERIC1,
1486 ENABLE_SCLK_PERIC,
1487 ENABLE_IP_PERIC0,
1488 ENABLE_IP_PERIC1,
1489 ENABLE_IP_PERIC2,
1490};
1491
d0f5de66
CC		 1492static struct samsung_div_clock peric_div_clks[] __initdata = {
1493 /* DIV_PERIC */
1494 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1495 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1496};
1497
96bd6224 1498static struct samsung_gate_clock peric_gate_clks[] __initdata = {
d0f5de66
CC		 1499 /* ENABLE_ACLK_PERIC */
1500 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1501 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1502 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1503 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1504 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1505 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1506 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1507 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1508
96bd6224 1509 /* ENABLE_PCLK_PERIC0 */
d0f5de66
CC		 1510 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1511 31, CLK_SET_RATE_PARENT, 0),
1512 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1513 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1514 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1515 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1516 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1517 28, CLK_SET_RATE_PARENT, 0),
1518 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1519 26, CLK_SET_RATE_PARENT, 0),
1520 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1521 25, CLK_SET_RATE_PARENT, 0),
1522 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1523 24, CLK_SET_RATE_PARENT, 0),
96bd6224
CC		 1524 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1525 23, CLK_SET_RATE_PARENT, 0),
1526 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1527 22, CLK_SET_RATE_PARENT, 0),
1528 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1529 21, CLK_SET_RATE_PARENT, 0),
d0f5de66
CC		 1530 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1531 20, CLK_SET_RATE_PARENT, 0),
1532 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1533 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1534 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1535 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1536 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1537 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1538 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1539 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1540 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1541 ENABLE_PCLK_PERIC0, 15,
1542 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
96bd6224
CC		 1543 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1544 14, CLK_SET_RATE_PARENT, 0),
1545 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1546 13, CLK_SET_RATE_PARENT, 0),
1547 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1548 12, CLK_SET_RATE_PARENT, 0),
1549 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1550 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1551 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1552 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1553 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1554 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1555 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1556 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1557 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1558 7, CLK_SET_RATE_PARENT, 0),
1559 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1560 6, CLK_SET_RATE_PARENT, 0),
1561 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1562 5, CLK_SET_RATE_PARENT, 0),
1563 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1564 4, CLK_SET_RATE_PARENT, 0),
1565 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1566 3, CLK_SET_RATE_PARENT, 0),
1567 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1568 2, CLK_SET_RATE_PARENT, 0),
1569 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1570 1, CLK_SET_RATE_PARENT, 0),
1571 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1572 0, CLK_SET_RATE_PARENT, 0),
1573
1574 /* ENABLE_PCLK_PERIC1 */
1575 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1576 9, CLK_SET_RATE_PARENT, 0),
1577 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1578 8, CLK_SET_RATE_PARENT, 0),
1579 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1580 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1581 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1582 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1583 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1584 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1585 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1586 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1587 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1588 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1589 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1590 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1591 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1592 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1593 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1594 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1595
1596 /* ENABLE_SCLK_PERIC */
d0f5de66
CC		 1597 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1598 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1599 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1600 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
96bd6224
CC		 1601 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1602 19, CLK_SET_RATE_PARENT, 0),
1603 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1604 18, CLK_SET_RATE_PARENT, 0),
d0f5de66
CC		 1605 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1606 17, 0, 0),
1607 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1608 16, 0, 0),
1609 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1610 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1611 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1612 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1613 ENABLE_SCLK_PERIC, 12,
1614 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1615 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1616 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1617 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1618 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1619 CLK_SET_RATE_PARENT, 0),
1620 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1621 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1622 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1623 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1624 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1625 ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
96bd6224
CC		 1626 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1627 5, CLK_SET_RATE_PARENT, 0),
1628 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
d0f5de66 1629 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
96bd6224
CC		 1630 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1631 3, CLK_SET_RATE_PARENT, 0),
1632 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1633 ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
1634 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1635 ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
1636 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1637 ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
1638};
1639
1640static struct samsung_cmu_info peric_cmu_info __initdata = {
d0f5de66
CC		 1641 .div_clks = peric_div_clks,
1642 .nr_div_clks = ARRAY_SIZE(peric_div_clks),
96bd6224
CC		 1643 .gate_clks = peric_gate_clks,
1644 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
1645 .nr_clk_ids = PERIC_NR_CLK,
1646 .clk_regs = peric_clk_regs,
1647 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
1648};
1649
1650static void __init exynos5433_cmu_peric_init(struct device_node *np)
1651{
1652 samsung_cmu_register_one(np, &peric_cmu_info);
1653}
1654
1655CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1656 exynos5433_cmu_peric_init);
1657
1658/*
1659 * Register offset definitions for CMU_PERIS
1660 */
56bcf3f3
CC		 1661#define ENABLE_ACLK_PERIS 0x0800
1662#define ENABLE_PCLK_PERIS 0x0900
1663#define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
1664#define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
1665#define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
1666#define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
1667#define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
1668#define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
1669#define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
1670#define ENABLE_SCLK_PERIS 0x0a00
1671#define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
1672#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
1673#define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
1674#define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
1675#define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
1676#define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
1677#define ENABLE_IP_PERIS0 0x0b00
1678#define ENABLE_IP_PERIS1 0x0b04
1679#define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
1680#define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
1681#define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
1682#define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
1683#define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
1684#define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1685#define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
96bd6224
CC		 1686
1687static unsigned long peris_clk_regs[] __initdata = {
1688 ENABLE_ACLK_PERIS,
1689 ENABLE_PCLK_PERIS,
56bcf3f3
CC		 1690 ENABLE_PCLK_PERIS_SECURE_TZPC,
1691 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1692 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1693 ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1694 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1695 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1696 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1697 ENABLE_SCLK_PERIS,
1698 ENABLE_SCLK_PERIS_SECURE_SECKEY,
1699 ENABLE_SCLK_PERIS_SECURE_CHIPID,
1700 ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1701 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1702 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1703 ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1704 ENABLE_IP_PERIS0,
1705 ENABLE_IP_PERIS1,
1706 ENABLE_IP_PERIS_SECURE_TZPC,
1707 ENABLE_IP_PERIS_SECURE_SECKEY,
1708 ENABLE_IP_PERIS_SECURE_CHIPID,
1709 ENABLE_IP_PERIS_SECURE_TOPRTC,
1710 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1711 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1712 ENABLE_IP_PERIS_SECURE_OTP_CON,
96bd6224
CC		 1713};
1714
1715static struct samsung_gate_clock peris_gate_clks[] __initdata = {
56bcf3f3
CC		 1716 /* ENABLE_ACLK_PERIS */
1717 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1718 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1719 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1720 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1721 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1722 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1723
96bd6224
CC		 1724 /* ENABLE_PCLK_PERIS */
1725 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1726 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1727 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1728 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1729 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1730 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1731 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1732 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1733 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1734 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1735 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1736 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1737 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1738 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1739 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1740 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1741 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1742 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1743 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1744 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
56bcf3f3
CC		 1745
1746 /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1747 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1748 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, 0, 0),
1749 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1750 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, 0, 0),
1751 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1752 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, 0, 0),
1753 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1754 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, 0, 0),
1755 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1756 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, 0, 0),
1757 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1758 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, 0, 0),
1759 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1760 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, 0, 0),
1761 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1762 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, 0, 0),
1763 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1764 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, 0, 0),
1765 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1766 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, 0, 0),
1767 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1768 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, 0, 0),
1769 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1770 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, 0, 0),
1771 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1772 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, 0, 0),
1773
1774 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1775 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1776 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, 0, 0),
1777
1778 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1779 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1780 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, 0, 0),
1781
1782 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1783 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1784 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1785
1786 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1787 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1788 "aclk_peris_66",
1789 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1790
1791 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1792 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1793 "aclk_peris_66",
1794 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1795
1796 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1797 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1798 "aclk_peris_66",
1799 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1800
1801 /* ENABLE_SCLK_PERIS */
1802 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1803 ENABLE_SCLK_PERIS, 10, 0, 0),
1804 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1805 ENABLE_SCLK_PERIS, 4, 0, 0),
1806 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1807 ENABLE_SCLK_PERIS, 3, 0, 0),
1808
1809 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1810 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1811 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, 0, 0),
1812
1813 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1814 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1815 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
1816
1817 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1818 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1819 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1820
1821 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1822 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1823 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1824
1825 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1826 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1827 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1828
1829 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1830 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1831 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
96bd6224
CC		 1832};
1833
1834static struct samsung_cmu_info peris_cmu_info __initdata = {
1835 .gate_clks = peris_gate_clks,
1836 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1837 .nr_clk_ids = PERIS_NR_CLK,
1838 .clk_regs = peris_clk_regs,
1839 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
1840};
1841
1842static void __init exynos5433_cmu_peris_init(struct device_node *np)
1843{
1844 samsung_cmu_register_one(np, &peris_cmu_info);
1845}
1846
1847CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1848 exynos5433_cmu_peris_init);
1849
1850/*
1851 * Register offset definitions for CMU_FSYS
1852 */
1853#define MUX_SEL_FSYS0 0x0200
1854#define MUX_SEL_FSYS1 0x0204
1855#define MUX_SEL_FSYS2 0x0208
1856#define MUX_SEL_FSYS3 0x020c
1857#define MUX_SEL_FSYS4 0x0210
1858#define MUX_ENABLE_FSYS0 0x0300
1859#define MUX_ENABLE_FSYS1 0x0304
1860#define MUX_ENABLE_FSYS2 0x0308
1861#define MUX_ENABLE_FSYS3 0x030c
1862#define MUX_ENABLE_FSYS4 0x0310
1863#define MUX_STAT_FSYS0 0x0400
1864#define MUX_STAT_FSYS1 0x0404
1865#define MUX_STAT_FSYS2 0x0408
1866#define MUX_STAT_FSYS3 0x040c
1867#define MUX_STAT_FSYS4 0x0410
1868#define MUX_IGNORE_FSYS2 0x0508
1869#define MUX_IGNORE_FSYS3 0x050c
1870#define ENABLE_ACLK_FSYS0 0x0800
1871#define ENABLE_ACLK_FSYS1 0x0804
1872#define ENABLE_PCLK_FSYS 0x0900
1873#define ENABLE_SCLK_FSYS 0x0a00
1874#define ENABLE_IP_FSYS0 0x0b00
1875#define ENABLE_IP_FSYS1 0x0b04
1876
1877/* list of all parent clock list */
4b801355 1878PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
96bd6224 1879PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", };
4b801355
CC		 1880PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
1881PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
96bd6224
CC		 1882PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
1883PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", };
1884PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", };
4b801355
CC		 1885PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",};
1886PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", };
1887
1888PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
1889 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
1890PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
1891 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
1892PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
1893 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
1894PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
1895 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
1896PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
1897 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
1898PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
1899 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
1900PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
1901 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
1902PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
1903 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
1904PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
1905 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
1906PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
1907 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
1908PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
1909 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
1910PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
1911 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
1912PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
1913 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
1914PNAME(mout_sclk_mphy_p)
1915 = { "mout_sclk_ufs_mphy_user",
1916 "mout_phyclk_lli_mphy_to_ufs_user", };
96bd6224
CC		 1917
1918static unsigned long fsys_clk_regs[] __initdata = {
1919 MUX_SEL_FSYS0,
1920 MUX_SEL_FSYS1,
1921 MUX_SEL_FSYS2,
1922 MUX_SEL_FSYS3,
1923 MUX_SEL_FSYS4,
1924 MUX_ENABLE_FSYS0,
1925 MUX_ENABLE_FSYS1,
1926 MUX_ENABLE_FSYS2,
1927 MUX_ENABLE_FSYS3,
1928 MUX_ENABLE_FSYS4,
1929 MUX_STAT_FSYS0,
1930 MUX_STAT_FSYS1,
1931 MUX_STAT_FSYS2,
1932 MUX_STAT_FSYS3,
1933 MUX_STAT_FSYS4,
1934 MUX_IGNORE_FSYS2,
1935 MUX_IGNORE_FSYS3,
1936 ENABLE_ACLK_FSYS0,
1937 ENABLE_ACLK_FSYS1,
1938 ENABLE_PCLK_FSYS,
1939 ENABLE_SCLK_FSYS,
1940 ENABLE_IP_FSYS0,
1941 ENABLE_IP_FSYS1,
1942};
1943
4b801355
CC		 1944static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = {
1945 /* PHY clocks from USBDRD30_PHY */
1946 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
1947 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
1948 CLK_IS_ROOT, 60000000),
1949 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
1950 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
1951 CLK_IS_ROOT, 125000000),
1952 /* PHY clocks from USBHOST30_PHY */
1953 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
1954 "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
1955 CLK_IS_ROOT, 60000000),
1956 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
1957 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
1958 CLK_IS_ROOT, 125000000),
1959 /* PHY clocks from USBHOST20_PHY */
1960 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
1961 "phyclk_usbhost20_phy_freeclk_phy", NULL, CLK_IS_ROOT,
1962 60000000),
1963 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
1964 "phyclk_usbhost20_phy_phyclock_phy", NULL, CLK_IS_ROOT,
1965 60000000),
1966 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
1967 "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
1968 CLK_IS_ROOT, 48000000),
1969 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
1970 "phyclk_usbhost20_phy_hsic1_phy", NULL, CLK_IS_ROOT,
1971 60000000),
1972 /* PHY clocks from UFS_PHY */
1973 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
1974 NULL, CLK_IS_ROOT, 300000000),
1975 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
1976 NULL, CLK_IS_ROOT, 300000000),
1977 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
1978 NULL, CLK_IS_ROOT, 300000000),
1979 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
1980 NULL, CLK_IS_ROOT, 300000000),
1981 /* PHY clocks from LLI_PHY */
1982 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
1983 NULL, CLK_IS_ROOT, 26000000),
1984};
1985
96bd6224
CC		 1986static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
1987 /* MUX_SEL_FSYS0 */
4b801355
CC		 1988 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
1989 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
96bd6224
CC		 1990 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
1991 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
1992
1993 /* MUX_SEL_FSYS1 */
4b801355
CC		 1994 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
1995 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
1996 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
1997 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
96bd6224
CC		 1998 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
1999 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
2000 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
2001 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
2002 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
2003 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
4b801355
CC		 2004 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
2005 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
2006 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
2007 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2008
2009 /* MUX_SEL_FSYS2 */
2010 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
2011 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2012 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
2013 MUX_SEL_FSYS2, 28, 1),
2014 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
2015 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2016 mout_phyclk_usbhost30_uhost30_phyclock_user_p,
2017 MUX_SEL_FSYS2, 24, 1),
2018 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
2019 "mout_phyclk_usbhost20_phy_hsic1",
2020 mout_phyclk_usbhost20_phy_hsic1_p,
2021 MUX_SEL_FSYS2, 20, 1),
2022 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2023 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2024 mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2025 MUX_SEL_FSYS2, 16, 1),
2026 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2027 "mout_phyclk_usbhost20_phy_phyclock_user",
2028 mout_phyclk_usbhost20_phy_phyclock_user_p,
2029 MUX_SEL_FSYS2, 12, 1),
2030 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2031 "mout_phyclk_usbhost20_phy_freeclk_user",
2032 mout_phyclk_usbhost20_phy_freeclk_user_p,
2033 MUX_SEL_FSYS2, 8, 1),
2034 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2035 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2036 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2037 MUX_SEL_FSYS2, 4, 1),
2038 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2039 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2040 mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2041 MUX_SEL_FSYS2, 0, 1),
2042
2043 /* MUX_SEL_FSYS3 */
2044 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2045 "mout_phyclk_ufs_rx1_symbol_user",
2046 mout_phyclk_ufs_rx1_symbol_user_p,
2047 MUX_SEL_FSYS3, 16, 1),
2048 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2049 "mout_phyclk_ufs_rx0_symbol_user",
2050 mout_phyclk_ufs_rx0_symbol_user_p,
2051 MUX_SEL_FSYS3, 12, 1),
2052 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2053 "mout_phyclk_ufs_tx1_symbol_user",
2054 mout_phyclk_ufs_tx1_symbol_user_p,
2055 MUX_SEL_FSYS3, 8, 1),
2056 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2057 "mout_phyclk_ufs_tx0_symbol_user",
2058 mout_phyclk_ufs_tx0_symbol_user_p,
2059 MUX_SEL_FSYS3, 4, 1),
2060 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2061 "mout_phyclk_lli_mphy_to_ufs_user",
2062 mout_phyclk_lli_mphy_to_ufs_user_p,
2063 MUX_SEL_FSYS3, 0, 1),
2064
2065 /* MUX_SEL_FSYS4 */
2066 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2067 MUX_SEL_FSYS4, 0, 1),
96bd6224
CC		 2068};
2069
2070static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
2071 /* ENABLE_ACLK_FSYS0 */
2072 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2073 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2074 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
2075 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2076 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
2077 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2078 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
2079 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2080 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
2081 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2082 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
2083 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2084 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
2085 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2086 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2087 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2088 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2089 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2090 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2091 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2092 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
2093 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2094
4b801355
CC		 2095 /* ENABLE_ACLK_FSYS1 */
2096 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2097 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2098 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2099 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2100 26, CLK_IGNORE_UNUSED, 0),
2101 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2102 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2103 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2104 ENABLE_ACLK_FSYS1, 24, 0, 0),
2105 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2106 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2107 22, CLK_IGNORE_UNUSED, 0),
2108 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2109 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2110 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2111 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2112 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2113 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2114 13, 0, 0),
2115 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2116 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2117 12, 0, 0),
2118 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2119 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2120 11, CLK_IGNORE_UNUSED, 0),
2121 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2122 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2123 10, CLK_IGNORE_UNUSED, 0),
2124 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2125 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2126 9, CLK_IGNORE_UNUSED, 0),
2127 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2128 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2129 8, CLK_IGNORE_UNUSED, 0),
2130 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2131 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2132 7, CLK_IGNORE_UNUSED, 0),
2133 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2134 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2135 6, CLK_IGNORE_UNUSED, 0),
2136 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2137 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2138 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2139 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2140 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2141 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2142 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2143 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2144 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2145 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2146 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2147 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2148
2149 /* ENABLE_PCLK_FSYS */
2150 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2151 ENABLE_PCLK_FSYS, 17, 0, 0),
2152 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2153 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2154 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2155 ENABLE_PCLK_FSYS, 14, 0, 0),
2156 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2157 ENABLE_PCLK_FSYS, 13, 0, 0),
2158 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2159 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2160 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2161 ENABLE_PCLK_FSYS, 5, 0, 0),
2162 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2163 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2164 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2165 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2166 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2167 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2168 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2169 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2170 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2171 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2172 0, CLK_IGNORE_UNUSED, 0),
2173
96bd6224 2174 /* ENABLE_SCLK_FSYS */
4b801355
CC		 2175 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2176 ENABLE_SCLK_FSYS, 21, 0, 0),
2177 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2178 "phyclk_usbhost30_uhost30_pipe_pclk",
2179 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2180 ENABLE_SCLK_FSYS, 18, 0, 0),
2181 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2182 "phyclk_usbhost30_uhost30_phyclock",
2183 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2184 ENABLE_SCLK_FSYS, 17, 0, 0),
2185 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2186 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2187 16, 0, 0),
2188 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2189 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2190 15, 0, 0),
2191 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2192 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2193 14, 0, 0),
2194 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2195 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2196 13, 0, 0),
2197 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2198 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2199 12, 0, 0),
2200 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2201 "phyclk_usbhost20_phy_clk48mohci",
2202 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2203 ENABLE_SCLK_FSYS, 11, 0, 0),
2204 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2205 "phyclk_usbhost20_phy_phyclock",
2206 "mout_phyclk_usbhost20_phy_phyclock_user",
2207 ENABLE_SCLK_FSYS, 10, 0, 0),
2208 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2209 "phyclk_usbhost20_phy_freeclk",
2210 "mout_phyclk_usbhost20_phy_freeclk_user",
2211 ENABLE_SCLK_FSYS, 9, 0, 0),
2212 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2213 "phyclk_usbdrd30_udrd30_pipe_pclk",
2214 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2215 ENABLE_SCLK_FSYS, 8, 0, 0),
2216 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2217 "phyclk_usbdrd30_udrd30_phyclock",
2218 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2219 ENABLE_SCLK_FSYS, 7, 0, 0),
2220 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2221 ENABLE_SCLK_FSYS, 6, 0, 0),
2222 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2223 ENABLE_SCLK_FSYS, 5, 0, 0),
96bd6224
CC		 2224 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
2225 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2226 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
2227 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2228 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
2229 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
4b801355
CC		 2230 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2231 ENABLE_SCLK_FSYS, 1, 0, 0),
2232 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2233 ENABLE_SCLK_FSYS, 0, 0, 0),
96bd6224
CC		 2234
2235 /* ENABLE_IP_FSYS0 */
2236 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2237 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2238};
2239
2240static struct samsung_cmu_info fsys_cmu_info __initdata = {
2241 .mux_clks = fsys_mux_clks,
2242 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
2243 .gate_clks = fsys_gate_clks,
2244 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
4b801355
CC		 2245 .fixed_clks = fsys_fixed_clks,
2246 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
96bd6224
CC		 2247 .nr_clk_ids = FSYS_NR_CLK,
2248 .clk_regs = fsys_clk_regs,
2249 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
2250};
2251
2252static void __init exynos5433_cmu_fsys_init(struct device_node *np)
2253{
2254 samsung_cmu_register_one(np, &fsys_cmu_info);
2255}
2256
2257CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
2258 exynos5433_cmu_fsys_init);
a29308da
CC		 2259
2260/*
2261 * Register offset definitions for CMU_G2D
2262 */
2263#define MUX_SEL_G2D0 0x0200
2264#define MUX_SEL_ENABLE_G2D0 0x0300
2265#define MUX_SEL_STAT_G2D0 0x0400
2266#define DIV_G2D 0x0600
2267#define DIV_STAT_G2D 0x0700
2268#define DIV_ENABLE_ACLK_G2D 0x0800
2269#define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
2270#define DIV_ENABLE_PCLK_G2D 0x0900
2271#define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
2272#define DIV_ENABLE_IP_G2D0 0x0b00
2273#define DIV_ENABLE_IP_G2D1 0x0b04
2274#define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2275
2276static unsigned long g2d_clk_regs[] __initdata = {
2277 MUX_SEL_G2D0,
2278 MUX_SEL_ENABLE_G2D0,
2279 MUX_SEL_STAT_G2D0,
2280 DIV_G2D,
2281 DIV_STAT_G2D,
2282 DIV_ENABLE_ACLK_G2D,
2283 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
2284 DIV_ENABLE_PCLK_G2D,
2285 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
2286 DIV_ENABLE_IP_G2D0,
2287 DIV_ENABLE_IP_G2D1,
2288 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2289};
2290
2291/* list of all parent clock list */
2292PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
2293PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
2294
2295static struct samsung_mux_clock g2d_mux_clks[] __initdata = {
2296 /* MUX_SEL_G2D0 */
2297 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2298 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
2299 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
2300 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2301};
2302
2303static struct samsung_div_clock g2d_div_clks[] __initdata = {
2304 /* DIV_G2D */
2305 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2306 DIV_G2D, 0, 2),
2307};
2308
2309static struct samsung_gate_clock g2d_gate_clks[] __initdata = {
2310 /* DIV_ENABLE_ACLK_G2D */
2311 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2312 DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2313 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2314 DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2315 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2316 DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2317 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2318 DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2319 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2320 DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2321 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
2322 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
2323 7, 0, 0),
2324 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2325 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2326 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2327 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2328 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2329 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2330 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
2331 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2332 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2333 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2334 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
2335 DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2336 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
2337 DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2338
2339 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2340 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2341 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2342
2343 /* DIV_ENABLE_PCLK_G2D */
2344 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
2345 DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2346 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
2347 DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2348 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
2349 DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2350 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
2351 DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2352 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2353 DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2354 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
2355 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2356 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
2357 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2358 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
2359 0, 0, 0),
2360
2361 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2362 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2363 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2364};
2365
2366static struct samsung_cmu_info g2d_cmu_info __initdata = {
2367 .mux_clks = g2d_mux_clks,
2368 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
2369 .div_clks = g2d_div_clks,
2370 .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
2371 .gate_clks = g2d_gate_clks,
2372 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
2373 .nr_clk_ids = G2D_NR_CLK,
2374 .clk_regs = g2d_clk_regs,
2375 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
2376};
2377
2378static void __init exynos5433_cmu_g2d_init(struct device_node *np)
2379{
2380 samsung_cmu_register_one(np, &g2d_cmu_info);
2381}
2382
2383CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
2384 exynos5433_cmu_g2d_init);
2a1808a6
CC		 2385
2386/*
2387 * Register offset definitions for CMU_DISP
2388 */
2389#define DISP_PLL_LOCK 0x0000
2390#define DISP_PLL_CON0 0x0100
2391#define DISP_PLL_CON1 0x0104
2392#define DISP_PLL_FREQ_DET 0x0108
2393#define MUX_SEL_DISP0 0x0200
2394#define MUX_SEL_DISP1 0x0204
2395#define MUX_SEL_DISP2 0x0208
2396#define MUX_SEL_DISP3 0x020c
2397#define MUX_SEL_DISP4 0x0210
2398#define MUX_ENABLE_DISP0 0x0300
2399#define MUX_ENABLE_DISP1 0x0304
2400#define MUX_ENABLE_DISP2 0x0308
2401#define MUX_ENABLE_DISP3 0x030c
2402#define MUX_ENABLE_DISP4 0x0310
2403#define MUX_STAT_DISP0 0x0400
2404#define MUX_STAT_DISP1 0x0404
2405#define MUX_STAT_DISP2 0x0408
2406#define MUX_STAT_DISP3 0x040c
2407#define MUX_STAT_DISP4 0x0410
2408#define MUX_IGNORE_DISP2 0x0508
2409#define DIV_DISP 0x0600
2410#define DIV_DISP_PLL_FREQ_DET 0x0604
2411#define DIV_STAT_DISP 0x0700
2412#define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
2413#define ENABLE_ACLK_DISP0 0x0800
2414#define ENABLE_ACLK_DISP1 0x0804
2415#define ENABLE_PCLK_DISP 0x0900
2416#define ENABLE_SCLK_DISP 0x0a00
2417#define ENABLE_IP_DISP0 0x0b00
2418#define ENABLE_IP_DISP1 0x0b04
2419#define CLKOUT_CMU_DISP 0x0c00
2420#define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2421
2422static unsigned long disp_clk_regs[] __initdata = {
2423 DISP_PLL_LOCK,
2424 DISP_PLL_CON0,
2425 DISP_PLL_CON1,
2426 DISP_PLL_FREQ_DET,
2427 MUX_SEL_DISP0,
2428 MUX_SEL_DISP1,
2429 MUX_SEL_DISP2,
2430 MUX_SEL_DISP3,
2431 MUX_SEL_DISP4,
2432 MUX_ENABLE_DISP0,
2433 MUX_ENABLE_DISP1,
2434 MUX_ENABLE_DISP2,
2435 MUX_ENABLE_DISP3,
2436 MUX_ENABLE_DISP4,
2437 MUX_STAT_DISP0,
2438 MUX_STAT_DISP1,
2439 MUX_STAT_DISP2,
2440 MUX_STAT_DISP3,
2441 MUX_STAT_DISP4,
2442 MUX_IGNORE_DISP2,
2443 DIV_DISP,
2444 DIV_DISP_PLL_FREQ_DET,
2445 DIV_STAT_DISP,
2446 DIV_STAT_DISP_PLL_FREQ_DET,
2447 ENABLE_ACLK_DISP0,
2448 ENABLE_ACLK_DISP1,
2449 ENABLE_PCLK_DISP,
2450 ENABLE_SCLK_DISP,
2451 ENABLE_IP_DISP0,
2452 ENABLE_IP_DISP1,
2453 CLKOUT_CMU_DISP,
2454 CLKOUT_CMU_DISP_DIV_STAT,
2455};
2456
2457/* list of all parent clock list */
2458PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", };
2459PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", };
2460PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", };
2461PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", };
2462PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk",
2463 "sclk_decon_tv_eclk_disp", };
2464PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk",
2465 "sclk_decon_vclk_disp", };
2466PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk",
2467 "sclk_decon_eclk_disp", };
2468PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk",
2469 "sclk_decon_tv_vclk_disp", };
2470PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", };
2471
2472PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk",
2473 "phyclk_mipidphy1_bitclkdiv8_phy", };
2474PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk",
2475 "phyclk_mipidphy1_rxclkesc0_phy", };
2476PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk",
2477 "phyclk_mipidphy0_bitclkdiv8_phy", };
2478PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk",
2479 "phyclk_mipidphy0_rxclkesc0_phy", };
2480PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk",
2481 "phyclk_hdmiphy_tmds_clko_phy", };
2482PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk",
2483 "phyclk_hdmiphy_pixel_clko_phy", };
2484
2485PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
2486 "mout_sclk_dsim0_user", };
2487PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
2488 "mout_sclk_decon_tv_eclk_user", };
2489PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
2490 "mout_sclk_decon_vclk_user", };
2491PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
2492 "mout_sclk_decon_eclk_user", };
2493
2494PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
2495 "mout_sclk_dsim1_user", };
2496PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2497 "mout_phyclk_hdmiphy_pixel_clko_user",
2498 "mout_sclk_decon_tv_vclk_b_disp", };
2499PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2500 "mout_sclk_decon_tv_vclk_user", };
2501
2502static struct samsung_pll_clock disp_pll_clks[] __initdata = {
2503 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2504 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates),
2505};
2506
2507static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = {
2508 /*
2509 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2510 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2511 * and sclk_decon_{vclk|tv_vclk}.
2512 */
2513 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2514 1, 2, 0),
2515 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2516 1, 2, 0),
2517};
2518
2519static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = {
2520 /* PHY clocks from MIPI_DPHY1 */
2521 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2522 188000000),
2523 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2524 100000000),
2525 /* PHY clocks from MIPI_DPHY0 */
2526 FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, CLK_IS_ROOT,
2527 188000000),
2528 FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
2529 100000000),
2530 /* PHY clocks from HDMI_PHY */
2531 FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000),
2532 FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000),
2533};
2534
2535static struct samsung_mux_clock disp_mux_clks[] __initdata = {
2536 /* MUX_SEL_DISP0 */
2537 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2538 0, 1),
2539
2540 /* MUX_SEL_DISP1 */
2541 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2542 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2543 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2544 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2545 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2546 MUX_SEL_DISP1, 20, 1),
2547 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2548 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2549 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2550 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2551 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2552 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2553 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2554 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2555 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2556 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2557
2558 /* MUX_SEL_DISP2 */
2559 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2560 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2561 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2562 20, 1),
2563 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2564 "mout_phyclk_mipidphy1_rxclkesc0_user",
2565 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2566 16, 1),
2567 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2568 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2569 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2570 12, 1),
2571 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2572 "mout_phyclk_mipidphy0_rxclkesc0_user",
2573 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2574 8, 1),
2575 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2576 "mout_phyclk_hdmiphy_tmds_clko_user",
2577 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2578 4, 1),
2579 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2580 "mout_phyclk_hdmiphy_pixel_clko_user",
2581 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2582 0, 1),
2583
2584 /* MUX_SEL_DISP3 */
2585 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2586 MUX_SEL_DISP3, 12, 1),
2587 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2588 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2589 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2590 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2591 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2592 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2593
2594 /* MUX_SEL_DISP4 */
2595 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2596 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2597 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2598 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2599 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2600 "mout_sclk_decon_tv_vclk_c_disp",
2601 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2602 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2603 "mout_sclk_decon_tv_vclk_b_disp",
2604 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2605 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2606 "mout_sclk_decon_tv_vclk_a_disp",
2607 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2608};
2609
2610static struct samsung_div_clock disp_div_clks[] __initdata = {
2611 /* DIV_DISP */
2612 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2613 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2614 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2615 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2616 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2617 DIV_DISP, 16, 3),
2618 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2619 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2620 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2621 "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2622 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2623 "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2624 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2625 DIV_DISP, 0, 2),
2626};
2627
2628static struct samsung_gate_clock disp_gate_clks[] __initdata = {
2629 /* ENABLE_ACLK_DISP0 */
2630 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2631 ENABLE_ACLK_DISP0, 2, 0, 0),
2632 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2633 ENABLE_ACLK_DISP0, 0, 0, 0),
2634
2635 /* ENABLE_ACLK_DISP1 */
2636 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2637 ENABLE_ACLK_DISP1, 25, 0, 0),
2638 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2639 ENABLE_ACLK_DISP1, 24, 0, 0),
2640 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2641 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2642 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2643 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2644 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2645 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2646 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2647 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2648 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2649 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2650 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2651 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2652 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2653 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2654 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2655 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2656 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2657 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2658 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2659 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2660 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2661 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2662 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2663 "div_pclk_disp", ENABLE_ACLK_DISP1,
2664 12, CLK_IGNORE_UNUSED, 0),
2665 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2666 "div_pclk_disp", ENABLE_ACLK_DISP1,
2667 11, CLK_IGNORE_UNUSED, 0),
2668 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2669 "div_pclk_disp", ENABLE_ACLK_DISP1,
2670 10, CLK_IGNORE_UNUSED, 0),
2671 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2672 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2673 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2674 ENABLE_ACLK_DISP1, 7, 0, 0),
2675 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2676 ENABLE_ACLK_DISP1, 6, 0, 0),
2677 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2678 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2679 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2680 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2681 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2682 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2683 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2684 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2685 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2686 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2687 CLK_IGNORE_UNUSED, 0),
2688 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2689 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2690 0, CLK_IGNORE_UNUSED, 0),
2691
2692 /* ENABLE_PCLK_DISP */
2693 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2694 ENABLE_PCLK_DISP, 23, 0, 0),
2695 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2696 ENABLE_PCLK_DISP, 22, 0, 0),
2697 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2698 ENABLE_PCLK_DISP, 21, 0, 0),
2699 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2700 ENABLE_PCLK_DISP, 20, 0, 0),
2701 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2702 ENABLE_PCLK_DISP, 19, 0, 0),
2703 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2704 ENABLE_PCLK_DISP, 18, 0, 0),
2705 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2706 ENABLE_PCLK_DISP, 17, 0, 0),
2707 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2708 ENABLE_PCLK_DISP, 16, 0, 0),
2709 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2710 ENABLE_PCLK_DISP, 15, 0, 0),
2711 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2712 ENABLE_PCLK_DISP, 14, 0, 0),
2713 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2714 ENABLE_PCLK_DISP, 13, 0, 0),
2715 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2716 ENABLE_PCLK_DISP, 12, 0, 0),
2717 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2718 ENABLE_PCLK_DISP, 11, 0, 0),
2719 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2720 ENABLE_PCLK_DISP, 10, 0, 0),
2721 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2722 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2723 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2724 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2725 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2726 ENABLE_PCLK_DISP, 7, 0, 0),
2727 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2728 ENABLE_PCLK_DISP, 6, 0, 0),
2729 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2730 ENABLE_PCLK_DISP, 5, 0, 0),
2731 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2732 ENABLE_PCLK_DISP, 3, 0, 0),
2733 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2734 ENABLE_PCLK_DISP, 2, 0, 0),
2735 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2736 ENABLE_PCLK_DISP, 1, 0, 0),
2737
2738 /* ENABLE_SCLK_DISP */
2739 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2740 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2741 ENABLE_SCLK_DISP, 26, 0, 0),
2742 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2743 "mout_phyclk_mipidphy1_rxclkesc0_user",
2744 ENABLE_SCLK_DISP, 25, 0, 0),
2745 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2746 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2747 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2748 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2749 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2750 ENABLE_SCLK_DISP, 22, 0, 0),
2751 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2752 "div_sclk_decon_tv_vclk_disp",
2753 ENABLE_SCLK_DISP, 21, 0, 0),
2754 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2755 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2756 ENABLE_SCLK_DISP, 15, 0, 0),
2757 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2758 "mout_phyclk_mipidphy0_rxclkesc0_user",
2759 ENABLE_SCLK_DISP, 14, 0, 0),
2760 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2761 "mout_phyclk_hdmiphy_tmds_clko_user",
2762 ENABLE_SCLK_DISP, 13, 0, 0),
2763 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2764 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2765 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2766 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2767 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2768 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2769 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2770 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2771 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2772 ENABLE_SCLK_DISP, 7, 0, 0),
2773 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2774 ENABLE_SCLK_DISP, 6, 0, 0),
2775 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2776 ENABLE_SCLK_DISP, 5, 0, 0),
2777 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2778 "div_sclk_decon_tv_eclk_disp",
2779 ENABLE_SCLK_DISP, 4, 0, 0),
2780 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2781 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2782 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2783 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2784};
2785
2786static struct samsung_cmu_info disp_cmu_info __initdata = {
2787 .pll_clks = disp_pll_clks,
2788 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
2789 .mux_clks = disp_mux_clks,
2790 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
2791 .div_clks = disp_div_clks,
2792 .nr_div_clks = ARRAY_SIZE(disp_div_clks),
2793 .gate_clks = disp_gate_clks,
2794 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
2795 .fixed_clks = disp_fixed_clks,
2796 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
2797 .fixed_factor_clks = disp_fixed_factor_clks,
2798 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
2799 .nr_clk_ids = DISP_NR_CLK,
2800 .clk_regs = disp_clk_regs,
2801 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
2802};
2803
2804static void __init exynos5433_cmu_disp_init(struct device_node *np)
2805{
2806 samsung_cmu_register_one(np, &disp_cmu_info);
2807}
2808
2809CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
2810 exynos5433_cmu_disp_init);
2e997c03
CC		 2811
2812/*
2813 * Register offset definitions for CMU_AUD
2814 */
2815#define MUX_SEL_AUD0 0x0200
2816#define MUX_SEL_AUD1 0x0204
2817#define MUX_ENABLE_AUD0 0x0300
2818#define MUX_ENABLE_AUD1 0x0304
2819#define MUX_STAT_AUD0 0x0400
2820#define DIV_AUD0 0x0600
2821#define DIV_AUD1 0x0604
2822#define DIV_STAT_AUD0 0x0700
2823#define DIV_STAT_AUD1 0x0704
2824#define ENABLE_ACLK_AUD 0x0800
2825#define ENABLE_PCLK_AUD 0x0900
2826#define ENABLE_SCLK_AUD0 0x0a00
2827#define ENABLE_SCLK_AUD1 0x0a04
2828#define ENABLE_IP_AUD0 0x0b00
2829#define ENABLE_IP_AUD1 0x0b04
2830
2831static unsigned long aud_clk_regs[] __initdata = {
2832 MUX_SEL_AUD0,
2833 MUX_SEL_AUD1,
2834 MUX_ENABLE_AUD0,
2835 MUX_ENABLE_AUD1,
2836 MUX_STAT_AUD0,
2837 DIV_AUD0,
2838 DIV_AUD1,
2839 DIV_STAT_AUD0,
2840 DIV_STAT_AUD1,
2841 ENABLE_ACLK_AUD,
2842 ENABLE_PCLK_AUD,
2843 ENABLE_SCLK_AUD0,
2844 ENABLE_SCLK_AUD1,
2845 ENABLE_IP_AUD0,
2846 ENABLE_IP_AUD1,
2847};
2848
2849/* list of all parent clock list */
2850PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
2851PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2852
2853static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = {
2854 FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 33000000),
2855 FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 25000000),
2856 FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 50000000),
2857};
2858
2859static struct samsung_mux_clock aud_mux_clks[] __initdata = {
2860 /* MUX_SEL_AUD0 */
2861 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2862 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2863
2864 /* MUX_SEL_AUD1 */
2865 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
2866 MUX_SEL_AUD1, 8, 1),
2867 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
2868 MUX_SEL_AUD1, 0, 1),
2869};
2870
2871static struct samsung_div_clock aud_div_clks[] __initdata = {
2872 /* DIV_AUD0 */
2873 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2874 12, 4),
2875 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
2876 8, 4),
2877 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
2878 4, 4),
2879 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
2880 0, 4),
2881
2882 /* DIV_AUD1 */
2883 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
2884 "mout_aud_pll_user", DIV_AUD1, 16, 5),
2885 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
2886 DIV_AUD1, 12, 4),
2887 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2888 DIV_AUD1, 4, 8),
2889 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
2890 DIV_AUD1, 0, 4),
2891};
2892
2893static struct samsung_gate_clock aud_gate_clks[] __initdata = {
2894 /* ENABLE_ACLK_AUD */
2895 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2896 ENABLE_ACLK_AUD, 12, 0, 0),
2897 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
2898 ENABLE_ACLK_AUD, 7, 0, 0),
2899 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
2900 ENABLE_ACLK_AUD, 0, 4, 0),
2901 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
2902 ENABLE_ACLK_AUD, 0, 3, 0),
2903 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
2904 ENABLE_ACLK_AUD, 0, 2, 0),
2905 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
2906 0, 1, 0),
2907 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
2908 0, CLK_IGNORE_UNUSED, 0),
2909
2910 /* ENABLE_PCLK_AUD */
2911 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
2912 13, 0, 0),
2913 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
2914 12, 0, 0),
2915 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
2916 11, 0, 0),
2917 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
2918 ENABLE_PCLK_AUD, 10, 0, 0),
2919 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
2920 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
2921 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
2922 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
2923 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
2924 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
2925 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
2926 ENABLE_PCLK_AUD, 6, 0, 0),
2927 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
2928 ENABLE_PCLK_AUD, 5, 0, 0),
2929 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
2930 ENABLE_PCLK_AUD, 4, 0, 0),
2931 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
2932 ENABLE_PCLK_AUD, 3, 0, 0),
2933 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
2934 2, 0, 0),
2935 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
2936 ENABLE_PCLK_AUD, 0, 0, 0),
2937
2938 /* ENABLE_SCLK_AUD0 */
2939 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
2940 2, 0, 0),
2941 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
2942 ENABLE_SCLK_AUD0, 1, 0, 0),
2943 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
2944 0, 0, 0),
2945
2946 /* ENABLE_SCLK_AUD1 */
2947 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
2948 ENABLE_SCLK_AUD1, 6, 0, 0),
2949 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
2950 ENABLE_SCLK_AUD1, 5, 0, 0),
2951 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
2952 ENABLE_SCLK_AUD1, 4, 0, 0),
2953 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
2954 ENABLE_SCLK_AUD1, 3, 0, 0),
2955 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
2956 ENABLE_SCLK_AUD1, 2, 0, 0),
2957 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
2958 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
2959 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
2960 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
2961};
2962
2963static struct samsung_cmu_info aud_cmu_info __initdata = {
2964 .mux_clks = aud_mux_clks,
2965 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
2966 .div_clks = aud_div_clks,
2967 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
2968 .gate_clks = aud_gate_clks,
2969 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
2970 .fixed_clks = aud_fixed_clks,
2971 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
2972 .nr_clk_ids = AUD_NR_CLK,
2973 .clk_regs = aud_clk_regs,
2974 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
2975};
2976
2977static void __init exynos5433_cmu_aud_init(struct device_node *np)
2978{
2979 samsung_cmu_register_one(np, &aud_cmu_info);
2980}
2981CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
2982 exynos5433_cmu_aud_init);
5785d6e6
CC		 2983
2984
2985/*
2986 * Register offset definitions for CMU_BUS{0|1|2}
2987 */
2988#define DIV_BUS 0x0600
2989#define DIV_STAT_BUS 0x0700
2990#define ENABLE_ACLK_BUS 0x0800
2991#define ENABLE_PCLK_BUS 0x0900
2992#define ENABLE_IP_BUS0 0x0b00
2993#define ENABLE_IP_BUS1 0x0b04
2994
2995#define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
2996#define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
2997#define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
2998
2999/* list of all parent clock list */
3000PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
3001
3002#define CMU_BUS_COMMON_CLK_REGS \
3003 DIV_BUS, \
3004 DIV_STAT_BUS, \
3005 ENABLE_ACLK_BUS, \
3006 ENABLE_PCLK_BUS, \
3007 ENABLE_IP_BUS0, \
3008 ENABLE_IP_BUS1
3009
3010static unsigned long bus01_clk_regs[] __initdata = {
3011 CMU_BUS_COMMON_CLK_REGS,
3012};
3013
3014static unsigned long bus2_clk_regs[] __initdata = {
3015 MUX_SEL_BUS2,
3016 MUX_ENABLE_BUS2,
3017 MUX_STAT_BUS2,
3018 CMU_BUS_COMMON_CLK_REGS,
3019};
3020
3021static struct samsung_div_clock bus0_div_clks[] __initdata = {
3022 /* DIV_BUS0 */
3023 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3024 DIV_BUS, 0, 3),
3025};
3026
3027/* CMU_BUS0 clocks */
3028static struct samsung_gate_clock bus0_gate_clks[] __initdata = {
3029 /* ENABLE_ACLK_BUS0 */
3030 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3031 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3032 GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
3033 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3034 GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
3035 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3036
3037 /* ENABLE_PCLK_BUS0 */
3038 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3039 ENABLE_PCLK_BUS, 2, 0, 0),
3040 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
3041 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3042 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3043 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3044};
3045
3046/* CMU_BUS1 clocks */
3047static struct samsung_div_clock bus1_div_clks[] __initdata = {
3048 /* DIV_BUS1 */
3049 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3050 DIV_BUS, 0, 3),
3051};
3052
3053static struct samsung_gate_clock bus1_gate_clks[] __initdata = {
3054 /* ENABLE_ACLK_BUS1 */
3055 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3056 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3057 GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
3058 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3059 GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
3060 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3061
3062 /* ENABLE_PCLK_BUS1 */
3063 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3064 ENABLE_PCLK_BUS, 2, 0, 0),
3065 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
3066 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3067 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3068 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3069};
3070
3071/* CMU_BUS2 clocks */
3072static struct samsung_mux_clock bus2_mux_clks[] __initdata = {
3073 /* MUX_SEL_BUS2 */
3074 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3075 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3076};
3077
3078static struct samsung_div_clock bus2_div_clks[] __initdata = {
3079 /* DIV_BUS2 */
3080 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3081 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3082};
3083
3084static struct samsung_gate_clock bus2_gate_clks[] __initdata = {
3085 /* ENABLE_ACLK_BUS2 */
3086 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3087 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3088 GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
3089 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3090 GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
3091 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3092 1, CLK_IGNORE_UNUSED, 0),
3093 GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
3094 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3095 0, CLK_IGNORE_UNUSED, 0),
3096
3097 /* ENABLE_PCLK_BUS2 */
3098 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3099 ENABLE_PCLK_BUS, 2, 0, 0),
3100 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
3101 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3102 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3103 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3104};
3105
3106#define CMU_BUS_INFO_CLKS(id) \
3107 .div_clks = bus##id##_div_clks, \
3108 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
3109 .gate_clks = bus##id##_gate_clks, \
3110 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
3111 .nr_clk_ids = BUSx_NR_CLK
3112
3113static struct samsung_cmu_info bus0_cmu_info __initdata = {
3114 CMU_BUS_INFO_CLKS(0),
3115 .clk_regs = bus01_clk_regs,
3116 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3117};
3118
3119static struct samsung_cmu_info bus1_cmu_info __initdata = {
3120 CMU_BUS_INFO_CLKS(1),
3121 .clk_regs = bus01_clk_regs,
3122 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3123};
3124
3125static struct samsung_cmu_info bus2_cmu_info __initdata = {
3126 CMU_BUS_INFO_CLKS(2),
3127 .mux_clks = bus2_mux_clks,
3128 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
3129 .clk_regs = bus2_clk_regs,
3130 .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs),
3131};
3132
3133#define exynos5433_cmu_bus_init(id) \
3134static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3135{ \
3136 samsung_cmu_register_one(np, &bus##id##_cmu_info); \
3137} \
3138CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
3139 "samsung,exynos5433-cmu-bus"#id, \
3140 exynos5433_cmu_bus##id##_init)
3141
3142exynos5433_cmu_bus_init(0);
3143exynos5433_cmu_bus_init(1);
3144exynos5433_cmu_bus_init(2);
453e519e
CC		 3145
3146/*
3147 * Register offset definitions for CMU_G3D
3148 */
3149#define G3D_PLL_LOCK 0x0000
3150#define G3D_PLL_CON0 0x0100
3151#define G3D_PLL_CON1 0x0104
3152#define G3D_PLL_FREQ_DET 0x010c
3153#define MUX_SEL_G3D 0x0200
3154#define MUX_ENABLE_G3D 0x0300
3155#define MUX_STAT_G3D 0x0400
3156#define DIV_G3D 0x0600
3157#define DIV_G3D_PLL_FREQ_DET 0x0604
3158#define DIV_STAT_G3D 0x0700
3159#define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
3160#define ENABLE_ACLK_G3D 0x0800
3161#define ENABLE_PCLK_G3D 0x0900
3162#define ENABLE_SCLK_G3D 0x0a00
3163#define ENABLE_IP_G3D0 0x0b00
3164#define ENABLE_IP_G3D1 0x0b04
3165#define CLKOUT_CMU_G3D 0x0c00
3166#define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3167#define CLK_STOPCTRL 0x1000
3168
3169static unsigned long g3d_clk_regs[] __initdata = {
3170 G3D_PLL_LOCK,
3171 G3D_PLL_CON0,
3172 G3D_PLL_CON1,
3173 G3D_PLL_FREQ_DET,
3174 MUX_SEL_G3D,
3175 MUX_ENABLE_G3D,
3176 MUX_STAT_G3D,
3177 DIV_G3D,
3178 DIV_G3D_PLL_FREQ_DET,
3179 DIV_STAT_G3D,
3180 DIV_STAT_G3D_PLL_FREQ_DET,
3181 ENABLE_ACLK_G3D,
3182 ENABLE_PCLK_G3D,
3183 ENABLE_SCLK_G3D,
3184 ENABLE_IP_G3D0,
3185 ENABLE_IP_G3D1,
3186 CLKOUT_CMU_G3D,
3187 CLKOUT_CMU_G3D_DIV_STAT,
3188 CLK_STOPCTRL,
3189};
3190
3191/* list of all parent clock list */
3192PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
3193PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
3194
3195static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
3196 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3197 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates),
3198};
3199
3200static struct samsung_mux_clock g3d_mux_clks[] __initdata = {
3201 /* MUX_SEL_G3D */
3202 MUX(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3203 MUX_SEL_G3D, 8, 1),
3204 MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3205 MUX_SEL_G3D, 0, 1),
3206};
3207
3208static struct samsung_div_clock g3d_div_clks[] __initdata = {
3209 /* DIV_G3D */
3210 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3211 8, 2),
3212 DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
3213 4, 3),
3214 DIV(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3215 0, 3),
3216};
3217
3218static struct samsung_gate_clock g3d_gate_clks[] __initdata = {
3219 /* ENABLE_ACLK_G3D */
3220 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3221 ENABLE_ACLK_G3D, 7, 0, 0),
3222 GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
3223 ENABLE_ACLK_G3D, 6, 0, 0),
3224 GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3225 ENABLE_ACLK_G3D, 5, 0, 0),
3226 GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3227 ENABLE_ACLK_G3D, 4, 0, 0),
3228 GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3229 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3230 GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
3231 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3232 GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
3233 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3234 GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
3235 ENABLE_ACLK_G3D, 0, 0, 0),
3236
3237 /* ENABLE_PCLK_G3D */
3238 GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
3239 ENABLE_PCLK_G3D, 3, 0, 0),
3240 GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
3241 ENABLE_PCLK_G3D, 2, 0, 0),
3242 GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
3243 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3244 GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
3245 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3246
3247 /* ENABLE_SCLK_G3D */
3248 GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3249 ENABLE_SCLK_G3D, 0, 0, 0),
3250};
3251
3252static struct samsung_cmu_info g3d_cmu_info __initdata = {
3253 .pll_clks = g3d_pll_clks,
3254 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
3255 .mux_clks = g3d_mux_clks,
3256 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
3257 .div_clks = g3d_div_clks,
3258 .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
3259 .gate_clks = g3d_gate_clks,
3260 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
3261 .nr_clk_ids = G3D_NR_CLK,
3262 .clk_regs = g3d_clk_regs,
3263 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
3264};
3265
3266static void __init exynos5433_cmu_g3d_init(struct device_node *np)
3267{
3268 samsung_cmu_register_one(np, &g3d_cmu_info);
3269}
3270CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
3271 exynos5433_cmu_g3d_init);
2a2f33e8
CC		 3272
3273/*
3274 * Register offset definitions for CMU_GSCL
3275 */
3276#define MUX_SEL_GSCL 0x0200
3277#define MUX_ENABLE_GSCL 0x0300
3278#define MUX_STAT_GSCL 0x0400
3279#define ENABLE_ACLK_GSCL 0x0800
3280#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
3281#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
3282#define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
3283#define ENABLE_PCLK_GSCL 0x0900
3284#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
3285#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
3286#define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
3287#define ENABLE_IP_GSCL0 0x0b00
3288#define ENABLE_IP_GSCL1 0x0b04
3289#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
3290#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3291#define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3292
3293static unsigned long gscl_clk_regs[] __initdata = {
3294 MUX_SEL_GSCL,
3295 MUX_ENABLE_GSCL,
3296 MUX_STAT_GSCL,
3297 ENABLE_ACLK_GSCL,
3298 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
3299 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
3300 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
3301 ENABLE_PCLK_GSCL,
3302 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
3303 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
3304 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
3305 ENABLE_IP_GSCL0,
3306 ENABLE_IP_GSCL1,
3307 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
3308 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
3309 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3310};
3311
3312/* list of all parent clock list */
3313PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
3314PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
3315
3316static struct samsung_mux_clock gscl_mux_clks[] __initdata = {
3317 /* MUX_SEL_GSCL */
3318 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3319 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
3320 MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
3321 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3322};
3323
3324static struct samsung_gate_clock gscl_gate_clks[] __initdata = {
3325 /* ENABLE_ACLK_GSCL */
3326 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3327 ENABLE_ACLK_GSCL, 11, 0, 0),
3328 GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3329 ENABLE_ACLK_GSCL, 10, 0, 0),
3330 GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3331 ENABLE_ACLK_GSCL, 9, 0, 0),
3332 GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
3333 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
3334 8, CLK_IGNORE_UNUSED, 0),
3335 GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3336 ENABLE_ACLK_GSCL, 7, 0, 0),
3337 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3338 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3339 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3340 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0),
3341 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3342 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0),
3343 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3344 ENABLE_ACLK_GSCL, 3, 0, 0),
3345 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
3346 ENABLE_ACLK_GSCL, 2, 0, 0),
3347 GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
3348 ENABLE_ACLK_GSCL, 1, 0, 0),
3349 GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
3350 ENABLE_ACLK_GSCL, 0, 0, 0),
3351
3352 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3353 GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3354 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3355
3356 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3357 GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3358 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3359
3360 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3361 GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3362 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3363
3364 /* ENABLE_PCLK_GSCL */
3365 GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3366 ENABLE_PCLK_GSCL, 7, 0, 0),
3367 GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3368 ENABLE_PCLK_GSCL, 6, 0, 0),
3369 GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3370 ENABLE_PCLK_GSCL, 5, 0, 0),
3371 GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3372 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3373 GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
3374 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3375 3, CLK_IGNORE_UNUSED, 0),
3376 GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
3377 ENABLE_PCLK_GSCL, 2, 0, 0),
3378 GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
3379 ENABLE_PCLK_GSCL, 1, 0, 0),
3380 GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
3381 ENABLE_PCLK_GSCL, 0, 0, 0),
3382
3383 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3384 GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3385 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3386
3387 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3388 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3389 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3390
3391 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3392 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3393 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3394};
3395
3396static struct samsung_cmu_info gscl_cmu_info __initdata = {
3397 .mux_clks = gscl_mux_clks,
3398 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
3399 .gate_clks = gscl_gate_clks,
3400 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
3401 .nr_clk_ids = GSCL_NR_CLK,
3402 .clk_regs = gscl_clk_regs,
3403 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
3404};
3405
3406static void __init exynos5433_cmu_gscl_init(struct device_node *np)
3407{
3408 samsung_cmu_register_one(np, &gscl_cmu_info);
3409}
3410CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
3411 exynos5433_cmu_gscl_init);
df40a13c
CC		 3412
3413/*
3414 * Register offset definitions for CMU_APOLLO
3415 */
3416#define APOLLO_PLL_LOCK 0x0000
3417#define APOLLO_PLL_CON0 0x0100
3418#define APOLLO_PLL_CON1 0x0104
3419#define APOLLO_PLL_FREQ_DET 0x010c
3420#define MUX_SEL_APOLLO0 0x0200
3421#define MUX_SEL_APOLLO1 0x0204
3422#define MUX_SEL_APOLLO2 0x0208
3423#define MUX_ENABLE_APOLLO0 0x0300
3424#define MUX_ENABLE_APOLLO1 0x0304
3425#define MUX_ENABLE_APOLLO2 0x0308
3426#define MUX_STAT_APOLLO0 0x0400
3427#define MUX_STAT_APOLLO1 0x0404
3428#define MUX_STAT_APOLLO2 0x0408
3429#define DIV_APOLLO0 0x0600
3430#define DIV_APOLLO1 0x0604
3431#define DIV_APOLLO_PLL_FREQ_DET 0x0608
3432#define DIV_STAT_APOLLO0 0x0700
3433#define DIV_STAT_APOLLO1 0x0704
3434#define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
3435#define ENABLE_ACLK_APOLLO 0x0800
3436#define ENABLE_PCLK_APOLLO 0x0900
3437#define ENABLE_SCLK_APOLLO 0x0a00
3438#define ENABLE_IP_APOLLO0 0x0b00
3439#define ENABLE_IP_APOLLO1 0x0b04
3440#define CLKOUT_CMU_APOLLO 0x0c00
3441#define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
3442#define ARMCLK_STOPCTRL 0x1000
3443#define APOLLO_PWR_CTRL 0x1020
3444#define APOLLO_PWR_CTRL2 0x1024
3445#define APOLLO_INTR_SPREAD_ENABLE 0x1080
3446#define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3447#define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3448
3449static unsigned long apollo_clk_regs[] __initdata = {
3450 APOLLO_PLL_LOCK,
3451 APOLLO_PLL_CON0,
3452 APOLLO_PLL_CON1,
3453 APOLLO_PLL_FREQ_DET,
3454 MUX_SEL_APOLLO0,
3455 MUX_SEL_APOLLO1,
3456 MUX_SEL_APOLLO2,
3457 MUX_ENABLE_APOLLO0,
3458 MUX_ENABLE_APOLLO1,
3459 MUX_ENABLE_APOLLO2,
3460 MUX_STAT_APOLLO0,
3461 MUX_STAT_APOLLO1,
3462 MUX_STAT_APOLLO2,
3463 DIV_APOLLO0,
3464 DIV_APOLLO1,
3465 DIV_APOLLO_PLL_FREQ_DET,
3466 DIV_STAT_APOLLO0,
3467 DIV_STAT_APOLLO1,
3468 DIV_STAT_APOLLO_PLL_FREQ_DET,
3469 ENABLE_ACLK_APOLLO,
3470 ENABLE_PCLK_APOLLO,
3471 ENABLE_SCLK_APOLLO,
3472 ENABLE_IP_APOLLO0,
3473 ENABLE_IP_APOLLO1,
3474 CLKOUT_CMU_APOLLO,
3475 CLKOUT_CMU_APOLLO_DIV_STAT,
3476 ARMCLK_STOPCTRL,
3477 APOLLO_PWR_CTRL,
3478 APOLLO_PWR_CTRL2,
3479 APOLLO_INTR_SPREAD_ENABLE,
3480 APOLLO_INTR_SPREAD_USE_STANDBYWFI,
3481 APOLLO_INTR_SPREAD_BLOCKING_DURATION,
3482};
3483
3484/* list of all parent clock list */
3485PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", };
3486PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
3487PNAME(mout_apollo_p) = { "mout_apollo_pll",
3488 "mout_bus_pll_apollo_user", };
3489
3490static struct samsung_pll_clock apollo_pll_clks[] __initdata = {
3491 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3492 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates),
3493};
3494
3495static struct samsung_mux_clock apollo_mux_clks[] __initdata = {
3496 /* MUX_SEL_APOLLO0 */
3497 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3498 MUX_SEL_APOLLO0, 0, 1, 0, CLK_MUX_READ_ONLY),
3499
3500 /* MUX_SEL_APOLLO1 */
3501 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
3502 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3503
3504 /* MUX_SEL_APOLLO2 */
3505 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3506 0, 1, 0, CLK_MUX_READ_ONLY),
3507};
3508
3509static struct samsung_div_clock apollo_div_clks[] __initdata = {
3510 /* DIV_APOLLO0 */
3511 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3512 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
3513 CLK_DIVIDER_READ_ONLY),
3514 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3515 DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
3516 CLK_DIVIDER_READ_ONLY),
3517 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3518 DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
3519 CLK_DIVIDER_READ_ONLY),
3520 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3521 DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
3522 CLK_DIVIDER_READ_ONLY),
3523 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3524 DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
3525 CLK_DIVIDER_READ_ONLY),
3526 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3527 DIV_APOLLO0, 4, 3, CLK_GET_RATE_NOCACHE,
3528 CLK_DIVIDER_READ_ONLY),
3529 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
3530 DIV_APOLLO0, 0, 3, CLK_GET_RATE_NOCACHE,
3531 CLK_DIVIDER_READ_ONLY),
3532
3533 /* DIV_APOLLO1 */
3534 DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
3535 DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
3536 CLK_DIVIDER_READ_ONLY),
3537 DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
3538 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3539 CLK_DIVIDER_READ_ONLY),
3540};
3541
3542static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
3543 /* ENABLE_ACLK_APOLLO */
3544 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3545 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3546 6, CLK_IGNORE_UNUSED, 0),
3547 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
3548 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3549 5, CLK_IGNORE_UNUSED, 0),
3550 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
3551 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3552 4, CLK_IGNORE_UNUSED, 0),
3553 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
3554 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3555 3, CLK_IGNORE_UNUSED, 0),
3556 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
3557 "div_aclk_apollo", ENABLE_ACLK_APOLLO,
3558 2, CLK_IGNORE_UNUSED, 0),
3559 GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
3560 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3561 1, CLK_IGNORE_UNUSED, 0),
3562 GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
3563 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3564 0, CLK_IGNORE_UNUSED, 0),
3565
3566 /* ENABLE_PCLK_APOLLO */
3567 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
3568 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
3569 2, CLK_IGNORE_UNUSED, 0),
3570 GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
3571 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3572 GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
3573 "div_pclk_apollo", ENABLE_PCLK_APOLLO,
3574 0, CLK_IGNORE_UNUSED, 0),
3575
3576 /* ENABLE_SCLK_APOLLO */
3577 GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
3578 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3579 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3580 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3581 GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo_pll",
3582 ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0),
3583};
3584
3585static struct samsung_cmu_info apollo_cmu_info __initdata = {
3586 .pll_clks = apollo_pll_clks,
3587 .nr_pll_clks = ARRAY_SIZE(apollo_pll_clks),
3588 .mux_clks = apollo_mux_clks,
3589 .nr_mux_clks = ARRAY_SIZE(apollo_mux_clks),
3590 .div_clks = apollo_div_clks,
3591 .nr_div_clks = ARRAY_SIZE(apollo_div_clks),
3592 .gate_clks = apollo_gate_clks,
3593 .nr_gate_clks = ARRAY_SIZE(apollo_gate_clks),
3594 .nr_clk_ids = APOLLO_NR_CLK,
3595 .clk_regs = apollo_clk_regs,
3596 .nr_clk_regs = ARRAY_SIZE(apollo_clk_regs),
3597};
3598
3599static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3600{
3601 samsung_cmu_register_one(np, &apollo_cmu_info);
3602}
3603CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3604 exynos5433_cmu_apollo_init);
6c5d76d1
CC		 3605
3606/*
3607 * Register offset definitions for CMU_ATLAS
3608 */
3609#define ATLAS_PLL_LOCK 0x0000
3610#define ATLAS_PLL_CON0 0x0100
3611#define ATLAS_PLL_CON1 0x0104
3612#define ATLAS_PLL_FREQ_DET 0x010c
3613#define MUX_SEL_ATLAS0 0x0200
3614#define MUX_SEL_ATLAS1 0x0204
3615#define MUX_SEL_ATLAS2 0x0208
3616#define MUX_ENABLE_ATLAS0 0x0300
3617#define MUX_ENABLE_ATLAS1 0x0304
3618#define MUX_ENABLE_ATLAS2 0x0308
3619#define MUX_STAT_ATLAS0 0x0400
3620#define MUX_STAT_ATLAS1 0x0404
3621#define MUX_STAT_ATLAS2 0x0408
3622#define DIV_ATLAS0 0x0600
3623#define DIV_ATLAS1 0x0604
3624#define DIV_ATLAS_PLL_FREQ_DET 0x0608
3625#define DIV_STAT_ATLAS0 0x0700
3626#define DIV_STAT_ATLAS1 0x0704
3627#define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
3628#define ENABLE_ACLK_ATLAS 0x0800
3629#define ENABLE_PCLK_ATLAS 0x0900
3630#define ENABLE_SCLK_ATLAS 0x0a00
3631#define ENABLE_IP_ATLAS0 0x0b00
3632#define ENABLE_IP_ATLAS1 0x0b04
3633#define CLKOUT_CMU_ATLAS 0x0c00
3634#define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
3635#define ARMCLK_STOPCTRL 0x1000
3636#define ATLAS_PWR_CTRL 0x1020
3637#define ATLAS_PWR_CTRL2 0x1024
3638#define ATLAS_INTR_SPREAD_ENABLE 0x1080
3639#define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3640#define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3641
3642static unsigned long atlas_clk_regs[] __initdata = {
3643 ATLAS_PLL_LOCK,
3644 ATLAS_PLL_CON0,
3645 ATLAS_PLL_CON1,
3646 ATLAS_PLL_FREQ_DET,
3647 MUX_SEL_ATLAS0,
3648 MUX_SEL_ATLAS1,
3649 MUX_SEL_ATLAS2,
3650 MUX_ENABLE_ATLAS0,
3651 MUX_ENABLE_ATLAS1,
3652 MUX_ENABLE_ATLAS2,
3653 MUX_STAT_ATLAS0,
3654 MUX_STAT_ATLAS1,
3655 MUX_STAT_ATLAS2,
3656 DIV_ATLAS0,
3657 DIV_ATLAS1,
3658 DIV_ATLAS_PLL_FREQ_DET,
3659 DIV_STAT_ATLAS0,
3660 DIV_STAT_ATLAS1,
3661 DIV_STAT_ATLAS_PLL_FREQ_DET,
3662 ENABLE_ACLK_ATLAS,
3663 ENABLE_PCLK_ATLAS,
3664 ENABLE_SCLK_ATLAS,
3665 ENABLE_IP_ATLAS0,
3666 ENABLE_IP_ATLAS1,
3667 CLKOUT_CMU_ATLAS,
3668 CLKOUT_CMU_ATLAS_DIV_STAT,
3669 ARMCLK_STOPCTRL,
3670 ATLAS_PWR_CTRL,
3671 ATLAS_PWR_CTRL2,
3672 ATLAS_INTR_SPREAD_ENABLE,
3673 ATLAS_INTR_SPREAD_USE_STANDBYWFI,
3674 ATLAS_INTR_SPREAD_BLOCKING_DURATION,
3675};
3676
3677/* list of all parent clock list */
3678PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", };
3679PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
3680PNAME(mout_atlas_p) = { "mout_atlas_pll",
3681 "mout_bus_pll_atlas_user", };
3682
3683static struct samsung_pll_clock atlas_pll_clks[] __initdata = {
3684 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3685 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates),
3686};
3687
3688static struct samsung_mux_clock atlas_mux_clks[] __initdata = {
3689 /* MUX_SEL_ATLAS0 */
3690 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3691 MUX_SEL_ATLAS0, 0, 1, 0, CLK_MUX_READ_ONLY),
3692
3693 /* MUX_SEL_ATLAS1 */
3694 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
3695 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3696
3697 /* MUX_SEL_ATLAS2 */
3698 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
3699 0, 1, 0, CLK_MUX_READ_ONLY),
3700};
3701
3702static struct samsung_div_clock atlas_div_clks[] __initdata = {
3703 /* DIV_ATLAS0 */
3704 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3705 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
3706 CLK_DIVIDER_READ_ONLY),
3707 DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
3708 DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
3709 CLK_DIVIDER_READ_ONLY),
3710 DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
3711 DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
3712 CLK_DIVIDER_READ_ONLY),
3713 DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
3714 DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
3715 CLK_DIVIDER_READ_ONLY),
3716 DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
3717 DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
3718 CLK_DIVIDER_READ_ONLY),
3719 DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
3720 DIV_ATLAS0, 4, 3, CLK_GET_RATE_NOCACHE,
3721 CLK_DIVIDER_READ_ONLY),
3722 DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
3723 DIV_ATLAS0, 0, 3, CLK_GET_RATE_NOCACHE,
3724 CLK_DIVIDER_READ_ONLY),
3725
3726 /* DIV_ATLAS1 */
3727 DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
3728 DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
3729 CLK_DIVIDER_READ_ONLY),
3730 DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
3731 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3732 CLK_DIVIDER_READ_ONLY),
3733};
3734
3735static struct samsung_gate_clock atlas_gate_clks[] __initdata = {
3736 /* ENABLE_ACLK_ATLAS */
3737 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3738 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3739 9, CLK_IGNORE_UNUSED, 0),
3740 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
3741 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3742 8, CLK_IGNORE_UNUSED, 0),
3743 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
3744 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3745 7, CLK_IGNORE_UNUSED, 0),
3746 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
3747 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3748 6, CLK_IGNORE_UNUSED, 0),
3749 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
3750 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3751 5, CLK_IGNORE_UNUSED, 0),
3752 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
3753 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3754 4, CLK_IGNORE_UNUSED, 0),
3755 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
3756 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3757 3, CLK_IGNORE_UNUSED, 0),
3758 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
3759 "div_aclk_atlas", ENABLE_ACLK_ATLAS,
3760 2, CLK_IGNORE_UNUSED, 0),
3761 GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3762 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3763 GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
3764 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3765
3766 /* ENABLE_PCLK_ATLAS */
3767 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
3768 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3769 5, CLK_IGNORE_UNUSED, 0),
3770 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
3771 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3772 4, CLK_IGNORE_UNUSED, 0),
3773 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
3774 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3775 3, CLK_IGNORE_UNUSED, 0),
3776 GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
3777 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3778 GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
3779 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3780 GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
3781 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3782
3783 /* ENABLE_SCLK_ATLAS */
3784 GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
3785 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3786 GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3787 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3788 GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
3789 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3790 GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
3791 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3792 GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
3793 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3794 GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3795 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3796 GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
3797 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3798 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3799 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3800 GATE(CLK_SCLK_ATLAS, "sclk_atlas", "div_atlas2",
3801 ENABLE_SCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3802};
3803
3804static struct samsung_cmu_info atlas_cmu_info __initdata = {
3805 .pll_clks = atlas_pll_clks,
3806 .nr_pll_clks = ARRAY_SIZE(atlas_pll_clks),
3807 .mux_clks = atlas_mux_clks,
3808 .nr_mux_clks = ARRAY_SIZE(atlas_mux_clks),
3809 .div_clks = atlas_div_clks,
3810 .nr_div_clks = ARRAY_SIZE(atlas_div_clks),
3811 .gate_clks = atlas_gate_clks,
3812 .nr_gate_clks = ARRAY_SIZE(atlas_gate_clks),
3813 .nr_clk_ids = ATLAS_NR_CLK,
3814 .clk_regs = atlas_clk_regs,
3815 .nr_clk_regs = ARRAY_SIZE(atlas_clk_regs),
3816};
3817
3818static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3819{
3820 samsung_cmu_register_one(np, &atlas_cmu_info);
3821}
3822CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3823 exynos5433_cmu_atlas_init);
b274bbfd
CC		 3824
3825/*
3826 * Register offset definitions for CMU_MSCL
3827 */
3828#define MUX_SEL_MSCL0 0x0200
3829#define MUX_SEL_MSCL1 0x0204
3830#define MUX_ENABLE_MSCL0 0x0300
3831#define MUX_ENABLE_MSCL1 0x0304
3832#define MUX_STAT_MSCL0 0x0400
3833#define MUX_STAT_MSCL1 0x0404
3834#define DIV_MSCL 0x0600
3835#define DIV_STAT_MSCL 0x0700
3836#define ENABLE_ACLK_MSCL 0x0800
3837#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
3838#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
3839#define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
3840#define ENABLE_PCLK_MSCL 0x0900
3841#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
3842#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
3843#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x000c
3844#define ENABLE_SCLK_MSCL 0x0a00
3845#define ENABLE_IP_MSCL0 0x0b00
3846#define ENABLE_IP_MSCL1 0x0b04
3847#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
3848#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
3849#define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
3850
3851static unsigned long mscl_clk_regs[] __initdata = {
3852 MUX_SEL_MSCL0,
3853 MUX_SEL_MSCL1,
3854 MUX_ENABLE_MSCL0,
3855 MUX_ENABLE_MSCL1,
3856 MUX_STAT_MSCL0,
3857 MUX_STAT_MSCL1,
3858 DIV_MSCL,
3859 DIV_STAT_MSCL,
3860 ENABLE_ACLK_MSCL,
3861 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
3862 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
3863 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
3864 ENABLE_PCLK_MSCL,
3865 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
3866 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
3867 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
3868 ENABLE_SCLK_MSCL,
3869 ENABLE_IP_MSCL0,
3870 ENABLE_IP_MSCL1,
3871 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
3872 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
3873 ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
3874};
3875
3876/* list of all parent clock list */
3877PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", };
3878PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
3879PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
3880 "mout_aclk_mscl_400_user", };
3881
3882static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
3883 /* MUX_SEL_MSCL0 */
3884 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
3885 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
3886 MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
3887 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
3888
3889 /* MUX_SEL_MSCL1 */
3890 MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
3891 MUX_SEL_MSCL1, 0, 1),
3892};
3893
3894static struct samsung_div_clock mscl_div_clks[] __initdata = {
3895 /* DIV_MSCL */
3896 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
3897 DIV_MSCL, 0, 3),
3898};
3899
3900static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
3901 /* ENABLE_ACLK_MSCL */
3902 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
3903 ENABLE_ACLK_MSCL, 9, 0, 0),
3904 GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
3905 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
3906 GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
3907 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
3908 GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
3909 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
3910 GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
3911 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
3912 GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
3913 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
3914 GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
3915 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
3916 GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
3917 ENABLE_ACLK_MSCL, 2, 0, 0),
3918 GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
3919 ENABLE_ACLK_MSCL, 1, 0, 0),
3920 GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
3921 ENABLE_ACLK_MSCL, 0, 0, 0),
3922
3923 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
3924 GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
3925 "mout_aclk_mscl_400_user",
3926 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
3927 0, CLK_IGNORE_UNUSED, 0),
3928
3929 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
3930 GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
3931 "mout_aclk_mscl_400_user",
3932 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
3933 0, CLK_IGNORE_UNUSED, 0),
3934
3935 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
3936 GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
3937 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
3938 0, CLK_IGNORE_UNUSED, 0),
3939
3940 /* ENABLE_PCLK_MSCL */
3941 GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
3942 ENABLE_PCLK_MSCL, 7, 0, 0),
3943 GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
3944 ENABLE_PCLK_MSCL, 6, 0, 0),
3945 GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
3946 ENABLE_PCLK_MSCL, 5, 0, 0),
3947 GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
3948 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
3949 GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
3950 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
3951 GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
3952 ENABLE_PCLK_MSCL, 2, 0, 0),
3953 GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
3954 ENABLE_PCLK_MSCL, 1, 0, 0),
3955 GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
3956 ENABLE_PCLK_MSCL, 0, 0, 0),
3957
3958 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
3959 GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
3960 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
3961 0, CLK_IGNORE_UNUSED, 0),
3962
3963 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
3964 GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
3965 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
3966 0, CLK_IGNORE_UNUSED, 0),
3967
3968 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
3969 GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
3970 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
3971 0, CLK_IGNORE_UNUSED, 0),
3972
3973 /* ENABLE_SCLK_MSCL */
3974 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
3975 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
3976};
3977
3978static struct samsung_cmu_info mscl_cmu_info __initdata = {
3979 .mux_clks = mscl_mux_clks,
3980 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
3981 .div_clks = mscl_div_clks,
3982 .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
3983 .gate_clks = mscl_gate_clks,
3984 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
3985 .nr_clk_ids = MSCL_NR_CLK,
3986 .clk_regs = mscl_clk_regs,
3987 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
3988};
3989
3990static void __init exynos5433_cmu_mscl_init(struct device_node *np)
3991{
3992 samsung_cmu_register_one(np, &mscl_cmu_info);
3993}
3994CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
3995 exynos5433_cmu_mscl_init);
9910b6bb
CC		 3996
3997/*
3998 * Register offset definitions for CMU_MFC
3999 */
4000#define MUX_SEL_MFC 0x0200
4001#define MUX_ENABLE_MFC 0x0300
4002#define MUX_STAT_MFC 0x0400
4003#define DIV_MFC 0x0600
4004#define DIV_STAT_MFC 0x0700
4005#define ENABLE_ACLK_MFC 0x0800
4006#define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
4007#define ENABLE_PCLK_MFC 0x0900
4008#define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
4009#define ENABLE_IP_MFC0 0x0b00
4010#define ENABLE_IP_MFC1 0x0b04
4011#define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4012
4013static unsigned long mfc_clk_regs[] __initdata = {
4014 MUX_SEL_MFC,
4015 MUX_ENABLE_MFC,
4016 MUX_STAT_MFC,
4017 DIV_MFC,
4018 DIV_STAT_MFC,
4019 ENABLE_ACLK_MFC,
4020 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4021 ENABLE_PCLK_MFC,
4022 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4023 ENABLE_IP_MFC0,
4024 ENABLE_IP_MFC1,
4025 ENABLE_IP_MFC_SECURE_SMMU_MFC,
4026};
4027
4028PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
4029
4030static struct samsung_mux_clock mfc_mux_clks[] __initdata = {
4031 /* MUX_SEL_MFC */
4032 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4033 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4034};
4035
4036static struct samsung_div_clock mfc_div_clks[] __initdata = {
4037 /* DIV_MFC */
4038 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4039 DIV_MFC, 0, 2),
4040};
4041
4042static struct samsung_gate_clock mfc_gate_clks[] __initdata = {
4043 /* ENABLE_ACLK_MFC */
4044 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4045 ENABLE_ACLK_MFC, 6, 0, 0),
4046 GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4047 ENABLE_ACLK_MFC, 5, 0, 0),
4048 GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4049 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4050 GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4051 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4052 GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
4053 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4054 GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4055 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4056 GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
4057 ENABLE_ACLK_MFC, 0, 0, 0),
4058
4059 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4060 GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4061 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4062 1, CLK_IGNORE_UNUSED, 0),
4063 GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4064 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4065 0, CLK_IGNORE_UNUSED, 0),
4066
4067 /* ENABLE_PCLK_MFC */
4068 GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
4069 ENABLE_PCLK_MFC, 4, 0, 0),
4070 GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
4071 ENABLE_PCLK_MFC, 3, 0, 0),
4072 GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
4073 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4074 GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
4075 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4076 GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
4077 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4078
4079 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4080 GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
4081 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4082 1, CLK_IGNORE_UNUSED, 0),
4083 GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
4084 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4085 0, CLK_IGNORE_UNUSED, 0),
4086};
4087
4088static struct samsung_cmu_info mfc_cmu_info __initdata = {
4089 .mux_clks = mfc_mux_clks,
4090 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
4091 .div_clks = mfc_div_clks,
4092 .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
4093 .gate_clks = mfc_gate_clks,
4094 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
4095 .nr_clk_ids = MFC_NR_CLK,
4096 .clk_regs = mfc_clk_regs,
4097 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
4098};
4099
4100static void __init exynos5433_cmu_mfc_init(struct device_node *np)
4101{
4102 samsung_cmu_register_one(np, &mfc_cmu_info);
4103}
4104CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
4105 exynos5433_cmu_mfc_init);
Ubuntu Hirsute Linux kernel mirror