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1 | /* |
2 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. | |
3 | * Author: Chanwoo Choi <cw00.choi@samsung.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * Common Clock Framework support for Exynos5443 SoC. | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/clkdev.h> | |
14 | #include <linux/clk-provider.h> | |
15 | #include <linux/of.h> | |
16 | ||
17 | #include <dt-bindings/clock/exynos5433.h> | |
18 | ||
19 | #include "clk.h" | |
20 | #include "clk-pll.h" | |
21 | ||
22 | /* | |
23 | * Register offset definitions for CMU_TOP | |
24 | */ | |
25 | #define ISP_PLL_LOCK 0x0000 | |
26 | #define AUD_PLL_LOCK 0x0004 | |
27 | #define ISP_PLL_CON0 0x0100 | |
28 | #define ISP_PLL_CON1 0x0104 | |
29 | #define ISP_PLL_FREQ_DET 0x0108 | |
30 | #define AUD_PLL_CON0 0x0110 | |
31 | #define AUD_PLL_CON1 0x0114 | |
32 | #define AUD_PLL_CON2 0x0118 | |
33 | #define AUD_PLL_FREQ_DET 0x011c | |
34 | #define MUX_SEL_TOP0 0x0200 | |
35 | #define MUX_SEL_TOP1 0x0204 | |
36 | #define MUX_SEL_TOP2 0x0208 | |
37 | #define MUX_SEL_TOP3 0x020c | |
38 | #define MUX_SEL_TOP4 0x0210 | |
39 | #define MUX_SEL_TOP_MSCL 0x0220 | |
40 | #define MUX_SEL_TOP_CAM1 0x0224 | |
41 | #define MUX_SEL_TOP_DISP 0x0228 | |
42 | #define MUX_SEL_TOP_FSYS0 0x0230 | |
43 | #define MUX_SEL_TOP_FSYS1 0x0234 | |
44 | #define MUX_SEL_TOP_PERIC0 0x0238 | |
45 | #define MUX_SEL_TOP_PERIC1 0x023c | |
46 | #define MUX_ENABLE_TOP0 0x0300 | |
47 | #define MUX_ENABLE_TOP1 0x0304 | |
48 | #define MUX_ENABLE_TOP2 0x0308 | |
49 | #define MUX_ENABLE_TOP3 0x030c | |
50 | #define MUX_ENABLE_TOP4 0x0310 | |
51 | #define MUX_ENABLE_TOP_MSCL 0x0320 | |
52 | #define MUX_ENABLE_TOP_CAM1 0x0324 | |
53 | #define MUX_ENABLE_TOP_DISP 0x0328 | |
54 | #define MUX_ENABLE_TOP_FSYS0 0x0330 | |
55 | #define MUX_ENABLE_TOP_FSYS1 0x0334 | |
56 | #define MUX_ENABLE_TOP_PERIC0 0x0338 | |
57 | #define MUX_ENABLE_TOP_PERIC1 0x033c | |
58 | #define MUX_STAT_TOP0 0x0400 | |
59 | #define MUX_STAT_TOP1 0x0404 | |
60 | #define MUX_STAT_TOP2 0x0408 | |
61 | #define MUX_STAT_TOP3 0x040c | |
62 | #define MUX_STAT_TOP4 0x0410 | |
63 | #define MUX_STAT_TOP_MSCL 0x0420 | |
64 | #define MUX_STAT_TOP_CAM1 0x0424 | |
65 | #define MUX_STAT_TOP_FSYS0 0x0430 | |
66 | #define MUX_STAT_TOP_FSYS1 0x0434 | |
67 | #define MUX_STAT_TOP_PERIC0 0x0438 | |
68 | #define MUX_STAT_TOP_PERIC1 0x043c | |
69 | #define DIV_TOP0 0x0600 | |
70 | #define DIV_TOP1 0x0604 | |
71 | #define DIV_TOP2 0x0608 | |
72 | #define DIV_TOP3 0x060c | |
73 | #define DIV_TOP4 0x0610 | |
74 | #define DIV_TOP_MSCL 0x0618 | |
75 | #define DIV_TOP_CAM10 0x061c | |
76 | #define DIV_TOP_CAM11 0x0620 | |
77 | #define DIV_TOP_FSYS0 0x062c | |
78 | #define DIV_TOP_FSYS1 0x0630 | |
79 | #define DIV_TOP_FSYS2 0x0634 | |
80 | #define DIV_TOP_PERIC0 0x0638 | |
81 | #define DIV_TOP_PERIC1 0x063c | |
82 | #define DIV_TOP_PERIC2 0x0640 | |
83 | #define DIV_TOP_PERIC3 0x0644 | |
84 | #define DIV_TOP_PERIC4 0x0648 | |
85 | #define DIV_TOP_PLL_FREQ_DET 0x064c | |
86 | #define DIV_STAT_TOP0 0x0700 | |
87 | #define DIV_STAT_TOP1 0x0704 | |
88 | #define DIV_STAT_TOP2 0x0708 | |
89 | #define DIV_STAT_TOP3 0x070c | |
90 | #define DIV_STAT_TOP4 0x0710 | |
91 | #define DIV_STAT_TOP_MSCL 0x0718 | |
92 | #define DIV_STAT_TOP_CAM10 0x071c | |
93 | #define DIV_STAT_TOP_CAM11 0x0720 | |
94 | #define DIV_STAT_TOP_FSYS0 0x072c | |
95 | #define DIV_STAT_TOP_FSYS1 0x0730 | |
96 | #define DIV_STAT_TOP_FSYS2 0x0734 | |
97 | #define DIV_STAT_TOP_PERIC0 0x0738 | |
98 | #define DIV_STAT_TOP_PERIC1 0x073c | |
99 | #define DIV_STAT_TOP_PERIC2 0x0740 | |
100 | #define DIV_STAT_TOP_PERIC3 0x0744 | |
101 | #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c | |
102 | #define ENABLE_ACLK_TOP 0x0800 | |
103 | #define ENABLE_SCLK_TOP 0x0a00 | |
104 | #define ENABLE_SCLK_TOP_MSCL 0x0a04 | |
105 | #define ENABLE_SCLK_TOP_CAM1 0x0a08 | |
106 | #define ENABLE_SCLK_TOP_DISP 0x0a0c | |
107 | #define ENABLE_SCLK_TOP_FSYS 0x0a10 | |
108 | #define ENABLE_SCLK_TOP_PERIC 0x0a14 | |
109 | #define ENABLE_IP_TOP 0x0b00 | |
110 | #define ENABLE_CMU_TOP 0x0c00 | |
111 | #define ENABLE_CMU_TOP_DIV_STAT 0x0c04 | |
112 | ||
113 | static unsigned long top_clk_regs[] __initdata = { | |
114 | ISP_PLL_LOCK, | |
115 | AUD_PLL_LOCK, | |
116 | ISP_PLL_CON0, | |
117 | ISP_PLL_CON1, | |
118 | ISP_PLL_FREQ_DET, | |
119 | AUD_PLL_CON0, | |
120 | AUD_PLL_CON1, | |
121 | AUD_PLL_CON2, | |
122 | AUD_PLL_FREQ_DET, | |
123 | MUX_SEL_TOP0, | |
124 | MUX_SEL_TOP1, | |
125 | MUX_SEL_TOP2, | |
126 | MUX_SEL_TOP3, | |
127 | MUX_SEL_TOP4, | |
128 | MUX_SEL_TOP_MSCL, | |
129 | MUX_SEL_TOP_CAM1, | |
130 | MUX_SEL_TOP_DISP, | |
131 | MUX_SEL_TOP_FSYS0, | |
132 | MUX_SEL_TOP_FSYS1, | |
133 | MUX_SEL_TOP_PERIC0, | |
134 | MUX_SEL_TOP_PERIC1, | |
135 | MUX_ENABLE_TOP0, | |
136 | MUX_ENABLE_TOP1, | |
137 | MUX_ENABLE_TOP2, | |
138 | MUX_ENABLE_TOP3, | |
139 | MUX_ENABLE_TOP4, | |
140 | MUX_ENABLE_TOP_MSCL, | |
141 | MUX_ENABLE_TOP_CAM1, | |
142 | MUX_ENABLE_TOP_DISP, | |
143 | MUX_ENABLE_TOP_FSYS0, | |
144 | MUX_ENABLE_TOP_FSYS1, | |
145 | MUX_ENABLE_TOP_PERIC0, | |
146 | MUX_ENABLE_TOP_PERIC1, | |
147 | MUX_STAT_TOP0, | |
148 | MUX_STAT_TOP1, | |
149 | MUX_STAT_TOP2, | |
150 | MUX_STAT_TOP3, | |
151 | MUX_STAT_TOP4, | |
152 | MUX_STAT_TOP_MSCL, | |
153 | MUX_STAT_TOP_CAM1, | |
154 | MUX_STAT_TOP_FSYS0, | |
155 | MUX_STAT_TOP_FSYS1, | |
156 | MUX_STAT_TOP_PERIC0, | |
157 | MUX_STAT_TOP_PERIC1, | |
158 | DIV_TOP0, | |
159 | DIV_TOP1, | |
160 | DIV_TOP2, | |
161 | DIV_TOP3, | |
162 | DIV_TOP4, | |
163 | DIV_TOP_MSCL, | |
164 | DIV_TOP_CAM10, | |
165 | DIV_TOP_CAM11, | |
166 | DIV_TOP_FSYS0, | |
167 | DIV_TOP_FSYS1, | |
168 | DIV_TOP_FSYS2, | |
169 | DIV_TOP_PERIC0, | |
170 | DIV_TOP_PERIC1, | |
171 | DIV_TOP_PERIC2, | |
172 | DIV_TOP_PERIC3, | |
173 | DIV_TOP_PERIC4, | |
174 | DIV_TOP_PLL_FREQ_DET, | |
175 | DIV_STAT_TOP0, | |
176 | DIV_STAT_TOP1, | |
177 | DIV_STAT_TOP2, | |
178 | DIV_STAT_TOP3, | |
179 | DIV_STAT_TOP4, | |
180 | DIV_STAT_TOP_MSCL, | |
181 | DIV_STAT_TOP_CAM10, | |
182 | DIV_STAT_TOP_CAM11, | |
183 | DIV_STAT_TOP_FSYS0, | |
184 | DIV_STAT_TOP_FSYS1, | |
185 | DIV_STAT_TOP_FSYS2, | |
186 | DIV_STAT_TOP_PERIC0, | |
187 | DIV_STAT_TOP_PERIC1, | |
188 | DIV_STAT_TOP_PERIC2, | |
189 | DIV_STAT_TOP_PERIC3, | |
190 | DIV_STAT_TOP_PLL_FREQ_DET, | |
191 | ENABLE_ACLK_TOP, | |
192 | ENABLE_SCLK_TOP, | |
193 | ENABLE_SCLK_TOP_MSCL, | |
194 | ENABLE_SCLK_TOP_CAM1, | |
195 | ENABLE_SCLK_TOP_DISP, | |
196 | ENABLE_SCLK_TOP_FSYS, | |
197 | ENABLE_SCLK_TOP_PERIC, | |
198 | ENABLE_IP_TOP, | |
199 | ENABLE_CMU_TOP, | |
200 | ENABLE_CMU_TOP_DIV_STAT, | |
201 | }; | |
202 | ||
203 | /* list of all parent clock list */ | |
204 | PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", }; | |
205 | PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", }; | |
206 | PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", }; | |
207 | PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", }; | |
208 | PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", }; | |
209 | PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", }; | |
210 | PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", }; | |
23236496 | 211 | PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", }; |
96bd6224 CC |
212 | |
213 | PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",}; | |
214 | PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",}; | |
215 | PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a", | |
216 | "mout_mfc_pll_user", }; | |
217 | PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", }; | |
218 | ||
23236496 CC |
219 | PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b", |
220 | "mout_mphy_pll_user", }; | |
221 | PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a", | |
222 | "mout_bus_pll_user", }; | |
223 | PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", }; | |
224 | ||
96bd6224 CC |
225 | PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user", |
226 | "mout_mphy_pll_user", }; | |
227 | PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a", | |
228 | "mout_mphy_pll_user", }; | |
229 | PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a", | |
230 | "mout_mphy_pll_user", }; | |
231 | ||
232 | PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",}; | |
233 | PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", }; | |
234 | ||
235 | PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",}; | |
236 | PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",}; | |
237 | PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", }; | |
238 | PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",}; | |
239 | PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", }; | |
240 | ||
23236496 CC |
241 | PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1", |
242 | "oscclk", "ioclk_spdif_extclk", }; | |
243 | PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk", | |
244 | "mout_aud_pll_user_t",}; | |
245 | PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk", | |
246 | "mout_aud_pll_user_t",}; | |
247 | ||
2a1808a6 CC |
248 | PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", }; |
249 | ||
56bcf3f3 CC |
250 | static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = { |
251 | FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0), | |
252 | }; | |
253 | ||
23236496 CC |
254 | static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = { |
255 | /* Xi2s{0|1}CDCLK input clock for I2S/PCM */ | |
256 | FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000), | |
257 | FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000), | |
258 | /* Xi2s1SDI input clock for SPDIF */ | |
259 | FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000), | |
d0f5de66 CC |
260 | /* XspiCLK[4:0] input clock for SPI */ |
261 | FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000), | |
262 | FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000), | |
263 | FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000), | |
264 | FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000), | |
265 | FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000), | |
266 | /* Xi2s1SCLK input clock for I2S1_BCLK */ | |
267 | FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000), | |
23236496 CC |
268 | }; |
269 | ||
96bd6224 CC |
270 | static struct samsung_mux_clock top_mux_clks[] __initdata = { |
271 | /* MUX_SEL_TOP0 */ | |
272 | MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0, | |
273 | 4, 1), | |
274 | MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0, | |
275 | 0, 1), | |
276 | ||
277 | /* MUX_SEL_TOP1 */ | |
278 | MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t", | |
279 | mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1), | |
280 | MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p, | |
281 | MUX_SEL_TOP1, 8, 1), | |
282 | MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p, | |
283 | MUX_SEL_TOP1, 4, 1), | |
284 | MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p, | |
285 | MUX_SEL_TOP1, 0, 1), | |
286 | ||
287 | /* MUX_SEL_TOP2 */ | |
288 | MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400", | |
289 | mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1), | |
290 | MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333", | |
291 | mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1), | |
292 | MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b", | |
293 | mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1), | |
294 | MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a", | |
295 | mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1), | |
296 | MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400", | |
297 | mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1), | |
298 | MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400", | |
299 | mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1), | |
300 | ||
301 | /* MUX_SEL_TOP3 */ | |
302 | MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400", | |
303 | mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1), | |
304 | MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b", | |
305 | mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1), | |
306 | MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a", | |
307 | mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1), | |
308 | MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333", | |
309 | mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1), | |
310 | MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b", | |
311 | mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1), | |
312 | MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a", | |
313 | mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1), | |
314 | ||
23236496 CC |
315 | /* MUX_SEL_TOP4 */ |
316 | MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c", | |
317 | mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1), | |
318 | MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b", | |
319 | mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1), | |
320 | MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a", | |
321 | mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1), | |
322 | ||
96bd6224 CC |
323 | /* MUX_SEL_TOP_MSCL */ |
324 | MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p, | |
325 | MUX_SEL_TOP_MSCL, 8, 1), | |
326 | MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p, | |
327 | MUX_SEL_TOP_MSCL, 4, 1), | |
328 | MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p, | |
329 | MUX_SEL_TOP_MSCL, 0, 1), | |
330 | ||
23236496 CC |
331 | /* MUX_SEL_TOP_CAM1 */ |
332 | MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2", | |
333 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1), | |
334 | MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1", | |
335 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1), | |
336 | MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0", | |
337 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1), | |
338 | MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart", | |
339 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1), | |
340 | MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1", | |
341 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1), | |
342 | MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0", | |
343 | mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1), | |
344 | ||
96bd6224 CC |
345 | /* MUX_SEL_TOP_FSYS0 */ |
346 | MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p, | |
347 | MUX_SEL_TOP_FSYS0, 28, 1), | |
348 | MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p, | |
349 | MUX_SEL_TOP_FSYS0, 24, 1), | |
350 | MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p, | |
351 | MUX_SEL_TOP_FSYS0, 20, 1), | |
352 | MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p, | |
353 | MUX_SEL_TOP_FSYS0, 16, 1), | |
354 | MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p, | |
355 | MUX_SEL_TOP_FSYS0, 12, 1), | |
356 | MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p, | |
357 | MUX_SEL_TOP_FSYS0, 8, 1), | |
358 | MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p, | |
359 | MUX_SEL_TOP_FSYS0, 4, 1), | |
360 | MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p, | |
361 | MUX_SEL_TOP_FSYS0, 0, 1), | |
362 | ||
23236496 CC |
363 | /* MUX_SEL_TOP_FSYS1 */ |
364 | MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p, | |
365 | MUX_SEL_TOP_FSYS1, 12, 1), | |
366 | MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro", | |
367 | mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1), | |
368 | MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30", | |
369 | mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1), | |
370 | MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30", | |
371 | mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1), | |
372 | ||
96bd6224 CC |
373 | /* MUX_SEL_TOP_PERIC0 */ |
374 | MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p, | |
375 | MUX_SEL_TOP_PERIC0, 28, 1), | |
376 | MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p, | |
377 | MUX_SEL_TOP_PERIC0, 24, 1), | |
378 | MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p, | |
379 | MUX_SEL_TOP_PERIC0, 20, 1), | |
380 | MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p, | |
381 | MUX_SEL_TOP_PERIC0, 16, 1), | |
382 | MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p, | |
383 | MUX_SEL_TOP_PERIC0, 12, 1), | |
384 | MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p, | |
385 | MUX_SEL_TOP_PERIC0, 8, 1), | |
386 | MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p, | |
387 | MUX_SEL_TOP_PERIC0, 4, 1), | |
388 | MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p, | |
389 | MUX_SEL_TOP_PERIC0, 0, 1), | |
23236496 CC |
390 | |
391 | /* MUX_SEL_TOP_PERIC1 */ | |
392 | MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p, | |
393 | MUX_SEL_TOP_PERIC1, 16, 1), | |
394 | MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p, | |
395 | MUX_SEL_TOP_PERIC1, 12, 2), | |
396 | MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p, | |
397 | MUX_SEL_TOP_PERIC1, 4, 2), | |
398 | MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p, | |
399 | MUX_SEL_TOP_PERIC1, 0, 2), | |
2a1808a6 CC |
400 | |
401 | /* MUX_SEL_TOP_DISP */ | |
402 | MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif", | |
403 | mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1), | |
96bd6224 CC |
404 | }; |
405 | ||
406 | static struct samsung_div_clock top_div_clks[] __initdata = { | |
a29308da CC |
407 | /* DIV_TOP1 */ |
408 | DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333", | |
409 | DIV_TOP1, 28, 3), | |
410 | DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333", | |
411 | DIV_TOP1, 24, 3), | |
412 | DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400", | |
413 | DIV_TOP1, 20, 3), | |
414 | DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c", | |
415 | DIV_TOP1, 12, 3), | |
416 | DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user", | |
417 | DIV_TOP1, 8, 3), | |
418 | DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b", | |
419 | DIV_TOP1, 0, 3), | |
420 | ||
96bd6224 CC |
421 | /* DIV_TOP2 */ |
422 | DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user", | |
423 | DIV_TOP2, 0, 3), | |
424 | ||
425 | /* DIV_TOP3 */ | |
426 | DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266", | |
427 | "mout_bus_pll_user", DIV_TOP3, 24, 3), | |
428 | DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200", | |
429 | "mout_bus_pll_user", DIV_TOP3, 20, 3), | |
430 | DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266", | |
431 | "mout_bus_pll_user", DIV_TOP3, 16, 3), | |
432 | DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b", | |
433 | "div_aclk_peric_66_a", DIV_TOP3, 12, 3), | |
434 | DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a", | |
435 | "mout_bus_pll_user", DIV_TOP3, 8, 3), | |
436 | DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b", | |
437 | "div_aclk_peris_66_a", DIV_TOP3, 4, 3), | |
438 | DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a", | |
439 | "mout_bus_pll_user", DIV_TOP3, 0, 3), | |
440 | ||
5785d6e6 CC |
441 | /* DIV_TOP4 */ |
442 | DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user", | |
443 | DIV_TOP4, 8, 3), | |
444 | DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400", | |
445 | DIV_TOP4, 4, 3), | |
446 | DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user", | |
447 | DIV_TOP4, 0, 3), | |
448 | ||
96bd6224 CC |
449 | /* DIV_TOP_FSYS0 */ |
450 | DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a", | |
451 | DIV_TOP_FSYS0, 16, 8), | |
452 | DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b", | |
453 | DIV_TOP_FSYS0, 12, 4), | |
454 | DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a", | |
455 | DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0), | |
456 | DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d", | |
457 | DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0), | |
458 | ||
459 | /* DIV_TOP_FSYS1 */ | |
460 | DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a", | |
461 | DIV_TOP_FSYS1, 4, 8), | |
462 | DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b", | |
463 | DIV_TOP_FSYS1, 0, 4), | |
464 | ||
4b801355 CC |
465 | /* DIV_TOP_FSYS2 */ |
466 | DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100", | |
467 | DIV_TOP_FSYS2, 12, 3), | |
468 | DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30", | |
469 | "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4), | |
470 | DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro", | |
471 | "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4), | |
472 | DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30", | |
473 | DIV_TOP_FSYS2, 0, 4), | |
474 | ||
96bd6224 CC |
475 | /* DIV_TOP_PERIC0 */ |
476 | DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a", | |
477 | DIV_TOP_PERIC0, 16, 8), | |
478 | DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1", | |
479 | DIV_TOP_PERIC0, 12, 4), | |
480 | DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a", | |
481 | DIV_TOP_PERIC0, 4, 8), | |
482 | DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0", | |
483 | DIV_TOP_PERIC0, 0, 4), | |
484 | ||
485 | /* DIV_TOP_PERIC1 */ | |
486 | DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a", | |
487 | DIV_TOP_PERIC1, 4, 8), | |
488 | DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2", | |
489 | DIV_TOP_PERIC1, 0, 4), | |
490 | ||
491 | /* DIV_TOP_PERIC2 */ | |
492 | DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2", | |
493 | DIV_TOP_PERIC2, 8, 4), | |
494 | DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0", | |
495 | DIV_TOP_PERIC2, 4, 4), | |
496 | DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1", | |
497 | DIV_TOP_PERIC2, 0, 4), | |
498 | ||
23236496 CC |
499 | /* DIV_TOP_PERIC3 */ |
500 | DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1", | |
501 | DIV_TOP_PERIC3, 16, 6), | |
502 | DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1", | |
503 | DIV_TOP_PERIC3, 8, 8), | |
504 | DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1", | |
505 | DIV_TOP_PERIC3, 4, 4), | |
506 | DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0", | |
507 | DIV_TOP_PERIC3, 0, 4), | |
508 | ||
96bd6224 CC |
509 | /* DIV_TOP_PERIC4 */ |
510 | DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a", | |
511 | DIV_TOP_PERIC4, 16, 8), | |
512 | DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4", | |
513 | DIV_TOP_PERIC4, 12, 4), | |
514 | DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a", | |
515 | DIV_TOP_PERIC4, 4, 8), | |
516 | DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3", | |
517 | DIV_TOP_PERIC4, 0, 4), | |
518 | }; | |
519 | ||
520 | static struct samsung_gate_clock top_gate_clks[] __initdata = { | |
521 | /* ENABLE_ACLK_TOP */ | |
5785d6e6 CC |
522 | GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400", |
523 | ENABLE_ACLK_TOP, 30, 0, 0), | |
524 | GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266", | |
525 | "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP, | |
526 | 29, CLK_IGNORE_UNUSED, 0), | |
527 | GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400", | |
528 | ENABLE_ACLK_TOP, 26, | |
529 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
530 | GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400", | |
531 | ENABLE_ACLK_TOP, 25, | |
532 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
533 | GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266", | |
534 | ENABLE_ACLK_TOP, 24, | |
535 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
536 | GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200", | |
537 | ENABLE_ACLK_TOP, 23, | |
538 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
96bd6224 CC |
539 | GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b", |
540 | ENABLE_ACLK_TOP, 22, | |
541 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
542 | GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b", | |
543 | ENABLE_ACLK_TOP, 21, | |
544 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
545 | GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200", | |
546 | ENABLE_ACLK_TOP, 18, | |
547 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
2a2f33e8 CC |
548 | GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111", |
549 | ENABLE_ACLK_TOP, 15, | |
550 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
551 | GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333", | |
552 | ENABLE_ACLK_TOP, 14, | |
553 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
a29308da CC |
554 | GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266", |
555 | ENABLE_ACLK_TOP, 2, | |
556 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
557 | GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400", | |
558 | ENABLE_ACLK_TOP, 0, | |
559 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
96bd6224 CC |
560 | |
561 | /* ENABLE_SCLK_TOP_FSYS */ | |
4b801355 CC |
562 | GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100", |
563 | ENABLE_SCLK_TOP_FSYS, 7, 0, 0), | |
96bd6224 CC |
564 | GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b", |
565 | ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0), | |
566 | GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b", | |
567 | ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0), | |
568 | GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b", | |
569 | ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0), | |
4b801355 CC |
570 | GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys", |
571 | "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS, | |
572 | 3, CLK_SET_RATE_PARENT, 0), | |
573 | GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys", | |
574 | "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS, | |
575 | 1, CLK_SET_RATE_PARENT, 0), | |
576 | GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys", | |
577 | "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS, | |
578 | 0, CLK_SET_RATE_PARENT, 0), | |
96bd6224 CC |
579 | |
580 | /* ENABLE_SCLK_TOP_PERIC */ | |
581 | GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b", | |
582 | ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0), | |
583 | GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b", | |
584 | ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0), | |
23236496 CC |
585 | GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif", |
586 | ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0), | |
587 | GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1", | |
588 | ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0), | |
589 | GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1", | |
590 | ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0), | |
96bd6224 CC |
591 | GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2", |
592 | ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0), | |
593 | GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1", | |
594 | ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0), | |
595 | GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0", | |
596 | ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0), | |
597 | GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b", | |
598 | ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0), | |
599 | GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b", | |
600 | ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0), | |
601 | GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b", | |
602 | ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0), | |
23236496 CC |
603 | |
604 | /* MUX_ENABLE_TOP_PERIC1 */ | |
605 | GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus", | |
606 | MUX_ENABLE_TOP_PERIC1, 16, 0, 0), | |
607 | GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1", | |
608 | MUX_ENABLE_TOP_PERIC1, 4, 0, 0), | |
609 | GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0", | |
610 | MUX_ENABLE_TOP_PERIC1, 0, 0, 0), | |
96bd6224 CC |
611 | }; |
612 | ||
613 | /* | |
614 | * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL | |
615 | * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL | |
616 | */ | |
617 | static struct samsung_pll_rate_table exynos5443_pll_rates[] = { | |
618 | PLL_35XX_RATE(2500000000U, 625, 6, 0), | |
619 | PLL_35XX_RATE(2400000000U, 500, 5, 0), | |
620 | PLL_35XX_RATE(2300000000U, 575, 6, 0), | |
621 | PLL_35XX_RATE(2200000000U, 550, 6, 0), | |
622 | PLL_35XX_RATE(2100000000U, 350, 4, 0), | |
623 | PLL_35XX_RATE(2000000000U, 500, 6, 0), | |
624 | PLL_35XX_RATE(1900000000U, 475, 6, 0), | |
625 | PLL_35XX_RATE(1800000000U, 375, 5, 0), | |
626 | PLL_35XX_RATE(1700000000U, 425, 6, 0), | |
627 | PLL_35XX_RATE(1600000000U, 400, 6, 0), | |
628 | PLL_35XX_RATE(1500000000U, 250, 4, 0), | |
629 | PLL_35XX_RATE(1400000000U, 350, 6, 0), | |
630 | PLL_35XX_RATE(1332000000U, 222, 4, 0), | |
631 | PLL_35XX_RATE(1300000000U, 325, 6, 0), | |
632 | PLL_35XX_RATE(1200000000U, 500, 5, 1), | |
633 | PLL_35XX_RATE(1100000000U, 550, 6, 1), | |
634 | PLL_35XX_RATE(1086000000U, 362, 4, 1), | |
635 | PLL_35XX_RATE(1066000000U, 533, 6, 1), | |
636 | PLL_35XX_RATE(1000000000U, 500, 6, 1), | |
637 | PLL_35XX_RATE(933000000U, 311, 4, 1), | |
638 | PLL_35XX_RATE(921000000U, 307, 4, 1), | |
639 | PLL_35XX_RATE(900000000U, 375, 5, 1), | |
640 | PLL_35XX_RATE(825000000U, 275, 4, 1), | |
641 | PLL_35XX_RATE(800000000U, 400, 6, 1), | |
642 | PLL_35XX_RATE(733000000U, 733, 12, 1), | |
643 | PLL_35XX_RATE(700000000U, 360, 6, 1), | |
644 | PLL_35XX_RATE(667000000U, 222, 4, 1), | |
645 | PLL_35XX_RATE(633000000U, 211, 4, 1), | |
646 | PLL_35XX_RATE(600000000U, 500, 5, 2), | |
647 | PLL_35XX_RATE(552000000U, 460, 5, 2), | |
648 | PLL_35XX_RATE(550000000U, 550, 6, 2), | |
649 | PLL_35XX_RATE(543000000U, 362, 4, 2), | |
650 | PLL_35XX_RATE(533000000U, 533, 6, 2), | |
651 | PLL_35XX_RATE(500000000U, 500, 6, 2), | |
652 | PLL_35XX_RATE(444000000U, 370, 5, 2), | |
653 | PLL_35XX_RATE(420000000U, 350, 5, 2), | |
654 | PLL_35XX_RATE(400000000U, 400, 6, 2), | |
655 | PLL_35XX_RATE(350000000U, 360, 6, 2), | |
656 | PLL_35XX_RATE(333000000U, 222, 4, 2), | |
657 | PLL_35XX_RATE(300000000U, 500, 5, 3), | |
658 | PLL_35XX_RATE(266000000U, 532, 6, 3), | |
659 | PLL_35XX_RATE(200000000U, 400, 6, 3), | |
660 | PLL_35XX_RATE(166000000U, 332, 6, 3), | |
661 | PLL_35XX_RATE(160000000U, 320, 6, 3), | |
662 | PLL_35XX_RATE(133000000U, 552, 6, 4), | |
663 | PLL_35XX_RATE(100000000U, 400, 6, 4), | |
664 | { /* sentinel */ } | |
665 | }; | |
666 | ||
667 | /* AUD_PLL */ | |
668 | static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = { | |
669 | PLL_36XX_RATE(400000000U, 200, 3, 2, 0), | |
670 | PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), | |
671 | PLL_36XX_RATE(384000000U, 128, 2, 2, 0), | |
672 | PLL_36XX_RATE(368640000U, 246, 4, 2, -15729), | |
673 | PLL_36XX_RATE(361507200U, 181, 3, 2, -16148), | |
674 | PLL_36XX_RATE(338688000U, 113, 2, 2, -6816), | |
675 | PLL_36XX_RATE(294912000U, 98, 1, 3, 19923), | |
676 | PLL_36XX_RATE(288000000U, 96, 1, 3, 0), | |
677 | PLL_36XX_RATE(252000000U, 84, 1, 3, 0), | |
678 | { /* sentinel */ } | |
679 | }; | |
680 | ||
681 | static struct samsung_pll_clock top_pll_clks[] __initdata = { | |
682 | PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", | |
683 | ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates), | |
684 | PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", | |
685 | AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates), | |
686 | }; | |
687 | ||
688 | static struct samsung_cmu_info top_cmu_info __initdata = { | |
689 | .pll_clks = top_pll_clks, | |
690 | .nr_pll_clks = ARRAY_SIZE(top_pll_clks), | |
691 | .mux_clks = top_mux_clks, | |
692 | .nr_mux_clks = ARRAY_SIZE(top_mux_clks), | |
693 | .div_clks = top_div_clks, | |
694 | .nr_div_clks = ARRAY_SIZE(top_div_clks), | |
695 | .gate_clks = top_gate_clks, | |
696 | .nr_gate_clks = ARRAY_SIZE(top_gate_clks), | |
23236496 CC |
697 | .fixed_clks = top_fixed_clks, |
698 | .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks), | |
56bcf3f3 CC |
699 | .fixed_factor_clks = top_fixed_factor_clks, |
700 | .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), | |
96bd6224 CC |
701 | .nr_clk_ids = TOP_NR_CLK, |
702 | .clk_regs = top_clk_regs, | |
703 | .nr_clk_regs = ARRAY_SIZE(top_clk_regs), | |
704 | }; | |
705 | ||
706 | static void __init exynos5433_cmu_top_init(struct device_node *np) | |
707 | { | |
708 | samsung_cmu_register_one(np, &top_cmu_info); | |
709 | } | |
710 | CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top", | |
711 | exynos5433_cmu_top_init); | |
712 | ||
713 | /* | |
714 | * Register offset definitions for CMU_CPIF | |
715 | */ | |
716 | #define MPHY_PLL_LOCK 0x0000 | |
717 | #define MPHY_PLL_CON0 0x0100 | |
718 | #define MPHY_PLL_CON1 0x0104 | |
719 | #define MPHY_PLL_FREQ_DET 0x010c | |
720 | #define MUX_SEL_CPIF0 0x0200 | |
721 | #define DIV_CPIF 0x0600 | |
722 | #define ENABLE_SCLK_CPIF 0x0a00 | |
723 | ||
724 | static unsigned long cpif_clk_regs[] __initdata = { | |
725 | MPHY_PLL_LOCK, | |
726 | MPHY_PLL_CON0, | |
727 | MPHY_PLL_CON1, | |
728 | MPHY_PLL_FREQ_DET, | |
729 | MUX_SEL_CPIF0, | |
730 | ENABLE_SCLK_CPIF, | |
731 | }; | |
732 | ||
733 | /* list of all parent clock list */ | |
734 | PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; | |
735 | ||
736 | static struct samsung_pll_clock cpif_pll_clks[] __initdata = { | |
737 | PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", | |
738 | MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates), | |
739 | }; | |
740 | ||
741 | static struct samsung_mux_clock cpif_mux_clks[] __initdata = { | |
742 | /* MUX_SEL_CPIF0 */ | |
743 | MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0, | |
744 | 0, 1), | |
745 | }; | |
746 | ||
747 | static struct samsung_div_clock cpif_div_clks[] __initdata = { | |
748 | /* DIV_CPIF */ | |
749 | DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF, | |
750 | 0, 6), | |
751 | }; | |
752 | ||
753 | static struct samsung_gate_clock cpif_gate_clks[] __initdata = { | |
754 | /* ENABLE_SCLK_CPIF */ | |
755 | GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll", | |
756 | ENABLE_SCLK_CPIF, 9, 0, 0), | |
757 | GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy", | |
758 | ENABLE_SCLK_CPIF, 4, 0, 0), | |
759 | }; | |
760 | ||
761 | static struct samsung_cmu_info cpif_cmu_info __initdata = { | |
762 | .pll_clks = cpif_pll_clks, | |
763 | .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks), | |
764 | .mux_clks = cpif_mux_clks, | |
765 | .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks), | |
766 | .div_clks = cpif_div_clks, | |
767 | .nr_div_clks = ARRAY_SIZE(cpif_div_clks), | |
768 | .gate_clks = cpif_gate_clks, | |
769 | .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks), | |
770 | .nr_clk_ids = CPIF_NR_CLK, | |
771 | .clk_regs = cpif_clk_regs, | |
772 | .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs), | |
773 | }; | |
774 | ||
775 | static void __init exynos5433_cmu_cpif_init(struct device_node *np) | |
776 | { | |
777 | samsung_cmu_register_one(np, &cpif_cmu_info); | |
778 | } | |
779 | CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif", | |
780 | exynos5433_cmu_cpif_init); | |
781 | ||
782 | /* | |
783 | * Register offset definitions for CMU_MIF | |
784 | */ | |
785 | #define MEM0_PLL_LOCK 0x0000 | |
786 | #define MEM1_PLL_LOCK 0x0004 | |
787 | #define BUS_PLL_LOCK 0x0008 | |
788 | #define MFC_PLL_LOCK 0x000c | |
789 | #define MEM0_PLL_CON0 0x0100 | |
790 | #define MEM0_PLL_CON1 0x0104 | |
791 | #define MEM0_PLL_FREQ_DET 0x010c | |
792 | #define MEM1_PLL_CON0 0x0110 | |
793 | #define MEM1_PLL_CON1 0x0114 | |
794 | #define MEM1_PLL_FREQ_DET 0x011c | |
795 | #define BUS_PLL_CON0 0x0120 | |
796 | #define BUS_PLL_CON1 0x0124 | |
797 | #define BUS_PLL_FREQ_DET 0x012c | |
798 | #define MFC_PLL_CON0 0x0130 | |
799 | #define MFC_PLL_CON1 0x0134 | |
800 | #define MFC_PLL_FREQ_DET 0x013c | |
06d2f9df CC |
801 | #define MUX_SEL_MIF0 0x0200 |
802 | #define MUX_SEL_MIF1 0x0204 | |
803 | #define MUX_SEL_MIF2 0x0208 | |
804 | #define MUX_SEL_MIF3 0x020c | |
805 | #define MUX_SEL_MIF4 0x0210 | |
806 | #define MUX_SEL_MIF5 0x0214 | |
807 | #define MUX_SEL_MIF6 0x0218 | |
808 | #define MUX_SEL_MIF7 0x021c | |
809 | #define MUX_ENABLE_MIF0 0x0300 | |
810 | #define MUX_ENABLE_MIF1 0x0304 | |
811 | #define MUX_ENABLE_MIF2 0x0308 | |
812 | #define MUX_ENABLE_MIF3 0x030c | |
813 | #define MUX_ENABLE_MIF4 0x0310 | |
814 | #define MUX_ENABLE_MIF5 0x0314 | |
815 | #define MUX_ENABLE_MIF6 0x0318 | |
816 | #define MUX_ENABLE_MIF7 0x031c | |
817 | #define MUX_STAT_MIF0 0x0400 | |
818 | #define MUX_STAT_MIF1 0x0404 | |
819 | #define MUX_STAT_MIF2 0x0408 | |
820 | #define MUX_STAT_MIF3 0x040c | |
821 | #define MUX_STAT_MIF4 0x0410 | |
822 | #define MUX_STAT_MIF5 0x0414 | |
823 | #define MUX_STAT_MIF6 0x0418 | |
824 | #define MUX_STAT_MIF7 0x041c | |
825 | #define DIV_MIF1 0x0604 | |
826 | #define DIV_MIF2 0x0608 | |
827 | #define DIV_MIF3 0x060c | |
828 | #define DIV_MIF4 0x0610 | |
829 | #define DIV_MIF5 0x0614 | |
830 | #define DIV_MIF_PLL_FREQ_DET 0x0618 | |
831 | #define DIV_STAT_MIF1 0x0704 | |
832 | #define DIV_STAT_MIF2 0x0708 | |
833 | #define DIV_STAT_MIF3 0x070c | |
834 | #define DIV_STAT_MIF4 0x0710 | |
835 | #define DIV_STAT_MIF5 0x0714 | |
836 | #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718 | |
837 | #define ENABLE_ACLK_MIF0 0x0800 | |
838 | #define ENABLE_ACLK_MIF1 0x0804 | |
839 | #define ENABLE_ACLK_MIF2 0x0808 | |
840 | #define ENABLE_ACLK_MIF3 0x080c | |
841 | #define ENABLE_PCLK_MIF 0x0900 | |
842 | #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904 | |
843 | #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908 | |
844 | #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c | |
845 | #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910 | |
846 | #define ENABLE_SCLK_MIF 0x0a00 | |
847 | #define ENABLE_IP_MIF0 0x0b00 | |
848 | #define ENABLE_IP_MIF1 0x0b04 | |
849 | #define ENABLE_IP_MIF2 0x0b08 | |
850 | #define ENABLE_IP_MIF3 0x0b0c | |
851 | #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10 | |
852 | #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14 | |
853 | #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18 | |
854 | #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c | |
855 | #define CLKOUT_CMU_MIF 0x0c00 | |
856 | #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04 | |
857 | #define DREX_FREQ_CTRL0 0x1000 | |
858 | #define DREX_FREQ_CTRL1 0x1004 | |
859 | #define PAUSE 0x1008 | |
860 | #define DDRPHY_LOCK_CTRL 0x100c | |
96bd6224 CC |
861 | |
862 | static unsigned long mif_clk_regs[] __initdata = { | |
863 | MEM0_PLL_LOCK, | |
864 | MEM1_PLL_LOCK, | |
865 | BUS_PLL_LOCK, | |
866 | MFC_PLL_LOCK, | |
867 | MEM0_PLL_CON0, | |
868 | MEM0_PLL_CON1, | |
869 | MEM0_PLL_FREQ_DET, | |
870 | MEM1_PLL_CON0, | |
871 | MEM1_PLL_CON1, | |
872 | MEM1_PLL_FREQ_DET, | |
873 | BUS_PLL_CON0, | |
874 | BUS_PLL_CON1, | |
875 | BUS_PLL_FREQ_DET, | |
876 | MFC_PLL_CON0, | |
877 | MFC_PLL_CON1, | |
878 | MFC_PLL_FREQ_DET, | |
06d2f9df CC |
879 | MUX_SEL_MIF0, |
880 | MUX_SEL_MIF1, | |
881 | MUX_SEL_MIF2, | |
882 | MUX_SEL_MIF3, | |
883 | MUX_SEL_MIF4, | |
884 | MUX_SEL_MIF5, | |
885 | MUX_SEL_MIF6, | |
886 | MUX_SEL_MIF7, | |
887 | MUX_ENABLE_MIF0, | |
888 | MUX_ENABLE_MIF1, | |
889 | MUX_ENABLE_MIF2, | |
890 | MUX_ENABLE_MIF3, | |
891 | MUX_ENABLE_MIF4, | |
892 | MUX_ENABLE_MIF5, | |
893 | MUX_ENABLE_MIF6, | |
894 | MUX_ENABLE_MIF7, | |
895 | MUX_STAT_MIF0, | |
896 | MUX_STAT_MIF1, | |
897 | MUX_STAT_MIF2, | |
898 | MUX_STAT_MIF3, | |
899 | MUX_STAT_MIF4, | |
900 | MUX_STAT_MIF5, | |
901 | MUX_STAT_MIF6, | |
902 | MUX_STAT_MIF7, | |
903 | DIV_MIF1, | |
904 | DIV_MIF2, | |
905 | DIV_MIF3, | |
906 | DIV_MIF4, | |
907 | DIV_MIF5, | |
908 | DIV_MIF_PLL_FREQ_DET, | |
909 | DIV_STAT_MIF1, | |
910 | DIV_STAT_MIF2, | |
911 | DIV_STAT_MIF3, | |
912 | DIV_STAT_MIF4, | |
913 | DIV_STAT_MIF5, | |
914 | DIV_STAT_MIF_PLL_FREQ_DET, | |
915 | ENABLE_ACLK_MIF0, | |
916 | ENABLE_ACLK_MIF1, | |
917 | ENABLE_ACLK_MIF2, | |
918 | ENABLE_ACLK_MIF3, | |
919 | ENABLE_PCLK_MIF, | |
920 | ENABLE_PCLK_MIF_SECURE_DREX0_TZ, | |
921 | ENABLE_PCLK_MIF_SECURE_DREX1_TZ, | |
922 | ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, | |
923 | ENABLE_PCLK_MIF_SECURE_RTC, | |
924 | ENABLE_SCLK_MIF, | |
925 | ENABLE_IP_MIF0, | |
926 | ENABLE_IP_MIF1, | |
927 | ENABLE_IP_MIF2, | |
928 | ENABLE_IP_MIF3, | |
929 | ENABLE_IP_MIF_SECURE_DREX0_TZ, | |
930 | ENABLE_IP_MIF_SECURE_DREX1_TZ, | |
931 | ENABLE_IP_MIF_SECURE_MONOTONIC_CNT, | |
932 | ENABLE_IP_MIF_SECURE_RTC, | |
933 | CLKOUT_CMU_MIF, | |
934 | CLKOUT_CMU_MIF_DIV_STAT, | |
935 | DREX_FREQ_CTRL0, | |
936 | DREX_FREQ_CTRL1, | |
937 | PAUSE, | |
938 | DDRPHY_LOCK_CTRL, | |
96bd6224 CC |
939 | }; |
940 | ||
941 | static struct samsung_pll_clock mif_pll_clks[] __initdata = { | |
942 | PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", | |
943 | MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates), | |
944 | PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", | |
945 | MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates), | |
946 | PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk", | |
947 | BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates), | |
948 | PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk", | |
949 | MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates), | |
950 | }; | |
951 | ||
06d2f9df CC |
952 | /* list of all parent clock list */ |
953 | PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", }; | |
954 | PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", }; | |
955 | PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", }; | |
956 | PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", }; | |
957 | PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", }; | |
958 | PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", }; | |
959 | PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", }; | |
960 | PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", }; | |
961 | ||
962 | PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", }; | |
963 | PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", }; | |
964 | PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", }; | |
965 | PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", }; | |
966 | ||
967 | PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", }; | |
968 | PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",}; | |
969 | ||
970 | PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a", | |
971 | "mout_bus_pll_div2", }; | |
972 | PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", }; | |
973 | ||
974 | PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b", | |
975 | "sclk_mphy_pll", }; | |
976 | PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a", | |
977 | "mout_mfc_pll_div2", }; | |
978 | PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", }; | |
979 | PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b", | |
980 | "sclk_mphy_pll", }; | |
981 | PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a", | |
982 | "mout_mfc_pll_div2", }; | |
983 | ||
984 | PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b", | |
985 | "sclk_mphy_pll", }; | |
986 | PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a", | |
987 | "mout_mfc_pll_div2", }; | |
988 | PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", }; | |
989 | PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", }; | |
990 | PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", }; | |
991 | ||
992 | PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", }; | |
993 | PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" }; | |
994 | ||
995 | PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b", | |
996 | "sclk_mphy_pll", }; | |
997 | PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a", | |
998 | "mout_mfc_pll_div2", }; | |
999 | PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", }; | |
1000 | PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",}; | |
1001 | ||
1002 | static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = { | |
1003 | /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ | |
1004 | FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0), | |
1005 | FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0), | |
1006 | FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0), | |
1007 | FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0), | |
1008 | }; | |
1009 | ||
1010 | static struct samsung_mux_clock mif_mux_clks[] __initdata = { | |
1011 | /* MUX_SEL_MIF0 */ | |
1012 | MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p, | |
1013 | MUX_SEL_MIF0, 28, 1), | |
1014 | MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p, | |
1015 | MUX_SEL_MIF0, 24, 1), | |
1016 | MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p, | |
1017 | MUX_SEL_MIF0, 20, 1), | |
1018 | MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p, | |
1019 | MUX_SEL_MIF0, 16, 1), | |
1020 | MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0, | |
1021 | 12, 1), | |
1022 | MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0, | |
1023 | 8, 1), | |
1024 | MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0, | |
1025 | 4, 1), | |
1026 | MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0, | |
1027 | 0, 1), | |
1028 | ||
1029 | /* MUX_SEL_MIF1 */ | |
1030 | MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p, | |
1031 | MUX_SEL_MIF1, 24, 1), | |
1032 | MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p, | |
1033 | MUX_SEL_MIF1, 20, 1), | |
1034 | MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p, | |
1035 | MUX_SEL_MIF1, 16, 1), | |
1036 | MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p, | |
1037 | MUX_SEL_MIF1, 12, 1), | |
1038 | MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p, | |
1039 | MUX_SEL_MIF1, 8, 1), | |
1040 | MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p, | |
1041 | MUX_SEL_MIF1, 4, 1), | |
1042 | ||
1043 | /* MUX_SEL_MIF2 */ | |
1044 | MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200", | |
1045 | mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1), | |
1046 | MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400", | |
1047 | mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1), | |
1048 | ||
1049 | /* MUX_SEL_MIF3 */ | |
1050 | MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b", | |
1051 | mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1), | |
1052 | MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a", | |
1053 | mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1), | |
1054 | ||
1055 | /* MUX_SEL_MIF4 */ | |
1056 | MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c", | |
1057 | mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1), | |
1058 | MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b", | |
1059 | mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1), | |
1060 | MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a", | |
1061 | mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1), | |
1062 | MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c", | |
1063 | mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1), | |
1064 | MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b", | |
1065 | mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1), | |
1066 | MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a", | |
1067 | mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1), | |
1068 | ||
1069 | /* MUX_SEL_MIF5 */ | |
1070 | MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c", | |
1071 | mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1), | |
1072 | MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b", | |
1073 | mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1), | |
1074 | MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a", | |
1075 | mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1), | |
1076 | MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p, | |
1077 | MUX_SEL_MIF5, 8, 1), | |
1078 | MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p, | |
1079 | MUX_SEL_MIF5, 4, 1), | |
1080 | MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p, | |
1081 | MUX_SEL_MIF5, 0, 1), | |
1082 | ||
1083 | /* MUX_SEL_MIF6 */ | |
1084 | MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p, | |
1085 | MUX_SEL_MIF6, 8, 1), | |
1086 | MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p, | |
1087 | MUX_SEL_MIF6, 4, 1), | |
1088 | MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p, | |
1089 | MUX_SEL_MIF6, 0, 1), | |
1090 | ||
1091 | /* MUX_SEL_MIF7 */ | |
1092 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c", | |
1093 | mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1), | |
1094 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b", | |
1095 | mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1), | |
1096 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a", | |
1097 | mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1), | |
1098 | MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p, | |
1099 | MUX_SEL_MIF7, 8, 1), | |
1100 | MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p, | |
1101 | MUX_SEL_MIF7, 4, 1), | |
1102 | MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p, | |
1103 | MUX_SEL_MIF7, 0, 1), | |
1104 | }; | |
1105 | ||
1106 | static struct samsung_div_clock mif_div_clks[] __initdata = { | |
1107 | /* DIV_MIF1 */ | |
1108 | DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy", | |
1109 | DIV_MIF1, 16, 2), | |
1110 | DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1, | |
1111 | 12, 2), | |
1112 | DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1, | |
1113 | 8, 2), | |
1114 | DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1, | |
1115 | 4, 4), | |
1116 | ||
1117 | /* DIV_MIF2 */ | |
1118 | DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2", | |
1119 | DIV_MIF2, 20, 3), | |
1120 | DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre", | |
1121 | DIV_MIF2, 16, 4), | |
1122 | DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre", | |
1123 | DIV_MIF2, 12, 4), | |
1124 | DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200", | |
1125 | "mout_aclk_mifnm_200", DIV_MIF2, 8, 3), | |
1126 | DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400", | |
1127 | DIV_MIF2, 4, 2), | |
1128 | DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400", | |
1129 | DIV_MIF2, 0, 3), | |
1130 | ||
1131 | /* DIV_MIF3 */ | |
1132 | DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre", | |
1133 | DIV_MIF3, 16, 4), | |
1134 | DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b", | |
1135 | DIV_MIF3, 4, 3), | |
1136 | DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200", | |
1137 | DIV_MIF3, 0, 3), | |
1138 | ||
1139 | /* DIV_MIF4 */ | |
1140 | DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c", | |
1141 | DIV_MIF4, 24, 4), | |
1142 | DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk", | |
1143 | "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4), | |
1144 | DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c", | |
1145 | DIV_MIF4, 16, 4), | |
1146 | DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c", | |
1147 | DIV_MIF4, 12, 4), | |
1148 | DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk", | |
1149 | "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4), | |
1150 | DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk", | |
1151 | "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4), | |
1152 | DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk", | |
1153 | "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4), | |
1154 | ||
1155 | /* DIV_MIF5 */ | |
1156 | DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5, | |
1157 | 0, 3), | |
1158 | }; | |
1159 | ||
1160 | static struct samsung_gate_clock mif_gate_clks[] __initdata = { | |
1161 | /* ENABLE_ACLK_MIF0 */ | |
1162 | GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0, | |
1163 | 19, CLK_IGNORE_UNUSED, 0), | |
1164 | GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0, | |
1165 | 18, CLK_IGNORE_UNUSED, 0), | |
1166 | GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, | |
1167 | 17, CLK_IGNORE_UNUSED, 0), | |
1168 | GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, | |
1169 | 16, CLK_IGNORE_UNUSED, 0), | |
1170 | GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0, | |
1171 | 15, CLK_IGNORE_UNUSED, 0), | |
1172 | GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0, | |
1173 | 14, CLK_IGNORE_UNUSED, 0), | |
1174 | GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1", | |
1175 | ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0), | |
1176 | GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0", | |
1177 | ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0), | |
1178 | GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1", | |
1179 | ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0), | |
1180 | GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0", | |
1181 | ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0), | |
1182 | GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1", | |
1183 | ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0), | |
1184 | GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0", | |
1185 | ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0), | |
1186 | GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1", | |
1187 | ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0), | |
1188 | GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0", | |
1189 | ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0), | |
1190 | GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1", | |
1191 | ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0), | |
1192 | GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0", | |
1193 | ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0), | |
1194 | GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1", | |
1195 | ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0), | |
1196 | GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0", | |
1197 | ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), | |
1198 | GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1", | |
1199 | ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), | |
1200 | GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0", | |
1201 | ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0), | |
1202 | ||
1203 | /* ENABLE_ACLK_MIF1 */ | |
1204 | GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem", | |
1205 | "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28, | |
1206 | CLK_IGNORE_UNUSED, 0), | |
1207 | GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci", | |
1208 | "div_aclk_mif_200", ENABLE_ACLK_MIF1, | |
1209 | 27, CLK_IGNORE_UNUSED, 0), | |
1210 | GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci", | |
1211 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, | |
1212 | 26, CLK_IGNORE_UNUSED, 0), | |
1213 | GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1", | |
1214 | "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, | |
1215 | 25, CLK_IGNORE_UNUSED, 0), | |
1216 | GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1", | |
1217 | "div_aclk_drex1", ENABLE_ACLK_MIF1, | |
1218 | 24, CLK_IGNORE_UNUSED, 0), | |
1219 | GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0", | |
1220 | "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, | |
1221 | 23, CLK_IGNORE_UNUSED, 0), | |
1222 | GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0", | |
1223 | "div_aclk_drex0", ENABLE_ACLK_MIF1, | |
1224 | 22, CLK_IGNORE_UNUSED, 0), | |
1225 | GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3", | |
1226 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, | |
1227 | 21, CLK_IGNORE_UNUSED, 0), | |
1228 | GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3", | |
1229 | "div_aclk_drex1", ENABLE_ACLK_MIF1, | |
1230 | 20, CLK_IGNORE_UNUSED, 0), | |
1231 | GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1", | |
1232 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, | |
1233 | 19, CLK_IGNORE_UNUSED, 0), | |
1234 | GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1", | |
1235 | "div_aclk_drex1", ENABLE_ACLK_MIF1, | |
1236 | 18, CLK_IGNORE_UNUSED, 0), | |
1237 | GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0", | |
1238 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, | |
1239 | 17, CLK_IGNORE_UNUSED, 0), | |
1240 | GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0", | |
1241 | "div_aclk_drex1", ENABLE_ACLK_MIF1, | |
1242 | 16, CLK_IGNORE_UNUSED, 0), | |
1243 | GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3", | |
1244 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, | |
1245 | 15, CLK_IGNORE_UNUSED, 0), | |
1246 | GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3", | |
1247 | "div_aclk_drex0", ENABLE_ACLK_MIF1, | |
1248 | 14, CLK_IGNORE_UNUSED, 0), | |
1249 | GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1", | |
1250 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, | |
1251 | 13, CLK_IGNORE_UNUSED, 0), | |
1252 | GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1", | |
1253 | "div_aclk_drex0", ENABLE_ACLK_MIF1, | |
1254 | 12, CLK_IGNORE_UNUSED, 0), | |
1255 | GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0", | |
1256 | "div_aclk_mif_133", ENABLE_ACLK_MIF1, | |
1257 | 11, CLK_IGNORE_UNUSED, 0), | |
1258 | GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0", | |
1259 | "div_aclk_drex0", ENABLE_ACLK_MIF1, | |
1260 | 10, CLK_IGNORE_UNUSED, 0), | |
1261 | GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133", | |
1262 | ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0), | |
1263 | GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133", | |
1264 | ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0), | |
1265 | GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133", | |
1266 | ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0), | |
1267 | GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400", | |
1268 | ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0), | |
1269 | GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200", | |
1270 | ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0), | |
1271 | GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133", | |
1272 | ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0), | |
1273 | GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200", | |
1274 | ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0), | |
1275 | GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133", | |
1276 | ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0), | |
1277 | GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400", | |
1278 | ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0), | |
1279 | GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1, | |
1280 | 0, CLK_IGNORE_UNUSED, 0), | |
1281 | ||
1282 | /* ENABLE_ACLK_MIF2 */ | |
1283 | GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266", | |
1284 | ENABLE_ACLK_MIF2, 20, 0, 0), | |
1285 | GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1", | |
1286 | ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0), | |
1287 | GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1", | |
1288 | ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0), | |
1289 | GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1", | |
1290 | ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0), | |
1291 | GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0", | |
1292 | ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0), | |
1293 | GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0", | |
1294 | ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0), | |
1295 | GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0", | |
1296 | ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0), | |
1297 | GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx", | |
1298 | "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7, | |
1299 | CLK_IGNORE_UNUSED, 0), | |
1300 | GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci", | |
1301 | "div_aclk_mif_400", ENABLE_ACLK_MIF2, | |
1302 | 5, CLK_IGNORE_UNUSED, 0), | |
1303 | GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400", | |
1304 | ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0), | |
1305 | GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d", | |
1306 | "div_aclk_mif_200", ENABLE_ACLK_MIF2, | |
1307 | 3, CLK_IGNORE_UNUSED, 0), | |
1308 | GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys", | |
1309 | "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0), | |
1310 | ||
1311 | /* ENABLE_ACLK_MIF3 */ | |
1312 | GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400", | |
1313 | ENABLE_ACLK_MIF3, 4, | |
1314 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
1315 | GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333", | |
1316 | ENABLE_ACLK_MIF3, 1, | |
1317 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
1318 | GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200", | |
1319 | ENABLE_ACLK_MIF3, 0, | |
1320 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
1321 | ||
1322 | /* ENABLE_PCLK_MIF */ | |
1323 | GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1", | |
1324 | ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0), | |
1325 | GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1", | |
1326 | ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0), | |
1327 | GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1", | |
1328 | ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0), | |
1329 | GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0", | |
1330 | ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0), | |
1331 | GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0", | |
1332 | ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0), | |
1333 | GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0", | |
1334 | ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0), | |
1335 | GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci", | |
1336 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 21, | |
1337 | CLK_IGNORE_UNUSED, 0), | |
1338 | GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133", | |
1339 | ENABLE_PCLK_MIF, 19, 0, 0), | |
1340 | GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133", | |
1341 | ENABLE_PCLK_MIF, 18, 0, 0), | |
1342 | GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3", | |
1343 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0), | |
1344 | GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1", | |
1345 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0), | |
1346 | GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0", | |
1347 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0), | |
1348 | GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3", | |
1349 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0), | |
1350 | GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1", | |
1351 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0), | |
1352 | GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0", | |
1353 | "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0), | |
1354 | GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133", | |
1355 | ENABLE_PCLK_MIF, 11, 0, 0), | |
1356 | GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133", | |
1357 | ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0), | |
1358 | GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133", | |
1359 | ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), | |
1360 | GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133", | |
1361 | ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), | |
1362 | GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133", | |
1363 | ENABLE_PCLK_MIF, 7, 0, 0), | |
1364 | GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133", | |
1365 | ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0), | |
1366 | GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133", | |
1367 | ENABLE_PCLK_MIF, 5, 0, 0), | |
1368 | GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133", | |
1369 | ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), | |
1370 | GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133", | |
1371 | ENABLE_PCLK_MIF, 2, 0, 0), | |
1372 | GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133", | |
1373 | ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), | |
1374 | ||
1375 | /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ | |
1376 | GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133", | |
1377 | ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0), | |
1378 | ||
1379 | /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */ | |
1380 | GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133", | |
1381 | ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0), | |
1382 | ||
1383 | /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ | |
1384 | GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133", | |
1385 | ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0), | |
1386 | ||
1387 | /* ENABLE_PCLK_MIF_SECURE_RTC */ | |
1388 | GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133", | |
1389 | ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0), | |
1390 | ||
1391 | /* ENABLE_SCLK_MIF */ | |
1392 | GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1", | |
1393 | ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0), | |
1394 | GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp", | |
1395 | "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF, | |
1396 | 14, CLK_IGNORE_UNUSED, 0), | |
1397 | GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0", | |
1398 | ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), | |
1399 | GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd", | |
1400 | ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), | |
1401 | GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp", | |
1402 | "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF, | |
1403 | 7, CLK_IGNORE_UNUSED, 0), | |
1404 | GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp", | |
1405 | "div_sclk_decon_vclk", ENABLE_SCLK_MIF, | |
1406 | 6, CLK_IGNORE_UNUSED, 0), | |
1407 | GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp", | |
1408 | "div_sclk_decon_eclk", ENABLE_SCLK_MIF, | |
1409 | 5, CLK_IGNORE_UNUSED, 0), | |
1410 | GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif", | |
1411 | ENABLE_SCLK_MIF, 4, | |
1412 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
1413 | GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2", | |
1414 | ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), | |
1415 | GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2", | |
1416 | ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0), | |
1417 | GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll", | |
1418 | ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0), | |
1419 | GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll", | |
1420 | ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), | |
2a1808a6 CC |
1421 | |
1422 | /* ENABLE_SCLK_TOP_DISP */ | |
1423 | GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp", | |
1424 | "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0, | |
1425 | CLK_IGNORE_UNUSED, 0), | |
06d2f9df CC |
1426 | }; |
1427 | ||
96bd6224 CC |
1428 | static struct samsung_cmu_info mif_cmu_info __initdata = { |
1429 | .pll_clks = mif_pll_clks, | |
1430 | .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), | |
06d2f9df CC |
1431 | .mux_clks = mif_mux_clks, |
1432 | .nr_mux_clks = ARRAY_SIZE(mif_mux_clks), | |
1433 | .div_clks = mif_div_clks, | |
1434 | .nr_div_clks = ARRAY_SIZE(mif_div_clks), | |
1435 | .gate_clks = mif_gate_clks, | |
1436 | .nr_gate_clks = ARRAY_SIZE(mif_gate_clks), | |
1437 | .fixed_factor_clks = mif_fixed_factor_clks, | |
1438 | .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks), | |
96bd6224 CC |
1439 | .nr_clk_ids = MIF_NR_CLK, |
1440 | .clk_regs = mif_clk_regs, | |
1441 | .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), | |
1442 | }; | |
1443 | ||
1444 | static void __init exynos5433_cmu_mif_init(struct device_node *np) | |
1445 | { | |
1446 | samsung_cmu_register_one(np, &mif_cmu_info); | |
1447 | } | |
1448 | CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", | |
1449 | exynos5433_cmu_mif_init); | |
1450 | ||
1451 | /* | |
1452 | * Register offset definitions for CMU_PERIC | |
1453 | */ | |
1454 | #define DIV_PERIC 0x0600 | |
d0f5de66 | 1455 | #define DIV_STAT_PERIC 0x0700 |
96bd6224 CC |
1456 | #define ENABLE_ACLK_PERIC 0x0800 |
1457 | #define ENABLE_PCLK_PERIC0 0x0900 | |
1458 | #define ENABLE_PCLK_PERIC1 0x0904 | |
1459 | #define ENABLE_SCLK_PERIC 0x0A00 | |
1460 | #define ENABLE_IP_PERIC0 0x0B00 | |
1461 | #define ENABLE_IP_PERIC1 0x0B04 | |
1462 | #define ENABLE_IP_PERIC2 0x0B08 | |
1463 | ||
1464 | static unsigned long peric_clk_regs[] __initdata = { | |
1465 | DIV_PERIC, | |
d0f5de66 | 1466 | DIV_STAT_PERIC, |
96bd6224 CC |
1467 | ENABLE_ACLK_PERIC, |
1468 | ENABLE_PCLK_PERIC0, | |
1469 | ENABLE_PCLK_PERIC1, | |
1470 | ENABLE_SCLK_PERIC, | |
1471 | ENABLE_IP_PERIC0, | |
1472 | ENABLE_IP_PERIC1, | |
1473 | ENABLE_IP_PERIC2, | |
1474 | }; | |
1475 | ||
d0f5de66 CC |
1476 | static struct samsung_div_clock peric_div_clks[] __initdata = { |
1477 | /* DIV_PERIC */ | |
1478 | DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), | |
1479 | DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4), | |
1480 | }; | |
1481 | ||
96bd6224 | 1482 | static struct samsung_gate_clock peric_gate_clks[] __initdata = { |
d0f5de66 CC |
1483 | /* ENABLE_ACLK_PERIC */ |
1484 | GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66", | |
1485 | ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0), | |
1486 | GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66", | |
1487 | ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0), | |
1488 | GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66", | |
1489 | ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0), | |
1490 | GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66", | |
1491 | ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0), | |
1492 | ||
96bd6224 | 1493 | /* ENABLE_PCLK_PERIC0 */ |
d0f5de66 CC |
1494 | GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
1495 | 31, CLK_SET_RATE_PARENT, 0), | |
1496 | GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66", | |
1497 | ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0), | |
1498 | GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66", | |
1499 | ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0), | |
1500 | GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1501 | 28, CLK_SET_RATE_PARENT, 0), | |
1502 | GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1503 | 26, CLK_SET_RATE_PARENT, 0), | |
1504 | GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1505 | 25, CLK_SET_RATE_PARENT, 0), | |
1506 | GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1507 | 24, CLK_SET_RATE_PARENT, 0), | |
96bd6224 CC |
1508 | GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
1509 | 23, CLK_SET_RATE_PARENT, 0), | |
1510 | GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1511 | 22, CLK_SET_RATE_PARENT, 0), | |
1512 | GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1513 | 21, CLK_SET_RATE_PARENT, 0), | |
d0f5de66 CC |
1514 | GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
1515 | 20, CLK_SET_RATE_PARENT, 0), | |
1516 | GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66", | |
1517 | ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0), | |
1518 | GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66", | |
1519 | ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0), | |
1520 | GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66", | |
1521 | ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0), | |
1522 | GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66", | |
1523 | ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0), | |
1524 | GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66", | |
1525 | ENABLE_PCLK_PERIC0, 15, | |
1526 | CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), | |
96bd6224 CC |
1527 | GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0, |
1528 | 14, CLK_SET_RATE_PARENT, 0), | |
1529 | GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1530 | 13, CLK_SET_RATE_PARENT, 0), | |
1531 | GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1532 | 12, CLK_SET_RATE_PARENT, 0), | |
1533 | GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66", | |
1534 | ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0), | |
1535 | GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66", | |
1536 | ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0), | |
1537 | GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66", | |
1538 | ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0), | |
1539 | GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66", | |
1540 | ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), | |
1541 | GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1542 | 7, CLK_SET_RATE_PARENT, 0), | |
1543 | GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1544 | 6, CLK_SET_RATE_PARENT, 0), | |
1545 | GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1546 | 5, CLK_SET_RATE_PARENT, 0), | |
1547 | GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1548 | 4, CLK_SET_RATE_PARENT, 0), | |
1549 | GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1550 | 3, CLK_SET_RATE_PARENT, 0), | |
1551 | GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1552 | 2, CLK_SET_RATE_PARENT, 0), | |
1553 | GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1554 | 1, CLK_SET_RATE_PARENT, 0), | |
1555 | GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0, | |
1556 | 0, CLK_SET_RATE_PARENT, 0), | |
1557 | ||
1558 | /* ENABLE_PCLK_PERIC1 */ | |
1559 | GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1, | |
1560 | 9, CLK_SET_RATE_PARENT, 0), | |
1561 | GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1, | |
1562 | 8, CLK_SET_RATE_PARENT, 0), | |
1563 | GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66", | |
1564 | ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0), | |
1565 | GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66", | |
1566 | ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0), | |
1567 | GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66", | |
1568 | ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0), | |
1569 | GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66", | |
1570 | ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), | |
1571 | GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66", | |
1572 | ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0), | |
1573 | GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66", | |
1574 | ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0), | |
1575 | GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66", | |
1576 | ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0), | |
1577 | GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66", | |
1578 | ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), | |
1579 | ||
1580 | /* ENABLE_SCLK_PERIC */ | |
d0f5de66 CC |
1581 | GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in", |
1582 | ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0), | |
1583 | GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in", | |
1584 | ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0), | |
96bd6224 CC |
1585 | GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC, |
1586 | 19, CLK_SET_RATE_PARENT, 0), | |
1587 | GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC, | |
1588 | 18, CLK_SET_RATE_PARENT, 0), | |
d0f5de66 CC |
1589 | GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC, |
1590 | 17, 0, 0), | |
1591 | GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC, | |
1592 | 16, 0, 0), | |
1593 | GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0), | |
1594 | GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in", | |
1595 | ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0), | |
1596 | GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in", | |
1597 | ENABLE_SCLK_PERIC, 12, | |
1598 | CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), | |
1599 | GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in", | |
1600 | ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), | |
1601 | GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", | |
1602 | "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10, | |
1603 | CLK_SET_RATE_PARENT, 0), | |
1604 | GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric", | |
1605 | ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), | |
1606 | GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric", | |
1607 | ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), | |
1608 | GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric", | |
1609 | ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), | |
96bd6224 CC |
1610 | GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC, |
1611 | 5, CLK_SET_RATE_PARENT, 0), | |
1612 | GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, | |
d0f5de66 | 1613 | 4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), |
96bd6224 CC |
1614 | GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, |
1615 | 3, CLK_SET_RATE_PARENT, 0), | |
1616 | GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric", | |
1617 | ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), | |
1618 | GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric", | |
1619 | ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), | |
1620 | GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric", | |
1621 | ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), | |
1622 | }; | |
1623 | ||
1624 | static struct samsung_cmu_info peric_cmu_info __initdata = { | |
d0f5de66 CC |
1625 | .div_clks = peric_div_clks, |
1626 | .nr_div_clks = ARRAY_SIZE(peric_div_clks), | |
96bd6224 CC |
1627 | .gate_clks = peric_gate_clks, |
1628 | .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), | |
1629 | .nr_clk_ids = PERIC_NR_CLK, | |
1630 | .clk_regs = peric_clk_regs, | |
1631 | .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), | |
1632 | }; | |
1633 | ||
1634 | static void __init exynos5433_cmu_peric_init(struct device_node *np) | |
1635 | { | |
1636 | samsung_cmu_register_one(np, &peric_cmu_info); | |
1637 | } | |
1638 | ||
1639 | CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric", | |
1640 | exynos5433_cmu_peric_init); | |
1641 | ||
1642 | /* | |
1643 | * Register offset definitions for CMU_PERIS | |
1644 | */ | |
56bcf3f3 CC |
1645 | #define ENABLE_ACLK_PERIS 0x0800 |
1646 | #define ENABLE_PCLK_PERIS 0x0900 | |
1647 | #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904 | |
1648 | #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908 | |
1649 | #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c | |
1650 | #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910 | |
1651 | #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914 | |
1652 | #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918 | |
1653 | #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c | |
1654 | #define ENABLE_SCLK_PERIS 0x0a00 | |
1655 | #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04 | |
1656 | #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08 | |
1657 | #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c | |
1658 | #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10 | |
1659 | #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14 | |
1660 | #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18 | |
1661 | #define ENABLE_IP_PERIS0 0x0b00 | |
1662 | #define ENABLE_IP_PERIS1 0x0b04 | |
1663 | #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08 | |
1664 | #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c | |
1665 | #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10 | |
1666 | #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14 | |
1667 | #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18 | |
1668 | #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c | |
1669 | #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20 | |
96bd6224 CC |
1670 | |
1671 | static unsigned long peris_clk_regs[] __initdata = { | |
1672 | ENABLE_ACLK_PERIS, | |
1673 | ENABLE_PCLK_PERIS, | |
56bcf3f3 CC |
1674 | ENABLE_PCLK_PERIS_SECURE_TZPC, |
1675 | ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, | |
1676 | ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, | |
1677 | ENABLE_PCLK_PERIS_SECURE_TOPRTC, | |
1678 | ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, | |
1679 | ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, | |
1680 | ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, | |
1681 | ENABLE_SCLK_PERIS, | |
1682 | ENABLE_SCLK_PERIS_SECURE_SECKEY, | |
1683 | ENABLE_SCLK_PERIS_SECURE_CHIPID, | |
1684 | ENABLE_SCLK_PERIS_SECURE_TOPRTC, | |
1685 | ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, | |
1686 | ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, | |
1687 | ENABLE_SCLK_PERIS_SECURE_OTP_CON, | |
1688 | ENABLE_IP_PERIS0, | |
1689 | ENABLE_IP_PERIS1, | |
1690 | ENABLE_IP_PERIS_SECURE_TZPC, | |
1691 | ENABLE_IP_PERIS_SECURE_SECKEY, | |
1692 | ENABLE_IP_PERIS_SECURE_CHIPID, | |
1693 | ENABLE_IP_PERIS_SECURE_TOPRTC, | |
1694 | ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE, | |
1695 | ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT, | |
1696 | ENABLE_IP_PERIS_SECURE_OTP_CON, | |
96bd6224 CC |
1697 | }; |
1698 | ||
1699 | static struct samsung_gate_clock peris_gate_clks[] __initdata = { | |
56bcf3f3 CC |
1700 | /* ENABLE_ACLK_PERIS */ |
1701 | GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66", | |
1702 | ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0), | |
1703 | GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66", | |
1704 | ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0), | |
1705 | GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66", | |
1706 | ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0), | |
1707 | ||
96bd6224 CC |
1708 | /* ENABLE_PCLK_PERIS */ |
1709 | GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66", | |
1710 | ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0), | |
1711 | GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66", | |
1712 | ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0), | |
1713 | GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66", | |
1714 | ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0), | |
1715 | GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66", | |
1716 | ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0), | |
1717 | GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66", | |
1718 | ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0), | |
1719 | GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66", | |
1720 | ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0), | |
1721 | GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66", | |
1722 | ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0), | |
1723 | GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66", | |
1724 | ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0), | |
1725 | GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66", | |
1726 | ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0), | |
1727 | GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66", | |
1728 | ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0), | |
56bcf3f3 CC |
1729 | |
1730 | /* ENABLE_PCLK_PERIS_SECURE_TZPC */ | |
1731 | GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66", | |
1732 | ENABLE_PCLK_PERIS_SECURE_TZPC, 12, 0, 0), | |
1733 | GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66", | |
1734 | ENABLE_PCLK_PERIS_SECURE_TZPC, 11, 0, 0), | |
1735 | GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66", | |
1736 | ENABLE_PCLK_PERIS_SECURE_TZPC, 10, 0, 0), | |
1737 | GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66", | |
1738 | ENABLE_PCLK_PERIS_SECURE_TZPC, 9, 0, 0), | |
1739 | GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66", | |
1740 | ENABLE_PCLK_PERIS_SECURE_TZPC, 8, 0, 0), | |
1741 | GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66", | |
1742 | ENABLE_PCLK_PERIS_SECURE_TZPC, 7, 0, 0), | |
1743 | GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66", | |
1744 | ENABLE_PCLK_PERIS_SECURE_TZPC, 6, 0, 0), | |
1745 | GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66", | |
1746 | ENABLE_PCLK_PERIS_SECURE_TZPC, 5, 0, 0), | |
1747 | GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66", | |
1748 | ENABLE_PCLK_PERIS_SECURE_TZPC, 4, 0, 0), | |
1749 | GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66", | |
1750 | ENABLE_PCLK_PERIS_SECURE_TZPC, 3, 0, 0), | |
1751 | GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66", | |
1752 | ENABLE_PCLK_PERIS_SECURE_TZPC, 2, 0, 0), | |
1753 | GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66", | |
1754 | ENABLE_PCLK_PERIS_SECURE_TZPC, 1, 0, 0), | |
1755 | GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66", | |
1756 | ENABLE_PCLK_PERIS_SECURE_TZPC, 0, 0, 0), | |
1757 | ||
1758 | /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */ | |
1759 | GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66", | |
1760 | ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, 0, 0), | |
1761 | ||
1762 | /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */ | |
1763 | GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66", | |
1764 | ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, 0, 0), | |
1765 | ||
1766 | /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */ | |
1767 | GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66", | |
1768 | ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), | |
1769 | ||
1770 | /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */ | |
1771 | GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif", | |
1772 | "aclk_peris_66", | |
1773 | ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0), | |
1774 | ||
1775 | /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */ | |
1776 | GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif", | |
1777 | "aclk_peris_66", | |
1778 | ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0), | |
1779 | ||
1780 | /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */ | |
1781 | GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif", | |
1782 | "aclk_peris_66", | |
1783 | ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0), | |
1784 | ||
1785 | /* ENABLE_SCLK_PERIS */ | |
1786 | GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common", | |
1787 | ENABLE_SCLK_PERIS, 10, 0, 0), | |
1788 | GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common", | |
1789 | ENABLE_SCLK_PERIS, 4, 0, 0), | |
1790 | GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common", | |
1791 | ENABLE_SCLK_PERIS, 3, 0, 0), | |
1792 | ||
1793 | /* ENABLE_SCLK_PERIS_SECURE_SECKEY */ | |
1794 | GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common", | |
1795 | ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, 0, 0), | |
1796 | ||
1797 | /* ENABLE_SCLK_PERIS_SECURE_CHIPID */ | |
1798 | GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common", | |
1799 | ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), | |
1800 | ||
1801 | /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */ | |
1802 | GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common", | |
1803 | ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), | |
1804 | ||
1805 | /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */ | |
1806 | GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common", | |
1807 | ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0), | |
1808 | ||
1809 | /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */ | |
1810 | GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common", | |
1811 | ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0), | |
1812 | ||
1813 | /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */ | |
1814 | GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common", | |
1815 | ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0), | |
96bd6224 CC |
1816 | }; |
1817 | ||
1818 | static struct samsung_cmu_info peris_cmu_info __initdata = { | |
1819 | .gate_clks = peris_gate_clks, | |
1820 | .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), | |
1821 | .nr_clk_ids = PERIS_NR_CLK, | |
1822 | .clk_regs = peris_clk_regs, | |
1823 | .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), | |
1824 | }; | |
1825 | ||
1826 | static void __init exynos5433_cmu_peris_init(struct device_node *np) | |
1827 | { | |
1828 | samsung_cmu_register_one(np, &peris_cmu_info); | |
1829 | } | |
1830 | ||
1831 | CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris", | |
1832 | exynos5433_cmu_peris_init); | |
1833 | ||
1834 | /* | |
1835 | * Register offset definitions for CMU_FSYS | |
1836 | */ | |
1837 | #define MUX_SEL_FSYS0 0x0200 | |
1838 | #define MUX_SEL_FSYS1 0x0204 | |
1839 | #define MUX_SEL_FSYS2 0x0208 | |
1840 | #define MUX_SEL_FSYS3 0x020c | |
1841 | #define MUX_SEL_FSYS4 0x0210 | |
1842 | #define MUX_ENABLE_FSYS0 0x0300 | |
1843 | #define MUX_ENABLE_FSYS1 0x0304 | |
1844 | #define MUX_ENABLE_FSYS2 0x0308 | |
1845 | #define MUX_ENABLE_FSYS3 0x030c | |
1846 | #define MUX_ENABLE_FSYS4 0x0310 | |
1847 | #define MUX_STAT_FSYS0 0x0400 | |
1848 | #define MUX_STAT_FSYS1 0x0404 | |
1849 | #define MUX_STAT_FSYS2 0x0408 | |
1850 | #define MUX_STAT_FSYS3 0x040c | |
1851 | #define MUX_STAT_FSYS4 0x0410 | |
1852 | #define MUX_IGNORE_FSYS2 0x0508 | |
1853 | #define MUX_IGNORE_FSYS3 0x050c | |
1854 | #define ENABLE_ACLK_FSYS0 0x0800 | |
1855 | #define ENABLE_ACLK_FSYS1 0x0804 | |
1856 | #define ENABLE_PCLK_FSYS 0x0900 | |
1857 | #define ENABLE_SCLK_FSYS 0x0a00 | |
1858 | #define ENABLE_IP_FSYS0 0x0b00 | |
1859 | #define ENABLE_IP_FSYS1 0x0b04 | |
1860 | ||
1861 | /* list of all parent clock list */ | |
4b801355 | 1862 | PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", }; |
96bd6224 | 1863 | PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", }; |
4b801355 CC |
1864 | PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",}; |
1865 | PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",}; | |
96bd6224 CC |
1866 | PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", }; |
1867 | PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", }; | |
1868 | PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", }; | |
4b801355 CC |
1869 | PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",}; |
1870 | PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", }; | |
1871 | ||
1872 | PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p) | |
1873 | = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", }; | |
1874 | PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p) | |
1875 | = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", }; | |
1876 | PNAME(mout_phyclk_usbhost20_phy_hsic1_p) | |
1877 | = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", }; | |
1878 | PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p) | |
1879 | = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", }; | |
1880 | PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p) | |
1881 | = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", }; | |
1882 | PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p) | |
1883 | = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", }; | |
1884 | PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p) | |
1885 | = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", }; | |
1886 | PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p) | |
1887 | = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", }; | |
1888 | PNAME(mout_phyclk_ufs_rx1_symbol_user_p) | |
1889 | = { "oscclk", "phyclk_ufs_rx1_symbol_phy", }; | |
1890 | PNAME(mout_phyclk_ufs_rx0_symbol_user_p) | |
1891 | = { "oscclk", "phyclk_ufs_rx0_symbol_phy", }; | |
1892 | PNAME(mout_phyclk_ufs_tx1_symbol_user_p) | |
1893 | = { "oscclk", "phyclk_ufs_tx1_symbol_phy", }; | |
1894 | PNAME(mout_phyclk_ufs_tx0_symbol_user_p) | |
1895 | = { "oscclk", "phyclk_ufs_tx0_symbol_phy", }; | |
1896 | PNAME(mout_phyclk_lli_mphy_to_ufs_user_p) | |
1897 | = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", }; | |
1898 | PNAME(mout_sclk_mphy_p) | |
1899 | = { "mout_sclk_ufs_mphy_user", | |
1900 | "mout_phyclk_lli_mphy_to_ufs_user", }; | |
96bd6224 CC |
1901 | |
1902 | static unsigned long fsys_clk_regs[] __initdata = { | |
1903 | MUX_SEL_FSYS0, | |
1904 | MUX_SEL_FSYS1, | |
1905 | MUX_SEL_FSYS2, | |
1906 | MUX_SEL_FSYS3, | |
1907 | MUX_SEL_FSYS4, | |
1908 | MUX_ENABLE_FSYS0, | |
1909 | MUX_ENABLE_FSYS1, | |
1910 | MUX_ENABLE_FSYS2, | |
1911 | MUX_ENABLE_FSYS3, | |
1912 | MUX_ENABLE_FSYS4, | |
1913 | MUX_STAT_FSYS0, | |
1914 | MUX_STAT_FSYS1, | |
1915 | MUX_STAT_FSYS2, | |
1916 | MUX_STAT_FSYS3, | |
1917 | MUX_STAT_FSYS4, | |
1918 | MUX_IGNORE_FSYS2, | |
1919 | MUX_IGNORE_FSYS3, | |
1920 | ENABLE_ACLK_FSYS0, | |
1921 | ENABLE_ACLK_FSYS1, | |
1922 | ENABLE_PCLK_FSYS, | |
1923 | ENABLE_SCLK_FSYS, | |
1924 | ENABLE_IP_FSYS0, | |
1925 | ENABLE_IP_FSYS1, | |
1926 | }; | |
1927 | ||
4b801355 CC |
1928 | static struct samsung_fixed_rate_clock fsys_fixed_clks[] __initdata = { |
1929 | /* PHY clocks from USBDRD30_PHY */ | |
1930 | FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY, | |
1931 | "phyclk_usbdrd30_udrd30_phyclock_phy", NULL, | |
1932 | CLK_IS_ROOT, 60000000), | |
1933 | FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY, | |
1934 | "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL, | |
1935 | CLK_IS_ROOT, 125000000), | |
1936 | /* PHY clocks from USBHOST30_PHY */ | |
1937 | FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY, | |
1938 | "phyclk_usbhost30_uhost30_phyclock_phy", NULL, | |
1939 | CLK_IS_ROOT, 60000000), | |
1940 | FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY, | |
1941 | "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL, | |
1942 | CLK_IS_ROOT, 125000000), | |
1943 | /* PHY clocks from USBHOST20_PHY */ | |
1944 | FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY, | |
1945 | "phyclk_usbhost20_phy_freeclk_phy", NULL, CLK_IS_ROOT, | |
1946 | 60000000), | |
1947 | FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY, | |
1948 | "phyclk_usbhost20_phy_phyclock_phy", NULL, CLK_IS_ROOT, | |
1949 | 60000000), | |
1950 | FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY, | |
1951 | "phyclk_usbhost20_phy_clk48mohci_phy", NULL, | |
1952 | CLK_IS_ROOT, 48000000), | |
1953 | FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY, | |
1954 | "phyclk_usbhost20_phy_hsic1_phy", NULL, CLK_IS_ROOT, | |
1955 | 60000000), | |
1956 | /* PHY clocks from UFS_PHY */ | |
1957 | FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy", | |
1958 | NULL, CLK_IS_ROOT, 300000000), | |
1959 | FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy", | |
1960 | NULL, CLK_IS_ROOT, 300000000), | |
1961 | FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy", | |
1962 | NULL, CLK_IS_ROOT, 300000000), | |
1963 | FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy", | |
1964 | NULL, CLK_IS_ROOT, 300000000), | |
1965 | /* PHY clocks from LLI_PHY */ | |
1966 | FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy", | |
1967 | NULL, CLK_IS_ROOT, 26000000), | |
1968 | }; | |
1969 | ||
96bd6224 CC |
1970 | static struct samsung_mux_clock fsys_mux_clks[] __initdata = { |
1971 | /* MUX_SEL_FSYS0 */ | |
4b801355 CC |
1972 | MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user", |
1973 | mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1), | |
96bd6224 CC |
1974 | MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user", |
1975 | mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1), | |
1976 | ||
1977 | /* MUX_SEL_FSYS1 */ | |
4b801355 CC |
1978 | MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user", |
1979 | mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1), | |
1980 | MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user", | |
1981 | mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1), | |
96bd6224 CC |
1982 | MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user", |
1983 | mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1), | |
1984 | MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user", | |
1985 | mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1), | |
1986 | MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user", | |
1987 | mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1), | |
4b801355 CC |
1988 | MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user", |
1989 | mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1), | |
1990 | MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user", | |
1991 | mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1), | |
1992 | ||
1993 | /* MUX_SEL_FSYS2 */ | |
1994 | MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER, | |
1995 | "mout_phyclk_usbhost30_uhost30_pipe_pclk_user", | |
1996 | mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p, | |
1997 | MUX_SEL_FSYS2, 28, 1), | |
1998 | MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER, | |
1999 | "mout_phyclk_usbhost30_uhost30_phyclock_user", | |
2000 | mout_phyclk_usbhost30_uhost30_phyclock_user_p, | |
2001 | MUX_SEL_FSYS2, 24, 1), | |
2002 | MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER, | |
2003 | "mout_phyclk_usbhost20_phy_hsic1", | |
2004 | mout_phyclk_usbhost20_phy_hsic1_p, | |
2005 | MUX_SEL_FSYS2, 20, 1), | |
2006 | MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER, | |
2007 | "mout_phyclk_usbhost20_phy_clk48mohci_user", | |
2008 | mout_phyclk_usbhost20_phy_clk48mohci_user_p, | |
2009 | MUX_SEL_FSYS2, 16, 1), | |
2010 | MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER, | |
2011 | "mout_phyclk_usbhost20_phy_phyclock_user", | |
2012 | mout_phyclk_usbhost20_phy_phyclock_user_p, | |
2013 | MUX_SEL_FSYS2, 12, 1), | |
2014 | MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER, | |
2015 | "mout_phyclk_usbhost20_phy_freeclk_user", | |
2016 | mout_phyclk_usbhost20_phy_freeclk_user_p, | |
2017 | MUX_SEL_FSYS2, 8, 1), | |
2018 | MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER, | |
2019 | "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user", | |
2020 | mout_phyclk_usbdrd30_udrd30_pipe_pclk_p, | |
2021 | MUX_SEL_FSYS2, 4, 1), | |
2022 | MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER, | |
2023 | "mout_phyclk_usbdrd30_udrd30_phyclock_user", | |
2024 | mout_phyclk_usbdrd30_udrd30_phyclock_user_p, | |
2025 | MUX_SEL_FSYS2, 0, 1), | |
2026 | ||
2027 | /* MUX_SEL_FSYS3 */ | |
2028 | MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER, | |
2029 | "mout_phyclk_ufs_rx1_symbol_user", | |
2030 | mout_phyclk_ufs_rx1_symbol_user_p, | |
2031 | MUX_SEL_FSYS3, 16, 1), | |
2032 | MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER, | |
2033 | "mout_phyclk_ufs_rx0_symbol_user", | |
2034 | mout_phyclk_ufs_rx0_symbol_user_p, | |
2035 | MUX_SEL_FSYS3, 12, 1), | |
2036 | MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER, | |
2037 | "mout_phyclk_ufs_tx1_symbol_user", | |
2038 | mout_phyclk_ufs_tx1_symbol_user_p, | |
2039 | MUX_SEL_FSYS3, 8, 1), | |
2040 | MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER, | |
2041 | "mout_phyclk_ufs_tx0_symbol_user", | |
2042 | mout_phyclk_ufs_tx0_symbol_user_p, | |
2043 | MUX_SEL_FSYS3, 4, 1), | |
2044 | MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER, | |
2045 | "mout_phyclk_lli_mphy_to_ufs_user", | |
2046 | mout_phyclk_lli_mphy_to_ufs_user_p, | |
2047 | MUX_SEL_FSYS3, 0, 1), | |
2048 | ||
2049 | /* MUX_SEL_FSYS4 */ | |
2050 | MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p, | |
2051 | MUX_SEL_FSYS4, 0, 1), | |
96bd6224 CC |
2052 | }; |
2053 | ||
2054 | static struct samsung_gate_clock fsys_gate_clks[] __initdata = { | |
2055 | /* ENABLE_ACLK_FSYS0 */ | |
2056 | GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user", | |
2057 | ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0), | |
2058 | GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user", | |
2059 | ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0), | |
2060 | GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user", | |
2061 | ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0), | |
2062 | GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user", | |
2063 | ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0), | |
2064 | GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user", | |
2065 | ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0), | |
2066 | GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user", | |
2067 | ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0), | |
2068 | GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user", | |
2069 | ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0), | |
2070 | GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user", | |
2071 | ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0), | |
2072 | GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user", | |
2073 | ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0), | |
2074 | GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user", | |
2075 | ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0), | |
2076 | GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user", | |
2077 | ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0), | |
2078 | ||
4b801355 CC |
2079 | /* ENABLE_ACLK_FSYS1 */ |
2080 | GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user", | |
2081 | ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0), | |
2082 | GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1", | |
2083 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2084 | 26, CLK_IGNORE_UNUSED, 0), | |
2085 | GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user", | |
2086 | ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0), | |
2087 | GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user", | |
2088 | ENABLE_ACLK_FSYS1, 24, 0, 0), | |
2089 | GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1", | |
2090 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2091 | 22, CLK_IGNORE_UNUSED, 0), | |
2092 | GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user", | |
2093 | ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0), | |
2094 | GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user", | |
2095 | ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0), | |
2096 | GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30", | |
2097 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2098 | 13, 0, 0), | |
2099 | GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30", | |
2100 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2101 | 12, 0, 0), | |
2102 | GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0", | |
2103 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2104 | 11, CLK_IGNORE_UNUSED, 0), | |
2105 | GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs", | |
2106 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2107 | 10, CLK_IGNORE_UNUSED, 0), | |
2108 | GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx", | |
2109 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2110 | 9, CLK_IGNORE_UNUSED, 0), | |
2111 | GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp", | |
2112 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2113 | 8, CLK_IGNORE_UNUSED, 0), | |
2114 | GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs", | |
2115 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2116 | 7, CLK_IGNORE_UNUSED, 0), | |
2117 | GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0", | |
2118 | "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, | |
2119 | 6, CLK_IGNORE_UNUSED, 0), | |
2120 | GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user", | |
2121 | ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0), | |
2122 | GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user", | |
2123 | ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0), | |
2124 | GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user", | |
2125 | ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0), | |
2126 | GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user", | |
2127 | ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0), | |
2128 | GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user", | |
2129 | ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0), | |
2130 | GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user", | |
2131 | ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0), | |
2132 | ||
2133 | /* ENABLE_PCLK_FSYS */ | |
2134 | GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user", | |
2135 | ENABLE_PCLK_FSYS, 17, 0, 0), | |
2136 | GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user", | |
2137 | ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0), | |
2138 | GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user", | |
2139 | ENABLE_PCLK_FSYS, 14, 0, 0), | |
2140 | GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user", | |
2141 | ENABLE_PCLK_FSYS, 13, 0, 0), | |
2142 | GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user", | |
2143 | ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0), | |
2144 | GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user", | |
2145 | ENABLE_PCLK_FSYS, 5, 0, 0), | |
2146 | GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30", | |
2147 | "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0), | |
2148 | GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30", | |
2149 | "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0), | |
2150 | GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user", | |
2151 | ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0), | |
2152 | GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user", | |
2153 | ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0), | |
2154 | GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys", | |
2155 | "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, | |
2156 | 0, CLK_IGNORE_UNUSED, 0), | |
2157 | ||
96bd6224 | 2158 | /* ENABLE_SCLK_FSYS */ |
4b801355 CC |
2159 | GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user", |
2160 | ENABLE_SCLK_FSYS, 21, 0, 0), | |
2161 | GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK, | |
2162 | "phyclk_usbhost30_uhost30_pipe_pclk", | |
2163 | "mout_phyclk_usbhost30_uhost30_pipe_pclk_user", | |
2164 | ENABLE_SCLK_FSYS, 18, 0, 0), | |
2165 | GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK, | |
2166 | "phyclk_usbhost30_uhost30_phyclock", | |
2167 | "mout_phyclk_usbhost30_uhost30_phyclock_user", | |
2168 | ENABLE_SCLK_FSYS, 17, 0, 0), | |
2169 | GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol", | |
2170 | "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS, | |
2171 | 16, 0, 0), | |
2172 | GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol", | |
2173 | "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS, | |
2174 | 15, 0, 0), | |
2175 | GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol", | |
2176 | "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS, | |
2177 | 14, 0, 0), | |
2178 | GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol", | |
2179 | "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS, | |
2180 | 13, 0, 0), | |
2181 | GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1", | |
2182 | "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS, | |
2183 | 12, 0, 0), | |
2184 | GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI, | |
2185 | "phyclk_usbhost20_phy_clk48mohci", | |
2186 | "mout_phyclk_usbhost20_phy_clk48mohci_user", | |
2187 | ENABLE_SCLK_FSYS, 11, 0, 0), | |
2188 | GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK, | |
2189 | "phyclk_usbhost20_phy_phyclock", | |
2190 | "mout_phyclk_usbhost20_phy_phyclock_user", | |
2191 | ENABLE_SCLK_FSYS, 10, 0, 0), | |
2192 | GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK, | |
2193 | "phyclk_usbhost20_phy_freeclk", | |
2194 | "mout_phyclk_usbhost20_phy_freeclk_user", | |
2195 | ENABLE_SCLK_FSYS, 9, 0, 0), | |
2196 | GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK, | |
2197 | "phyclk_usbdrd30_udrd30_pipe_pclk", | |
2198 | "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user", | |
2199 | ENABLE_SCLK_FSYS, 8, 0, 0), | |
2200 | GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK, | |
2201 | "phyclk_usbdrd30_udrd30_phyclock", | |
2202 | "mout_phyclk_usbdrd30_udrd30_phyclock_user", | |
2203 | ENABLE_SCLK_FSYS, 7, 0, 0), | |
2204 | GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy", | |
2205 | ENABLE_SCLK_FSYS, 6, 0, 0), | |
2206 | GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user", | |
2207 | ENABLE_SCLK_FSYS, 5, 0, 0), | |
96bd6224 CC |
2208 | GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user", |
2209 | ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0), | |
2210 | GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user", | |
2211 | ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0), | |
2212 | GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user", | |
2213 | ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), | |
4b801355 CC |
2214 | GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user", |
2215 | ENABLE_SCLK_FSYS, 1, 0, 0), | |
2216 | GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user", | |
2217 | ENABLE_SCLK_FSYS, 0, 0, 0), | |
96bd6224 CC |
2218 | |
2219 | /* ENABLE_IP_FSYS0 */ | |
2220 | GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0), | |
2221 | GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0), | |
2222 | }; | |
2223 | ||
2224 | static struct samsung_cmu_info fsys_cmu_info __initdata = { | |
2225 | .mux_clks = fsys_mux_clks, | |
2226 | .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), | |
2227 | .gate_clks = fsys_gate_clks, | |
2228 | .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), | |
4b801355 CC |
2229 | .fixed_clks = fsys_fixed_clks, |
2230 | .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks), | |
96bd6224 CC |
2231 | .nr_clk_ids = FSYS_NR_CLK, |
2232 | .clk_regs = fsys_clk_regs, | |
2233 | .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), | |
2234 | }; | |
2235 | ||
2236 | static void __init exynos5433_cmu_fsys_init(struct device_node *np) | |
2237 | { | |
2238 | samsung_cmu_register_one(np, &fsys_cmu_info); | |
2239 | } | |
2240 | ||
2241 | CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys", | |
2242 | exynos5433_cmu_fsys_init); | |
a29308da CC |
2243 | |
2244 | /* | |
2245 | * Register offset definitions for CMU_G2D | |
2246 | */ | |
2247 | #define MUX_SEL_G2D0 0x0200 | |
2248 | #define MUX_SEL_ENABLE_G2D0 0x0300 | |
2249 | #define MUX_SEL_STAT_G2D0 0x0400 | |
2250 | #define DIV_G2D 0x0600 | |
2251 | #define DIV_STAT_G2D 0x0700 | |
2252 | #define DIV_ENABLE_ACLK_G2D 0x0800 | |
2253 | #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804 | |
2254 | #define DIV_ENABLE_PCLK_G2D 0x0900 | |
2255 | #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904 | |
2256 | #define DIV_ENABLE_IP_G2D0 0x0b00 | |
2257 | #define DIV_ENABLE_IP_G2D1 0x0b04 | |
2258 | #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08 | |
2259 | ||
2260 | static unsigned long g2d_clk_regs[] __initdata = { | |
2261 | MUX_SEL_G2D0, | |
2262 | MUX_SEL_ENABLE_G2D0, | |
2263 | MUX_SEL_STAT_G2D0, | |
2264 | DIV_G2D, | |
2265 | DIV_STAT_G2D, | |
2266 | DIV_ENABLE_ACLK_G2D, | |
2267 | DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, | |
2268 | DIV_ENABLE_PCLK_G2D, | |
2269 | DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, | |
2270 | DIV_ENABLE_IP_G2D0, | |
2271 | DIV_ENABLE_IP_G2D1, | |
2272 | DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D, | |
2273 | }; | |
2274 | ||
2275 | /* list of all parent clock list */ | |
2276 | PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", }; | |
2277 | PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", }; | |
2278 | ||
2279 | static struct samsung_mux_clock g2d_mux_clks[] __initdata = { | |
2280 | /* MUX_SEL_G2D0 */ | |
2281 | MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user", | |
2282 | mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1), | |
2283 | MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user", | |
2284 | mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1), | |
2285 | }; | |
2286 | ||
2287 | static struct samsung_div_clock g2d_div_clks[] __initdata = { | |
2288 | /* DIV_G2D */ | |
2289 | DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user", | |
2290 | DIV_G2D, 0, 2), | |
2291 | }; | |
2292 | ||
2293 | static struct samsung_gate_clock g2d_gate_clks[] __initdata = { | |
2294 | /* DIV_ENABLE_ACLK_G2D */ | |
2295 | GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user", | |
2296 | DIV_ENABLE_ACLK_G2D, 12, 0, 0), | |
2297 | GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user", | |
2298 | DIV_ENABLE_ACLK_G2D, 11, 0, 0), | |
2299 | GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user", | |
2300 | DIV_ENABLE_ACLK_G2D, 10, 0, 0), | |
2301 | GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user", | |
2302 | DIV_ENABLE_ACLK_G2D, 9, 0, 0), | |
2303 | GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user", | |
2304 | DIV_ENABLE_ACLK_G2D, 8, 0, 0), | |
2305 | GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx", | |
2306 | "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D, | |
2307 | 7, 0, 0), | |
2308 | GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d", | |
2309 | DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0), | |
2310 | GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d", | |
2311 | DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0), | |
2312 | GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user", | |
2313 | DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0), | |
2314 | GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d", | |
2315 | DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0), | |
2316 | GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user", | |
2317 | DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0), | |
2318 | GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user", | |
2319 | DIV_ENABLE_ACLK_G2D, 1, 0, 0), | |
2320 | GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user", | |
2321 | DIV_ENABLE_ACLK_G2D, 0, 0, 0), | |
2322 | ||
2323 | /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */ | |
2324 | GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user", | |
2325 | DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), | |
2326 | ||
2327 | /* DIV_ENABLE_PCLK_G2D */ | |
2328 | GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d", | |
2329 | DIV_ENABLE_PCLK_G2D, 7, 0, 0), | |
2330 | GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d", | |
2331 | DIV_ENABLE_PCLK_G2D, 6, 0, 0), | |
2332 | GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d", | |
2333 | DIV_ENABLE_PCLK_G2D, 5, 0, 0), | |
2334 | GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d", | |
2335 | DIV_ENABLE_PCLK_G2D, 4, 0, 0), | |
2336 | GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d", | |
2337 | DIV_ENABLE_PCLK_G2D, 3, 0, 0), | |
2338 | GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d", | |
2339 | DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0), | |
2340 | GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d", | |
2341 | DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0), | |
2342 | GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D, | |
2343 | 0, 0, 0), | |
2344 | ||
2345 | /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */ | |
2346 | GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d", | |
2347 | DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), | |
2348 | }; | |
2349 | ||
2350 | static struct samsung_cmu_info g2d_cmu_info __initdata = { | |
2351 | .mux_clks = g2d_mux_clks, | |
2352 | .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks), | |
2353 | .div_clks = g2d_div_clks, | |
2354 | .nr_div_clks = ARRAY_SIZE(g2d_div_clks), | |
2355 | .gate_clks = g2d_gate_clks, | |
2356 | .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks), | |
2357 | .nr_clk_ids = G2D_NR_CLK, | |
2358 | .clk_regs = g2d_clk_regs, | |
2359 | .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs), | |
2360 | }; | |
2361 | ||
2362 | static void __init exynos5433_cmu_g2d_init(struct device_node *np) | |
2363 | { | |
2364 | samsung_cmu_register_one(np, &g2d_cmu_info); | |
2365 | } | |
2366 | ||
2367 | CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d", | |
2368 | exynos5433_cmu_g2d_init); | |
2a1808a6 CC |
2369 | |
2370 | /* | |
2371 | * Register offset definitions for CMU_DISP | |
2372 | */ | |
2373 | #define DISP_PLL_LOCK 0x0000 | |
2374 | #define DISP_PLL_CON0 0x0100 | |
2375 | #define DISP_PLL_CON1 0x0104 | |
2376 | #define DISP_PLL_FREQ_DET 0x0108 | |
2377 | #define MUX_SEL_DISP0 0x0200 | |
2378 | #define MUX_SEL_DISP1 0x0204 | |
2379 | #define MUX_SEL_DISP2 0x0208 | |
2380 | #define MUX_SEL_DISP3 0x020c | |
2381 | #define MUX_SEL_DISP4 0x0210 | |
2382 | #define MUX_ENABLE_DISP0 0x0300 | |
2383 | #define MUX_ENABLE_DISP1 0x0304 | |
2384 | #define MUX_ENABLE_DISP2 0x0308 | |
2385 | #define MUX_ENABLE_DISP3 0x030c | |
2386 | #define MUX_ENABLE_DISP4 0x0310 | |
2387 | #define MUX_STAT_DISP0 0x0400 | |
2388 | #define MUX_STAT_DISP1 0x0404 | |
2389 | #define MUX_STAT_DISP2 0x0408 | |
2390 | #define MUX_STAT_DISP3 0x040c | |
2391 | #define MUX_STAT_DISP4 0x0410 | |
2392 | #define MUX_IGNORE_DISP2 0x0508 | |
2393 | #define DIV_DISP 0x0600 | |
2394 | #define DIV_DISP_PLL_FREQ_DET 0x0604 | |
2395 | #define DIV_STAT_DISP 0x0700 | |
2396 | #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704 | |
2397 | #define ENABLE_ACLK_DISP0 0x0800 | |
2398 | #define ENABLE_ACLK_DISP1 0x0804 | |
2399 | #define ENABLE_PCLK_DISP 0x0900 | |
2400 | #define ENABLE_SCLK_DISP 0x0a00 | |
2401 | #define ENABLE_IP_DISP0 0x0b00 | |
2402 | #define ENABLE_IP_DISP1 0x0b04 | |
2403 | #define CLKOUT_CMU_DISP 0x0c00 | |
2404 | #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04 | |
2405 | ||
2406 | static unsigned long disp_clk_regs[] __initdata = { | |
2407 | DISP_PLL_LOCK, | |
2408 | DISP_PLL_CON0, | |
2409 | DISP_PLL_CON1, | |
2410 | DISP_PLL_FREQ_DET, | |
2411 | MUX_SEL_DISP0, | |
2412 | MUX_SEL_DISP1, | |
2413 | MUX_SEL_DISP2, | |
2414 | MUX_SEL_DISP3, | |
2415 | MUX_SEL_DISP4, | |
2416 | MUX_ENABLE_DISP0, | |
2417 | MUX_ENABLE_DISP1, | |
2418 | MUX_ENABLE_DISP2, | |
2419 | MUX_ENABLE_DISP3, | |
2420 | MUX_ENABLE_DISP4, | |
2421 | MUX_STAT_DISP0, | |
2422 | MUX_STAT_DISP1, | |
2423 | MUX_STAT_DISP2, | |
2424 | MUX_STAT_DISP3, | |
2425 | MUX_STAT_DISP4, | |
2426 | MUX_IGNORE_DISP2, | |
2427 | DIV_DISP, | |
2428 | DIV_DISP_PLL_FREQ_DET, | |
2429 | DIV_STAT_DISP, | |
2430 | DIV_STAT_DISP_PLL_FREQ_DET, | |
2431 | ENABLE_ACLK_DISP0, | |
2432 | ENABLE_ACLK_DISP1, | |
2433 | ENABLE_PCLK_DISP, | |
2434 | ENABLE_SCLK_DISP, | |
2435 | ENABLE_IP_DISP0, | |
2436 | ENABLE_IP_DISP1, | |
2437 | CLKOUT_CMU_DISP, | |
2438 | CLKOUT_CMU_DISP_DIV_STAT, | |
2439 | }; | |
2440 | ||
2441 | /* list of all parent clock list */ | |
2442 | PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", }; | |
2443 | PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", }; | |
2444 | PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", }; | |
2445 | PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", }; | |
2446 | PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk", | |
2447 | "sclk_decon_tv_eclk_disp", }; | |
2448 | PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk", | |
2449 | "sclk_decon_vclk_disp", }; | |
2450 | PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk", | |
2451 | "sclk_decon_eclk_disp", }; | |
2452 | PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk", | |
2453 | "sclk_decon_tv_vclk_disp", }; | |
2454 | PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", }; | |
2455 | ||
2456 | PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk", | |
2457 | "phyclk_mipidphy1_bitclkdiv8_phy", }; | |
2458 | PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk", | |
2459 | "phyclk_mipidphy1_rxclkesc0_phy", }; | |
2460 | PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk", | |
2461 | "phyclk_mipidphy0_bitclkdiv8_phy", }; | |
2462 | PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk", | |
2463 | "phyclk_mipidphy0_rxclkesc0_phy", }; | |
2464 | PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk", | |
2465 | "phyclk_hdmiphy_tmds_clko_phy", }; | |
2466 | PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk", | |
2467 | "phyclk_hdmiphy_pixel_clko_phy", }; | |
2468 | ||
2469 | PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll", | |
2470 | "mout_sclk_dsim0_user", }; | |
2471 | PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll", | |
2472 | "mout_sclk_decon_tv_eclk_user", }; | |
2473 | PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll", | |
2474 | "mout_sclk_decon_vclk_user", }; | |
2475 | PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll", | |
2476 | "mout_sclk_decon_eclk_user", }; | |
2477 | ||
2478 | PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp", | |
2479 | "mout_sclk_dsim1_user", }; | |
2480 | PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = { | |
2481 | "mout_phyclk_hdmiphy_pixel_clko_user", | |
2482 | "mout_sclk_decon_tv_vclk_b_disp", }; | |
2483 | PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp", | |
2484 | "mout_sclk_decon_tv_vclk_user", }; | |
2485 | ||
2486 | static struct samsung_pll_clock disp_pll_clks[] __initdata = { | |
2487 | PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", | |
2488 | DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates), | |
2489 | }; | |
2490 | ||
2491 | static struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initdata = { | |
2492 | /* | |
2493 | * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}. | |
2494 | * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk} | |
2495 | * and sclk_decon_{vclk|tv_vclk}. | |
2496 | */ | |
2497 | FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk", | |
2498 | 1, 2, 0), | |
2499 | FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk", | |
2500 | 1, 2, 0), | |
2501 | }; | |
2502 | ||
2503 | static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = { | |
2504 | /* PHY clocks from MIPI_DPHY1 */ | |
2505 | FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, CLK_IS_ROOT, | |
2506 | 188000000), | |
2507 | FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, CLK_IS_ROOT, | |
2508 | 100000000), | |
2509 | /* PHY clocks from MIPI_DPHY0 */ | |
2510 | FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, CLK_IS_ROOT, | |
2511 | 188000000), | |
2512 | FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT, | |
2513 | 100000000), | |
2514 | /* PHY clocks from HDMI_PHY */ | |
2515 | FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000), | |
2516 | FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000), | |
2517 | }; | |
2518 | ||
2519 | static struct samsung_mux_clock disp_mux_clks[] __initdata = { | |
2520 | /* MUX_SEL_DISP0 */ | |
2521 | MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0, | |
2522 | 0, 1), | |
2523 | ||
2524 | /* MUX_SEL_DISP1 */ | |
2525 | MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user", | |
2526 | mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1), | |
2527 | MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user", | |
2528 | mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1), | |
2529 | MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p, | |
2530 | MUX_SEL_DISP1, 20, 1), | |
2531 | MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user", | |
2532 | mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1), | |
2533 | MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user", | |
2534 | mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1), | |
2535 | MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user", | |
2536 | mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1), | |
2537 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user", | |
2538 | mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1), | |
2539 | MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user", | |
2540 | mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1), | |
2541 | ||
2542 | /* MUX_SEL_DISP2 */ | |
2543 | MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, | |
2544 | "mout_phyclk_mipidphy1_bitclkdiv8_user", | |
2545 | mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2, | |
2546 | 20, 1), | |
2547 | MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, | |
2548 | "mout_phyclk_mipidphy1_rxclkesc0_user", | |
2549 | mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2, | |
2550 | 16, 1), | |
2551 | MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, | |
2552 | "mout_phyclk_mipidphy0_bitclkdiv8_user", | |
2553 | mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2, | |
2554 | 12, 1), | |
2555 | MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, | |
2556 | "mout_phyclk_mipidphy0_rxclkesc0_user", | |
2557 | mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2, | |
2558 | 8, 1), | |
2559 | MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER, | |
2560 | "mout_phyclk_hdmiphy_tmds_clko_user", | |
2561 | mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2, | |
2562 | 4, 1), | |
2563 | MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, | |
2564 | "mout_phyclk_hdmiphy_pixel_clko_user", | |
2565 | mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2, | |
2566 | 0, 1), | |
2567 | ||
2568 | /* MUX_SEL_DISP3 */ | |
2569 | MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p, | |
2570 | MUX_SEL_DISP3, 12, 1), | |
2571 | MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk", | |
2572 | mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1), | |
2573 | MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk", | |
2574 | mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1), | |
2575 | MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk", | |
2576 | mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1), | |
2577 | ||
2578 | /* MUX_SEL_DISP4 */ | |
2579 | MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp", | |
2580 | mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1), | |
2581 | MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp", | |
2582 | mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1), | |
2583 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP, | |
2584 | "mout_sclk_decon_tv_vclk_c_disp", | |
2585 | mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1), | |
2586 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP, | |
2587 | "mout_sclk_decon_tv_vclk_b_disp", | |
2588 | mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1), | |
2589 | MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP, | |
2590 | "mout_sclk_decon_tv_vclk_a_disp", | |
2591 | mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1), | |
2592 | }; | |
2593 | ||
2594 | static struct samsung_div_clock disp_div_clks[] __initdata = { | |
2595 | /* DIV_DISP */ | |
2596 | DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp", | |
2597 | "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3), | |
2598 | DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp", | |
2599 | "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3), | |
2600 | DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0", | |
2601 | DIV_DISP, 16, 3), | |
2602 | DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp", | |
2603 | "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3), | |
2604 | DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp", | |
2605 | "mout_sclk_decon_vclk", DIV_DISP, 8, 3), | |
2606 | DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp", | |
2607 | "mout_sclk_decon_eclk", DIV_DISP, 4, 3), | |
2608 | DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user", | |
2609 | DIV_DISP, 0, 2), | |
2610 | }; | |
2611 | ||
2612 | static struct samsung_gate_clock disp_gate_clks[] __initdata = { | |
2613 | /* ENABLE_ACLK_DISP0 */ | |
2614 | GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user", | |
2615 | ENABLE_ACLK_DISP0, 2, 0, 0), | |
2616 | GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user", | |
2617 | ENABLE_ACLK_DISP0, 0, 0, 0), | |
2618 | ||
2619 | /* ENABLE_ACLK_DISP1 */ | |
2620 | GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user", | |
2621 | ENABLE_ACLK_DISP1, 25, 0, 0), | |
2622 | GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user", | |
2623 | ENABLE_ACLK_DISP1, 24, 0, 0), | |
2624 | GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x", | |
2625 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0), | |
2626 | GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x", | |
2627 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0), | |
2628 | GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3", | |
2629 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0), | |
2630 | GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2", | |
2631 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0), | |
2632 | GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1", | |
2633 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0), | |
2634 | GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0", | |
2635 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0), | |
2636 | GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4", | |
2637 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0), | |
2638 | GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3", | |
2639 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0), | |
2640 | GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2", | |
2641 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0), | |
2642 | GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1", | |
2643 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0), | |
2644 | GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0", | |
2645 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0), | |
2646 | GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p", | |
2647 | "div_pclk_disp", ENABLE_ACLK_DISP1, | |
2648 | 12, CLK_IGNORE_UNUSED, 0), | |
2649 | GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p", | |
2650 | "div_pclk_disp", ENABLE_ACLK_DISP1, | |
2651 | 11, CLK_IGNORE_UNUSED, 0), | |
2652 | GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p", | |
2653 | "div_pclk_disp", ENABLE_ACLK_DISP1, | |
2654 | 10, CLK_IGNORE_UNUSED, 0), | |
2655 | GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp", | |
2656 | ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0), | |
2657 | GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user", | |
2658 | ENABLE_ACLK_DISP1, 7, 0, 0), | |
2659 | GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user", | |
2660 | ENABLE_ACLK_DISP1, 6, 0, 0), | |
2661 | GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x", | |
2662 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0), | |
2663 | GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x", | |
2664 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0), | |
2665 | GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user", | |
2666 | ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0), | |
2667 | GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp", | |
2668 | ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0), | |
2669 | GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333", | |
2670 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1, | |
2671 | CLK_IGNORE_UNUSED, 0), | |
2672 | GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333", | |
2673 | "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, | |
2674 | 0, CLK_IGNORE_UNUSED, 0), | |
2675 | ||
2676 | /* ENABLE_PCLK_DISP */ | |
2677 | GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp", | |
2678 | ENABLE_PCLK_DISP, 23, 0, 0), | |
2679 | GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp", | |
2680 | ENABLE_PCLK_DISP, 22, 0, 0), | |
2681 | GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp", | |
2682 | ENABLE_PCLK_DISP, 21, 0, 0), | |
2683 | GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp", | |
2684 | ENABLE_PCLK_DISP, 20, 0, 0), | |
2685 | GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp", | |
2686 | ENABLE_PCLK_DISP, 19, 0, 0), | |
2687 | GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp", | |
2688 | ENABLE_PCLK_DISP, 18, 0, 0), | |
2689 | GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp", | |
2690 | ENABLE_PCLK_DISP, 17, 0, 0), | |
2691 | GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp", | |
2692 | ENABLE_PCLK_DISP, 16, 0, 0), | |
2693 | GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp", | |
2694 | ENABLE_PCLK_DISP, 15, 0, 0), | |
2695 | GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp", | |
2696 | ENABLE_PCLK_DISP, 14, 0, 0), | |
2697 | GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp", | |
2698 | ENABLE_PCLK_DISP, 13, 0, 0), | |
2699 | GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp", | |
2700 | ENABLE_PCLK_DISP, 12, 0, 0), | |
2701 | GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp", | |
2702 | ENABLE_PCLK_DISP, 11, 0, 0), | |
2703 | GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp", | |
2704 | ENABLE_PCLK_DISP, 10, 0, 0), | |
2705 | GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp", | |
2706 | ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0), | |
2707 | GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp", | |
2708 | ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0), | |
2709 | GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp", | |
2710 | ENABLE_PCLK_DISP, 7, 0, 0), | |
2711 | GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp", | |
2712 | ENABLE_PCLK_DISP, 6, 0, 0), | |
2713 | GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp", | |
2714 | ENABLE_PCLK_DISP, 5, 0, 0), | |
2715 | GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp", | |
2716 | ENABLE_PCLK_DISP, 3, 0, 0), | |
2717 | GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp", | |
2718 | ENABLE_PCLK_DISP, 2, 0, 0), | |
2719 | GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp", | |
2720 | ENABLE_PCLK_DISP, 1, 0, 0), | |
2721 | ||
2722 | /* ENABLE_SCLK_DISP */ | |
2723 | GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8", | |
2724 | "mout_phyclk_mipidphy1_bitclkdiv8_user", | |
2725 | ENABLE_SCLK_DISP, 26, 0, 0), | |
2726 | GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0", | |
2727 | "mout_phyclk_mipidphy1_rxclkesc0_user", | |
2728 | ENABLE_SCLK_DISP, 25, 0, 0), | |
2729 | GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1", | |
2730 | "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0), | |
2731 | GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1", | |
2732 | "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0), | |
2733 | GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp", | |
2734 | ENABLE_SCLK_DISP, 22, 0, 0), | |
2735 | GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk", | |
2736 | "div_sclk_decon_tv_vclk_disp", | |
2737 | ENABLE_SCLK_DISP, 21, 0, 0), | |
2738 | GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8", | |
2739 | "mout_phyclk_mipidphy0_bitclkdiv8_user", | |
2740 | ENABLE_SCLK_DISP, 15, 0, 0), | |
2741 | GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0", | |
2742 | "mout_phyclk_mipidphy0_rxclkesc0_user", | |
2743 | ENABLE_SCLK_DISP, 14, 0, 0), | |
2744 | GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko", | |
2745 | "mout_phyclk_hdmiphy_tmds_clko_user", | |
2746 | ENABLE_SCLK_DISP, 13, 0, 0), | |
2747 | GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel", | |
2748 | "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0), | |
2749 | GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies", | |
2750 | "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0), | |
2751 | GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0", | |
2752 | "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0), | |
2753 | GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0", | |
2754 | "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0), | |
2755 | GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user", | |
2756 | ENABLE_SCLK_DISP, 7, 0, 0), | |
2757 | GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp", | |
2758 | ENABLE_SCLK_DISP, 6, 0, 0), | |
2759 | GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp", | |
2760 | ENABLE_SCLK_DISP, 5, 0, 0), | |
2761 | GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk", | |
2762 | "div_sclk_decon_tv_eclk_disp", | |
2763 | ENABLE_SCLK_DISP, 4, 0, 0), | |
2764 | GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk", | |
2765 | "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0), | |
2766 | GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk", | |
2767 | "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0), | |
2768 | }; | |
2769 | ||
2770 | static struct samsung_cmu_info disp_cmu_info __initdata = { | |
2771 | .pll_clks = disp_pll_clks, | |
2772 | .nr_pll_clks = ARRAY_SIZE(disp_pll_clks), | |
2773 | .mux_clks = disp_mux_clks, | |
2774 | .nr_mux_clks = ARRAY_SIZE(disp_mux_clks), | |
2775 | .div_clks = disp_div_clks, | |
2776 | .nr_div_clks = ARRAY_SIZE(disp_div_clks), | |
2777 | .gate_clks = disp_gate_clks, | |
2778 | .nr_gate_clks = ARRAY_SIZE(disp_gate_clks), | |
2779 | .fixed_clks = disp_fixed_clks, | |
2780 | .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks), | |
2781 | .fixed_factor_clks = disp_fixed_factor_clks, | |
2782 | .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks), | |
2783 | .nr_clk_ids = DISP_NR_CLK, | |
2784 | .clk_regs = disp_clk_regs, | |
2785 | .nr_clk_regs = ARRAY_SIZE(disp_clk_regs), | |
2786 | }; | |
2787 | ||
2788 | static void __init exynos5433_cmu_disp_init(struct device_node *np) | |
2789 | { | |
2790 | samsung_cmu_register_one(np, &disp_cmu_info); | |
2791 | } | |
2792 | ||
2793 | CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp", | |
2794 | exynos5433_cmu_disp_init); | |
2e997c03 CC |
2795 | |
2796 | /* | |
2797 | * Register offset definitions for CMU_AUD | |
2798 | */ | |
2799 | #define MUX_SEL_AUD0 0x0200 | |
2800 | #define MUX_SEL_AUD1 0x0204 | |
2801 | #define MUX_ENABLE_AUD0 0x0300 | |
2802 | #define MUX_ENABLE_AUD1 0x0304 | |
2803 | #define MUX_STAT_AUD0 0x0400 | |
2804 | #define DIV_AUD0 0x0600 | |
2805 | #define DIV_AUD1 0x0604 | |
2806 | #define DIV_STAT_AUD0 0x0700 | |
2807 | #define DIV_STAT_AUD1 0x0704 | |
2808 | #define ENABLE_ACLK_AUD 0x0800 | |
2809 | #define ENABLE_PCLK_AUD 0x0900 | |
2810 | #define ENABLE_SCLK_AUD0 0x0a00 | |
2811 | #define ENABLE_SCLK_AUD1 0x0a04 | |
2812 | #define ENABLE_IP_AUD0 0x0b00 | |
2813 | #define ENABLE_IP_AUD1 0x0b04 | |
2814 | ||
2815 | static unsigned long aud_clk_regs[] __initdata = { | |
2816 | MUX_SEL_AUD0, | |
2817 | MUX_SEL_AUD1, | |
2818 | MUX_ENABLE_AUD0, | |
2819 | MUX_ENABLE_AUD1, | |
2820 | MUX_STAT_AUD0, | |
2821 | DIV_AUD0, | |
2822 | DIV_AUD1, | |
2823 | DIV_STAT_AUD0, | |
2824 | DIV_STAT_AUD1, | |
2825 | ENABLE_ACLK_AUD, | |
2826 | ENABLE_PCLK_AUD, | |
2827 | ENABLE_SCLK_AUD0, | |
2828 | ENABLE_SCLK_AUD1, | |
2829 | ENABLE_IP_AUD0, | |
2830 | ENABLE_IP_AUD1, | |
2831 | }; | |
2832 | ||
2833 | /* list of all parent clock list */ | |
2834 | PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", }; | |
2835 | PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; | |
2836 | ||
2837 | static struct samsung_fixed_rate_clock aud_fixed_clks[] __initdata = { | |
2838 | FRATE(0, "ioclk_jtag_tclk", NULL, CLK_IS_ROOT, 33000000), | |
2839 | FRATE(0, "ioclk_slimbus_clk", NULL, CLK_IS_ROOT, 25000000), | |
2840 | FRATE(0, "ioclk_i2s_bclk", NULL, CLK_IS_ROOT, 50000000), | |
2841 | }; | |
2842 | ||
2843 | static struct samsung_mux_clock aud_mux_clks[] __initdata = { | |
2844 | /* MUX_SEL_AUD0 */ | |
2845 | MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user", | |
2846 | mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1), | |
2847 | ||
2848 | /* MUX_SEL_AUD1 */ | |
2849 | MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p, | |
2850 | MUX_SEL_AUD1, 8, 1), | |
2851 | MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p, | |
2852 | MUX_SEL_AUD1, 0, 1), | |
2853 | }; | |
2854 | ||
2855 | static struct samsung_div_clock aud_div_clks[] __initdata = { | |
2856 | /* DIV_AUD0 */ | |
2857 | DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0, | |
2858 | 12, 4), | |
2859 | DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0, | |
2860 | 8, 4), | |
2861 | DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0, | |
2862 | 4, 4), | |
2863 | DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0, | |
2864 | 0, 4), | |
2865 | ||
2866 | /* DIV_AUD1 */ | |
2867 | DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus", | |
2868 | "mout_aud_pll_user", DIV_AUD1, 16, 5), | |
2869 | DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user", | |
2870 | DIV_AUD1, 12, 4), | |
2871 | DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm", | |
2872 | DIV_AUD1, 4, 8), | |
2873 | DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s", | |
2874 | DIV_AUD1, 0, 4), | |
2875 | }; | |
2876 | ||
2877 | static struct samsung_gate_clock aud_gate_clks[] __initdata = { | |
2878 | /* ENABLE_ACLK_AUD */ | |
2879 | GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud", | |
2880 | ENABLE_ACLK_AUD, 12, 0, 0), | |
2881 | GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud", | |
2882 | ENABLE_ACLK_AUD, 7, 0, 0), | |
2883 | GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud", | |
2884 | ENABLE_ACLK_AUD, 0, 4, 0), | |
2885 | GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud", | |
2886 | ENABLE_ACLK_AUD, 0, 3, 0), | |
2887 | GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud", | |
2888 | ENABLE_ACLK_AUD, 0, 2, 0), | |
2889 | GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD, | |
2890 | 0, 1, 0), | |
2891 | GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD, | |
2892 | 0, CLK_IGNORE_UNUSED, 0), | |
2893 | ||
2894 | /* ENABLE_PCLK_AUD */ | |
2895 | GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD, | |
2896 | 13, 0, 0), | |
2897 | GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD, | |
2898 | 12, 0, 0), | |
2899 | GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD, | |
2900 | 11, 0, 0), | |
2901 | GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud", | |
2902 | ENABLE_PCLK_AUD, 10, 0, 0), | |
2903 | GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud", | |
2904 | ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0), | |
2905 | GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud", | |
2906 | ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0), | |
2907 | GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud", | |
2908 | ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0), | |
2909 | GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud", | |
2910 | ENABLE_PCLK_AUD, 6, 0, 0), | |
2911 | GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud", | |
2912 | ENABLE_PCLK_AUD, 5, 0, 0), | |
2913 | GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud", | |
2914 | ENABLE_PCLK_AUD, 4, 0, 0), | |
2915 | GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud", | |
2916 | ENABLE_PCLK_AUD, 3, 0, 0), | |
2917 | GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD, | |
2918 | 2, 0, 0), | |
2919 | GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud", | |
2920 | ENABLE_PCLK_AUD, 0, 0, 0), | |
2921 | ||
2922 | /* ENABLE_SCLK_AUD0 */ | |
2923 | GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0, | |
2924 | 2, 0, 0), | |
2925 | GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud", | |
2926 | ENABLE_SCLK_AUD0, 1, 0, 0), | |
2927 | GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0, | |
2928 | 0, 0, 0), | |
2929 | ||
2930 | /* ENABLE_SCLK_AUD1 */ | |
2931 | GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk", | |
2932 | ENABLE_SCLK_AUD1, 6, 0, 0), | |
2933 | GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk", | |
2934 | ENABLE_SCLK_AUD1, 5, 0, 0), | |
2935 | GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus", | |
2936 | ENABLE_SCLK_AUD1, 4, 0, 0), | |
2937 | GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart", | |
2938 | ENABLE_SCLK_AUD1, 3, 0, 0), | |
2939 | GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm", | |
2940 | ENABLE_SCLK_AUD1, 2, 0, 0), | |
2941 | GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk", | |
2942 | ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0), | |
2943 | GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s", | |
2944 | ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0), | |
2945 | }; | |
2946 | ||
2947 | static struct samsung_cmu_info aud_cmu_info __initdata = { | |
2948 | .mux_clks = aud_mux_clks, | |
2949 | .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), | |
2950 | .div_clks = aud_div_clks, | |
2951 | .nr_div_clks = ARRAY_SIZE(aud_div_clks), | |
2952 | .gate_clks = aud_gate_clks, | |
2953 | .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), | |
2954 | .fixed_clks = aud_fixed_clks, | |
2955 | .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), | |
2956 | .nr_clk_ids = AUD_NR_CLK, | |
2957 | .clk_regs = aud_clk_regs, | |
2958 | .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), | |
2959 | }; | |
2960 | ||
2961 | static void __init exynos5433_cmu_aud_init(struct device_node *np) | |
2962 | { | |
2963 | samsung_cmu_register_one(np, &aud_cmu_info); | |
2964 | } | |
2965 | CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud", | |
2966 | exynos5433_cmu_aud_init); | |
5785d6e6 CC |
2967 | |
2968 | ||
2969 | /* | |
2970 | * Register offset definitions for CMU_BUS{0|1|2} | |
2971 | */ | |
2972 | #define DIV_BUS 0x0600 | |
2973 | #define DIV_STAT_BUS 0x0700 | |
2974 | #define ENABLE_ACLK_BUS 0x0800 | |
2975 | #define ENABLE_PCLK_BUS 0x0900 | |
2976 | #define ENABLE_IP_BUS0 0x0b00 | |
2977 | #define ENABLE_IP_BUS1 0x0b04 | |
2978 | ||
2979 | #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */ | |
2980 | #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */ | |
2981 | #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */ | |
2982 | ||
2983 | /* list of all parent clock list */ | |
2984 | PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", }; | |
2985 | ||
2986 | #define CMU_BUS_COMMON_CLK_REGS \ | |
2987 | DIV_BUS, \ | |
2988 | DIV_STAT_BUS, \ | |
2989 | ENABLE_ACLK_BUS, \ | |
2990 | ENABLE_PCLK_BUS, \ | |
2991 | ENABLE_IP_BUS0, \ | |
2992 | ENABLE_IP_BUS1 | |
2993 | ||
2994 | static unsigned long bus01_clk_regs[] __initdata = { | |
2995 | CMU_BUS_COMMON_CLK_REGS, | |
2996 | }; | |
2997 | ||
2998 | static unsigned long bus2_clk_regs[] __initdata = { | |
2999 | MUX_SEL_BUS2, | |
3000 | MUX_ENABLE_BUS2, | |
3001 | MUX_STAT_BUS2, | |
3002 | CMU_BUS_COMMON_CLK_REGS, | |
3003 | }; | |
3004 | ||
3005 | static struct samsung_div_clock bus0_div_clks[] __initdata = { | |
3006 | /* DIV_BUS0 */ | |
3007 | DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400", | |
3008 | DIV_BUS, 0, 3), | |
3009 | }; | |
3010 | ||
3011 | /* CMU_BUS0 clocks */ | |
3012 | static struct samsung_gate_clock bus0_gate_clks[] __initdata = { | |
3013 | /* ENABLE_ACLK_BUS0 */ | |
3014 | GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133", | |
3015 | ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), | |
3016 | GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133", | |
3017 | ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), | |
3018 | GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400", | |
3019 | ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), | |
3020 | ||
3021 | /* ENABLE_PCLK_BUS0 */ | |
3022 | GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133", | |
3023 | ENABLE_PCLK_BUS, 2, 0, 0), | |
3024 | GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133", | |
3025 | ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), | |
3026 | GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133", | |
3027 | ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), | |
3028 | }; | |
3029 | ||
3030 | /* CMU_BUS1 clocks */ | |
3031 | static struct samsung_div_clock bus1_div_clks[] __initdata = { | |
3032 | /* DIV_BUS1 */ | |
3033 | DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400", | |
3034 | DIV_BUS, 0, 3), | |
3035 | }; | |
3036 | ||
3037 | static struct samsung_gate_clock bus1_gate_clks[] __initdata = { | |
3038 | /* ENABLE_ACLK_BUS1 */ | |
3039 | GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133", | |
3040 | ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), | |
3041 | GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133", | |
3042 | ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), | |
3043 | GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400", | |
3044 | ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), | |
3045 | ||
3046 | /* ENABLE_PCLK_BUS1 */ | |
3047 | GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133", | |
3048 | ENABLE_PCLK_BUS, 2, 0, 0), | |
3049 | GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133", | |
3050 | ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), | |
3051 | GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133", | |
3052 | ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), | |
3053 | }; | |
3054 | ||
3055 | /* CMU_BUS2 clocks */ | |
3056 | static struct samsung_mux_clock bus2_mux_clks[] __initdata = { | |
3057 | /* MUX_SEL_BUS2 */ | |
3058 | MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user", | |
3059 | mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1), | |
3060 | }; | |
3061 | ||
3062 | static struct samsung_div_clock bus2_div_clks[] __initdata = { | |
3063 | /* DIV_BUS2 */ | |
3064 | DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133", | |
3065 | "mout_aclk_bus2_400_user", DIV_BUS, 0, 3), | |
3066 | }; | |
3067 | ||
3068 | static struct samsung_gate_clock bus2_gate_clks[] __initdata = { | |
3069 | /* ENABLE_ACLK_BUS2 */ | |
3070 | GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133", | |
3071 | ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0), | |
3072 | GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133", | |
3073 | ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), | |
3074 | GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400", | |
3075 | "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, | |
3076 | 1, CLK_IGNORE_UNUSED, 0), | |
3077 | GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400", | |
3078 | "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, | |
3079 | 0, CLK_IGNORE_UNUSED, 0), | |
3080 | ||
3081 | /* ENABLE_PCLK_BUS2 */ | |
3082 | GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133", | |
3083 | ENABLE_PCLK_BUS, 2, 0, 0), | |
3084 | GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133", | |
3085 | ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), | |
3086 | GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133", | |
3087 | ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), | |
3088 | }; | |
3089 | ||
3090 | #define CMU_BUS_INFO_CLKS(id) \ | |
3091 | .div_clks = bus##id##_div_clks, \ | |
3092 | .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \ | |
3093 | .gate_clks = bus##id##_gate_clks, \ | |
3094 | .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \ | |
3095 | .nr_clk_ids = BUSx_NR_CLK | |
3096 | ||
3097 | static struct samsung_cmu_info bus0_cmu_info __initdata = { | |
3098 | CMU_BUS_INFO_CLKS(0), | |
3099 | .clk_regs = bus01_clk_regs, | |
3100 | .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), | |
3101 | }; | |
3102 | ||
3103 | static struct samsung_cmu_info bus1_cmu_info __initdata = { | |
3104 | CMU_BUS_INFO_CLKS(1), | |
3105 | .clk_regs = bus01_clk_regs, | |
3106 | .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), | |
3107 | }; | |
3108 | ||
3109 | static struct samsung_cmu_info bus2_cmu_info __initdata = { | |
3110 | CMU_BUS_INFO_CLKS(2), | |
3111 | .mux_clks = bus2_mux_clks, | |
3112 | .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks), | |
3113 | .clk_regs = bus2_clk_regs, | |
3114 | .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs), | |
3115 | }; | |
3116 | ||
3117 | #define exynos5433_cmu_bus_init(id) \ | |
3118 | static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\ | |
3119 | { \ | |
3120 | samsung_cmu_register_one(np, &bus##id##_cmu_info); \ | |
3121 | } \ | |
3122 | CLK_OF_DECLARE(exynos5433_cmu_bus##id, \ | |
3123 | "samsung,exynos5433-cmu-bus"#id, \ | |
3124 | exynos5433_cmu_bus##id##_init) | |
3125 | ||
3126 | exynos5433_cmu_bus_init(0); | |
3127 | exynos5433_cmu_bus_init(1); | |
3128 | exynos5433_cmu_bus_init(2); | |
453e519e CC |
3129 | |
3130 | /* | |
3131 | * Register offset definitions for CMU_G3D | |
3132 | */ | |
3133 | #define G3D_PLL_LOCK 0x0000 | |
3134 | #define G3D_PLL_CON0 0x0100 | |
3135 | #define G3D_PLL_CON1 0x0104 | |
3136 | #define G3D_PLL_FREQ_DET 0x010c | |
3137 | #define MUX_SEL_G3D 0x0200 | |
3138 | #define MUX_ENABLE_G3D 0x0300 | |
3139 | #define MUX_STAT_G3D 0x0400 | |
3140 | #define DIV_G3D 0x0600 | |
3141 | #define DIV_G3D_PLL_FREQ_DET 0x0604 | |
3142 | #define DIV_STAT_G3D 0x0700 | |
3143 | #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704 | |
3144 | #define ENABLE_ACLK_G3D 0x0800 | |
3145 | #define ENABLE_PCLK_G3D 0x0900 | |
3146 | #define ENABLE_SCLK_G3D 0x0a00 | |
3147 | #define ENABLE_IP_G3D0 0x0b00 | |
3148 | #define ENABLE_IP_G3D1 0x0b04 | |
3149 | #define CLKOUT_CMU_G3D 0x0c00 | |
3150 | #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04 | |
3151 | #define CLK_STOPCTRL 0x1000 | |
3152 | ||
3153 | static unsigned long g3d_clk_regs[] __initdata = { | |
3154 | G3D_PLL_LOCK, | |
3155 | G3D_PLL_CON0, | |
3156 | G3D_PLL_CON1, | |
3157 | G3D_PLL_FREQ_DET, | |
3158 | MUX_SEL_G3D, | |
3159 | MUX_ENABLE_G3D, | |
3160 | MUX_STAT_G3D, | |
3161 | DIV_G3D, | |
3162 | DIV_G3D_PLL_FREQ_DET, | |
3163 | DIV_STAT_G3D, | |
3164 | DIV_STAT_G3D_PLL_FREQ_DET, | |
3165 | ENABLE_ACLK_G3D, | |
3166 | ENABLE_PCLK_G3D, | |
3167 | ENABLE_SCLK_G3D, | |
3168 | ENABLE_IP_G3D0, | |
3169 | ENABLE_IP_G3D1, | |
3170 | CLKOUT_CMU_G3D, | |
3171 | CLKOUT_CMU_G3D_DIV_STAT, | |
3172 | CLK_STOPCTRL, | |
3173 | }; | |
3174 | ||
3175 | /* list of all parent clock list */ | |
3176 | PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", }; | |
3177 | PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", }; | |
3178 | ||
3179 | static struct samsung_pll_clock g3d_pll_clks[] __initdata = { | |
3180 | PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", | |
3181 | G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates), | |
3182 | }; | |
3183 | ||
3184 | static struct samsung_mux_clock g3d_mux_clks[] __initdata = { | |
3185 | /* MUX_SEL_G3D */ | |
3186 | MUX(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p, | |
3187 | MUX_SEL_G3D, 8, 1), | |
3188 | MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, | |
3189 | MUX_SEL_G3D, 0, 1), | |
3190 | }; | |
3191 | ||
3192 | static struct samsung_div_clock g3d_div_clks[] __initdata = { | |
3193 | /* DIV_G3D */ | |
3194 | DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D, | |
3195 | 8, 2), | |
3196 | DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D, | |
3197 | 4, 3), | |
3198 | DIV(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D, | |
3199 | 0, 3), | |
3200 | }; | |
3201 | ||
3202 | static struct samsung_gate_clock g3d_gate_clks[] __initdata = { | |
3203 | /* ENABLE_ACLK_G3D */ | |
3204 | GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d", | |
3205 | ENABLE_ACLK_G3D, 7, 0, 0), | |
3206 | GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d", | |
3207 | ENABLE_ACLK_G3D, 6, 0, 0), | |
3208 | GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d", | |
3209 | ENABLE_ACLK_G3D, 5, 0, 0), | |
3210 | GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d", | |
3211 | ENABLE_ACLK_G3D, 4, 0, 0), | |
3212 | GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d", | |
3213 | ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0), | |
3214 | GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d", | |
3215 | ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0), | |
3216 | GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d", | |
3217 | ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0), | |
3218 | GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d", | |
3219 | ENABLE_ACLK_G3D, 0, 0, 0), | |
3220 | ||
3221 | /* ENABLE_PCLK_G3D */ | |
3222 | GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d", | |
3223 | ENABLE_PCLK_G3D, 3, 0, 0), | |
3224 | GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d", | |
3225 | ENABLE_PCLK_G3D, 2, 0, 0), | |
3226 | GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d", | |
3227 | ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0), | |
3228 | GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d", | |
3229 | ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0), | |
3230 | ||
3231 | /* ENABLE_SCLK_G3D */ | |
3232 | GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d", | |
3233 | ENABLE_SCLK_G3D, 0, 0, 0), | |
3234 | }; | |
3235 | ||
3236 | static struct samsung_cmu_info g3d_cmu_info __initdata = { | |
3237 | .pll_clks = g3d_pll_clks, | |
3238 | .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), | |
3239 | .mux_clks = g3d_mux_clks, | |
3240 | .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks), | |
3241 | .div_clks = g3d_div_clks, | |
3242 | .nr_div_clks = ARRAY_SIZE(g3d_div_clks), | |
3243 | .gate_clks = g3d_gate_clks, | |
3244 | .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), | |
3245 | .nr_clk_ids = G3D_NR_CLK, | |
3246 | .clk_regs = g3d_clk_regs, | |
3247 | .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), | |
3248 | }; | |
3249 | ||
3250 | static void __init exynos5433_cmu_g3d_init(struct device_node *np) | |
3251 | { | |
3252 | samsung_cmu_register_one(np, &g3d_cmu_info); | |
3253 | } | |
3254 | CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d", | |
3255 | exynos5433_cmu_g3d_init); | |
2a2f33e8 CC |
3256 | |
3257 | /* | |
3258 | * Register offset definitions for CMU_GSCL | |
3259 | */ | |
3260 | #define MUX_SEL_GSCL 0x0200 | |
3261 | #define MUX_ENABLE_GSCL 0x0300 | |
3262 | #define MUX_STAT_GSCL 0x0400 | |
3263 | #define ENABLE_ACLK_GSCL 0x0800 | |
3264 | #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804 | |
3265 | #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808 | |
3266 | #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c | |
3267 | #define ENABLE_PCLK_GSCL 0x0900 | |
3268 | #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904 | |
3269 | #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908 | |
3270 | #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c | |
3271 | #define ENABLE_IP_GSCL0 0x0b00 | |
3272 | #define ENABLE_IP_GSCL1 0x0b04 | |
3273 | #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08 | |
3274 | #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c | |
3275 | #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10 | |
3276 | ||
3277 | static unsigned long gscl_clk_regs[] __initdata = { | |
3278 | MUX_SEL_GSCL, | |
3279 | MUX_ENABLE_GSCL, | |
3280 | MUX_STAT_GSCL, | |
3281 | ENABLE_ACLK_GSCL, | |
3282 | ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, | |
3283 | ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, | |
3284 | ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, | |
3285 | ENABLE_PCLK_GSCL, | |
3286 | ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, | |
3287 | ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, | |
3288 | ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, | |
3289 | ENABLE_IP_GSCL0, | |
3290 | ENABLE_IP_GSCL1, | |
3291 | ENABLE_IP_GSCL_SECURE_SMMU_GSCL0, | |
3292 | ENABLE_IP_GSCL_SECURE_SMMU_GSCL1, | |
3293 | ENABLE_IP_GSCL_SECURE_SMMU_GSCL2, | |
3294 | }; | |
3295 | ||
3296 | /* list of all parent clock list */ | |
3297 | PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", }; | |
3298 | PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", }; | |
3299 | ||
3300 | static struct samsung_mux_clock gscl_mux_clks[] __initdata = { | |
3301 | /* MUX_SEL_GSCL */ | |
3302 | MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user", | |
3303 | aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1), | |
3304 | MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user", | |
3305 | aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1), | |
3306 | }; | |
3307 | ||
3308 | static struct samsung_gate_clock gscl_gate_clks[] __initdata = { | |
3309 | /* ENABLE_ACLK_GSCL */ | |
3310 | GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user", | |
3311 | ENABLE_ACLK_GSCL, 11, 0, 0), | |
3312 | GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user", | |
3313 | ENABLE_ACLK_GSCL, 10, 0, 0), | |
3314 | GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user", | |
3315 | ENABLE_ACLK_GSCL, 9, 0, 0), | |
3316 | GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp", | |
3317 | "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL, | |
3318 | 8, CLK_IGNORE_UNUSED, 0), | |
3319 | GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user", | |
3320 | ENABLE_ACLK_GSCL, 7, 0, 0), | |
3321 | GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user", | |
3322 | ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0), | |
3323 | GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333", | |
3324 | "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 0, 0), | |
3325 | GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333", | |
3326 | "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 0, 0), | |
3327 | GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user", | |
3328 | ENABLE_ACLK_GSCL, 3, 0, 0), | |
3329 | GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user", | |
3330 | ENABLE_ACLK_GSCL, 2, 0, 0), | |
3331 | GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user", | |
3332 | ENABLE_ACLK_GSCL, 1, 0, 0), | |
3333 | GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user", | |
3334 | ENABLE_ACLK_GSCL, 0, 0, 0), | |
3335 | ||
3336 | /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */ | |
3337 | GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user", | |
3338 | ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), | |
3339 | ||
3340 | /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */ | |
3341 | GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user", | |
3342 | ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0), | |
3343 | ||
3344 | /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */ | |
3345 | GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user", | |
3346 | ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), | |
3347 | ||
3348 | /* ENABLE_PCLK_GSCL */ | |
3349 | GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user", | |
3350 | ENABLE_PCLK_GSCL, 7, 0, 0), | |
3351 | GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user", | |
3352 | ENABLE_PCLK_GSCL, 6, 0, 0), | |
3353 | GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user", | |
3354 | ENABLE_PCLK_GSCL, 5, 0, 0), | |
3355 | GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user", | |
3356 | ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0), | |
3357 | GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl", | |
3358 | "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL, | |
3359 | 3, CLK_IGNORE_UNUSED, 0), | |
3360 | GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user", | |
3361 | ENABLE_PCLK_GSCL, 2, 0, 0), | |
3362 | GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user", | |
3363 | ENABLE_PCLK_GSCL, 1, 0, 0), | |
3364 | GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user", | |
3365 | ENABLE_PCLK_GSCL, 0, 0, 0), | |
3366 | ||
3367 | /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */ | |
3368 | GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user", | |
3369 | ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), | |
3370 | ||
3371 | /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */ | |
3372 | GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user", | |
3373 | ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), | |
3374 | ||
3375 | /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */ | |
3376 | GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user", | |
3377 | ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), | |
3378 | }; | |
3379 | ||
3380 | static struct samsung_cmu_info gscl_cmu_info __initdata = { | |
3381 | .mux_clks = gscl_mux_clks, | |
3382 | .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks), | |
3383 | .gate_clks = gscl_gate_clks, | |
3384 | .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks), | |
3385 | .nr_clk_ids = GSCL_NR_CLK, | |
3386 | .clk_regs = gscl_clk_regs, | |
3387 | .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs), | |
3388 | }; | |
3389 | ||
3390 | static void __init exynos5433_cmu_gscl_init(struct device_node *np) | |
3391 | { | |
3392 | samsung_cmu_register_one(np, &gscl_cmu_info); | |
3393 | } | |
3394 | CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl", | |
3395 | exynos5433_cmu_gscl_init); | |
df40a13c CC |
3396 | |
3397 | /* | |
3398 | * Register offset definitions for CMU_APOLLO | |
3399 | */ | |
3400 | #define APOLLO_PLL_LOCK 0x0000 | |
3401 | #define APOLLO_PLL_CON0 0x0100 | |
3402 | #define APOLLO_PLL_CON1 0x0104 | |
3403 | #define APOLLO_PLL_FREQ_DET 0x010c | |
3404 | #define MUX_SEL_APOLLO0 0x0200 | |
3405 | #define MUX_SEL_APOLLO1 0x0204 | |
3406 | #define MUX_SEL_APOLLO2 0x0208 | |
3407 | #define MUX_ENABLE_APOLLO0 0x0300 | |
3408 | #define MUX_ENABLE_APOLLO1 0x0304 | |
3409 | #define MUX_ENABLE_APOLLO2 0x0308 | |
3410 | #define MUX_STAT_APOLLO0 0x0400 | |
3411 | #define MUX_STAT_APOLLO1 0x0404 | |
3412 | #define MUX_STAT_APOLLO2 0x0408 | |
3413 | #define DIV_APOLLO0 0x0600 | |
3414 | #define DIV_APOLLO1 0x0604 | |
3415 | #define DIV_APOLLO_PLL_FREQ_DET 0x0608 | |
3416 | #define DIV_STAT_APOLLO0 0x0700 | |
3417 | #define DIV_STAT_APOLLO1 0x0704 | |
3418 | #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708 | |
3419 | #define ENABLE_ACLK_APOLLO 0x0800 | |
3420 | #define ENABLE_PCLK_APOLLO 0x0900 | |
3421 | #define ENABLE_SCLK_APOLLO 0x0a00 | |
3422 | #define ENABLE_IP_APOLLO0 0x0b00 | |
3423 | #define ENABLE_IP_APOLLO1 0x0b04 | |
3424 | #define CLKOUT_CMU_APOLLO 0x0c00 | |
3425 | #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04 | |
3426 | #define ARMCLK_STOPCTRL 0x1000 | |
3427 | #define APOLLO_PWR_CTRL 0x1020 | |
3428 | #define APOLLO_PWR_CTRL2 0x1024 | |
3429 | #define APOLLO_INTR_SPREAD_ENABLE 0x1080 | |
3430 | #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084 | |
3431 | #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088 | |
3432 | ||
3433 | static unsigned long apollo_clk_regs[] __initdata = { | |
3434 | APOLLO_PLL_LOCK, | |
3435 | APOLLO_PLL_CON0, | |
3436 | APOLLO_PLL_CON1, | |
3437 | APOLLO_PLL_FREQ_DET, | |
3438 | MUX_SEL_APOLLO0, | |
3439 | MUX_SEL_APOLLO1, | |
3440 | MUX_SEL_APOLLO2, | |
3441 | MUX_ENABLE_APOLLO0, | |
3442 | MUX_ENABLE_APOLLO1, | |
3443 | MUX_ENABLE_APOLLO2, | |
3444 | MUX_STAT_APOLLO0, | |
3445 | MUX_STAT_APOLLO1, | |
3446 | MUX_STAT_APOLLO2, | |
3447 | DIV_APOLLO0, | |
3448 | DIV_APOLLO1, | |
3449 | DIV_APOLLO_PLL_FREQ_DET, | |
3450 | DIV_STAT_APOLLO0, | |
3451 | DIV_STAT_APOLLO1, | |
3452 | DIV_STAT_APOLLO_PLL_FREQ_DET, | |
3453 | ENABLE_ACLK_APOLLO, | |
3454 | ENABLE_PCLK_APOLLO, | |
3455 | ENABLE_SCLK_APOLLO, | |
3456 | ENABLE_IP_APOLLO0, | |
3457 | ENABLE_IP_APOLLO1, | |
3458 | CLKOUT_CMU_APOLLO, | |
3459 | CLKOUT_CMU_APOLLO_DIV_STAT, | |
3460 | ARMCLK_STOPCTRL, | |
3461 | APOLLO_PWR_CTRL, | |
3462 | APOLLO_PWR_CTRL2, | |
3463 | APOLLO_INTR_SPREAD_ENABLE, | |
3464 | APOLLO_INTR_SPREAD_USE_STANDBYWFI, | |
3465 | APOLLO_INTR_SPREAD_BLOCKING_DURATION, | |
3466 | }; | |
3467 | ||
3468 | /* list of all parent clock list */ | |
3469 | PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", }; | |
3470 | PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", }; | |
3471 | PNAME(mout_apollo_p) = { "mout_apollo_pll", | |
3472 | "mout_bus_pll_apollo_user", }; | |
3473 | ||
3474 | static struct samsung_pll_clock apollo_pll_clks[] __initdata = { | |
3475 | PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk", | |
3476 | APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates), | |
3477 | }; | |
3478 | ||
3479 | static struct samsung_mux_clock apollo_mux_clks[] __initdata = { | |
3480 | /* MUX_SEL_APOLLO0 */ | |
3481 | MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p, | |
3482 | MUX_SEL_APOLLO0, 0, 1, 0, CLK_MUX_READ_ONLY), | |
3483 | ||
3484 | /* MUX_SEL_APOLLO1 */ | |
3485 | MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user", | |
3486 | mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1), | |
3487 | ||
3488 | /* MUX_SEL_APOLLO2 */ | |
3489 | MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2, | |
3490 | 0, 1, 0, CLK_MUX_READ_ONLY), | |
3491 | }; | |
3492 | ||
3493 | static struct samsung_div_clock apollo_div_clks[] __initdata = { | |
3494 | /* DIV_APOLLO0 */ | |
3495 | DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2", | |
3496 | DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE, | |
3497 | CLK_DIVIDER_READ_ONLY), | |
3498 | DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2", | |
3499 | DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE, | |
3500 | CLK_DIVIDER_READ_ONLY), | |
3501 | DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2", | |
3502 | DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE, | |
3503 | CLK_DIVIDER_READ_ONLY), | |
3504 | DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2", | |
3505 | DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE, | |
3506 | CLK_DIVIDER_READ_ONLY), | |
3507 | DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2", | |
3508 | DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE, | |
3509 | CLK_DIVIDER_READ_ONLY), | |
3510 | DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1", | |
3511 | DIV_APOLLO0, 4, 3, CLK_GET_RATE_NOCACHE, | |
3512 | CLK_DIVIDER_READ_ONLY), | |
3513 | DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo", | |
3514 | DIV_APOLLO0, 0, 3, CLK_GET_RATE_NOCACHE, | |
3515 | CLK_DIVIDER_READ_ONLY), | |
3516 | ||
3517 | /* DIV_APOLLO1 */ | |
3518 | DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo", | |
3519 | DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE, | |
3520 | CLK_DIVIDER_READ_ONLY), | |
3521 | DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo", | |
3522 | DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE, | |
3523 | CLK_DIVIDER_READ_ONLY), | |
3524 | }; | |
3525 | ||
3526 | static struct samsung_gate_clock apollo_gate_clks[] __initdata = { | |
3527 | /* ENABLE_ACLK_APOLLO */ | |
3528 | GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys", | |
3529 | "div_atclk_apollo", ENABLE_ACLK_APOLLO, | |
3530 | 6, CLK_IGNORE_UNUSED, 0), | |
3531 | GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys", | |
3532 | "div_atclk_apollo", ENABLE_ACLK_APOLLO, | |
3533 | 5, CLK_IGNORE_UNUSED, 0), | |
3534 | GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys", | |
3535 | "div_atclk_apollo", ENABLE_ACLK_APOLLO, | |
3536 | 4, CLK_IGNORE_UNUSED, 0), | |
3537 | GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys", | |
3538 | "div_atclk_apollo", ENABLE_ACLK_APOLLO, | |
3539 | 3, CLK_IGNORE_UNUSED, 0), | |
3540 | GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci", | |
3541 | "div_aclk_apollo", ENABLE_ACLK_APOLLO, | |
3542 | 2, CLK_IGNORE_UNUSED, 0), | |
3543 | GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop", | |
3544 | "div_pclk_apollo", ENABLE_ACLK_APOLLO, | |
3545 | 1, CLK_IGNORE_UNUSED, 0), | |
3546 | GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200", | |
3547 | "div_pclk_apollo", ENABLE_ACLK_APOLLO, | |
3548 | 0, CLK_IGNORE_UNUSED, 0), | |
3549 | ||
3550 | /* ENABLE_PCLK_APOLLO */ | |
3551 | GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo", | |
3552 | "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO, | |
3553 | 2, CLK_IGNORE_UNUSED, 0), | |
3554 | GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo", | |
3555 | ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), | |
3556 | GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo", | |
3557 | "div_pclk_apollo", ENABLE_PCLK_APOLLO, | |
3558 | 0, CLK_IGNORE_UNUSED, 0), | |
3559 | ||
3560 | /* ENABLE_SCLK_APOLLO */ | |
3561 | GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo", | |
3562 | ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0), | |
3563 | GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", | |
3564 | ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), | |
3565 | GATE(CLK_SCLK_APOLLO, "sclk_apollo", "div_apollo_pll", | |
3566 | ENABLE_SCLK_APOLLO, 0, CLK_IGNORE_UNUSED, 0), | |
3567 | }; | |
3568 | ||
3569 | static struct samsung_cmu_info apollo_cmu_info __initdata = { | |
3570 | .pll_clks = apollo_pll_clks, | |
3571 | .nr_pll_clks = ARRAY_SIZE(apollo_pll_clks), | |
3572 | .mux_clks = apollo_mux_clks, | |
3573 | .nr_mux_clks = ARRAY_SIZE(apollo_mux_clks), | |
3574 | .div_clks = apollo_div_clks, | |
3575 | .nr_div_clks = ARRAY_SIZE(apollo_div_clks), | |
3576 | .gate_clks = apollo_gate_clks, | |
3577 | .nr_gate_clks = ARRAY_SIZE(apollo_gate_clks), | |
3578 | .nr_clk_ids = APOLLO_NR_CLK, | |
3579 | .clk_regs = apollo_clk_regs, | |
3580 | .nr_clk_regs = ARRAY_SIZE(apollo_clk_regs), | |
3581 | }; | |
3582 | ||
3583 | static void __init exynos5433_cmu_apollo_init(struct device_node *np) | |
3584 | { | |
3585 | samsung_cmu_register_one(np, &apollo_cmu_info); | |
3586 | } | |
3587 | CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo", | |
3588 | exynos5433_cmu_apollo_init); |