[mirror_ubuntu-jammy-kernel.git] / drivers / clk / shmobile / r8a7795-cpg-mssr.c

/*
 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
 *
 * Copyright (C) 2015 Glider bvba
 *
 * Based on clk-rcar-gen3.c
 *
 * Copyright (C) 2015 Renesas Electronics Corp.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 */

#include <linux/bug.h>
#include <linux/clk-provider.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/slab.h>

#include <dt-bindings/clock/r8a7795-cpg-mssr.h>

#include "renesas-cpg-mssr.h"


enum clk_ids {
	/* Core Clock Outputs exported to DT */
	LAST_DT_CORE_CLK = R8A7795_CLK_OSC,

	/* External Input Clocks */
	CLK_EXTAL,
	CLK_EXTALR,

	/* Internal Core Clocks */
	CLK_MAIN,
	CLK_PLL0,
	CLK_PLL1,
	CLK_PLL2,
	CLK_PLL3,
	CLK_PLL4,
	CLK_PLL1_DIV2,
	CLK_PLL1_DIV4,
	CLK_S0,
	CLK_S1,
	CLK_S2,
	CLK_S3,
	CLK_SDSRC,
	CLK_SSPSRC,

	/* Module Clocks */
	MOD_CLK_BASE
};

enum r8a7795_clk_types {
	CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
	CLK_TYPE_GEN3_PLL0,
	CLK_TYPE_GEN3_PLL1,
	CLK_TYPE_GEN3_PLL2,
	CLK_TYPE_GEN3_PLL3,
	CLK_TYPE_GEN3_PLL4,
	CLK_TYPE_GEN3_SD,
};

static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
	/* External Clock Inputs */
	DEF_INPUT("extal",  CLK_EXTAL),
	DEF_INPUT("extalr", CLK_EXTALR),

	/* Internal Core Clocks */
	DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
	DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
	DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
	DEF_BASE(".pll2",       CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
	DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
	DEF_BASE(".pll4",       CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),

	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
	DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
	DEF_FIXED(".s0",        CLK_S0,            CLK_PLL1_DIV2,  2, 1),
	DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  3, 1),
	DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
	DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),

	/* Core Clock Outputs */
	DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
	DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
	DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
	DEF_FIXED("zx",         R8A7795_CLK_ZX,    CLK_PLL1_DIV2,  2, 1),
	DEF_FIXED("s0d1",       R8A7795_CLK_S0D1,  CLK_S0,         1, 1),
	DEF_FIXED("s0d4",       R8A7795_CLK_S0D4,  CLK_S0,         4, 1),
	DEF_FIXED("s1d1",       R8A7795_CLK_S1D1,  CLK_S1,         1, 1),
	DEF_FIXED("s1d2",       R8A7795_CLK_S1D2,  CLK_S1,         2, 1),
	DEF_FIXED("s1d4",       R8A7795_CLK_S1D4,  CLK_S1,         4, 1),
	DEF_FIXED("s2d1",       R8A7795_CLK_S2D1,  CLK_S2,         1, 1),
	DEF_FIXED("s2d2",       R8A7795_CLK_S2D2,  CLK_S2,         2, 1),
	DEF_FIXED("s2d4",       R8A7795_CLK_S2D4,  CLK_S2,         4, 1),
	DEF_FIXED("s3d1",       R8A7795_CLK_S3D1,  CLK_S3,         1, 1),
	DEF_FIXED("s3d2",       R8A7795_CLK_S3D2,  CLK_S3,         2, 1),
	DEF_FIXED("s3d4",       R8A7795_CLK_S3D4,  CLK_S3,         4, 1),

	DEF_SD("sd0",           R8A7795_CLK_SD0,   CLK_PLL1_DIV2, 0x0074),
	DEF_SD("sd1",           R8A7795_CLK_SD1,   CLK_PLL1_DIV2, 0x0078),
	DEF_SD("sd2",           R8A7795_CLK_SD2,   CLK_PLL1_DIV2, 0x0268),
	DEF_SD("sd3",           R8A7795_CLK_SD3,   CLK_PLL1_DIV2, 0x026c),

	DEF_FIXED("cl",         R8A7795_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
	DEF_FIXED("cp",         R8A7795_CLK_CP,    CLK_EXTAL,      2, 1),

	DEF_DIV6P1("mso",       R8A7795_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
	DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV2, 0x250),
};

static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
	DEF_MOD("scif5",		 202,	R8A7795_CLK_S3D4),
	DEF_MOD("scif4",		 203,	R8A7795_CLK_S3D4),
	DEF_MOD("scif3",		 204,	R8A7795_CLK_S3D4),
	DEF_MOD("scif1",		 206,	R8A7795_CLK_S3D4),
	DEF_MOD("scif0",		 207,	R8A7795_CLK_S3D4),
	DEF_MOD("msiof3",		 208,	R8A7795_CLK_MSO),
	DEF_MOD("msiof2",		 209,	R8A7795_CLK_MSO),
	DEF_MOD("msiof1",		 210,	R8A7795_CLK_MSO),
	DEF_MOD("msiof0",		 211,	R8A7795_CLK_MSO),
	DEF_MOD("sys-dmac2",		 217,	R8A7795_CLK_S3D1),
	DEF_MOD("sys-dmac1",		 218,	R8A7795_CLK_S3D1),
	DEF_MOD("sys-dmac0",		 219,	R8A7795_CLK_S3D1),
	DEF_MOD("scif2",		 310,	R8A7795_CLK_S3D4),
	DEF_MOD("sdif3",		 311,	R8A7795_CLK_SD3),
	DEF_MOD("sdif2",		 312,	R8A7795_CLK_SD2),
	DEF_MOD("sdif1",		 313,	R8A7795_CLK_SD1),
	DEF_MOD("sdif0",		 314,	R8A7795_CLK_SD0),
	DEF_MOD("pcie1",		 318,	R8A7795_CLK_S3D1),
	DEF_MOD("pcie0",		 319,	R8A7795_CLK_S3D1),
	DEF_MOD("usb3-if1",		 327,	R8A7795_CLK_S3D1),
	DEF_MOD("usb3-if0",		 328,	R8A7795_CLK_S3D1),
	DEF_MOD("usb-dmac0",		 330,	R8A7795_CLK_S3D1),
	DEF_MOD("usb-dmac1",		 331,	R8A7795_CLK_S3D1),
	DEF_MOD("intc-ap",		 408,	R8A7795_CLK_S3D1),
	DEF_MOD("audmac0",		 502,	R8A7795_CLK_S3D4),
	DEF_MOD("audmac1",		 501,	R8A7795_CLK_S3D4),
	DEF_MOD("hscif4",		 516,	R8A7795_CLK_S3D1),
	DEF_MOD("hscif3",		 517,	R8A7795_CLK_S3D1),
	DEF_MOD("hscif2",		 518,	R8A7795_CLK_S3D1),
	DEF_MOD("hscif1",		 519,	R8A7795_CLK_S3D1),
	DEF_MOD("hscif0",		 520,	R8A7795_CLK_S3D1),
	DEF_MOD("vspd3",		 620,	R8A7795_CLK_S2D1),
	DEF_MOD("vspd2",		 621,	R8A7795_CLK_S2D1),
	DEF_MOD("vspd1",		 622,	R8A7795_CLK_S2D1),
	DEF_MOD("vspd0",		 623,	R8A7795_CLK_S2D1),
	DEF_MOD("vspbc",		 624,	R8A7795_CLK_S2D1),
	DEF_MOD("vspbd",		 626,	R8A7795_CLK_S2D1),
	DEF_MOD("vspi2",		 629,	R8A7795_CLK_S2D1),
	DEF_MOD("vspi1",		 630,	R8A7795_CLK_S2D1),
	DEF_MOD("vspi0",		 631,	R8A7795_CLK_S2D1),
	DEF_MOD("ehci2",		 701,	R8A7795_CLK_S3D4),
	DEF_MOD("ehci1",		 702,	R8A7795_CLK_S3D4),
	DEF_MOD("ehci0",		 703,	R8A7795_CLK_S3D4),
	DEF_MOD("hsusb",		 704,	R8A7795_CLK_S3D4),
	DEF_MOD("du3",			 721,	R8A7795_CLK_S2D1),
	DEF_MOD("du2",			 722,	R8A7795_CLK_S2D1),
	DEF_MOD("du1",			 723,	R8A7795_CLK_S2D1),
	DEF_MOD("du0",			 724,	R8A7795_CLK_S2D1),
	DEF_MOD("hdmi1",		 728,	R8A7795_CLK_HDMI),
	DEF_MOD("hdmi0",		 729,	R8A7795_CLK_HDMI),
	DEF_MOD("etheravb",		 812,	R8A7795_CLK_S3D2),
	DEF_MOD("sata0",		 815,	R8A7795_CLK_S3D2),
	DEF_MOD("gpio7",		 905,	R8A7795_CLK_CP),
	DEF_MOD("gpio6",		 906,	R8A7795_CLK_CP),
	DEF_MOD("gpio5",		 907,	R8A7795_CLK_CP),
	DEF_MOD("gpio4",		 908,	R8A7795_CLK_CP),
	DEF_MOD("gpio3",		 909,	R8A7795_CLK_CP),
	DEF_MOD("gpio2",		 910,	R8A7795_CLK_CP),
	DEF_MOD("gpio1",		 911,	R8A7795_CLK_CP),
	DEF_MOD("gpio0",		 912,	R8A7795_CLK_CP),
	DEF_MOD("i2c6",			 918,	R8A7795_CLK_S3D2),
	DEF_MOD("i2c5",			 919,	R8A7795_CLK_S3D2),
	DEF_MOD("i2c4",			 927,	R8A7795_CLK_S3D2),
	DEF_MOD("i2c3",			 928,	R8A7795_CLK_S3D2),
	DEF_MOD("i2c2",			 929,	R8A7795_CLK_S3D2),
	DEF_MOD("i2c1",			 930,	R8A7795_CLK_S3D2),
	DEF_MOD("i2c0",			 931,	R8A7795_CLK_S3D2),
	DEF_MOD("ssi-all",		1005,	R8A7795_CLK_S3D4),
	DEF_MOD("ssi9",			1006,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi8",			1007,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi7",			1008,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi6",			1009,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi5",			1010,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi4",			1011,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi3",			1012,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi2",			1013,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi1",			1014,	MOD_CLK_ID(1005)),
	DEF_MOD("ssi0",			1015,	MOD_CLK_ID(1005)),
	DEF_MOD("scu-all",		1017,	R8A7795_CLK_S3D4),
	DEF_MOD("scu-dvc1",		1018,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-dvc0",		1019,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-ctu1-mix1",	1020,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-ctu0-mix0",	1021,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src9",		1022,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src8",		1023,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src7",		1024,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src6",		1025,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src5",		1026,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src4",		1027,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src3",		1028,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src2",		1029,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src1",		1030,	MOD_CLK_ID(1017)),
	DEF_MOD("scu-src0",		1031,	MOD_CLK_ID(1017)),
};

static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
};

/* -----------------------------------------------------------------------------
 * SDn Clock
 *
 */
#define CPG_SD_STP_HCK		BIT(9)
#define CPG_SD_STP_CK		BIT(8)

#define CPG_SD_STP_MASK		(CPG_SD_STP_HCK | CPG_SD_STP_CK)
#define CPG_SD_FC_MASK		(0x7 << 2 | 0x3 << 0)

#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
{ \
	.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
	       ((stp_ck) ? CPG_SD_STP_CK : 0) | \
	       ((sd_srcfc) << 2) | \
	       ((sd_fc) << 0), \
	.div = (sd_div), \
}

struct sd_div_table {
	u32 val;
	unsigned int div;
};

struct sd_clock {
	struct clk_hw hw;
	void __iomem *reg;
	const struct sd_div_table *div_table;
	unsigned int div_num;
	unsigned int div_min;
	unsigned int div_max;
};

/* SDn divider
 *                     sd_srcfc   sd_fc   div
 * stp_hck   stp_ck    (div)      (div)     = sd_srcfc x sd_fc
 *-------------------------------------------------------------------
 *  0         0         0 (1)      1 (4)      4
 *  0         0         1 (2)      1 (4)      8
 *  1         0         2 (4)      1 (4)     16
 *  1         0         3 (8)      1 (4)     32
 *  1         0         4 (16)     1 (4)     64
 *  0         0         0 (1)      0 (2)      2
 *  0         0         1 (2)      0 (2)      4
 *  1         0         2 (4)      0 (2)      8
 *  1         0         3 (8)      0 (2)     16
 *  1         0         4 (16)     0 (2)     32
 */
static const struct sd_div_table cpg_sd_div_table[] = {
/*	CPG_SD_DIV_TABLE_DATA(stp_hck,  stp_ck,   sd_srcfc,   sd_fc,  sd_div) */
	CPG_SD_DIV_TABLE_DATA(0,        0,        0,          1,        4),
	CPG_SD_DIV_TABLE_DATA(0,        0,        1,          1,        8),
	CPG_SD_DIV_TABLE_DATA(1,        0,        2,          1,       16),
	CPG_SD_DIV_TABLE_DATA(1,        0,        3,          1,       32),
	CPG_SD_DIV_TABLE_DATA(1,        0,        4,          1,       64),
	CPG_SD_DIV_TABLE_DATA(0,        0,        0,          0,        2),
	CPG_SD_DIV_TABLE_DATA(0,        0,        1,          0,        4),
	CPG_SD_DIV_TABLE_DATA(1,        0,        2,          0,        8),
	CPG_SD_DIV_TABLE_DATA(1,        0,        3,          0,       16),
	CPG_SD_DIV_TABLE_DATA(1,        0,        4,          0,       32),
};

#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)

static int cpg_sd_clock_enable(struct clk_hw *hw)
{
	struct sd_clock *clock = to_sd_clock(hw);
	u32 val, sd_fc;
	unsigned int i;

	val = clk_readl(clock->reg);

	sd_fc = val & CPG_SD_FC_MASK;
	for (i = 0; i < clock->div_num; i++)
		if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
			break;

	if (i >= clock->div_num)
		return -EINVAL;

	val &= ~(CPG_SD_STP_MASK);
	val |= clock->div_table[i].val & CPG_SD_STP_MASK;

	clk_writel(val, clock->reg);

	return 0;
}

static void cpg_sd_clock_disable(struct clk_hw *hw)
{
	struct sd_clock *clock = to_sd_clock(hw);

	clk_writel(clk_readl(clock->reg) | CPG_SD_STP_MASK, clock->reg);
}

static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
{
	struct sd_clock *clock = to_sd_clock(hw);

	return !(clk_readl(clock->reg) & CPG_SD_STP_MASK);
}

static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
						unsigned long parent_rate)
{
	struct sd_clock *clock = to_sd_clock(hw);
	unsigned long rate = parent_rate;
	u32 val, sd_fc;
	unsigned int i;

	val = clk_readl(clock->reg);

	sd_fc = val & CPG_SD_FC_MASK;
	for (i = 0; i < clock->div_num; i++)
		if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
			break;

	if (i >= clock->div_num)
		return -EINVAL;

	return DIV_ROUND_CLOSEST(rate, clock->div_table[i].div);
}

static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
					  unsigned long rate,
					  unsigned long parent_rate)
{
	unsigned int div;

	if (!rate)
		rate = 1;

	div = DIV_ROUND_CLOSEST(parent_rate, rate);

	return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
}

static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
				      unsigned long *parent_rate)
{
	struct sd_clock *clock = to_sd_clock(hw);
	unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);

	return DIV_ROUND_CLOSEST(*parent_rate, div);
}

static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
				   unsigned long parent_rate)
{
	struct sd_clock *clock = to_sd_clock(hw);
	unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
	u32 val;
	unsigned int i;

	for (i = 0; i < clock->div_num; i++)
		if (div == clock->div_table[i].div)
			break;

	if (i >= clock->div_num)
		return -EINVAL;

	val = clk_readl(clock->reg);
	val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
	val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
	clk_writel(val, clock->reg);

	return 0;
}

static const struct clk_ops cpg_sd_clock_ops = {
	.enable = cpg_sd_clock_enable,
	.disable = cpg_sd_clock_disable,
	.is_enabled = cpg_sd_clock_is_enabled,
	.recalc_rate = cpg_sd_clock_recalc_rate,
	.round_rate = cpg_sd_clock_round_rate,
	.set_rate = cpg_sd_clock_set_rate,
};

static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
					       void __iomem *base,
					       const char *parent_name)
{
	struct clk_init_data init;
	struct sd_clock *clock;
	struct clk *clk;
	unsigned int i;

	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
	if (!clock)
		return ERR_PTR(-ENOMEM);

	init.name = core->name;
	init.ops = &cpg_sd_clock_ops;
	init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
	init.parent_names = &parent_name;
	init.num_parents = 1;

	clock->reg = base + core->offset;
	clock->hw.init = &init;
	clock->div_table = cpg_sd_div_table;
	clock->div_num = ARRAY_SIZE(cpg_sd_div_table);

	clock->div_max = clock->div_table[0].div;
	clock->div_min = clock->div_max;
	for (i = 1; i < clock->div_num; i++) {
		clock->div_max = max(clock->div_max, clock->div_table[i].div);
		clock->div_min = min(clock->div_min, clock->div_table[i].div);
	}

	clk = clk_register(NULL, &clock->hw);
	if (IS_ERR(clk))
		kfree(clock);

	return clk;
}

#define CPG_PLL0CR	0x00d8
#define CPG_PLL2CR	0x002c
#define CPG_PLL4CR	0x01f4

/*
 * CPG Clock Data
 */

/*
 *   MD		EXTAL		PLL0	PLL1	PLL2	PLL3	PLL4
 * 14 13 19 17	(MHz)
 *-------------------------------------------------------------------
 * 0  0  0  0	16.66 x 1	x180	x192	x144	x192	x144
 * 0  0  0  1	16.66 x 1	x180	x192	x144	x128	x144
 * 0  0  1  0	Prohibited setting
 * 0  0  1  1	16.66 x 1	x180	x192	x144	x192	x144
 * 0  1  0  0	20    x 1	x150	x160	x120	x160	x120
 * 0  1  0  1	20    x 1	x150	x160	x120	x106	x120
 * 0  1  1  0	Prohibited setting
 * 0  1  1  1	20    x 1	x150	x160	x120	x160	x120
 * 1  0  0  0	25    x 1	x120	x128	x96	x128	x96
 * 1  0  0  1	25    x 1	x120	x128	x96	x84	x96
 * 1  0  1  0	Prohibited setting
 * 1  0  1  1	25    x 1	x120	x128	x96	x128	x96
 * 1  1  0  0	33.33 / 2	x180	x192	x144	x192	x144
 * 1  1  0  1	33.33 / 2	x180	x192	x144	x128	x144
 * 1  1  1  0	Prohibited setting
 * 1  1  1  1	33.33 / 2	x180	x192	x144	x192	x144
 */
#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 11) | \
					 (((md) & BIT(13)) >> 11) | \
					 (((md) & BIT(19)) >> 18) | \
					 (((md) & BIT(17)) >> 17))

struct cpg_pll_config {
	unsigned int extal_div;
	unsigned int pll1_mult;
	unsigned int pll3_mult;
};

static const struct cpg_pll_config cpg_pll_configs[16] __initconst = {
	/* EXTAL div	PLL1 mult	PLL3 mult */
	{ 1,		192,		192,	},
	{ 1,		192,		128,	},
	{ 0, /* Prohibited setting */		},
	{ 1,		192,		192,	},
	{ 1,		160,		160,	},
	{ 1,		160,		106,	},
	{ 0, /* Prohibited setting */		},
	{ 1,		160,		160,	},
	{ 1,		128,		128,	},
	{ 1,		128,		84,	},
	{ 0, /* Prohibited setting */		},
	{ 1,		128,		128,	},
	{ 2,		192,		192,	},
	{ 2,		192,		128,	},
	{ 0, /* Prohibited setting */		},
	{ 2,		192,		192,	},
};

static const struct cpg_pll_config *cpg_pll_config __initdata;

static
struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
					     const struct cpg_core_clk *core,
					     const struct cpg_mssr_info *info,
					     struct clk **clks,
					     void __iomem *base)
{
	const struct clk *parent;
	unsigned int mult = 1;
	unsigned int div = 1;
	u32 value;

	parent = clks[core->parent];
	if (IS_ERR(parent))
		return ERR_CAST(parent);

	switch (core->type) {
	case CLK_TYPE_GEN3_MAIN:
		div = cpg_pll_config->extal_div;
		break;

	case CLK_TYPE_GEN3_PLL0:
		/*
		 * PLL0 is a configurable multiplier clock. Register it as a
		 * fixed factor clock for now as there's no generic multiplier
		 * clock implementation and we currently have no need to change
		 * the multiplier value.
		 */
		value = readl(base + CPG_PLL0CR);
		mult = (((value >> 24) & 0x7f) + 1) * 2;
		break;

	case CLK_TYPE_GEN3_PLL1:
		mult = cpg_pll_config->pll1_mult;
		break;

	case CLK_TYPE_GEN3_PLL2:
		/*
		 * PLL2 is a configurable multiplier clock. Register it as a
		 * fixed factor clock for now as there's no generic multiplier
		 * clock implementation and we currently have no need to change
		 * the multiplier value.
		 */
		value = readl(base + CPG_PLL2CR);
		mult = (((value >> 24) & 0x7f) + 1) * 2;
		break;

	case CLK_TYPE_GEN3_PLL3:
		mult = cpg_pll_config->pll3_mult;
		break;

	case CLK_TYPE_GEN3_PLL4:
		/*
		 * PLL4 is a configurable multiplier clock. Register it as a
		 * fixed factor clock for now as there's no generic multiplier
		 * clock implementation and we currently have no need to change
		 * the multiplier value.
		 */
		value = readl(base + CPG_PLL4CR);
		mult = (((value >> 24) & 0x7f) + 1) * 2;
		break;

	case CLK_TYPE_GEN3_SD:
		return cpg_sd_clk_register(core, base, __clk_get_name(parent));

	default:
		return ERR_PTR(-EINVAL);
	}

	return clk_register_fixed_factor(NULL, core->name,
					 __clk_get_name(parent), 0, mult, div);
}

/*
 * Reset register definitions.
 */
#define MODEMR	0xe6160060

static u32 rcar_gen3_read_mode_pins(void)
{
	void __iomem *modemr = ioremap_nocache(MODEMR, 4);
	u32 mode;

	BUG_ON(!modemr);
	mode = ioread32(modemr);
	iounmap(modemr);

	return mode;
}

static int __init r8a7795_cpg_mssr_init(struct device *dev)
{
	u32 cpg_mode = rcar_gen3_read_mode_pins();

	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
	if (!cpg_pll_config->extal_div) {
		dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
		return -EINVAL;
	}

	return 0;
}

const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
	/* Core Clocks */
	.core_clks = r8a7795_core_clks,
	.num_core_clks = ARRAY_SIZE(r8a7795_core_clks),
	.last_dt_core_clk = LAST_DT_CORE_CLK,
	.num_total_core_clks = MOD_CLK_BASE,

	/* Module Clocks */
	.mod_clks = r8a7795_mod_clks,
	.num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks),
	.num_hw_mod_clks = 12 * 32,

	/* Critical Module Clocks */
	.crit_mod_clks = r8a7795_crit_mod_clks,
	.num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks),

	/* Callbacks */
	.init = r8a7795_cpg_mssr_init,
	.cpg_clk_register = r8a7795_cpg_clk_register,
};
Commit	Line	Data
c5dae0df GU	1	/*
	2	* r8a7795 Clock Pulse Generator / Module Standby and Software Reset
	3	*
	4	* Copyright (C) 2015 Glider bvba
	5	*
	6	* Based on clk-rcar-gen3.c
	7	*
	8	* Copyright (C) 2015 Renesas Electronics Corp.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*/
	14
	15	#include <linux/bug.h>
	16	#include <linux/clk-provider.h>
	17	#include <linux/device.h>
	18	#include <linux/err.h>
	19	#include <linux/init.h>
	20	#include <linux/io.h>
	21	#include <linux/kernel.h>
	22	#include <linux/of.h>
90c073e5	23	#include <linux/slab.h>
c5dae0df GU	24
	25	#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
	26
	27	#include "renesas-cpg-mssr.h"
	28
	29
	30	enum clk_ids {
	31	/* Core Clock Outputs exported to DT */
	32	LAST_DT_CORE_CLK = R8A7795_CLK_OSC,
	33
	34	/* External Input Clocks */
	35	CLK_EXTAL,
	36	CLK_EXTALR,
	37
	38	/* Internal Core Clocks */
	39	CLK_MAIN,
	40	CLK_PLL0,
	41	CLK_PLL1,
	42	CLK_PLL2,
	43	CLK_PLL3,
	44	CLK_PLL4,
	45	CLK_PLL1_DIV2,
	46	CLK_PLL1_DIV4,
	47	CLK_S0,
	48	CLK_S1,
	49	CLK_S2,
	50	CLK_S3,
	51	CLK_SDSRC,
	52	CLK_SSPSRC,
	53
	54	/* Module Clocks */
	55	MOD_CLK_BASE
	56	};
	57
	58	enum r8a7795_clk_types {
	59	CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
	60	CLK_TYPE_GEN3_PLL0,
	61	CLK_TYPE_GEN3_PLL1,
	62	CLK_TYPE_GEN3_PLL2,
	63	CLK_TYPE_GEN3_PLL3,
	64	CLK_TYPE_GEN3_PLL4,
90c073e5	65	CLK_TYPE_GEN3_SD,
c5dae0df GU	66	};
	67
	68	static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
	69	/* External Clock Inputs */
	70	DEF_INPUT("extal", CLK_EXTAL),
	71	DEF_INPUT("extalr", CLK_EXTALR),
	72
	73	/* Internal Core Clocks */
	74	DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
	75	DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
	76	DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
	77	DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
	78	DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
	79	DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
	80
	81	DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
	82	DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
	83	DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
	84	DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
	85	DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
	86	DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
	87
	88	/* Core Clock Outputs */
	89	DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
	90	DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
	91	DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
	92	DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
	93	DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
	94	DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
	95	DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
	96	DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
	97	DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
	98	DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
	99	DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
	100	DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
	101	DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
	102	DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
	103	DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
90c073e5 DB	104
	105	DEF_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074),
	106	DEF_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078),
	107	DEF_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268),
	108	DEF_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c),
	109
c5dae0df GU	110	DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
	111	DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
	112
	113	DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
	114	DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
	115	};
	116
	117	static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
	118	DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
	119	DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
	120	DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
	121	DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
	122	DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
	123	DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
	124	DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
	125	DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
	126	DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
	127	DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
	128	DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
	129	DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1),
	130	DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
90c073e5 DB	131	DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
	132	DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
	133	DEF_MOD("sdif1", 313, R8A7795_CLK_SD1),
	134	DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
c5dae0df GU	135	DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
c5dae0df GU	136	DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
b7c9b91d YS	137	DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1),
b7c9b91d YS	138	DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
7826c611 YS	139	DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
7826c611 YS	140	DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
c5dae0df GU	141	DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
	142	DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
	143	DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4),
	144	DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
	145	DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
	146	DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
	147	DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
	148	DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
	149	DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1),
	150	DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1),
	151	DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1),
	152	DEF_MOD("vspd0", 623, R8A7795_CLK_S2D1),
	153	DEF_MOD("vspbc", 624, R8A7795_CLK_S2D1),
	154	DEF_MOD("vspbd", 626, R8A7795_CLK_S2D1),
	155	DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1),
	156	DEF_MOD("vspi1", 630, R8A7795_CLK_S2D1),
	157	DEF_MOD("vspi0", 631, R8A7795_CLK_S2D1),
	158	DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
	159	DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
	160	DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
	161	DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
	162	DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
	163	DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
	164	DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
	165	DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
	166	DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
	167	DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
	168	DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2),
c1c5864d	169	DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
c5dae0df GU	170	DEF_MOD("gpio7", 905, R8A7795_CLK_CP),
	171	DEF_MOD("gpio6", 906, R8A7795_CLK_CP),
	172	DEF_MOD("gpio5", 907, R8A7795_CLK_CP),
	173	DEF_MOD("gpio4", 908, R8A7795_CLK_CP),
	174	DEF_MOD("gpio3", 909, R8A7795_CLK_CP),
	175	DEF_MOD("gpio2", 910, R8A7795_CLK_CP),
	176	DEF_MOD("gpio1", 911, R8A7795_CLK_CP),
	177	DEF_MOD("gpio0", 912, R8A7795_CLK_CP),
	178	DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2),
	179	DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2),
	180	DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2),
	181	DEF_MOD("i2c3", 928, R8A7795_CLK_S3D2),
	182	DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
	183	DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
	184	DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
	185	DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
	186	DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
	187	DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
	188	DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
	189	DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
	190	DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
	191	DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
	192	DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
	193	DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
	194	DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
	195	DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
	196	DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
	197	DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
	198	DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
	199	DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
	200	DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
	201	DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
	202	DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
	203	DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
	204	DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
	205	DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
	206	DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
	207	DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
	208	DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
	209	DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
	210	DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
	211	};
	212
	213	static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
	214	MOD_CLK_ID(408), /* INTC-AP (GIC) */
	215	};
	216
90c073e5 DB	217	/* -----------------------------------------------------------------------------
	218	* SDn Clock
	219	*
	220	*/
	221	#define CPG_SD_STP_HCK BIT(9)
	222	#define CPG_SD_STP_CK BIT(8)
	223
	224	#define CPG_SD_STP_MASK (CPG_SD_STP_HCK \| CPG_SD_STP_CK)
	225	#define CPG_SD_FC_MASK (0x7 << 2 \| 0x3 << 0)
	226
	227	#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
	228	{ \
	229	.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) \| \
	230	((stp_ck) ? CPG_SD_STP_CK : 0) \| \
	231	((sd_srcfc) << 2) \| \
	232	((sd_fc) << 0), \
	233	.div = (sd_div), \
	234	}
	235
	236	struct sd_div_table {
	237	u32 val;
	238	unsigned int div;
	239	};
	240
	241	struct sd_clock {
	242	struct clk_hw hw;
	243	void __iomem *reg;
	244	const struct sd_div_table *div_table;
	245	unsigned int div_num;
	246	unsigned int div_min;
	247	unsigned int div_max;
	248	};
	249
	250	/* SDn divider
	251	* sd_srcfc sd_fc div
	252	* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
	253	*-------------------------------------------------------------------
	254	* 0 0 0 (1) 1 (4) 4
	255	* 0 0 1 (2) 1 (4) 8
	256	* 1 0 2 (4) 1 (4) 16
	257	* 1 0 3 (8) 1 (4) 32
	258	* 1 0 4 (16) 1 (4) 64
	259	* 0 0 0 (1) 0 (2) 2
	260	* 0 0 1 (2) 0 (2) 4
	261	* 1 0 2 (4) 0 (2) 8
	262	* 1 0 3 (8) 0 (2) 16
	263	* 1 0 4 (16) 0 (2) 32
	264	*/
	265	static const struct sd_div_table cpg_sd_div_table[] = {
	266	/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
	267	CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
	268	CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
	269	CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
	270	CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
	271	CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
	272	CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
	273	CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
	274	CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
	275	CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
	276	CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
	277	};
	278
	279	#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
	280
281	static int cpg_sd_clock_enable(struct clk_hw *hw)
282	{
283	struct sd_clock *clock = to_sd_clock(hw);
284	u32 val, sd_fc;
285	unsigned int i;
286
287	val = clk_readl(clock->reg);
288
289	sd_fc = val & CPG_SD_FC_MASK;
290	for (i = 0; i < clock->div_num; i++)
291	if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
292	break;
293
294	if (i >= clock->div_num)
295	return -EINVAL;
296
297	val &= ~(CPG_SD_STP_MASK);
298	val \|= clock->div_table[i].val & CPG_SD_STP_MASK;
299
300	clk_writel(val, clock->reg);
301
302	return 0;
303	}
304
305	static void cpg_sd_clock_disable(struct clk_hw *hw)
306	{
307	struct sd_clock *clock = to_sd_clock(hw);
308
309	clk_writel(clk_readl(clock->reg) \| CPG_SD_STP_MASK, clock->reg);
310	}
311
312	static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
313	{
314	struct sd_clock *clock = to_sd_clock(hw);
315
316	return !(clk_readl(clock->reg) & CPG_SD_STP_MASK);
317	}
318
319	static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
320	unsigned long parent_rate)
321	{
322	struct sd_clock *clock = to_sd_clock(hw);
323	unsigned long rate = parent_rate;
324	u32 val, sd_fc;
325	unsigned int i;
326
327	val = clk_readl(clock->reg);
328
329	sd_fc = val & CPG_SD_FC_MASK;
330	for (i = 0; i < clock->div_num; i++)
331	if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
332	break;
333
334	if (i >= clock->div_num)
335	return -EINVAL;
336
337	return DIV_ROUND_CLOSEST(rate, clock->div_table[i].div);
338	}
339
340	static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
341	unsigned long rate,
342	unsigned long parent_rate)
343	{
344	unsigned int div;
345
346	if (!rate)
347	rate = 1;
348
349	div = DIV_ROUND_CLOSEST(parent_rate, rate);
350
351	return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
352	}
353
354	static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
355	unsigned long *parent_rate)
356	{
357	struct sd_clock *clock = to_sd_clock(hw);
358	unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
359
360	return DIV_ROUND_CLOSEST(*parent_rate, div);
361	}
362
363	static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
364	unsigned long parent_rate)
365	{
366	struct sd_clock *clock = to_sd_clock(hw);
367	unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
368	u32 val;
369	unsigned int i;
370
371	for (i = 0; i < clock->div_num; i++)
372	if (div == clock->div_table[i].div)
373	break;
374
375	if (i >= clock->div_num)
376	return -EINVAL;
377
378	val = clk_readl(clock->reg);
379	val &= ~(CPG_SD_STP_MASK \| CPG_SD_FC_MASK);
380	val \|= clock->div_table[i].val & (CPG_SD_STP_MASK \| CPG_SD_FC_MASK);
381	clk_writel(val, clock->reg);
382
383	return 0;
384	}
385
386	static const struct clk_ops cpg_sd_clock_ops = {
387	.enable = cpg_sd_clock_enable,
388	.disable = cpg_sd_clock_disable,
389	.is_enabled = cpg_sd_clock_is_enabled,
390	.recalc_rate = cpg_sd_clock_recalc_rate,
391	.round_rate = cpg_sd_clock_round_rate,
392	.set_rate = cpg_sd_clock_set_rate,
393	};
394
395	static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
396	void __iomem *base,
397	const char *parent_name)
398	{
399	struct clk_init_data init;
400	struct sd_clock *clock;
401	struct clk *clk;
402	unsigned int i;
403
404	clock = kzalloc(sizeof(*clock), GFP_KERNEL);
405	if (!clock)
406	return ERR_PTR(-ENOMEM);
407
408	init.name = core->name;
409	init.ops = &cpg_sd_clock_ops;
410	init.flags = CLK_IS_BASIC \| CLK_SET_RATE_PARENT;
411	init.parent_names = &parent_name;
412	init.num_parents = 1;
413
414	clock->reg = base + core->offset;
415	clock->hw.init = &init;
416	clock->div_table = cpg_sd_div_table;
417	clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
418
419	clock->div_max = clock->div_table[0].div;
420	clock->div_min = clock->div_max;
421	for (i = 1; i < clock->div_num; i++) {
422	clock->div_max = max(clock->div_max, clock->div_table[i].div);
423	clock->div_min = min(clock->div_min, clock->div_table[i].div);
424	}
425
426	clk = clk_register(NULL, &clock->hw);
427	if (IS_ERR(clk))
428	kfree(clock);
429
430	return clk;
431	}
c5dae0df GU	432
	433	#define CPG_PLL0CR 0x00d8
	434	#define CPG_PLL2CR 0x002c
	435	#define CPG_PLL4CR 0x01f4
	436
	437	/*
	438	* CPG Clock Data
	439	*/
	440
	441	/*
	442	* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
	443	* 14 13 19 17 (MHz)
	444	*-------------------------------------------------------------------
	445	* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
	446	* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
	447	* 0 0 1 0 Prohibited setting
	448	* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
	449	* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
	450	* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
	451	* 0 1 1 0 Prohibited setting
	452	* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
	453	* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
	454	* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
	455	* 1 0 1 0 Prohibited setting
	456	* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
	457	* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
	458	* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
	459	* 1 1 1 0 Prohibited setting
	460	* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
	461	*/
	462	#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) \| \
	463	(((md) & BIT(13)) >> 11) \| \
	464	(((md) & BIT(19)) >> 18) \| \
	465	(((md) & BIT(17)) >> 17))
	466
	467	struct cpg_pll_config {
	468	unsigned int extal_div;
	469	unsigned int pll1_mult;
	470	unsigned int pll3_mult;
	471	};
	472
	473	static const struct cpg_pll_config cpg_pll_configs[16] __initconst = {
	474	/* EXTAL div PLL1 mult PLL3 mult */
	475	{ 1, 192, 192, },
	476	{ 1, 192, 128, },
	477	{ 0, /* Prohibited setting */ },
	478	{ 1, 192, 192, },
	479	{ 1, 160, 160, },
	480	{ 1, 160, 106, },
	481	{ 0, /* Prohibited setting */ },
	482	{ 1, 160, 160, },
	483	{ 1, 128, 128, },
	484	{ 1, 128, 84, },
	485	{ 0, /* Prohibited setting */ },
	486	{ 1, 128, 128, },
	487	{ 2, 192, 192, },
	488	{ 2, 192, 128, },
	489	{ 0, /* Prohibited setting */ },
	490	{ 2, 192, 192, },
	491	};
	492
	493	static const struct cpg_pll_config *cpg_pll_config __initdata;
	494
	495	static
496	struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
497	const struct cpg_core_clk *core,
498	const struct cpg_mssr_info *info,
499	struct clk **clks,
500	void __iomem *base)
501	{
502	const struct clk *parent;
503	unsigned int mult = 1;
504	unsigned int div = 1;
505	u32 value;
506
507	parent = clks[core->parent];
508	if (IS_ERR(parent))
509	return ERR_CAST(parent);
510
511	switch (core->type) {
512	case CLK_TYPE_GEN3_MAIN:
513	div = cpg_pll_config->extal_div;
514	break;
515
516	case CLK_TYPE_GEN3_PLL0:
517	/*
518	* PLL0 is a configurable multiplier clock. Register it as a
519	* fixed factor clock for now as there's no generic multiplier
520	* clock implementation and we currently have no need to change
521	* the multiplier value.
522	*/
523	value = readl(base + CPG_PLL0CR);
524	mult = (((value >> 24) & 0x7f) + 1) * 2;
525	break;
526
527	case CLK_TYPE_GEN3_PLL1:
528	mult = cpg_pll_config->pll1_mult;
529	break;
530
531	case CLK_TYPE_GEN3_PLL2:
532	/*
533	* PLL2 is a configurable multiplier clock. Register it as a
534	* fixed factor clock for now as there's no generic multiplier
535	* clock implementation and we currently have no need to change
536	* the multiplier value.
537	*/
538	value = readl(base + CPG_PLL2CR);
539	mult = (((value >> 24) & 0x7f) + 1) * 2;
540	break;
541
542	case CLK_TYPE_GEN3_PLL3:
543	mult = cpg_pll_config->pll3_mult;
544	break;
545
546	case CLK_TYPE_GEN3_PLL4:
547	/*
548	* PLL4 is a configurable multiplier clock. Register it as a
549	* fixed factor clock for now as there's no generic multiplier
550	* clock implementation and we currently have no need to change
551	* the multiplier value.
552	*/
553	value = readl(base + CPG_PLL4CR);
554	mult = (((value >> 24) & 0x7f) + 1) * 2;
555	break;
556
90c073e5 DB	557	case CLK_TYPE_GEN3_SD:
	558	return cpg_sd_clk_register(core, base, __clk_get_name(parent));
	559
c5dae0df GU	560	default:
	561	return ERR_PTR(-EINVAL);
	562	}
	563
	564	return clk_register_fixed_factor(NULL, core->name,
	565	__clk_get_name(parent), 0, mult, div);
	566	}
	567
	568	/*
	569	* Reset register definitions.
	570	*/
	571	#define MODEMR 0xe6160060
	572
	573	static u32 rcar_gen3_read_mode_pins(void)
	574	{
	575	void __iomem *modemr = ioremap_nocache(MODEMR, 4);
	576	u32 mode;
	577
	578	BUG_ON(!modemr);
	579	mode = ioread32(modemr);
	580	iounmap(modemr);
	581
	582	return mode;
	583	}
	584
	585	static int __init r8a7795_cpg_mssr_init(struct device *dev)
	586	{
	587	u32 cpg_mode = rcar_gen3_read_mode_pins();
	588
	589	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
	590	if (!cpg_pll_config->extal_div) {
	591	dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
	592	return -EINVAL;
	593	}
	594
	595	return 0;
	596	}
	597
	598	const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
	599	/* Core Clocks */
	600	.core_clks = r8a7795_core_clks,
	601	.num_core_clks = ARRAY_SIZE(r8a7795_core_clks),
	602	.last_dt_core_clk = LAST_DT_CORE_CLK,
	603	.num_total_core_clks = MOD_CLK_BASE,
	604
	605	/* Module Clocks */
	606	.mod_clks = r8a7795_mod_clks,
	607	.num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks),
	608	.num_hw_mod_clks = 12 * 32,
	609
	610	/* Critical Module Clocks */
	611	.crit_mod_clks = r8a7795_crit_mod_clks,
	612	.num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks),
	613
	614	/* Callbacks */
	615	.init = r8a7795_cpg_mssr_init,
	616	.cpg_clk_register = r8a7795_cpg_clk_register,
	617	};