[mirror_ubuntu-eoan-kernel.git] / drivers / clk / sirf / clk-atlas6.c

/*
 * Clock tree for CSR SiRFatlasVI
 *
 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
 * company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/syscore_ops.h>

#include "atlas6.h"
#include "clk-common.c"

static struct clk_dmn clk_mmc01 = {
	.regofs = SIRFSOC_CLKC_MMC01_CFG,
	.enable_bit = 59,
	.hw = {
		.init = &clk_mmc01_init,
	},
};

static struct clk_dmn clk_mmc23 = {
	.regofs = SIRFSOC_CLKC_MMC23_CFG,
	.enable_bit = 60,
	.hw = {
		.init = &clk_mmc23_init,
	},
};

static struct clk_dmn clk_mmc45 = {
	.regofs = SIRFSOC_CLKC_MMC45_CFG,
	.enable_bit = 61,
	.hw = {
		.init = &clk_mmc45_init,
	},
};

static struct clk_init_data clk_nand_init = {
	.name = "nand",
	.ops = &dmn_ops,
	.parent_names = dmn_clk_parents,
	.num_parents = ARRAY_SIZE(dmn_clk_parents),
};

static struct clk_dmn clk_nand = {
	.regofs = SIRFSOC_CLKC_NAND_CFG,
	.enable_bit = 34,
	.hw = {
		.init = &clk_nand_init,
	},
};

enum atlas6_clk_index {
	/* 0    1     2      3      4      5      6       7         8      9 */
	rtc,    osc,   pll1,  pll2,  pll3,  mem,   sys,   security, dsp,   gps,
	mf,     io,    cpu,   uart0, uart1, uart2, tsc,   i2c0,     i2c1,  spi0,
	spi1,   pwmc,  efuse, pulse, dmac0, dmac1, nand,  audio,    usp0,  usp1,
	usp2,   vip,   gfx,   gfx2d,    lcd,   vpp,   mmc01, mmc23,    mmc45, usbpll,
	usb0,  usb1,   cphif, maxclk,
};

static __initdata struct clk_hw *atlas6_clk_hw_array[maxclk] = {
	NULL, /* dummy */
	NULL,
	&clk_pll1.hw,
	&clk_pll2.hw,
	&clk_pll3.hw,
	&clk_mem.hw,
	&clk_sys.hw,
	&clk_security.hw,
	&clk_dsp.hw,
	&clk_gps.hw,
	&clk_mf.hw,
	&clk_io.hw,
	&clk_cpu.hw,
	&clk_uart0.hw,
	&clk_uart1.hw,
	&clk_uart2.hw,
	&clk_tsc.hw,
	&clk_i2c0.hw,
	&clk_i2c1.hw,
	&clk_spi0.hw,
	&clk_spi1.hw,
	&clk_pwmc.hw,
	&clk_efuse.hw,
	&clk_pulse.hw,
	&clk_dmac0.hw,
	&clk_dmac1.hw,
	&clk_nand.hw,
	&clk_audio.hw,
	&clk_usp0.hw,
	&clk_usp1.hw,
	&clk_usp2.hw,
	&clk_vip.hw,
	&clk_gfx.hw,
	&clk_gfx2d.hw,
	&clk_lcd.hw,
	&clk_vpp.hw,
	&clk_mmc01.hw,
	&clk_mmc23.hw,
	&clk_mmc45.hw,
	&usb_pll_clk_hw,
	&clk_usb0.hw,
	&clk_usb1.hw,
	&clk_cphif.hw,
};

static struct clk *atlas6_clks[maxclk];

static void __init atlas6_clk_init(struct device_node *np)
{
	struct device_node *rscnp;
	int i;

	rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
	sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
	if (!sirfsoc_rsc_vbase)
		panic("unable to map rsc registers\n");
	of_node_put(rscnp);

	sirfsoc_clk_vbase = of_iomap(np, 0);
	if (!sirfsoc_clk_vbase)
		panic("unable to map clkc registers\n");

	/* These are always available (RTC and 26MHz OSC)*/
	atlas6_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL,
		CLK_IS_ROOT, 32768);
	atlas6_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL,
		CLK_IS_ROOT, 26000000);

	for (i = pll1; i < maxclk; i++) {
		atlas6_clks[i] = clk_register(NULL, atlas6_clk_hw_array[i]);
		BUG_ON(!atlas6_clks[i]);
	}
	clk_register_clkdev(atlas6_clks[cpu], NULL, "cpu");
	clk_register_clkdev(atlas6_clks[io],  NULL, "io");
	clk_register_clkdev(atlas6_clks[mem],  NULL, "mem");
	clk_register_clkdev(atlas6_clks[mem],  NULL, "osc");

	clk_data.clks = atlas6_clks;
	clk_data.clk_num = maxclk;

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}
CLK_OF_DECLARE(atlas6_clk, "sirf,atlas6-clkc", atlas6_clk_init);
Commit	Line	Data
7bf21bc8 BS	1	/*
	2	* Clock tree for CSR SiRFatlasVI
	3	*
77366929 BS	4	* Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
77366929 BS	5	* company.
7bf21bc8 BS	6	*
	7	* Licensed under GPLv2 or later.
	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/bitops.h>
	12	#include <linux/io.h>
7bf21bc8 BS	13	#include <linux/clkdev.h>
	14	#include <linux/clk-provider.h>
	15	#include <linux/of_address.h>
	16	#include <linux/syscore_ops.h>
	17
	18	#include "atlas6.h"
	19	#include "clk-common.c"
	20
	21	static struct clk_dmn clk_mmc01 = {
	22	.regofs = SIRFSOC_CLKC_MMC01_CFG,
	23	.enable_bit = 59,
	24	.hw = {
	25	.init = &clk_mmc01_init,
	26	},
	27	};
	28
	29	static struct clk_dmn clk_mmc23 = {
	30	.regofs = SIRFSOC_CLKC_MMC23_CFG,
	31	.enable_bit = 60,
	32	.hw = {
	33	.init = &clk_mmc23_init,
	34	},
	35	};
	36
	37	static struct clk_dmn clk_mmc45 = {
	38	.regofs = SIRFSOC_CLKC_MMC45_CFG,
	39	.enable_bit = 61,
	40	.hw = {
	41	.init = &clk_mmc45_init,
	42	},
	43	};
	44
	45	static struct clk_init_data clk_nand_init = {
	46	.name = "nand",
	47	.ops = &dmn_ops,
	48	.parent_names = dmn_clk_parents,
	49	.num_parents = ARRAY_SIZE(dmn_clk_parents),
	50	};
	51
	52	static struct clk_dmn clk_nand = {
	53	.regofs = SIRFSOC_CLKC_NAND_CFG,
	54	.enable_bit = 34,
	55	.hw = {
	56	.init = &clk_nand_init,
	57	},
	58	};
	59
	60	enum atlas6_clk_index {
	61	/* 0 1 2 3 4 5 6 7 8 9 */
	62	rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
	63	mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
	64	spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
	65	usp2, vip, gfx, gfx2d, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
	66	usb0, usb1, cphif, maxclk,
	67	};
	68
	69	static __initdata struct clk_hw *atlas6_clk_hw_array[maxclk] = {
	70	NULL, /* dummy */
	71	NULL,
	72	&clk_pll1.hw,
	73	&clk_pll2.hw,
	74	&clk_pll3.hw,
	75	&clk_mem.hw,
	76	&clk_sys.hw,
77	&clk_security.hw,
78	&clk_dsp.hw,
79	&clk_gps.hw,
80	&clk_mf.hw,
81	&clk_io.hw,
82	&clk_cpu.hw,
83	&clk_uart0.hw,
84	&clk_uart1.hw,
85	&clk_uart2.hw,
86	&clk_tsc.hw,
87	&clk_i2c0.hw,
88	&clk_i2c1.hw,
89	&clk_spi0.hw,
90	&clk_spi1.hw,
91	&clk_pwmc.hw,
92	&clk_efuse.hw,
93	&clk_pulse.hw,
94	&clk_dmac0.hw,
95	&clk_dmac1.hw,
96	&clk_nand.hw,
97	&clk_audio.hw,
98	&clk_usp0.hw,
99	&clk_usp1.hw,
100	&clk_usp2.hw,
101	&clk_vip.hw,
102	&clk_gfx.hw,
103	&clk_gfx2d.hw,
104	&clk_lcd.hw,
105	&clk_vpp.hw,
106	&clk_mmc01.hw,
107	&clk_mmc23.hw,
108	&clk_mmc45.hw,
109	&usb_pll_clk_hw,
110	&clk_usb0.hw,
111	&clk_usb1.hw,
112	&clk_cphif.hw,
113	};
114
115	static struct clk *atlas6_clks[maxclk];
116
117	static void __init atlas6_clk_init(struct device_node *np)
118	{
119	struct device_node *rscnp;
120	int i;
121
122	rscnp = of_find_compatible_node(NULL, NULL, "sirf,prima2-rsc");
123	sirfsoc_rsc_vbase = of_iomap(rscnp, 0);
124	if (!sirfsoc_rsc_vbase)
125	panic("unable to map rsc registers\n");
126	of_node_put(rscnp);
127
128	sirfsoc_clk_vbase = of_iomap(np, 0);
129	if (!sirfsoc_clk_vbase)
130	panic("unable to map clkc registers\n");
131
132	/* These are always available (RTC and 26MHz OSC)*/
133	atlas6_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL,
134	CLK_IS_ROOT, 32768);
135	atlas6_clks[osc] = clk_register_fixed_rate(NULL, "osc", NULL,
136	CLK_IS_ROOT, 26000000);
137
138	for (i = pll1; i < maxclk; i++) {
139	atlas6_clks[i] = clk_register(NULL, atlas6_clk_hw_array[i]);
140	BUG_ON(!atlas6_clks[i]);
141	}
142	clk_register_clkdev(atlas6_clks[cpu], NULL, "cpu");
143	clk_register_clkdev(atlas6_clks[io], NULL, "io");
144	clk_register_clkdev(atlas6_clks[mem], NULL, "mem");
145	clk_register_clkdev(atlas6_clks[mem], NULL, "osc");
146
147	clk_data.clks = atlas6_clks;
148	clk_data.clk_num = maxclk;
149
150	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
151	}
152	CLK_OF_DECLARE(atlas6_clk, "sirf,atlas6-clkc", atlas6_clk_init);