[mirror_ubuntu-kernels.git] / drivers / clk / socfpga / clk-gate.c

/*
 *  Copyright 2011-2012 Calxeda, Inc.
 *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * Based from clk-highbank.c
 *
 */
#include <linux/slab.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/regmap.h>

#include "clk.h"

#define SOCFPGA_L4_MP_CLK		"l4_mp_clk"
#define SOCFPGA_L4_SP_CLK		"l4_sp_clk"
#define SOCFPGA_NAND_CLK		"nand_clk"
#define SOCFPGA_NAND_X_CLK		"nand_x_clk"
#define SOCFPGA_MMC_CLK			"sdmmc_clk"
#define SOCFPGA_GPIO_DB_CLK_OFFSET	0xA8

#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)

/* SDMMC Group for System Manager defines */
#define SYSMGR_SDMMCGRP_CTRL_OFFSET    0x108

static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
{
	u32 l4_src;
	u32 perpll_src;

	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
		return l4_src &= 0x1;
	}
	if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
		return !!(l4_src & 2);
	}

	perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
	if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
		return perpll_src &= 0x3;
	if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
			return (perpll_src >> 2) & 3;

	/* QSPI clock */
	return (perpll_src >> 4) & 3;

}

static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
{
	u32 src_reg;

	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
		src_reg &= ~0x1;
		src_reg |= parent;
		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
	} else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
		src_reg &= ~0x2;
		src_reg |= (parent << 1);
		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
	} else {
		src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
		if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
			src_reg &= ~0x3;
			src_reg |= parent;
		} else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
			src_reg &= ~0xC;
			src_reg |= (parent << 2);
		} else {/* QSPI clock */
			src_reg &= ~0x30;
			src_reg |= (parent << 4);
		}
		writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
	}

	return 0;
}

static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
	unsigned long parent_rate)
{
	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
	u32 div = 1, val;

	if (socfpgaclk->fixed_div)
		div = socfpgaclk->fixed_div;
	else if (socfpgaclk->div_reg) {
		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
		val &= GENMASK(socfpgaclk->width - 1, 0);
		/* Check for GPIO_DB_CLK by its offset */
		if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
			div = val + 1;
		else
			div = (1 << val);
	}

	return parent_rate / div;
}

static int socfpga_clk_prepare(struct clk_hw *hwclk)
{
	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
	struct regmap *sys_mgr_base_addr;
	int i;
	u32 hs_timing;
	u32 clk_phase[2];

	if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
		sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
		if (IS_ERR(sys_mgr_base_addr)) {
			pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
			return -EINVAL;
		}

		for (i = 0; i < 2; i++) {
			switch (socfpgaclk->clk_phase[i]) {
			case 0:
				clk_phase[i] = 0;
				break;
			case 45:
				clk_phase[i] = 1;
				break;
			case 90:
				clk_phase[i] = 2;
				break;
			case 135:
				clk_phase[i] = 3;
				break;
			case 180:
				clk_phase[i] = 4;
				break;
			case 225:
				clk_phase[i] = 5;
				break;
			case 270:
				clk_phase[i] = 6;
				break;
			case 315:
				clk_phase[i] = 7;
				break;
			default:
				clk_phase[i] = 0;
				break;
			}
		}
		hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
		regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
			hs_timing);
	}
	return 0;
}

static struct clk_ops gateclk_ops = {
	.prepare = socfpga_clk_prepare,
	.recalc_rate = socfpga_clk_recalc_rate,
	.get_parent = socfpga_clk_get_parent,
	.set_parent = socfpga_clk_set_parent,
};

void __init socfpga_gate_init(struct device_node *node)
{
	u32 clk_gate[2];
	u32 div_reg[3];
	u32 clk_phase[2];
	u32 fixed_div;
	struct clk *clk;
	struct socfpga_gate_clk *socfpga_clk;
	const char *clk_name = node->name;
	const char *parent_name[SOCFPGA_MAX_PARENTS];
	struct clk_init_data init;
	struct clk_ops *ops;
	int rc;

	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
	if (WARN_ON(!socfpga_clk))
		return;

	ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
	if (WARN_ON(!ops))
		return;

	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
	if (rc)
		clk_gate[0] = 0;

	if (clk_gate[0]) {
		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
		socfpga_clk->hw.bit_idx = clk_gate[1];

		ops->enable = clk_gate_ops.enable;
		ops->disable = clk_gate_ops.disable;
	}

	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
	if (rc)
		socfpga_clk->fixed_div = 0;
	else
		socfpga_clk->fixed_div = fixed_div;

	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
	if (!rc) {
		socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
		socfpga_clk->shift = div_reg[1];
		socfpga_clk->width = div_reg[2];
	} else {
		socfpga_clk->div_reg = NULL;
	}

	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
	if (!rc) {
		socfpga_clk->clk_phase[0] = clk_phase[0];
		socfpga_clk->clk_phase[1] = clk_phase[1];
	}

	of_property_read_string(node, "clock-output-names", &clk_name);

	init.name = clk_name;
	init.ops = ops;
	init.flags = 0;

	init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
	if (init.num_parents < 2) {
		ops->get_parent = NULL;
		ops->set_parent = NULL;
	}

	init.parent_names = parent_name;
	socfpga_clk->hw.hw.init = &init;

	clk = clk_register(NULL, &socfpga_clk->hw.hw);
	if (WARN_ON(IS_ERR(clk))) {
		kfree(socfpga_clk);
		return;
	}
	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
	if (WARN_ON(rc))
		return;
}
Commit	Line	Data
97259e99 ST	1	/*
	2	* Copyright 2011-2012 Calxeda, Inc.
	3	* Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* Based from clk-highbank.c
	16	*
	17	*/
b0af24b5	18	#include <linux/slab.h>
97259e99 ST	19	#include <linux/clk-provider.h>
97259e99 ST	20	#include <linux/io.h>
044abbde	21	#include <linux/mfd/syscon.h>
97259e99	22	#include <linux/of.h>
044abbde	23	#include <linux/regmap.h>
97259e99 ST	24
	25	#include "clk.h"
	26
	27	#define SOCFPGA_L4_MP_CLK "l4_mp_clk"
	28	#define SOCFPGA_L4_SP_CLK "l4_sp_clk"
	29	#define SOCFPGA_NAND_CLK "nand_clk"
	30	#define SOCFPGA_NAND_X_CLK "nand_x_clk"
	31	#define SOCFPGA_MMC_CLK "sdmmc_clk"
	32	#define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
	33
97259e99 ST	34	#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
97259e99 ST	35
044abbde DN	36	/* SDMMC Group for System Manager defines */
044abbde DN	37	#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108
044abbde	38
97259e99 ST	39	static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
	40	{
	41	u32 l4_src;
	42	u32 perpll_src;
	43
	44	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
	45	l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
	46	return l4_src &= 0x1;
	47	}
	48	if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
	49	l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
	50	return !!(l4_src & 2);
	51	}
	52
	53	perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
	54	if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
	55	return perpll_src &= 0x3;
	56	if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) \|\|
	57	streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
	58	return (perpll_src >> 2) & 3;
	59
	60	/* QSPI clock */
	61	return (perpll_src >> 4) & 3;
	62
	63	}
	64
	65	static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
	66	{
	67	u32 src_reg;
	68
	69	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
	70	src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
	71	src_reg &= ~0x1;
	72	src_reg \|= parent;
	73	writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
	74	} else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
	75	src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
	76	src_reg &= ~0x2;
	77	src_reg \|= (parent << 1);
	78	writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
	79	} else {
	80	src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
	81	if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
	82	src_reg &= ~0x3;
	83	src_reg \|= parent;
	84	} else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) \|\|
	85	streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
	86	src_reg &= ~0xC;
	87	src_reg \|= (parent << 2);
	88	} else {/* QSPI clock */
	89	src_reg &= ~0x30;
	90	src_reg \|= (parent << 4);
	91	}
	92	writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
	93	}
	94
	95	return 0;
	96	}
	97
	98	static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
	99	unsigned long parent_rate)
	100	{
	101	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
	102	u32 div = 1, val;
103
104	if (socfpgaclk->fixed_div)
105	div = socfpgaclk->fixed_div;
106	else if (socfpgaclk->div_reg) {
107	val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
25d4d341	108	val &= GENMASK(socfpgaclk->width - 1, 0);
97259e99 ST	109	/* Check for GPIO_DB_CLK by its offset */
	110	if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
	111	div = val + 1;
	112	else
	113	div = (1 << val);
	114	}
	115
	116	return parent_rate / div;
	117	}
	118
044abbde DN	119	static int socfpga_clk_prepare(struct clk_hw *hwclk)
	120	{
	121	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
	122	struct regmap *sys_mgr_base_addr;
	123	int i;
	124	u32 hs_timing;
	125	u32 clk_phase[2];
	126
	127	if (socfpgaclk->clk_phase[0] \|\| socfpgaclk->clk_phase[1]) {
	128	sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
	129	if (IS_ERR(sys_mgr_base_addr)) {
	130	pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
	131	return -EINVAL;
	132	}
	133
	134	for (i = 0; i < 2; i++) {
	135	switch (socfpgaclk->clk_phase[i]) {
	136	case 0:
	137	clk_phase[i] = 0;
	138	break;
	139	case 45:
	140	clk_phase[i] = 1;
	141	break;
	142	case 90:
	143	clk_phase[i] = 2;
	144	break;
	145	case 135:
	146	clk_phase[i] = 3;
	147	break;
	148	case 180:
	149	clk_phase[i] = 4;
	150	break;
	151	case 225:
	152	clk_phase[i] = 5;
	153	break;
	154	case 270:
	155	clk_phase[i] = 6;
	156	break;
	157	case 315:
	158	clk_phase[i] = 7;
	159	break;
	160	default:
	161	clk_phase[i] = 0;
	162	break;
	163	}
	164	}
	165	hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
	166	regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
	167	hs_timing);
	168	}
	169	return 0;
	170	}
	171
97259e99	172	static struct clk_ops gateclk_ops = {
044abbde	173	.prepare = socfpga_clk_prepare,
97259e99 ST	174	.recalc_rate = socfpga_clk_recalc_rate,
	175	.get_parent = socfpga_clk_get_parent,
	176	.set_parent = socfpga_clk_set_parent,
	177	};
	178
a30a67be	179	void __init socfpga_gate_init(struct device_node *node)
97259e99 ST	180	{
	181	u32 clk_gate[2];
	182	u32 div_reg[3];
044abbde	183	u32 clk_phase[2];
97259e99 ST	184	u32 fixed_div;
	185	struct clk *clk;
	186	struct socfpga_gate_clk *socfpga_clk;
	187	const char *clk_name = node->name;
	188	const char *parent_name[SOCFPGA_MAX_PARENTS];
	189	struct clk_init_data init;
a30a67be	190	struct clk_ops *ops;
97259e99	191	int rc;
97259e99 ST	192
	193	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
	194	if (WARN_ON(!socfpga_clk))
	195	return;
	196
a30a67be SB	197	ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
	198	if (WARN_ON(!ops))
	199	return;
	200
97259e99 ST	201	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
	202	if (rc)
	203	clk_gate[0] = 0;
	204
	205	if (clk_gate[0]) {
	206	socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
	207	socfpga_clk->hw.bit_idx = clk_gate[1];
	208
a30a67be SB	209	ops->enable = clk_gate_ops.enable;
a30a67be SB	210	ops->disable = clk_gate_ops.disable;
97259e99 ST	211	}
	212
	213	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
	214	if (rc)
	215	socfpga_clk->fixed_div = 0;
	216	else
	217	socfpga_clk->fixed_div = fixed_div;
	218
	219	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
	220	if (!rc) {
	221	socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
	222	socfpga_clk->shift = div_reg[1];
	223	socfpga_clk->width = div_reg[2];
	224	} else {
b011d386	225	socfpga_clk->div_reg = NULL;
97259e99 ST	226	}
97259e99 ST	227
044abbde DN	228	rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
	229	if (!rc) {
	230	socfpga_clk->clk_phase[0] = clk_phase[0];
	231	socfpga_clk->clk_phase[1] = clk_phase[1];
	232	}
	233
97259e99 ST	234	of_property_read_string(node, "clock-output-names", &clk_name);
	235
	236	init.name = clk_name;
	237	init.ops = ops;
	238	init.flags = 0;
97259e99	239
761d3e32	240	init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
a30a67be SB	241	if (init.num_parents < 2) {
	242	ops->get_parent = NULL;
	243	ops->set_parent = NULL;
	244	}
	245
97259e99	246	init.parent_names = parent_name;
97259e99 ST	247	socfpga_clk->hw.hw.init = &init;
	248
	249	clk = clk_register(NULL, &socfpga_clk->hw.hw);
	250	if (WARN_ON(IS_ERR(clk))) {
	251	kfree(socfpga_clk);
	252	return;
	253	}
	254	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
	255	if (WARN_ON(rc))
	256	return;
	257	}