[mirror_ubuntu-zesty-kernel.git] / drivers / clk / socfpga / clk-pll.c

/*
 *  Copyright 2011-2012 Calxeda, Inc.
 *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * Based from clk-highbank.c
 *
 */
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include "clk.h"

/* Clock bypass bits */
#define MAINPLL_BYPASS		(1<<0)
#define SDRAMPLL_BYPASS		(1<<1)
#define SDRAMPLL_SRC_BYPASS	(1<<2)
#define PERPLL_BYPASS		(1<<3)
#define PERPLL_SRC_BYPASS	(1<<4)

#define SOCFPGA_PLL_BG_PWRDWN		0
#define SOCFPGA_PLL_EXT_ENA		1
#define SOCFPGA_PLL_PWR_DOWN		2
#define SOCFPGA_PLL_DIVF_MASK		0x0000FFF8
#define SOCFPGA_PLL_DIVF_SHIFT		3
#define SOCFPGA_PLL_DIVQ_MASK		0x003F0000
#define SOCFPGA_PLL_DIVQ_SHIFT		16

#define CLK_MGR_PLL_CLK_SRC_SHIFT	22
#define CLK_MGR_PLL_CLK_SRC_MASK	0x3

#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)

void __iomem *clk_mgr_base_addr;

static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
					 unsigned long parent_rate)
{
	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
	unsigned long divf, divq, reg;
	unsigned long long vco_freq;
	unsigned long bypass;

	reg = readl(socfpgaclk->hw.reg);
	bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
	if (bypass & MAINPLL_BYPASS)
		return parent_rate;

	divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
	divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
	vco_freq = (unsigned long long)parent_rate * (divf + 1);
	do_div(vco_freq, (1 + divq));
	return (unsigned long)vco_freq;
}

static u8 clk_pll_get_parent(struct clk_hw *hwclk)
{
	u32 pll_src;
	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);

	pll_src = readl(socfpgaclk->hw.reg);
	return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
			CLK_MGR_PLL_CLK_SRC_MASK;
}

static struct clk_ops clk_pll_ops = {
	.recalc_rate = clk_pll_recalc_rate,
	.get_parent = clk_pll_get_parent,
};

static __init struct clk *__socfpga_pll_init(struct device_node *node,
	const struct clk_ops *ops)
{
	u32 reg;
	struct clk *clk;
	struct socfpga_pll *pll_clk;
	const char *clk_name = node->name;
	const char *parent_name[SOCFPGA_MAX_PARENTS];
	struct clk_init_data init;
	struct device_node *clkmgr_np;
	int rc;
	int i = 0;

	of_property_read_u32(node, "reg", &reg);

	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
	if (WARN_ON(!pll_clk))
		return NULL;

	clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
	clk_mgr_base_addr = of_iomap(clkmgr_np, 0);
	BUG_ON(!clk_mgr_base_addr);
	pll_clk->hw.reg = clk_mgr_base_addr + reg;

	of_property_read_string(node, "clock-output-names", &clk_name);

	init.name = clk_name;
	init.ops = ops;
	init.flags = 0;

	while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
			of_clk_get_parent_name(node, i)) != NULL)
		i++;

	init.num_parents = i;
	init.parent_names = parent_name;
	pll_clk->hw.hw.init = &init;

	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
	clk_pll_ops.enable = clk_gate_ops.enable;
	clk_pll_ops.disable = clk_gate_ops.disable;

	clk = clk_register(NULL, &pll_clk->hw.hw);
	if (WARN_ON(IS_ERR(clk))) {
		kfree(pll_clk);
		return NULL;
	}
	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
	return clk;
}

void __init socfpga_pll_init(struct device_node *node)
{
	__socfpga_pll_init(node, &clk_pll_ops);
}
Commit	Line	Data
97259e99 ST	1	/*
	2	* Copyright 2011-2012 Calxeda, Inc.
	3	* Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* Based from clk-highbank.c
	16	*
	17	*/
	18	#include <linux/clk.h>
	19	#include <linux/clkdev.h>
	20	#include <linux/clk-provider.h>
	21	#include <linux/io.h>
	22	#include <linux/of.h>
a30d27ed	23	#include <linux/of_address.h>
97259e99 ST	24
	25	#include "clk.h"
	26
	27	/* Clock bypass bits */
	28	#define MAINPLL_BYPASS (1<<0)
	29	#define SDRAMPLL_BYPASS (1<<1)
	30	#define SDRAMPLL_SRC_BYPASS (1<<2)
	31	#define PERPLL_BYPASS (1<<3)
	32	#define PERPLL_SRC_BYPASS (1<<4)
	33
	34	#define SOCFPGA_PLL_BG_PWRDWN 0
	35	#define SOCFPGA_PLL_EXT_ENA 1
	36	#define SOCFPGA_PLL_PWR_DOWN 2
	37	#define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8
	38	#define SOCFPGA_PLL_DIVF_SHIFT 3
	39	#define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
	40	#define SOCFPGA_PLL_DIVQ_SHIFT 16
	41
b89cd950 DN	42	#define CLK_MGR_PLL_CLK_SRC_SHIFT 22
	43	#define CLK_MGR_PLL_CLK_SRC_MASK 0x3
	44
97259e99 ST	45	#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
97259e99 ST	46
a30d27ed DN	47	void __iomem *clk_mgr_base_addr;
a30d27ed DN	48
97259e99 ST	49	static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
	50	unsigned long parent_rate)
	51	{
	52	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
5585f731 DN	53	unsigned long divf, divq, reg;
5585f731 DN	54	unsigned long long vco_freq;
97259e99 ST	55	unsigned long bypass;
	56
	57	reg = readl(socfpgaclk->hw.reg);
	58	bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
	59	if (bypass & MAINPLL_BYPASS)
	60	return parent_rate;
	61
	62	divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
	63	divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
5585f731 DN	64	vco_freq = (unsigned long long)parent_rate * (divf + 1);
	65	do_div(vco_freq, (1 + divq));
	66	return (unsigned long)vco_freq;
97259e99 ST	67	}
97259e99 ST	68
b89cd950 DN	69	static u8 clk_pll_get_parent(struct clk_hw *hwclk)
	70	{
	71	u32 pll_src;
	72	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
	73
	74	pll_src = readl(socfpgaclk->hw.reg);
	75	return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
	76	CLK_MGR_PLL_CLK_SRC_MASK;
	77	}
	78
97259e99 ST	79	static struct clk_ops clk_pll_ops = {
97259e99 ST	80	.recalc_rate = clk_pll_recalc_rate,
b89cd950	81	.get_parent = clk_pll_get_parent,
97259e99 ST	82	};
	83
	84	static __init struct clk __socfpga_pll_init(struct device_node node,
	85	const struct clk_ops *ops)
	86	{
	87	u32 reg;
	88	struct clk *clk;
	89	struct socfpga_pll *pll_clk;
	90	const char *clk_name = node->name;
b89cd950	91	const char *parent_name[SOCFPGA_MAX_PARENTS];
97259e99	92	struct clk_init_data init;
a30d27ed	93	struct device_node *clkmgr_np;
97259e99	94	int rc;
b89cd950	95	int i = 0;
97259e99 ST	96
	97	of_property_read_u32(node, "reg", &reg);
	98
	99	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
	100	if (WARN_ON(!pll_clk))
	101	return NULL;
	102
a30d27ed DN	103	clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
	104	clk_mgr_base_addr = of_iomap(clkmgr_np, 0);
	105	BUG_ON(!clk_mgr_base_addr);
97259e99 ST	106	pll_clk->hw.reg = clk_mgr_base_addr + reg;
	107
	108	of_property_read_string(node, "clock-output-names", &clk_name);
	109
	110	init.name = clk_name;
	111	init.ops = ops;
	112	init.flags = 0;
97259e99	113
b89cd950 DN	114	while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
	115	of_clk_get_parent_name(node, i)) != NULL)
	116	i++;
	117
	118	init.num_parents = i;
	119	init.parent_names = parent_name;
97259e99 ST	120	pll_clk->hw.hw.init = &init;
	121
	122	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
	123	clk_pll_ops.enable = clk_gate_ops.enable;
	124	clk_pll_ops.disable = clk_gate_ops.disable;
	125
	126	clk = clk_register(NULL, &pll_clk->hw.hw);
	127	if (WARN_ON(IS_ERR(clk))) {
	128	kfree(pll_clk);
	129	return NULL;
	130	}
	131	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
	132	return clk;
	133	}
	134
	135	void __init socfpga_pll_init(struct device_node *node)
	136	{
	137	__socfpga_pll_init(node, &clk_pll_ops);
	138	}