]>
Commit | Line | Data |
---|---|---|
b1165170 GF |
1 | /* |
2 | * clk-flexgen.c | |
3 | * | |
4 | * Copyright (C) ST-Microelectronics SA 2013 | |
5 | * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics. | |
6 | * License terms: GNU General Public License (GPL), version 2 */ | |
7 | ||
8 | #include <linux/clk-provider.h> | |
9 | #include <linux/module.h> | |
10 | #include <linux/slab.h> | |
11 | #include <linux/io.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/string.h> | |
14 | #include <linux/of.h> | |
15 | #include <linux/of_address.h> | |
16 | ||
17 | struct flexgen { | |
18 | struct clk_hw hw; | |
19 | ||
20 | /* Crossbar */ | |
21 | struct clk_mux mux; | |
22 | /* Pre-divisor's gate */ | |
23 | struct clk_gate pgate; | |
24 | /* Pre-divisor */ | |
25 | struct clk_divider pdiv; | |
26 | /* Final divisor's gate */ | |
27 | struct clk_gate fgate; | |
28 | /* Final divisor */ | |
29 | struct clk_divider fdiv; | |
30 | }; | |
31 | ||
32 | #define to_flexgen(_hw) container_of(_hw, struct flexgen, hw) | |
33 | ||
34 | static int flexgen_enable(struct clk_hw *hw) | |
35 | { | |
36 | struct flexgen *flexgen = to_flexgen(hw); | |
37 | struct clk_hw *pgate_hw = &flexgen->pgate.hw; | |
38 | struct clk_hw *fgate_hw = &flexgen->fgate.hw; | |
39 | ||
4e907ef6 JMC |
40 | __clk_hw_set_clk(pgate_hw, hw); |
41 | __clk_hw_set_clk(fgate_hw, hw); | |
b1165170 GF |
42 | |
43 | clk_gate_ops.enable(pgate_hw); | |
44 | ||
45 | clk_gate_ops.enable(fgate_hw); | |
46 | ||
47 | pr_debug("%s: flexgen output enabled\n", __clk_get_name(hw->clk)); | |
48 | return 0; | |
49 | } | |
50 | ||
51 | static void flexgen_disable(struct clk_hw *hw) | |
52 | { | |
53 | struct flexgen *flexgen = to_flexgen(hw); | |
54 | struct clk_hw *fgate_hw = &flexgen->fgate.hw; | |
55 | ||
56 | /* disable only the final gate */ | |
4e907ef6 | 57 | __clk_hw_set_clk(fgate_hw, hw); |
b1165170 GF |
58 | |
59 | clk_gate_ops.disable(fgate_hw); | |
60 | ||
61 | pr_debug("%s: flexgen output disabled\n", __clk_get_name(hw->clk)); | |
62 | } | |
63 | ||
64 | static int flexgen_is_enabled(struct clk_hw *hw) | |
65 | { | |
66 | struct flexgen *flexgen = to_flexgen(hw); | |
67 | struct clk_hw *fgate_hw = &flexgen->fgate.hw; | |
68 | ||
4e907ef6 | 69 | __clk_hw_set_clk(fgate_hw, hw); |
b1165170 GF |
70 | |
71 | if (!clk_gate_ops.is_enabled(fgate_hw)) | |
72 | return 0; | |
73 | ||
74 | return 1; | |
75 | } | |
76 | ||
77 | static u8 flexgen_get_parent(struct clk_hw *hw) | |
78 | { | |
79 | struct flexgen *flexgen = to_flexgen(hw); | |
80 | struct clk_hw *mux_hw = &flexgen->mux.hw; | |
81 | ||
4e907ef6 | 82 | __clk_hw_set_clk(mux_hw, hw); |
b1165170 GF |
83 | |
84 | return clk_mux_ops.get_parent(mux_hw); | |
85 | } | |
86 | ||
87 | static int flexgen_set_parent(struct clk_hw *hw, u8 index) | |
88 | { | |
89 | struct flexgen *flexgen = to_flexgen(hw); | |
90 | struct clk_hw *mux_hw = &flexgen->mux.hw; | |
91 | ||
4e907ef6 | 92 | __clk_hw_set_clk(mux_hw, hw); |
b1165170 GF |
93 | |
94 | return clk_mux_ops.set_parent(mux_hw, index); | |
95 | } | |
96 | ||
97 | static inline unsigned long | |
98 | clk_best_div(unsigned long parent_rate, unsigned long rate) | |
99 | { | |
100 | return parent_rate / rate + ((rate > (2*(parent_rate % rate))) ? 0 : 1); | |
101 | } | |
102 | ||
103 | static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate, | |
104 | unsigned long *prate) | |
105 | { | |
106 | unsigned long div; | |
107 | ||
108 | /* Round div according to exact prate and wished rate */ | |
109 | div = clk_best_div(*prate, rate); | |
110 | ||
111 | if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { | |
112 | *prate = rate * div; | |
113 | return rate; | |
114 | } | |
115 | ||
116 | return *prate / div; | |
117 | } | |
118 | ||
119 | unsigned long flexgen_recalc_rate(struct clk_hw *hw, | |
120 | unsigned long parent_rate) | |
121 | { | |
122 | struct flexgen *flexgen = to_flexgen(hw); | |
123 | struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; | |
124 | struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; | |
125 | unsigned long mid_rate; | |
126 | ||
4e907ef6 JMC |
127 | __clk_hw_set_clk(pdiv_hw, hw); |
128 | __clk_hw_set_clk(fdiv_hw, hw); | |
b1165170 GF |
129 | |
130 | mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate); | |
131 | ||
132 | return clk_divider_ops.recalc_rate(fdiv_hw, mid_rate); | |
133 | } | |
134 | ||
135 | static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate, | |
136 | unsigned long parent_rate) | |
137 | { | |
138 | struct flexgen *flexgen = to_flexgen(hw); | |
139 | struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; | |
140 | struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; | |
edc30077 | 141 | unsigned long div = 0; |
b1165170 GF |
142 | int ret = 0; |
143 | ||
4e907ef6 JMC |
144 | __clk_hw_set_clk(pdiv_hw, hw); |
145 | __clk_hw_set_clk(fdiv_hw, hw); | |
b1165170 | 146 | |
edc30077 | 147 | div = clk_best_div(parent_rate, rate); |
b1165170 | 148 | |
edc30077 PG |
149 | /* |
150 | * pdiv is mainly targeted for low freq results, while fdiv | |
151 | * should be used for div <= 64. The other way round can | |
152 | * lead to 'duty cycle' issues. | |
153 | */ | |
154 | ||
155 | if (div <= 64) { | |
156 | clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate); | |
157 | ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div); | |
158 | } else { | |
159 | clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate); | |
160 | ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div); | |
161 | } | |
b1165170 GF |
162 | |
163 | return ret; | |
164 | } | |
165 | ||
166 | static const struct clk_ops flexgen_ops = { | |
167 | .enable = flexgen_enable, | |
168 | .disable = flexgen_disable, | |
169 | .is_enabled = flexgen_is_enabled, | |
170 | .get_parent = flexgen_get_parent, | |
171 | .set_parent = flexgen_set_parent, | |
172 | .round_rate = flexgen_round_rate, | |
173 | .recalc_rate = flexgen_recalc_rate, | |
174 | .set_rate = flexgen_set_rate, | |
175 | }; | |
176 | ||
177 | struct clk *clk_register_flexgen(const char *name, | |
178 | const char **parent_names, u8 num_parents, | |
179 | void __iomem *reg, spinlock_t *lock, u32 idx, | |
180 | unsigned long flexgen_flags) { | |
181 | struct flexgen *fgxbar; | |
182 | struct clk *clk; | |
183 | struct clk_init_data init; | |
184 | u32 xbar_shift; | |
185 | void __iomem *xbar_reg, *fdiv_reg; | |
186 | ||
187 | fgxbar = kzalloc(sizeof(struct flexgen), GFP_KERNEL); | |
188 | if (!fgxbar) | |
189 | return ERR_PTR(-ENOMEM); | |
190 | ||
191 | init.name = name; | |
192 | init.ops = &flexgen_ops; | |
193 | init.flags = CLK_IS_BASIC | flexgen_flags; | |
194 | init.parent_names = parent_names; | |
195 | init.num_parents = num_parents; | |
196 | ||
197 | xbar_reg = reg + 0x18 + (idx & ~0x3); | |
198 | xbar_shift = (idx % 4) * 0x8; | |
199 | fdiv_reg = reg + 0x164 + idx * 4; | |
200 | ||
201 | /* Crossbar element config */ | |
202 | fgxbar->mux.lock = lock; | |
203 | fgxbar->mux.mask = BIT(6) - 1; | |
204 | fgxbar->mux.reg = xbar_reg; | |
205 | fgxbar->mux.shift = xbar_shift; | |
206 | fgxbar->mux.table = NULL; | |
207 | ||
208 | ||
209 | /* Pre-divider's gate config (in xbar register)*/ | |
210 | fgxbar->pgate.lock = lock; | |
211 | fgxbar->pgate.reg = xbar_reg; | |
212 | fgxbar->pgate.bit_idx = xbar_shift + 6; | |
213 | ||
214 | /* Pre-divider config */ | |
215 | fgxbar->pdiv.lock = lock; | |
216 | fgxbar->pdiv.reg = reg + 0x58 + idx * 4; | |
217 | fgxbar->pdiv.width = 10; | |
218 | ||
219 | /* Final divider's gate config */ | |
220 | fgxbar->fgate.lock = lock; | |
221 | fgxbar->fgate.reg = fdiv_reg; | |
222 | fgxbar->fgate.bit_idx = 6; | |
223 | ||
224 | /* Final divider config */ | |
225 | fgxbar->fdiv.lock = lock; | |
226 | fgxbar->fdiv.reg = fdiv_reg; | |
227 | fgxbar->fdiv.width = 6; | |
228 | ||
229 | fgxbar->hw.init = &init; | |
230 | ||
231 | clk = clk_register(NULL, &fgxbar->hw); | |
232 | if (IS_ERR(clk)) | |
233 | kfree(fgxbar); | |
234 | else | |
235 | pr_debug("%s: parent %s rate %u\n", | |
236 | __clk_get_name(clk), | |
237 | __clk_get_name(clk_get_parent(clk)), | |
238 | (unsigned int)clk_get_rate(clk)); | |
239 | return clk; | |
240 | } | |
241 | ||
242 | static const char ** __init flexgen_get_parents(struct device_node *np, | |
243 | int *num_parents) | |
244 | { | |
245 | const char **parents; | |
246 | int nparents, i; | |
247 | ||
248 | nparents = of_count_phandle_with_args(np, "clocks", "#clock-cells"); | |
249 | if (WARN_ON(nparents <= 0)) | |
250 | return NULL; | |
251 | ||
252 | parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL); | |
253 | if (!parents) | |
254 | return NULL; | |
255 | ||
256 | for (i = 0; i < nparents; i++) | |
257 | parents[i] = of_clk_get_parent_name(np, i); | |
258 | ||
259 | *num_parents = nparents; | |
260 | return parents; | |
261 | } | |
262 | ||
263 | void __init st_of_flexgen_setup(struct device_node *np) | |
264 | { | |
265 | struct device_node *pnode; | |
266 | void __iomem *reg; | |
267 | struct clk_onecell_data *clk_data; | |
268 | const char **parents; | |
269 | int num_parents, i; | |
270 | spinlock_t *rlock = NULL; | |
271 | unsigned long flex_flags = 0; | |
272 | ||
273 | pnode = of_get_parent(np); | |
274 | if (!pnode) | |
275 | return; | |
276 | ||
277 | reg = of_iomap(pnode, 0); | |
278 | if (!reg) | |
279 | return; | |
280 | ||
281 | parents = flexgen_get_parents(np, &num_parents); | |
282 | if (!parents) | |
283 | return; | |
284 | ||
285 | clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); | |
286 | if (!clk_data) | |
287 | goto err; | |
288 | ||
289 | clk_data->clk_num = of_property_count_strings(np , | |
290 | "clock-output-names"); | |
291 | if (clk_data->clk_num <= 0) { | |
292 | pr_err("%s: Failed to get number of output clocks (%d)", | |
293 | __func__, clk_data->clk_num); | |
294 | goto err; | |
295 | } | |
296 | ||
297 | clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *), | |
298 | GFP_KERNEL); | |
299 | if (!clk_data->clks) | |
300 | goto err; | |
301 | ||
302 | rlock = kzalloc(sizeof(spinlock_t), GFP_KERNEL); | |
303 | if (!rlock) | |
304 | goto err; | |
305 | ||
306 | for (i = 0; i < clk_data->clk_num; i++) { | |
307 | struct clk *clk; | |
308 | const char *clk_name; | |
309 | ||
310 | if (of_property_read_string_index(np, "clock-output-names", | |
311 | i, &clk_name)) { | |
312 | break; | |
313 | } | |
314 | ||
315 | /* | |
316 | * If we read an empty clock name then the output is unused | |
317 | */ | |
318 | if (*clk_name == '\0') | |
319 | continue; | |
320 | ||
321 | clk = clk_register_flexgen(clk_name, parents, num_parents, | |
322 | reg, rlock, i, flex_flags); | |
323 | ||
324 | if (IS_ERR(clk)) | |
325 | goto err; | |
326 | ||
327 | clk_data->clks[i] = clk; | |
328 | } | |
329 | ||
330 | kfree(parents); | |
331 | of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); | |
332 | ||
333 | return; | |
334 | ||
335 | err: | |
336 | if (clk_data) | |
337 | kfree(clk_data->clks); | |
338 | kfree(clk_data); | |
339 | kfree(parents); | |
340 | kfree(rlock); | |
341 | } | |
342 | CLK_OF_DECLARE(flexgen, "st,flexgen", st_of_flexgen_setup); |